KR19980031650A - Data mapping device in the system employing PDP - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data mapping apparatus in a system employing a plasma display panel (PDP). The present invention relates to a signal input unit 100 that outputs a horizontal / vertical synchronization signal, a luminance signal, and an analog image signal after receiving and processing a composite video signal. ) And horizontal and vertical positions, horizontal and vertical position selection unit 110 for outputting horizontal and vertical position selection signals, and receiving the horizontal / vertical synchronization signal to generate a frame classification signal and generating the analog image signal. In a system employing a PDP configured to include a data A / D converter 120 for receiving input and converting the digital image data into digital image data according to the horizontal and vertical position selection signals, the luminance signal is obtained to obtain an average luminance level of the luminance signal. An average brightness level converting unit 130 for converting the signal to a DC level; A level A / D converter 140 for converting the average luminance level of the DC level into digital average luminance level data according to the frame division signal; An address selector 150 for selecting an address according to the digital average luminance level data; A mapping memory 160 for newly mapping the digital image data according to a signal from the address selector 150; And a storage unit 170 that reads or writes the newly mapped data according to the horizontal and vertical position selection signals, and the PDP does not apply the PDP because the luminance characteristic of the input image signal is approached to the luminance characteristic of the PDP. It has the effect of pursuing the long life of the.

Description

An apparatus for mapping data in a system using Plasma Display Panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data mapping apparatus in a system employing a plasma display panel (hereinafter referred to as a PDP). In particular, the present invention relates to an input image data in order to match the luminance characteristic of an input image signal to the luminance characteristic of an actual PDP. The present invention relates to a data mapping apparatus configured to newly map data arbitrarily configured according to luminance characteristics of an actual PDP.

In general, a PDP is a flat panel display device using a penning gas for discharge, that is, a gas based on a neon or helium gas having a relatively high atmospheric pressure (over 100 Torr) is coated with a dielectric. It refers to a display device using the light emitting phenomenon of the phosphor due to the discharge between the narrow electrodes, and essentially has a performance suitable for computer terminals, educational systems, etc., and has been practically used as a computer display.

The penning gas is mainly Ne + Xe, Ne + He + Xe, and the reason for using such a mixed gas is that the discharge voltage can be lowered when the mixed gas is more than one gas component. The discharge start voltage depends on the type of gas, the fanning gas pressure, and the structure and shape of the panel.

Such a PDP has the following advantages over other display devices.

Since PDP does not discharge below a certain voltage (Firing voltage), such a nonlinearity eliminates the limitation on the number of plasma display lines, thereby enabling large-scale manufacturing and using multiplexing technology to reduce the number of driving circuits.

The large matrix display has a memory function, which is necessary to eliminate high brightness and flicker, while the CRT has a lifespan of 20,000 hours while the PDP has a lifespan of 50,000 hours.

In addition, PDP is suitable for mass production because there are no easily broken parts other than glass, and its structure is simple, so that large panels can be manufactured, and because of its strong nonlinearity, it can have a resolution of 100 Line / inch or more.

Since the discharging material is a gas, the refractive index value is 1, which means that the light is not extinguished by the internal reflection and the external light is not reflected or scattered by the display material.

In addition, unlike other flat panels, the PDP is sealed with glass above 400 ° C, which means that the plasma display can operate even under high humidity conditions or the presence of reactive gases. The change is only caused by the circuit.

1 is a block diagram showing the overall configuration of a system employing a conventional PDP, in which a system employing a PDP includes a signal input unit 2, horizontal and vertical position selection units 4, and a data A / D conversion unit 6; ), Storage unit 8, interface unit 10, address voltage generator 12, sustain voltage generator 14, scan and sustain voltage generator 16, control timing generator 18, panel unit It consists of 20.

The signal input unit 2 receives a composite video signal, amplifies it to be suitable for a system employing the PDP, performs a video processing process, and then a horizontal synchronizing signal (H.sync) and a vertical synchronizing signal (Vertical synchronizing). signal: outputs a V.sync) and an analog video signal (RG B signal).

The horizontal and vertical position selector 4 receives a horizontal sync signal (H.Sync) from the signal input unit 2, selects a horizontal position (H.Position), and then selects a horizontal position select signal (H.Position signal). In addition, the vertical position selection signal (V.Position signal) is selected after receiving a horizontal synchronization signal (H.Sync) and a vertical synchronization signal (V.Sync) from the signal input unit 2 and selecting a vertical position (V.Position). ) Here, when the case where it is necessary to set only a section having image information in one line occurs, the horizontal position refers to an appropriate section having image information in one line, and the vertical position should set only a line having image information in one frame. When this occurs, it refers to an appropriate section in which the image information among the frames.

The data A / D converter 6 receives an analog video signal (RG B signal) from the signal input unit 2 and converts it into digital video data (RG B data) according to the horizontal and vertical position selection signals. .

The storage unit 8 writes or reads the digital image data R. G. B data according to the horizontal and vertical position selection signals input from the horizontal and vertical position selection units 4.

The interface unit 10 is suitable for receiving and displaying digital image data (RG B data) from the storage unit 8 according to the horizontal and vertical position selection signals input from the horizontal and vertical position selection units 4. Reorder the data so that computer data is output in parallel.

The address voltage generator 12 receives scan information and parallel data from the interface unit 10 to generate an address voltage to generate wall charges.

The sustain voltage generator 14 generates a sustain voltage, and the scan and sustain voltage generator 16 performs a scan and generates a sustain voltage.

The control timing generator 18 generates a time for addressing data to the interface unit 10 and the address voltage generator 12 according to the horizontal and vertical synchronization signals input from the signal input unit 2, A sustain time is generated in the sustain voltage generator 14, and a scan and sustain time is generated in the scan and sustain voltage generator 16.

In the panel unit 20, the address from the address voltage generator 12 is applied while the sustain voltages from the sustain voltage generator 14 and the scan and sustain voltage generator 16 are applied to all of the cells. When voltage is applied, the necessary information is displayed.

2A is a graph illustrating an example of luminance characteristics according to data weights of an input image signal, and (B) is a graph illustrating an example of luminance characteristics according to data weights of an actual PDP. (c) is a problem to be achieved in the present invention, in which the luminance characteristic of the input video signal shown in (a) is adapted to the luminance characteristic of the actual PDP shown in (b).

As shown in (a) of FIG. 2, as the weight of the image data increases, the luminance component also increases linearly, whereas as shown in (b), the actual PDP shows the image data. As the weight of increases, the luminance component increases non-linearly. The reason why the luminance component of the actual PDP increases nonlinearly is because of the physical characteristics of the phosphor used for displaying data on the PDP or other inherent characteristics of the panel.

As described above, when the input image signal is displayed in a state where the luminance characteristic of the input image signal does not match the luminance characteristic of the actual PDP, the image having the desired color and luminance is not displayed. For example, based on the experiment, the red data (R), green data (G), and blue data (B) having the same luminance characteristics as in FIG. 2A have the same ratio (R: G: B = 1: 1). In the case of displaying on a PDP having the luminance characteristic as shown in (1) in (1), a color other than white was displayed even though white was to be displayed.

In addition to the problems described above, even if the brightness characteristics of the input video signal does not match the brightness characteristics of the actual PDP, there is a problem in that the display of the video signal continues to impose a burden on the panel to shorten the life of the PDP.

Accordingly, the present invention has been made to solve the above problems, and in order to match the luminance characteristics of the input image signal to the luminance characteristics of the actual PDP, the input image data is newly mapped to data arbitrarily configured according to the luminance characteristics of the actual PDP. Its purpose is to provide a data mapping device intended for mapping.

The data mapping apparatus of the present invention for achieving the above object is a signal input unit for outputting a horizontal and vertical synchronization signal, a luminance signal, and an analog image signal after receiving and amplifying and video processing a composite video signal and the horizontal and vertical synchronization After receiving the signal and selecting the horizontal and vertical position, the horizontal and vertical position selection unit for outputting the horizontal and vertical position selection signal, the horizontal and vertical synchronizing signal is received to generate a frame separation signal, the analog from the signal input unit In a system employing a PDP configured to receive a video signal and convert the image signal into digital video data according to the horizontal and vertical position selection signals, the average brightness level of the brightness signal received from the signal input unit is determined. Average luminance of converting the luminance signal to a DC level for A level converter; A level A / D converter for converting the average brightness level of the DC level into digital average brightness level data according to the frame division signal from the data A / D converter; An address selector which selects an address according to the digital average luminance level data received from the level A / D converter and outputs an address selection signal; A mapping memory having a memory map composed of data corresponding to luminance characteristics of the PDP, and mapping digital image data received from the data A / D converter according to the address selection signal to data formed according to the luminance characteristics of the PDP; And a storage unit that reads or writes the newly mapped data according to the horizontal and vertical position selection signals.

According to the present invention as described above, the maximum luminance in the memory map by arbitrarily configuring a memory map composed of data corresponding to the luminance characteristics of the PDP in order to bring the luminance characteristics of the input video signal to the maximum luminance characteristics of the actual PDP. The white level can be arbitrarily limited, that is, the PDP is not overwhelmed and the life of the PDP is increased.

1 is a block diagram showing the overall configuration of a system employing a conventional plasma display panel (PDP);

2A is a graph illustrating an example of luminance characteristics according to data weights of an input image signal;

(b) is a graph showing an example of luminance characteristics according to data weight of an actual PDP;

(c) is a problem to be achieved in the present invention, a view showing a state to match the luminance characteristics of the input image signal shown in (a) to the luminance characteristics of the PDP shown in (b),

3 is a block diagram showing a data mapping apparatus in a system employing a PDP according to the present invention;

4 is a block diagram showing in detail the configuration of the address selector shown in FIG. 3;

FIG. 5 illustrates an example of a process of one-to-one mapping of digital image data to data previously stored in a mapping memory map according to an average luminance level; FIG.

6 is a block diagram showing the configuration of a data mapping apparatus in a television employing a PDP as an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

130 .... average luminance level conversion unit 140 .... level A / D conversion unit

150 .... Address selector 160 .... Mapping memory

170 .... storage

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram showing a data mapping apparatus in a system employing a PDP according to the present invention, wherein the data mapping apparatus includes a signal input unit 100; Horizontal and vertical position selector 110; A data A / D converter 120; An average brightness level converting unit 130; A level A / D converter 140; An address selector 150; Mapping memory 160; Storage unit 170; An interface unit 180; An address voltage generator 190; Sustain voltage generator 200; Scan and sustain voltage generator 210; A control timing generator 220; And a panel unit 230.

FIG. 4 is a block diagram showing the configuration of the address selector 150 shown in FIG. 3, wherein the address selector 150 shown in FIG. 4 includes a first end gate 152; Second and gate 153; And a buffer 156.

First, the data A / D converter 120 converts an analog video signal into 8-bit digital video data, and the level A / D converter 140 converts an average luminance level of a DC level into 5-bit digital data. Assume that we convert to average luminance level data.

The signal input unit 100 receives a composite signal and amplifies and processes the video signal, and then a horizontal sync signal (H.sync), a vertical sync signal (V.sync), and a luminance signal (Y signal). And an analog image signal (RG B signal).

The horizontal and vertical position selector 110 receives the horizontal synchronization signal (H.sync), selects a horizontal position (H.Position), outputs a horizontal position selection signal (H.Position signal), and outputs a vertical synchronization signal. After inputting (V.sync), select the vertical position (V.Position) and output the vertical position selection signal (V.Position signal). In this case, the horizontal position refers to an appropriate section in which image information is included in one line when the case where it is necessary to set only a section including image information in one line, and the vertical position should set only a line in which image information is included in one frame. When this occurs, it refers to an appropriate section in which there is video information in the frame.

The data A / D converter 120 receives a horizontal and vertical synchronization signal from the signal input unit 100 as a clock CLK to generate a frame division signal F.sync, and the signal input unit 100. An analog image signal (RG B signal) is received from the digital signal and converted into 8-bit digital image data (RG B data) according to the horizontal and vertical position selection signals. Here, the frame division signal (F.sync) is a signal for distinguishing one frame.

The average luminance level converter 130 converts the luminance signal to a DC level to obtain an average picture luminance level APL of the luminance signal received from the signal input unit 100.

The level A / D converter 140 converts the average luminance level signal of the DC level into digital average luminance level data in units of 5 bits according to the frame division signal F.sync from the data A / D converter 120. To.

The address selector 150 selects an address according to the 5-bit digital average luminance level data received from the level A / D converter 140 and outputs the address selection signal.

That is, the address selector 150 includes a first and gate 152, a second and gate 154, and a buffer 156. Here, the first AND gate 152 receives the horizontal position selection signal and the vertical position selection signal and performs a logical product to output a result value (address selection start signal), and the second AND gate 154 The result of the logical product input from the first AND gate 152 and the logical product of the digital average luminance level from the level A / D converter 140 are output, and then an address selection signal is output. ) Buffers the logical AND result of the first AND gate 152 and outputs the result to the storage unit 170.

The meaning contained in the result value of the first and gate 152 is to cause the address selector 150 to start operation only in a section in which the actual image information is present, and is contained in the result value of the second and gate 154. The meaning is that the address selector 150 selects an address according to the digital average luminance level only in a section in which the actual image information is present, and the buffer 154 determines the logical product of the first and gate 152. The reason for buffering and outputting the data to the storage unit 170 is to read or write the digital image data only in a section in which the actual image information exists.

The mapping memory 160 stores 32 luminance steps according to the luminance characteristics of the actual PDP, stores 256 data for each luminance step, and then determines the luminance step according to the address selection signal. The digital image data received from the / D converter 120 is mapped to one data in the determined brightness step, and the mapped data is output.

FIG. 5 is a diagram illustrating an example of a process of one-to-one mapping of digital image data to data stored in a memory map of a mapping memory according to the average luminance level.

As shown in FIG. 5, since the level A / D converter 140 shown in FIG. 3 outputs 5-bit average luminance level data, the average luminance is 32 steps (1 level to 32 level: as the level is higher). Brightness is high.). At this time, the memory map in the mapping memory 160 shown in FIG. 3 has 32 luminance steps (to match the average luminance level of the 32 steps) in accordance with the luminance characteristics of the actual PDP, and 256 units for each luminance step. Data LSB, LSB + 1, LSB + 2, ... LSB + 253, LSB + 254, MSB are stored. The reason why 256 data is stored for each luminance step is that the 8-bit digital image data and a total of 256 data are stored in the mapping memory 160 from the data A / D converter 120 shown in FIG. One-to-one mapping to 256 data sets.

The storage unit 170 reads or writes data mapped to the mapping memory 160 according to the horizontal and vertical position selection signals.

The interface unit 180 outputs computer data in parallel by rearranging the data order so as to be suitable for receiving and displaying data from the storage unit 170 according to the horizontal and vertical position selection signals.

The address voltage generator 190 receives scan information and parallel data from the interface unit 180 to generate an address voltage to generate wall charges.

The sustain voltage generator 200 generates a sustain voltage, and the scan and sustain voltage generator 210 performs a scan and generates a sustain voltage.

The control timing generator 220 generates a time for addressing data to the interface unit 180 and the address voltage generator 190 according to the horizontal and vertical synchronization signals input from the signal input unit 100. A sustain time is generated in the sustain voltage generator 200, and a scan and sustain time is generated in the scan and sustain voltage generator 210.

In the panel 230, the address from the address voltage generator 190 is applied to the cells in which the sustain voltages from the sustain voltage generator 200 and the scan and sustain voltage generator 210 are applied to all cells. Voltage is applied to display the required information.

The operation of the present invention configured as described above will be described in detail with reference to FIGS. 3, 4, and 5 as follows.

In order to explain the operation of the data mapping apparatus of the present invention, 1) the average luminance level is 1 level and the digital image data is 0000 0000; and 2) the average luminance level is 15 level and the digital image data is 0100 1100. The average luminance level is 32 levels and the digital image data is 1111 to 1111. For example, as follows.

1) When the average luminance level is 1 level and the digital image data is 0000 0000, the image signal inputted to the signal input unit 100 (see FIG. 3) is the darkest, and thus the level A / D converter 140 (see FIG. 3). When the average luminance level output from S is 1 level, the address selector 150 selects an address (step 1) according to the average luminance level of the 1 level.

Accordingly, the mapping memory 160 (refer to FIG. 3) stores digital image data 0000 0000 (lowest bit: LSB) input from the data A / D converter 120 (refer to FIG. 3) as 0000 in the selected address (1 step). The LSB data is output by mapping to LSB data corresponding to 0000.

The LSB data is displayed through the storage unit 170 (see FIG. 3) and the interface unit 180 (see FIG. 3).

2) When the average luminance level is 15 levels and the digital image data is 0100 1100, when the average luminance level output from the level A / D converter 140 (see FIG. 3) is 15 levels, the address selector 150: 3 selects an address (step 15) according to the average luminance level of the 15 levels.

Accordingly, the mapping memory 160 (see FIG. 3) stores the digital image data 0100 1100 (LSB + 76 th bit) input from the data A / D converter 120 (see FIG. 3) within the selected address (15 step). The LSB + 76 th data is output by mapping the LSB + 76 th data corresponding to 0100 1100.

The LSB + 76 th data is displayed through the storage unit 170 (see FIG. 3) and the interface unit 180 (see FIG. 3).

3) When the average luminance level is 32 level and the digital image data is 1111 1111, the image signal input to the signal input unit 100 (see FIG. 3) is the brightest, and the level A / D converter 140 (see FIG. 3) When the output average luminance level is 32 levels (highest level), the address selector 150 (see FIG. 3) selects an address (step 32) corresponding to the average luminance level of the 32 levels.

Accordingly, the mapping memory 160 (refer to FIG. 3) stores the digital image data 1111 1111 (highest bit: MSB) input from the data A / D converter 120 (refer to FIG. 3) 1111 within the selected address (32 step). The MSB data is output by mapping to MSB data corresponding to 1111.

The MSB data is displayed via the storage unit 170 (see FIG. 3) and the interface unit 180 (see FIG. 3).

As described above, the MSB data value of the 32 steps of the maximum luminance level may be arbitrarily set according to how many stages the average luminance level is divided.

Example 1

Fig. 6 is a block diagram showing a data mapping apparatus in a television employing a PDP, which is an embodiment of the present invention. The data mapping apparatus in a television employing a PDP includes a tuner 102 and an intermediate frequency amplifier 104. And a signal input unit 100 composed of a video processor 106; Horizontal and vertical position selector 110; A data A / D converter 120; An average brightness level selector 130; A level A / D converter 140; An address selector 150; Mapping memory 160; Storage unit 170; An interface unit 180; An address voltage generator 190; Sustain voltage generator 200; Scan and sustain voltage generator 210; A control timing generator 220; And a panel unit 230.

First, the data A / D converter 120 converts an analog video signal into 8-bit digital image data, and the level A / D converter 140 converts an average luminance level signal of a DC level into 5-bit units. Suppose that you want to convert to digital average luminance level data. The signal input unit 100 receives a composite video signal, amplifies and processes the video signal, and then the horizontal sync signal (H.sync), the vertical sync signal (V.sync), the luminance signal (Y signal), and the analog video signal (RG B). signal).

The horizontal and vertical position selection unit 110 receives the horizontal synchronization signal (H.sync), selects a horizontal position (H.Position), outputs a horizontal position selection signal (H.Position signal), and outputs a vertical synchronization signal. After inputting (V.sync), select the vertical position (V.Position) and output the vertical position selection signal (V.Position signal).

The data A / D converter 120 receives horizontal and vertical synchronization signals from the signal input unit 100 to generate a frame discrimination signal, and an analog image signal (RG B signal) from the signal input unit 100. Is converted into 8-bit digital image data (RG B data) according to the horizontal and vertical position selection signals.

The average luminance level converter 130 converts the luminance signal to a DC level to obtain an average picture luminance level APL of the luminance signal received from the signal input unit 100.

The level A / D converter 140 converts the average brightness level signal of the DC level into digital average brightness level data in units of 5 bits according to the frame division signal from the data A / D converter 120.

The address selector 150 selects an address according to 5-bit digital average luminance level data received from the level A / D converter 140 and outputs the address selection signal.

The mapping memory 160 stores 32 luminance steps according to the luminance characteristics of the actual PDP, stores 256 data for each luminance step, and then determines the luminance step according to the address selection signal. The digital image data received from the / D converter 120 is mapped to one data in the determined brightness step, and the mapped data is output.

The storage unit 170 reads or writes data mapped to the mapping memory 160 according to the horizontal and vertical position selection signals.

The interface unit 180 outputs computer data in parallel by rearranging the data order so as to be suitable for receiving and displaying data from the storage unit 170 according to the horizontal and vertical position selection signals.

The address voltage generator 190 receives scan information and parallel data from the interface unit 180 to generate an address voltage to generate wall charges.

The sustain voltage generator 200 generates a sustain voltage, and the scan and sustain voltage generator 210 performs a scan and generates a sustain voltage.

The control timing generator 220 generates a time for addressing data to the interface unit 180 and the address voltage generator 190 according to the horizontal and vertical synchronization signals input from the signal input unit 100. A sustain time is generated in the sustain voltage generator 200, and a scan and sustain time is generated in the scan and sustain voltage generator 210.

In the panel 230, the address from the address voltage generator 190 is applied to the cells in which the sustain voltages from the sustain voltage generator 200 and the scan and sustain voltage generator 210 are applied to all cells. Voltage is applied to display the required information.

The embodiments described above are merely illustrative in all respects and should not be construed as limiting, and all modifications that fall within the true spirit and scope of the present invention shall fall within the claims of the present invention.

As described above, according to the present invention, in order to maximize the luminance characteristic of the input image signal to the luminance characteristic of the actual PDP, the image signal is normally colored by arbitrarily configuring a memory map composed of data corresponding to the luminance characteristic of the PDP. Displayed with over-luminance, and can be arbitrarily limited to the maximum brightness level (white level) in the memory map, that is, does not impose a burden on the PDP has the effect of increasing the life of the PDP.

Claims (3)

After receiving the composite video signal, amplifying and video processing, the horizontal and vertical synchronization signals, the luminance signal, and the analog and video signal input unit 100 for outputting the horizontal and vertical synchronization signals to receive the horizontal and vertical positions, Horizontal and vertical position selection unit 110 for outputting a horizontal and vertical position selection signal, and receives the horizontal and vertical synchronization signal to generate a frame discrimination signal, and receives the analog image signal from the signal input unit 100 In a system employing a PDP comprising a data A / D converter 120 for converting digital image data according to horizontal and vertical position selection signals, An average brightness level converting unit (130) for converting the brightness signal into a DC level to obtain an average brightness level of the brightness signal received from the signal input unit (100); A level A / D converter 140 for converting the average brightness level of the DC level into digital average brightness level data according to the frame division signal from the data A / D converter 120; An address selector 150 for selecting an address according to the digital average luminance level data received from the level A / D converter 140 and outputting an address selection signal; A mapping memory having a memory map composed of data corresponding to luminance characteristics of the PDP, and mapping digital image data received from the data A / D converter according to the address selection signal to data formed according to luminance characteristics of the PDP; 160); And And a storage unit 170 configured to read or write the newly mapped digital image data according to the horizontal and vertical position selection signals. The method of claim 1, wherein the address selector 150 is A first AND gate 152 which receives the horizontal position selection signal and the vertical position selection signal and performs an AND; A second AND gate 154 performing a logical product of a result of the AND product input from the first AND gate 154 and the digital luminance level data from the level A / D converter 140; And And a buffer (156) for buffering the logical AND result from the first AND gate (152) and outputting the result to the storage. The data mapping apparatus of claim 1, wherein the mapping memory (160) is implemented as a ROM.