KR19980029392A - System Clock Generation Circuit of Synchronous Semiconductor Memory Device - Google Patents

Abstract

A system clock generation circuit capable of preventing a malfunction that may occur in an output buffer of a synchronous semiconductor memory device is disclosed. The system clock generation circuit of the synchronous semiconductor memory device includes a second system clock generator for generating a second system clock which is a synchronization signal of a data multiplexer, and a first system clock generator for generating a first system clock, which is a synchronization signal of an output buffer. do. The first system clock generator generates the first system clock based on an external clock applied from the outside of the semiconductor memory device. The first system clock generator includes a PLL and a DLL circuit. The second system clock generator generates the second system clock based on the input of the first system clock. Therefore, when the rising edge and the falling edge of the first system clock change, the rising edge and the falling edge of the second system clock change accordingly. Thus, there is an advantage that the margin required for driving the output buffer of the data output from the data multiplexer is kept constant, thereby preventing malfunction.

Description

System Clock Generation Circuit of Synchronous Semiconductor Memory Device

The present invention relates to a system clock generation circuit, and more particularly, to a system clock generation circuit of a synchronous semiconductor memory device.

The synchronous semiconductor memory device performs an input / output operation of data in synchronization with a clock. The synchronous semiconductor memory device according to the related art is shown in FIG. 1. In FIG. 1, a synchronous semiconductor memory device includes a memory cell 101, a sense amplifier 102, a data multiplexer 103, an output buffer 104, a column buffer 105, a column predecoder 106, and a column decoder 107. ), A clock buffer 108, a first system clock generator 110, and a second system clock generator 109. The external clock applied from the outside of the semiconductor memory device is output after being buffered by the clock buffer 108. The second system clock generator 109 inputs an output CLOCK of the clock buffer 108 to generate a second system clock ICLK2, and the first system clock generator 110 inputs an external clock to generate a first clock. Generate the system clock ICLK1. The output CLOCK, the first system clock ICLK1, and the second system clock ICLK2 of the clock buffer 108 each exhibit a waveform as shown in FIG.

The column buffer 105, the column predecoder 106, and the column decoder 107 buffer and decode the column address in synchronization with the output CLOCK of the clock buffer 108 to activate the selected column select line. Thus, data read and write operations in the memory cell 101 are performed. Referring to FIG. 2, the data read operation is applied to the sense amplifier 102 via the IO line in the memory cell 101 in synchronization with the output CLOCK of the clock buffer 108 at the time point T0. The data DIO_0 amplified by the sense amplifier 102 is activated at the falling edge of the output CLOCK of the clock buffer 108 after the time point T1. The data multiplexer 103 selectively samples the outputs of the sense amplifier 102 at the rising edge of the second system clock ICLK2 and activates the output after a predetermined period of time. As can be seen in FIG. 2, the second system clock ICLK2 is generated by delaying the output CLOCK of the clock buffer 108 by a period d1. Thus, after the output DIO of the sense amplifier 102 is activated, there is a margin for α period until the data multiplexer 103 performs the sampling operation at the rising edge of the second system clock ICLK2, thereby operating stably. . After the output DO of the data multiplexer 103 is activated, the output buffer 104 inputs it at the rising edge of the first system clock ICLK1, and as shown in FIG. 2, there is a margin of β period. . Data input to the output buffer 104 is output to the outside of the semiconductor memory device through the data output pad.

In such a semiconductor memory device, the first system clock generator 110 generates a first system clock ICLK1 using a PLL and a DLL from an external clock, and the second system clock generator 109 uses a clock buffer ( This occurs by delaying the output (CLOCK) of 108) in the period d1. Accordingly, although the first system clock ICLK1 and the second system clock ICLK2 are generated based on an external clock, the first system clock ICLK1 is not affected by the delay caused by the clock buffer 108. On the other hand, the second system clock ICLK2 may be affected by the delay caused by the clock buffer 108, and thus, a generation time may change independently of each other. For example, as shown in FIG. 2, when the first system clock ICLK1 is generated as early as the tg period, the sampling operation of the output buffer 104 is performed before the output of the data multiplexer 103 is activated, thereby causing an error. There is a problem that the data is output. In other words, the margin of the? Period is lost, causing the output buffer 104 to malfunction. In particular, in order to speed up the operation of the semiconductor memory device, it is necessary to reduce the delay caused by the output buffer. To this end, a method of quickly generating the first system clock ICLK1 is generally performed. In such a case, the problems mentioned above appear, which is an obstacle to speeding up.

Accordingly, it is an object of the present invention to provide a system clock generation circuit of a synchronous semiconductor memory device capable of preventing malfunctions that may occur in an output buffer.

Another object of the present invention is to generate a system clock of a synchronous semiconductor memory device capable of preventing a malfunction of an output buffer by performing a level shift operation with a constant margin of a system clock driving a data multiplexer and a system clock driving an output buffer. To provide a circuit.

Another object of the present invention is to provide a system clock generation method capable of preventing a malfunction of an output buffer in a synchronous semiconductor memory device.

1 is a block diagram of a synchronous semiconductor memory device having a system clock generation circuit according to the prior art.

FIG. 2 is a timing diagram illustrating an operation of the synchronous semiconductor memory device shown in FIG. 1.

3 is a block diagram of a synchronous semiconductor memory device having a system clock generation circuit in accordance with the present invention.

FIG. 4 is a timing diagram illustrating an operation of the synchronous semiconductor memory device shown in FIG. 3.

* Explanation of symbols for the main parts of the drawings

101: memory cell 102: sense amplifier

103: data multiplexer 104: output buffer

105: column buffer 106: column predecoder

107: column decoder 108: clock buffer

109: second system clock generator 110: first system clock generator

In order to achieve these objects, the system clock generation circuit of the synchronous semiconductor memory device according to the present invention includes a first system that is a synchronization signal of an output buffer and a second system clock generator that generates a second system clock that is a synchronization signal of a data multiplexer. The first system clock generator generates a clock. The first system clock generator generates the first system clock based on an external clock applied from the outside of the semiconductor memory device. The first system clock generator includes a PLL and a DLL circuit. The second system clock generator generates the second system clock based on the input of the first system clock. Therefore, when the rising edge and the falling edge of the first system clock change, the rising edge and the falling edge of the second system clock change accordingly.

A system clock generation method of a synchronous semiconductor memory device according to the present invention includes a data multiplexer for selecting any one of data read from a memory cell and amplified by a sense amplifier, and a synchronous semiconductor memory including an output buffer for driving an output of the data multiplexer. CLAIMS What is claimed is: 1. A method of generating a system clock of a device, comprising: generating a first system clock based on an external clock applied externally of a semiconductor memory device; And inputting a first system clock to generate a second system clock. Here, the data multiplexer operates in synchronization with the second system clock and the output buffer operates in synchronization with the first system clock.

Next, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a synchronous semiconductor memory device having a system clock generation circuit according to the present invention, which includes a memory cell 101, a sense amplifier 102, a data multiplexer 103, an output buffer 104, and a column buffer ( 105, the column predecoder 106, the column decoder 107, the first system clock generator 110 and the second system clock generator 109. The first system clock generator 110 generates an first system clock ICLK1 by inputting an external clock. The first system clock generator 110 includes a PLL or a DLL circuit. Unlike the related art, the second system clock generator 109 inputs the first system clock ICLK1 and delays it for a predetermined period to generate the second system clock ICLK2. Accordingly, when the generation time of the first system clock ICLK1 is changed, the generation time of the second system clock ICLK2 is changed accordingly, and as shown in FIG. 4, a constant margin is maintained and the operation is stably performed. .

In FIG. 3, an external clock applied from the outside of the semiconductor memory device is buffered and output by the clock buffer 108, and the column buffer 105 buffers the column address applied from the outside in synchronization with the output CLOCK. . The column address is decoded by column predecoder 106 and column decoder 107 to activate the selected word line. The data IO output from the memory cell 101 is applied to the sense amplifier 102. The data multiplexer 103 samples the output of the sense amplifier 102 in synchronization with the second system clock ICLK2, and the output buffer 104 synchronizes the output of the data multiplexer 103 in synchronization with the first system clock ICLK1. Sample. In FIG. 4, DIO represents the output of the sense amplifier 102, DO represents the output of the data multiplexer 103, and DOUT represents the output of the output buffer 104. In FIG. 4, since the first system clock ICLK1 and the second system clock ICLK2 are interlocked with each other so that a level transition occurs, the rising edge of the second system clock becomes faster in the tg period, thereby outputting the data multiplexer 103. Even when activated as soon as this time, the rising edge of the subsequent first system clock ICLK1 is similarly accelerated by the tg period, thereby driving data without malfunction. Therefore, the β margin is always maintained and thus the output data DOUT is always valid, and no obstacle of speedup occurs.

The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the spirit of the present invention.

The system clock generation circuit of such a synchronous semiconductor memory device can prevent malfunction due to the output buffer even when the generation time of the system clock is changed to speed up, thereby increasing the reliability of the device, and stably. We can promote speedup.

Claims (4)

A synchronous semiconductor memory device comprising a data multiplexer for selecting any one of data read from a memory cell and amplified by a sense amplifier and an output buffer for driving an output of the data multiplexer, the external device being externally applied to the semiconductor memory device. A first system clock generator configured to input a clock to generate a first system clock; And a second system clock generator configured to input the first system clock to generate a second system clock, wherein the data multiplexer operates in synchronization with the second system clock and the output buffer is synchronized with the first system clock. And a system clock generation circuit of a synchronous semiconductor memory device. The system clock generator circuit of claim 1, wherein the first system clock generator is a PLL circuit. The system clock generation circuit of claim 1, wherein the first system clock generation unit comprises a DLL circuit. 13. A method of generating a system clock of a synchronous semiconductor memory device comprising a data multiplexer for selecting any one of data read from a memory cell and amplified by a sense amplifier and an output buffer for driving an output of the data multiplexer. Generating a first system clock based on an external clock applied externally of the device and inputting the first system clock to generate a second system clock, wherein the data multiplexer is coupled to the second system clock. Operating in synchronization with the output buffer in synchronization with the first system clock.