KR19980028713A - Register file - Google Patents

Abstract

The present invention relates to a register file. In particular, as the processing speed of a microprocessor increases, the design of a register file that operates at a high speed must be necessary. Therefore, a single read and a write operation can be simultaneously performed. It is designed to perform high speed operation by combining phase clock and dynamic logic circuit. To this end, the present invention receives the row addresses rA [4: 0] (rB [4: 0]) and read block blocks 201 for outputting the row select signal ARSEL BRBR to the memory cell 205. 202, a write decoder block 203 for receiving the write address rW [4: 0] and outputting a row select signal WRSEL to the memory cell 205, and a write signal W. The write driver 204 for outputting a bit signal WB (/ WB) to the memory cell 205 and the data carried on the bit line RB (/ RB) of the memory cell 205 are sensed. It consists of a sense amplifier block 206 which outputs externally.

Description

Register file

1 is a block diagram showing a register file of the present invention.

2 is a circuit diagram of a memory cell in FIG.

3 is a table showing the layout of transistors in the memory cell of FIG.

4 is a block diagram of a read decoder block in FIG.

5 is a circuit diagram of an address driving stage in FIG. 4;

6 is a circuit diagram of a decoder tree in FIG.

FIG. 7 is a circuit diagram of a row line selector in FIG.

8 is an exemplary view of a row line selector in FIG.

9 to 11 are operation timing diagrams of FIG.

FIG. 12 is a table showing the layout of transistors in FIG.

13 and 14 are circuit diagrams of the light driver in FIG.

15 and 16 are timing diagrams in FIGS. 13 and 14;

17 is a circuit diagram of a sense amplifier block in FIG.

FIG. 18 is a timing diagram in FIG. 17. FIG.

FIG. 19 is a table showing layout sizes of transistors in FIG. 17. FIG.

20 is an exemplary view showing a final layout of the present invention.

Explanation of symbols for main parts of the drawings

201 and 202: read decoder block 203: write decoder block

204: Light driver 205: Memory cell

206: sense amplifier block 210, 240, 270: dirtless driving unit

220, 250, 280: decoder tree 230, 260, 290: low line driver

The present invention relates to the design of a register file. In particular, a register file having two read ports and one write port is designed as a dynamic circuit having a 0.8 μm CMOS structure to minimize the area and to operate the register file at high speed. It is about.

In general, most of the VLSI design process requires the design of memory blocks that include on-board caches, register arrays, transition look-side buffers (TBLs), and directories for caches.

Dual register files often have fewer bits and have multiple I / O ports so that data can be written simultaneously and read through one or two bit lines.

Intel's i486 32-bit microprocessor, which is widely used today, operates at 50 / 66Hz clock, so a 100MHz register file would be sufficient.

The 32-bit register file from VLSI Technology's 0.8um CMOS data path library also has an operating speed of about 100 MHz.

However, as the processing speed of the microprocessor gradually increases, the design of a register file that operates at a high speed must be essential.

Accordingly, an object of the present invention is to provide a register file invented to perform a high speed operation by combining a single phase clock and a dynamic logic circuit to simultaneously perform two read and one write operations to satisfy this need. There is this.

1 is a block diagram of a register file according to the present invention. As shown in FIG. 1, row addresses rA [4: 0] and rB [4: 0] are respectively inputted to receive a row select signal ARSEL BRBR. The write decoder block 201 and 202 output to the memory cell 205 and the write decoder receiving the write address rW [4: 0] and outputting a row select signal WRSEL to the memory cell 205. A block 203, a write driver 205 for outputting a bit signal WB (/ WB) to the memory cell 205 with the write signal W as an input, and a bit line of the memory cell 205; A sense amplifier block 206 which senses the data contained in (RB) (/ RB) and outputs it to the outside.

As shown in FIG. 4, the read decoder block 201 receives an address rA4 to rA0 according to the clock CLK and outputs the addresses A4 to A0 (/ A4 to / A0). And a decoder tree 220 for outputting the selection signals AS0 to AS31 by performing a logical operation on the output address A4 to A0 (/ A4 to A0) of the address driver 210, and the decoder. A row line driver 230 is configured to hold the output signals AS0 to AS31 of the tree 220 according to the clock CLK to output the row select signals ARSEL0 to ARSEL31.

The address driver 210 receives the address rA according to the clock CLK and outputs the address AD (/ AD) to the decoder tree 220, respectively. Consists of.

As shown in FIG. 5, the address driving terminals 210-1 to 210-5 have the gate of the PMOS transistor M11 to which the voltage Vcc is applied to the source, and the NMOS transistor M13 to which the source is grounded. The clock CLK is applied to the gate of the NMOS transistor, an address rA is applied to the gate of the NMOS transistor M12 having a source connected to the drain of the NMOS transistor M13, and the MOS transistor M11 ( The drain of the M12 is connected in common, and its connection point is commonly connected to the gate of the PMOS transistor M14 to which the voltage Vcc is applied to the source and the gate of the NMOS transistor M16 to which the source is grounded. The clock CLK is applied to the gate of the NMOS transistor M15 having a source connected to the drain of M16, and the clock is applied to the gate of the PMOS transistor M17 and M19 to which a voltage Vcc is applied to the source. CLK is applied to drain the MOS transistors M14 and M15. The common terminal is connected to the output terminal of the inverter IN1 to which the connection point is connected, the source of which is connected to the gate of the PMOS transistor M18 connected to the drain of the PMOS transistor M17 and the input terminal of the inverter IN2, The output terminal of the inverter IN2 is connected to the gate of the PMOS transistor M20 whose source is connected to the drain of the PMOS transistor M19, so that the address AD at the source of the PMOS transistor M18 and M20 ( / AD) is configured separately.

As shown in FIG. 6, the decoder unit 220 has an NMOS at each address line so that the number of transistors connected to any address line is doubled with the number of transistors connected to the upper address line. The gates of the PMOS transistors to which the voltage Vcc is applied are respectively connected to the gates and the sources of the transistors, and the common connection point of the transistors connected to the upper address line Ai (/ Ai) is the lower address line Ai-1 ( / Ai-1) so that the source of the NMOS transistor connected to each of the NMOS transistors connected to the tree form a common tree, the source of the NMOS transistor connected to the highest address line is grounded, and the drain common point of the MOS transistor connected to the lowest address line. The select signal Si is outputted at each stage (where i = 1 to 4).

In the above description, the PMOS transistors and the NMOS transistors commonly connected to the address lines of the respective stages have the same size.

The row line driver 230 inputs the output signals AS0 to AS31 of the decoder tree 220, respectively, and outputs the row select signals ARSEL0 to ARSEL31, respectively. Consists of.

As illustrated in FIG. 7, the low signal output terminals 230-1 to 230-32 may output an output signal of the decoder tree 220 to a gate of the PMOS transistor M31 to which a voltage Vcc is applied to a source. S is connected, and the clock CLK is connected to the gate of the NMOS transistor M32 having the source grounded, and the drain connection point of the MOS transistors M31 and M32 is applied to the source. The clock CLK is connected to the gate of the NMOS transistor M35 in which the gate and the source of the MOS transistor M33 are grounded, and the drain of the NMOS transistor M35 is connected to the gate of the PMOS transistor M34. ), The drain of the PMOS transistor M33 and the source of the PMOS transistor M34 are commonly connected, and a connection point thereof is connected to an input terminal of the inverter IN3 to select a row as an output terminal of the inverter IN3. Each configured to output the signal (ARSEL) .

The read decoder block 202 receives the addresses rB4 to rB0 and outputs row selection signals BRSELS0 to BRSEL31 so that the address driver 240, the decoder tree 250, and the row are the same as the decoder block 201. The line driver 260 is configured.

The write decoder block 203 includes an address driver 270 for inputting a write address rW [4: 0], and a decoder tree 208 for decoding the output signal of the address driver 270 and outputting a selection signal. And a low line driver 290 which receives an output signal of the decoder tree 280 and outputs a row select signal WRSEL to the memory cell 205. A detailed circuit includes a read decoder block 201. same.

As shown in FIG. 14, the light driving unit 204 includes two light driving stages 204-1 and 204-2.

As shown in FIG. 13, the write driving stages 204-1 and 204-2 have an NMOS transistor in which the gate and the source of the PMOS transistor M41 to which the voltage Vcc is applied are grounded. The clock CLK is applied to the gate of M43, the write data W is applied to the gate of the PMOS transistor M42 having a source connected to the drain of the PMOS transistor M41, and the MOS transistor M42. The drain of M43 is connected in common, and its connection point is commonly connected to the gate of the PMOS transistor M44 to which the voltage Vcc is applied to the source and the gate of the NMOS transistor M46 to which the source is grounded. The clock CLK is applied to the gate of the PMOS transistor M45 having a source connected to the drain of the MOS transistor M44, and the clock CLK is applied to the gate of the NMOS transistor 49 having the source grounded. The drains of the MOS transistors M45 and M46 are connected in common. The output terminal of the inverter IN4 to which the connection point is connected is commonly connected to the gate of the NMOS transistor M47 whose source is connected to the drain of the NMOS transistor M49 and the input terminal of the inverter IN5. The output terminal of IN5 is connected to the gate of the NMOS transistor M48 whose source is connected to the drain of the NMOS transistor M49, and the drain of the NMOS transistors M47 and M48 is input to the input terminal of the memory cell 205. Each is configured to be connected to (WB) (/ WB).

As shown in FIG. 2, the memory cell 205 has a row select signal WRSELL at the gate of the NMOS transistors M3 and M7 to which the write bit signal WB (/ WB) is respectively connected to the drain. Is applied, and the source of the NMOS transistors M4 and M8 to which the row select signal ARSEL (BRSEL) is applied to the gate is connected to the output terminal RB (/ RB), respectively. The drains of the applied PMOS transistors M1 and M5 are connected to the drains of the NMOS transistors M2 and M6 having a grounded source, respectively, and the connection points of the MOS transistors M1 and M2 are connected to the MOS transistors M5. M6 is connected to the gate of the MOS transistor M7, the source of the MOS transistor M7, and the drain of the MOS transistor M8, and the connection point of the MOS transistors M5 and M6 is connected to the gate of the MOS transistor M1 and M2. And the source of the MOS transistor M3 and the drain of the MOS transistor M4.

As illustrated in FIG. 17, the sense amplifier block 206 includes a first sense amplifier 206-1 for sensing data carried on the bit line RB of the memory cell 205, and the memory cell 205. And a second sense amplifier 206-2 which senses data carried on the bit line / RB.

The first sense amplifier 206-1 connects the output RB of the memory cell 205 to the gate of the PMOS transistor M51 to which the voltage Vcc is applied to a source, and the NMOS transistor of which the source is grounded. A clock (/ CLK) is applied to the gate of M52 to connect the drain connection point of the MOS transistors M51 and M52 to the gate of the NMOS transistor M54 whose source is grounded, and a voltage Vcc is applied to the source. A gate of the PMOS transistor M55 to which a clock CLK is applied to the gate of the applied PMOS transistor M35, and a drain connection point of the MOS transistors M35 and M54 is applied to a source; A source is commonly connected to the gate of the grounded NMOS transistor M57, a clock CLK is applied to the gate of the NMOS transistor M56 having a source connected to the drain of the MOS transistor M57, and the MOS transistor Inverter IN6 with connection point of (M55) (M56) connected to input terminal The data (AOR) is output to the output terminal of.

The second sense amplifier 206-2 is an MOS transistor M61 to M67 and an inverter IN7 configured in the same manner as the first sense amplifier 206-1 and connected to an output terminal of the inverter IN7. Configure the data (BOR) to be output at (IN8).

Referring to the operation and effect of the present invention configured in this way in detail as follows.

The present invention will be described taking only one cell as an example.

First, during the write operation of data, the write and decoder block 203 decodes the write decoder 280 when the write address rW [4: 0] is inputted by the address driver 270 and the decoded signal is selected. It is input to the driver 290. Accordingly, the selection signal driver 290 outputs the selection signal WRSEL to the memory cell 205 to be in the write enable state.

Thereafter, the write driving stage 204 receives the write data W as an input and outputs the bit data WBIT (/ WBIT) to the memory cell 205.

Accordingly, the memory cell 205 stores the output data BIT (/ BIT) from the write driving stage 204.

On the other hand, when reading the stored data as described above, when the read decoder 201 inputs the read address rA [4: 0] to the address driver 210, the decoder tree 220 selects the signals AS0 to AS31. ) Will be generated.

In this case, the row line driver 230 receiving the selection signals AS0 to AS31 of the decoder tree 220 outputs the row selection signals ARSELO to ARSEL31 to the memory cells 205 to be in the write enable state.

Accordingly, the sense amplifier block 206 senses the stored data AOR of the memory cell 205 and outputs it to the outside.

Also, when the read decoder 202 receives the read address rB [4: 0], the row select signals BRSEL0 to BRSEL31 are sequentially passed through the address driver 240, the decoder tree 250, and the row line driver 260. Is output to the memory cell 205.

Accordingly, the sense amplifier block 206 senses the stored data BOR of the memory cell 205 and outputs it to the outside.

The present invention for performing the above operation will be described for each block as follows.

The overall layout size, shape and performance of the present invention is determined by the structure of the memory cell 205 consisting of 32 rows x 32 columns.

The memory cell 205 of the present invention has two read ports and one write port.

That is, when the write signal WRSEL becomes high during the write operation, the memory cell 205 turns on the NMOS transistor 3 (M7) so that the bit data WB (/ WB) becomes the MOS transistors M5 and M6 ( The data storage operation is performed by being applied to M1 and M2. When the row select signal ARSEL BRSEL becomes high during the read operation, the NMOS transistor M8 and M4 are turned on to turn on the bit line BL. The stored data is output to the outside by detecting the data loaded on the / BL in the sense amplifier block 206.

The layout sizes of the transistors M1 to M8 constituting the memory cell 205 in this operation are shown in the table of FIG.

In addition, the bit cell of the memory cell 205 may be configured in the form of a static cross coupled inverter with four transistors.

In the present invention, the read decoder blocks 201 and 202 and the write decoder block 203 exist as blocks for enabling the bit lines B (/ B) of the memory cells 205 for write and read operations. , All of which are identical.

Accordingly, the read decoder block 201 will be described below with reference to FIGS. 4 through 11.

The address driver 210 to which the clock CLK as shown in FIG. 9A is input includes five address drivers 210-1 to 210-5, and the address drivers 210-1 to 210-. 5) Data rA0 to rA4 are respectively inputted to the rising edge of the clock CLK as shown in FIG. 10, and the address terminals A4 to A0 (/ A4 to A0) are discharged. It becomes a state.

In this case, the clock CLK is 250 MHz.

That is, the address driving terminal 210-1 has the NMOS transistor M12 turned off and the PMOS transistor M11 turned off when the clock CLK immediately before the address rA0 transitions high. In the turned-on state, the terminal ADDR is turned high, and the PMOS transistor M14 and the NMOS transistor M15 are turned off by the high signal ADDR and the clock clock CLK turned high to turn off the terminal (/ ADDR). ) Goes low.

At this time, since the low signal of the terminal / ADDR is inverted and turned high at the inverter IN1, the PMOS transistor M18 is turned off and the high signal of the inverter IN1 is turned low through the inverter IN2. The MOS transistor M20 is turned on.

Accordingly, the PMOS transistor M17 and M19 are turned on by the clock CLK that is low, but the terminal A0 is low due to the turn-off of the PMOS transistor M18 and the PMOS transistor M20 is turned on. The terminal / A0 is high by turning on.

Subsequently, when data rA0 is input high on the rising edge of the clock CLK, the address driving stage 201-1 turns all of the NMOS transistors M12 and M13 on, so that the terminal ADDR becomes low. The PMOS transistor M14 is turned on by the low signal of the terminal ADDR to make the terminal / ADDR high.

At this time, all of the PMOS transistors M17 and M19 are turned off by the high clock CLK, and the high signal of the terminal / ADDR sequentially passes through the inverters IN1 and IN2 to the PMOS transistor M18. ) Is turned on and the PMOS transistor M13 is turned off.

As a result, the terminals A0 (/ A0) are both low.

After that, when the clock CLK becomes low while the data rA0 is high, the PMOS transistor M11 is turned on to turn the terminal ADDR high and the terminal ADDR becomes high. The PIM transistor M14 and the NMOS transistor M15 are turned off by the high signal and the high clock CLK, so that the terminal / ADDR remains high.

At this time, since the high signal of the terminal / ADDR is sequentially inverted in the inverter IN1 (IN2), the PMOS transistor M18 maintains the turn-on state and the PMOS transistor M20 maintains the turn-off state. .

Accordingly, since the PMOS transistors M17 and M19 are turned on by the clock CLK which is low, the terminal A0 is made high and the terminal / A0 is kept low.

After that, when the clock CLK becomes high and the data rA0 becomes low, the PMOS transistor M1 and the NMOS transistor M12 are turned off so that the address driving terminal 201-1 turns off the terminal ADDR. Is maintained in a high state, and both the NMOS transistors M15 and M16 are turned on by the high signal of the terminal ADDR and the clock CLK that is high, so that the terminal / ADDR becomes low.

At this time, the PMOS transistor M18 is turned off and the PMOS transistor M20 is turned on by the low signal of the terminal / ADDR being sequentially inverted in the inverter IN1 (IN2).

Accordingly, since the PMOS transistors M17 and M19 are both turned off by the high clock CLK, the terminals A0 and / A0 are all turned low.

That is, each address driver 210-1-210-5 of the address driver 210 transmits a signal to the node AD (/ AD) before the falling edge of the clock CLK, and In the low phase, the address lines A0 (/ A0) are differentially precharged according to whether the transistors M18 and M20 are turned on or off.

This operation is performed in the same manner as the timing diagram of FIG.

The address driving stages 210-2 to 210-5 also perform the same operations as the address driving stage 210-1 to address (A1, / A1) (A2, / A2) (A3, / A3) (A4). , / A4) to the decoder tree 220, respectively.

Accordingly, while the clock CLK is low, the output signals A0 to A4 (/ A0 to / A4) of the address driver 210 maintain the state, and the decoder tree 220 as shown in FIG. The address line selected by the signals A0 to A4 (/ A0 to / A4) is precharged high to form a pass tree by turning on the NMOS transistor connected to the address line.

For example, when the address lines A0 to A4 are discharged low and the address lines / A0 to A4 are precharged high, a pass tree as shown in FIG. 8 is formed so that the ground potential is low. Is input to the corresponding low line drive stage.

At this time, the decoder tree 220 outputs only the selection signal AS0 low and outputs the remaining signals AS1 to AS31 high.

Here, the decoder tree 220 is manufactured such that the NMOS transistor forming the pass tree forms a path from the low phase to the ground side at a high speed for the high speed operation, so that the size of the transistor is doubled toward the ground side.

Accordingly, when the selection signal AS0 is input low, the PMOS transistor M31 of the row line driver 230 is turned on so that the terminal RSEL0 is turned high and the terminal RSEL0 of the row line driver 230 is turned on. Since the NMOS transistor M35 is turned on by the high signal and the NMOS transistor M34 is turned on by the clock CLK which is low, a low signal is applied to the inverter IN3.

Therefore, the row select signal ARSEL0 that is high through the inverter IN3 is input to the memory cell 250.

If the selection signal AS0 that is high is input to the row line driver 230, one of the 32 row line driver stages 230-1 to 230-32 is connected to the gate of the PMOS transistor M33. Since the connected terminal RSEL is always kept low and the voltage Vcc is applied to the inverter IN3 through the PMOS transistor M33, the row select signal ARSEL0 output from the inverter IN3 is low. Will be maintained.

Here, the 32 row line driving stages 230-1 to 230-32 constituting the row line driving unit 230 all perform the same operation when a low in signal is input.

For example, when the data rA0 to rA4 as shown in FIG. 10 is input to the address driver 210, the decoder tree 220 sequentially forms a pass path so that the row line driver 230 may perform the eleventh degree. Similarly, the row select signals RSEL0 to RSEL31 are sequentially output to the memory cells 205.

In this case, the read decoder block 201 must drive the low line of the memory cell 250 before the falling edge of the clock CLK of 250 MHz. When the gate signal AD (/ AD) of the MOS transistors M18 and M20 is low, the address line A // is differentially input to the high cell 205.

If the selection signal AS0 that is high is input to the row line driver 230, one of the 32 row line driver terminals 230-1 to 230-32 is connected to the gate of the PMOS transistor M33. Since the connected terminal RSEL is always kept low and the voltage Vcc is applied to the inverter IN3 through the PMOS transistor M33, the row select signal ARSELO output from the inverter IN3 is low. Will be maintained.

Here, the 32 row line driving stages 230-1 to 230-32 constituting the row line driving unit 230 all perform the same operation when a low in signal is input.

For example, when the data rA0 to rA4 as shown in FIG. 10 is input to the address driver 210, the decoder tree 220 sequentially forms a pass path so that the row line driver 230 may perform the eleventh degree. Similarly, the row select signals RSEL0 to RSEL31 are sequentially output to the memory cells 205.

The read decoder block 201 needs to drive a low line of the memory cell 205 before the falling edge of the clock CLK of 250 MHz. The clock CLK is in the low phase and the clock phase as shown in the timing diagram of FIG. When the gate signal AD (/ AD) of the MOS transistors M18 and M20 is low, the address line A (/ A) is differentially precharged to a high level so that the address line A (/ A) When about 1.5 ns has elapsed after is selected, the row select signal ARSEL0 is output from the row line driver 230.

That is, since the low select signals ARSEL0 and ARSEL1 are output before the rising edge of the high phase of the clock CLK before the next input signal is transmitted, it can be seen that the clock CLK of 250 MHz normally operates. .

The layout sizes of the transistors M11 to M37 constituting the read decoder block 201 for performing such an operation are the same as in the table of FIG.

Also, the read decoder block 202 and the write decoder block 203 may operate in the same manner as the read decoder block 201 performing the above process.

On the other hand, when the memory cell 205 is in the write enable state by the write decoder block 203 during the write operation, the write driver 204 which receives the write data W as an input and stores the write data W in the memory cell 205. The operation is described as follows.

As shown in FIG. 14, the write driver 204 includes two write driving stages 204-1 and 204-2, and when the clock CLK and the write data W0 and W1 are inputted. After the clock CLK becomes the rising edge, the data driving stages 204-1 and 204-2 to which the write data W0 and W1 are respectively inputted respectively write the write data WB (/ WB) to the memory cells. And outputs to 205.

That is, when the clock CLK immediately before the data W0 is input to the high state, the write driving terminal 204-1 turns the PMOS transistor M42 on but the PMOS transistor M41 turns on. In the off state, the NMOS transistor M43 is turned on and the terminal V1 is turned low. The PMOS transistor M44 and the NMOS transistor are turned on by the low signal V1 and the high clock CLK. M46 is turned on and the PMOS transistor M45 is turned off so that the terminal V2 is turned low.

At this time, the low signal of the terminal V2 is inverted at the inverter IN4 and becomes high, and the high signal is turned low through the inverter IN5.

Accordingly, the NMOS transistor M49 is turned on by the high clock CLK, so the NMOS transistor M47 is turned on, the NMOS transistor M48 is turned off, and the write data WB0 is turned low and the write data WB0 is turned off. The data / WB0 goes high.

After that, when the data W0 is input high, the write driving terminal 204-1 turns off the PMOS transistors M41 and M42 and the NMOS transistor M43 is turned on so that the terminal V1 is turned on. The PMOS transistor M44 and the NMOS transistor M46 are turned on and the PMOS transistor M45 is turned off by the low signal V1 and the clock CLK that is high. Terminal V2 remains low.

At this time, the low signal of the terminal V2 is inverted at the inverter IN4 and becomes high, and the high signal is turned low through the inverter IN5.

Accordingly, since the NMOS transistor M49 is turned on by the clock CLK which is high, the NMOS transistor M47 is turned on and the NMOS transistor M48 is turned off so that the write data WBO is maintained. Remains low and write data (/ WBO) remains high.

Subsequently, when the clock goes low while the data WO is high, the write driving terminal 204-1 may turn on the PMOS transistor M11, but the PMOS transistor M42 is turned off. Is kept low and the PMOS transistor M44 and M45 are turned on and the NMOS transistor M46 is turned off by the clock signal CLK which is low with the low signal V1, so that the terminal V2 is turned high. do.

At this time, the high signal of the terminal V2 is inverted at the inverter IN4 to be low, and this low signal V3 is inverted at the inverter IN5 to be high, and the NMOS transistor M49 is low at the clock CLK. ) To turn off.

Therefore, the NMOS transistors M47 and M48 are both turned off and the write data WBO (/ WBO) are all high.

Thereafter, when the clock CLK becomes high while the data W0 is high, the PMOS transistor M41 and M42 are turned off and the NMOS transistor M43 is turned on in the write driving stage 204-1. The terminal V1 remains low and the PMOS transistor M44 is turned on by the low signal V1 and the clock CLK which is high, but the PMOS transistor M45 and the NMOS transistor M46 are turned on. OFF, the terminal V2 remains high.

At this time, the high signal V3 is inverted low in the inverter IN4 and the low signal V4 is inverted high in the inverter IN5.

Accordingly, since the NMOS transistor M49 is turned on by the clock CLK that is high, the NMOS transistor M47 is turned off by the low signal V4 and the NMOS transistor M49 is turned on by the high signal V5. M48 is turned on so that the write data WB0 remains high and the write data / WB0 goes low.

After that, when the data WO goes low and the predetermined time has elapsed and the clock CLK goes low, the PMOS transistor M41 and M42 are turned on and the NMOS transistor M43 is turned on. ) Is turned off so that the terminal V1 becomes high and the PMOS transistor M44 is turned off and the NMOS transistor M46 is turned on by the high signal V1 and the clock CLK which is low, and the terminal V2 is turned on. ) Goes low.

At this time, the clock CLK becomes low and the NMOS transistor M49 is turned off. Accordingly, the low signal V2 is inverted high at the inverter IN4 and the high signal V4 is inverted low at the inverter IN5, but the NMOS transistor M49 is turned off so that the write data WB0 ( / WB0) goes high.

The operation of the write driving stage 204-1 as described above is performed in the same manner as the timings of FIGS. 15 and 16.

In addition, as the clock CLK and the data W1 are input, the write driver 204-2 also performs the same process as the operation of the write driver 204-2.

On the other hand, the data stored in the memory cell 205 is sensed by the sense amplifier block 206 and output to the outside.

The operation of the sense amplifier block 206 will be described with reference to the timing diagram of FIG.

As the clock CLK is input as shown in FIG. 18A, the bit terminal BL0 (/ BL0) of the memory cell 205 has a waveform signal as shown in FIG. 18C. In (RB0) (/ RB0), a signal having a waveform as shown in FIG. 18 (e) (bar) appears.

In other words, when the clock CLK is input from low to high, the sense amplifier 206-1 turns the NMOS transistor M52 from the turn-on state to the turn-off state, and the level of the terminal RB0 becomes the high level, thereby making the PMOS transistor. Since the M51 is turned off from the turned on state, the level of the terminal AOS1 remains low, the PMOS transistor M53 is turned off from the turned on state, and the NMOS transistor M54 is turned off. Since the level of the terminal AOS2 remains high.

At this time, the NMOS transistor M57 is turned on and the NMOS transistor M46 is turned on from the turned off state, so the level of the terminal AOS3 is turned low.

Thereafter, when the level of the terminal RB0 gradually decreases and becomes smaller than the predetermined level while the clock CLK is high, the PMOS transistor M51 is turned on so that the level of the terminal AOS1 becomes high and this high signal ( The NMOS transistor M54 is turned on by the AOS1 so that the level of the terminal AOS2 goes low.

At this time, the PMOS transistor M55 is turned on and the NMOS transistor M57 is turned off so that the level of the terminal AOS3 becomes high.

Thereafter, when the clock CLK goes from high to low, the NMOS transistor M52 is turned on, and the level of the terminal AOS1 is turned low. The NMOS transistor M54 is turned off by this low signal AOS1. The PMOS transistor M53 is turned on by the clock CLK which is low, and the level of the terminal AOS2 becomes high.

At this time, the PMOS transistor M56 is turned off by the high signal of the terminal AOS2 and the NMOS transistor M57 is turned on and the NMOS transistor M56 is turned off by the low clock CLK. The level of AOS3) will remain high.

The above operation is repeatedly performed as the clock CLK is input as shown in FIG.

Therefore, if the terminal AOS3 goes low or high when the clock CLK is input as shown in FIG. 18A, after a predetermined time elapses, the output terminal AOR of the inverter IN6 becomes the 18th order (difference). As shown in the figure, it becomes high or low.

Since the sense amplifier 206-2 is inputted from the low state to the high state as shown in FIG. 18 (bar), the terminal BOS1 transitions from the high state to the low state so that the low state is maintained. do.

At this time, since the NMOS transistor M64 is turned off from the turned-on state, the PMOS transistor M63 turns on and off in accordance with the level of the clock CLK, but the level of the terminal BO2 is high in the low state. State to maintain its high state.

Accordingly, the PMOS transistor M65 is turned off at the turn-on, while the NMOS transistor M67 is turned on at the turn-off state, and the NMOS transistor M66 is turned on according to the level of the clock CLK. By repeatedly turning off, the terminal BOS3 goes low from the high state to maintain the low state.

Accordingly, the signal of the terminal BO3 is inverted sequentially through the inverters IN7 and IN8, so that the level of the terminal BOR is temporarily high as shown in FIG. .

That is, when reading data stored in the bit cell of the memory cell 205, the word line is selected by the write decoder block 203 and the row select signals ARSEL0 and BRSEL0 are respectively high by the read decoder block 201. FIG. The NMOS transistors M7 and M3 are turned on because the row line '0' is selected.

At this time, when the clock CLK is low, data loaded on the bit line BL0 (/ BL0) charged high (= 5V) is sensed by the sense amplifiers 206-1 and 206-2, respectively, and amplified and latched. It is output to the outside through the output terminal AOR (BOR).

As described above, the operation of the sense amplifier block 206 is performed in the same manner as the timing diagram of FIG.

That is, for example, when the bit line BL0 is initialized to "0" and the bit line / BL0 is set to "1", when the size of the NMOS transistors M3 and M7 is 321, the pull-down speed of the terminal RB0 is increased. It can be seen that when the clock CLK phase is high, the pull-down voltage becomes 3V, which is improved from 3.5V.

Accordingly, it can be seen that the delay time between the output terminal and the pad output terminal of the sense amplifier block 206 is improved to 2ns and 3ns, respectively, as shown in FIG.

The layout sizes of the transistors M51 to M57 (M61 to M67) constituting the sense amplifier block 206 in the above operation are as shown in FIG.

Meanwhile, when the precharge device is replaced with an NMOS transistor instead of the PMOS transistor, the bit line is charged only by 'Vdd-Vtn', thereby improving the access speed of the memory cell 205.

Thereafter, as shown in FIG. 20, the core cells are manufactured by connecting the blocks 201 to 206 which perform the above operation to each other.

As described in detail above, the present invention has an effect that can be applied to a high speed chip by optimizing the size of transistors constituting each block to improve operating characteristics at high speed.

Claims (15)

First and second read decoder blocks receiving row addresses rB [4: 0] and rA [4: 0], respectively, and outputting row select signals ARSEL BRBR to memory cells; a write decoder block that receives rW [4: 0]) and outputs a row select signal WRSEL to the memory cell, and a write signal W as an input to receive a bit signal WB (/ WB) from the memory cell; And a sense driver block configured to output data to a write driver for outputting the data to a bit line (RB) (/ RB) of the memory cell and outputting the data to the outside. The address read unit of claim 1, wherein the first read decoder block receives the addresses rA4 to rA0 according to the clock CLK, and outputs the addresses A4 to A0 (/ A4 to A0). A decoder tree for outputting the selection signals AS0 to AS31 by performing a logical operation on the output addresses A4 to A0 (/ A4 to / A0) of the clock signal, and the clock signals CLK to the output signals AS0 to AS31 of the decoder tree. And a row line driver configured to hold in accordance with the output and output row select signals ARSEL0 to ARSEL31. The address driver of claim 2, wherein the address driver comprises first to fifth address driving stages that receive the address rA according to the clock CLK and output the address AD (/ AD) to the decoder tree, respectively. Register file. 4. The clock CLK of claim 3, wherein the first to fifth address driving stages include a gate of the PMOS transistor M11 to which the voltage Vcc is applied to the source, and a clock CLK to the gate of the NMOS transistor M13 to which the source is grounded. Is applied to the gate of the NMOS transistor M12 having a source connected to the drain of the NMOS transistor M13, and the drains of the MOS transistors M11 and M12 are commonly connected to each other. The connection point is commonly connected to the gate of the PMOS transistor M14 to which the voltage Vcc is applied to the source and the gate of the NMOS transistor M16 to which the source is grounded, and the source is connected to the drain of the NMOS transistor M16. The clock CLK is applied to the gate of the connected NMOS transistor M15, the clock CLK is applied to the gate of the PMOS transistor M17 and M19 to which the voltage Vcc is applied to the source, and the MOS is applied. The drains of the transistors M14 and M15 are connected in common and The output terminal of the inverter IN1 to which the connection point is connected is commonly connected to the gate of the PMOS transistor M18 connected to the drain of the PMOS transistor M17 and the input terminal of the inverter IN2, and the inverter IN2 is connected. The output terminal of the PMOS transistor M20 is connected to the gate of the PMOS transistor M20 whose source is connected to the drain of the PMOS transistor M19, and the address AD (/ AD) is output from the source of the PMOS transistor M18. Register files characterized in that each configured as possible 3. The decoder tree of claim 2, wherein the decoder tree has a voltage Vcc at the gate and the source of the NMOS transistor at the address line of each stage such that the number of transistors connected to any address line is doubled with the number of transistors connected to the upper address line. Are connected to the gates of the PMOS transistors to which the PMOS transistors are applied, and the common connection point of the transistors connected to the upper address line Ai (/ Ai) is connected to the lower address line Ai-1 (/ Ai-1). The source of the NMOS transistor connected to the highest address line is grounded and the select signal Si is output at the drain common point of the MOS transistor connected to the lowest address line. A register file characterized in that it is configured so that i = 1 to 4 6. The register file according to claim 5, wherein the PMOS transistors and NMOS transistors commonly connected to the address lines of each stage are configured to have the same size. The low line driver of claim 2, wherein the row line driver comprises first to thirty-second row signal output stages for outputting the row select signals ARSEL0 to ARSEL31, respectively, using the output signals AS0 to AS31 of the decoder tree. Register file. 8. The output signal S of the decoder tree 220 is connected to a gate of a PMOS transistor M31 to which a voltage Vcc is applied to a source. The clock CLK is connected to the gate of the grounded NMOS transistor M32, and the drain connection point of the MOS transistors M31 and M32 is applied to the gate of the PMOS transistor M33 to which a voltage Vcc is applied. A clock CLK is connected to a gate of a PMOS transistor M34 having a source connected to a gate of the NMOS transistor M35 having a ground connected to the drain thereof, and a drain connected to a drain of the NMOS transistor M35. The drain of the transistor M33 and the source of the PMOS transistor M34 are commonly connected, and the connection point thereof is connected to the input terminal of the inverter IN3 so that the row select signal ARSEL is output from the inverter IN3. Characteristic Regis File. 2. The register file according to claim 1, wherein the second read decoder block is configured in the same way as the first read decoder block to output the row select signals BRSEL0 to BRSEL31 as inputs of the addresses rB4 to rB0. The write decoder block according to claim 1, wherein the write decoder block comprises: an address driver for inputting the write address (rW [4: 0]), a decoder tree for decoding the output signal of the address driver and outputting a selection signal, And a row line driver configured to receive an output signal and output a row select signal (WRSEL) to a memory cell, the same as a first read decoder block. 2. The first and second write driving devices of claim 1, wherein the write driver outputs the bit signals WB (/ WB) to the memory cells using the data W0 and W1 as inputs according to the clock CLK. A register file comprising a stage. 12. The clock CLK of claim 11, wherein the first and second write driving stages include a gate of the PMOS transistor M41 to which the voltage Vcc is applied to the source, and a clock CLK to the gate of the NMOS transistor M43 to which the source is grounded. Is applied, the write data W is applied to the gate of the PMOS transistor M42 having a source connected to the drain of the PMOS transistor M41, and the drains of the MOS transistors M42 and M43 are commonly connected. The connection point is commonly connected to the gate of the PMOS transistor M44 to which the voltage Vcc is applied to the source and the gate of the NMOS transistor M46 to which the source is grounded, and the source is connected to the drain of the PMOS transistor M44. Clock CLK is applied to the gate of the PMOS transistor M45 to which the PMOS transistor M45 is connected, and the clock CLK is applied to the gate of the NMOS transistor M49 to which the source is grounded, and the MOS transistors M5 and M6 are applied. Drains are connected in common The output terminal of the connected inverter IN4 is commonly connected to the gate of the NMOS transistor M47 connected to the drain of the NMOS transistor M49 and the input terminal of the inverter IN5, and the output terminal of the inverter IN5 is connected. A source is connected to the gate of the NMOS transistor M48 connected to the drain of the NMOS transistor M49, and the drain of the NMOS transistors M47 and M48 is input to the input terminal WB of the memory cell 205 (/). A register file, each configured to be connected to WB). The register file according to claim 1, wherein the sense amplifier block comprises first and second sense amplifiers which respectively sense data output on a bit line (RB) (/ RB) of a memory cell and output them to the outside. 15. The MMOS transistor of claim 13, wherein the first sense amplifier connects an output RB of the memory cell 205 to a gate of a PMOS transistor M51 to which a voltage Vcc is applied to a source, and the source is grounded. A clock (/ CLK) is applied to the gate of M52 to connect the drain connection point of the MOS transistors M51 and M52 to the gate of the NMOS transistor M54 whose source is grounded, and a voltage Vcc is applied to the source. The gate of the PMOS transistor M55 to which the clock CLK is applied to the gate of the applied PMOS transistor M53, and the drain connection point of the MOS transistors M53 and M54 is applied to the source. A source is commonly connected to the gate of the grounded NMOS transistor M57, a clock CLK is applied to the gate of the NMOS transistor M56 having a source connected to the drain of the MOS transistor M57, and the MOS transistor The connection point of (M55) (M56) is connected to the input terminal. Emitter register file, characterized in that the output stage is configured with the data (AOR) of (IN6) to output. 15. The inverter of claim 14, wherein the second sense amplifier is configured in the same manner as the first sense amplifier 206-1 by the MOS transistors M61 to M67 and the inverter IN7, and is connected to an output terminal of the inverter IN7. A register file characterized by being configured to output data (BOR) at (IN8).