KR19980027498A - Switch for Shared FIFO Memory - Google Patents

Abstract

The present invention relates to a switch for shared first-in first-out (FIFO) memory, and more particularly to an asynchronous transfer mode (ATM) cell input from multiple ports. It is about a switch to route the data in order to store the data in a shared FIFO memory.

The present invention provides a routing bit for receiving an address that is an output of a fetch and adder address generator, a routing bit for switching corresponding data, and a strobe signal for determining whether the data is stored in a shared FIFO memory. A routing control unit for generating a; And a data switching unit for switching the corresponding data using the routing bit.

Description

Switch for Shared FIFO Memory

The present invention relates to a switch for shared first-in first-out (FIFO) memory, and more particularly to an asynchronous transfer mode (ATM) cell input from multiple ports. It is about a switch to route the data in order to store the data in a shared FIFO memory.

Broadband intergrated services digital network (BISDN) has emerged to implement all existing communication networks into one integrated single network to satisfy various information needs of humans and society.

The ATM method has emerged as a technical solution for implementing such a BISDN.

The ATM method converts low-speed audio data, high-speed image and video data into ATM cells of the same size, and then communicates them as unit packets.

In a structure in which FIFOs are provided to each existing output port so that each output port can use only the FIFO, an inefficiency of using FIFO is caused when a burst occurs in an ATM cell input to a specific port. To improve this, a shared FIFO structure has been proposed.

In order to implement such a shared FIFO structure, an address generator for generating a recursive recursive address as large as a switch size is required for ATM cells input to each port. For this purpose, a conventional fetch and adder recursive recursive address generator is required. (Hereinafter referred to as address generator) is used.

The present invention performs a routing function of determining the corresponding data by using the sequential addresses generated by the shared FIFO circular repetitive address generator, controlling whether data is stored in the shared memory, and switching and storing the data in the shared memory. The purpose is to provide a switch.

1 is an overall configuration diagram according to an embodiment of the present invention.

Figure 2 is a detailed view of a 2x2 unit address switch.

3 is a detailed view of the routing bit latch circuit.

4 is a detailed view of a 2 × 2 unit data switch.

FIG. 5 is a timing diagram illustrating pass / cross operation in accordance with the present invention when all four ports have send bits. FIG.

FIG. 6 is a timing diagram illustrating a pass / cross operation according to the present invention when there are send bits only in DI0 and DI2 among four ports. FIG.

* Explanation of symbols for the main parts of the drawings

I10: routing control unit I20: data switching unit

100, 101, 102, 103: unit address switch 104, 105: routing bit latch circuit

106, 107, 108, 109: unit data switch

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram showing an embodiment according to the present invention, particularly in the case of a 4 × 4 switch. In FIG. 1, I10 is a routing controller and I20 is a data switching unit.

Referring to FIG. 1, the routing control unit is composed of four BANYAN 2 × 2 unit address switches (hereinafter, unit address switches) and two routing bit latch circuits. As the size of the switch changes, the number of unit switches and routing bit latch circuits varies accordingly.

First and second address signals are input to first and second input terminals of the first unit address switch, respectively, among address signals output through a fetch and add sequential cyclic address generator.

The first unit address switch sets a cross path or a pass path according to the first address signal and the second address signal in response to a first routing control signal input from the outside, and receives the input signal. Output In addition, a control signal for controlling the routing function in the data switching unit is made.

In the case of the second unit address switch, the third and fourth address signals are received through the first input port I0 and the second input port I1 among the address signals generated through the address generator, respectively. Like the address switch, it is controlled by the first routing control signal.

In the case of the third unit address switch, a first input port is connected to the first output port of the first unit address switch, and a second input port is connected to the first output port of the second unit address switch. It is controlled by a routing control signal.

In the case of a fourth unit address switch, a first input port is connected to a second output port of the first unit address switch, and a second input port is connected to a second output port of the second unit address switch. It is controlled by a routing control signal.

The signal output through the output terminals of the third and fourth unit address switches is used as a strobe signal to determine whether to store data corresponding to the address in the shared FIFO memory.

A first routing bit latch unit configured to receive the routing bits output through the routing bit output ports of the first and second unit address switches as inputs, and to control the data switching unit in response to a first routing latch signal; Generate a second control signal.

A second routing bit latch unit configured to receive the routing bit output through the routing bit output ports of the third and fourth unit address switches as an input, and to control the data switching unit in response to a second routing latch signal; Generate a fourth control signal.

In connection with FIG. The data switching unit is composed of four Bennyyan 2 × 2 unit data switches (hereinafter, unit data switches).

The first unit data switch receives the first and second data signals from the externally input data signals through the first input port I0 and the second input port I1, respectively.

The first unit data switch receives a control signal generated from the first routing bit latch circuit through a CTL terminal to cross or pass data. Specific operations will be described later in detail.

The second unit data switch receives the third and fourth data signals from the externally input data through the first input port I0 and the second input port I1, respectively, and outputs the first and second routing bits from the first routing bit latch circuit. The control signal is controlled.

The third unit data switch has a first input port connected to the first output port of the first unit data switch, a second input port connected to the first output port of the second unit data switch, and the second routing. It is controlled by a control signal output from the bit latch circuit.

The fourth unit data switch has a first input port connected to a second output port of the first unit data switch, a second input port connected to a second output port of the second unit data switch, and the second routing. Controlled by a control signal from the bit latch circuit.

FIG. 2 is a diagram showing in detail a Bennyan 2x2 unit address switch of a routing control unit used in an embodiment of the present invention.

Address 2 bits (LSB are input first) and send 1 bit are input to the input ports I0 and I1, respectively, and operate as shown in Table 1 below.

2 × 2 unit address switch operation Occation I0 I1 O0 O1 R_BIT function One 0 0 I0 + I1 0 I1 I1 send bit check 2 One 0 I1 I0 One Cross path (I0-O1, I1-O0) 3 0 One I0 I1 0 Path Path (I0-O0, I1-O1) 4 One One 0 0 0 Uncheck send bit

The second and third cases are basic operations of the Beniyan switch.

In the first case, after seeing the send bit of I1, if 0 is not an address of valid data, the routing bit R_BIT is set to 0 to pass, and if 1, it is an address of valid data. To set the routing bit (R_BIT) to 1. If both I0 and I1 are zero, the send bit cannot generate 11 on the switch matrix, so only one I1 may be checked.

In the fourth case, since both I0 and I1 are 1, the routing bit is set to 0 to pass as is without checking the send bit.

3 is a diagram showing in detail the configuration of the routing latch circuit used in the present invention, and is composed of a D flip-flop having an enable function.

Through the terminal D0 and the terminal D1, the routing bit output through the routing bit output port of the unit address switch is received as an input, and the control signal is input through the terminal CE.

If the control signal input through the terminal CE is an enable signal, the inputs D0 and D1 of the terminal T1 are latched, and if the control signal is disabled, the current state is maintained.

4 is a diagram illustrating a configuration of a Beniyan 2 × 2 unit data switch used in the data switching unit used in the present invention.

As shown in FIG. 1, the routing bits output from the output terminals Q0 and Q1 of the routing bit latch circuits 104 and 105 of the routing control unit I10 are input through the terminal CTL of the unit data switch. Actual data is input to the input stage of the first stage unit data switches 106 and 107, and the output stage of the first stage unit data switches 106 and 107 is connected to the input stage of the next stage unit data switches 108 and 109. .

Each unit data switch 106 to 109 is operated as shown in Table 2 according to the routing bit input through the terminal CTL.

Function of unit data switch CTL (R_BIT) O0 O1 function 0 I0 I1 Pass path One I1 I0 Cross path

The operation of the present invention will now be described with reference to FIGS. 5 and 6.

5 shows simulation results when DI0 = 0, DI1 = 1000, DI2 = 100, DI3 = 1100, ADD3 = 1, ADD2 = 101, ADD1 = 11, and ADD0 = 111 (in this case, MSB is a send bit). It is a timing chart shown. In FIG. 5, the front part is a case of cross switching with DI0-D03, DI1-D02, DI2-D01, DI3-D00, and the rear part is DI0-D00, DI1-D01, DI2-D02, DI3-D03 The case of low pass switching is shown.

FIG. 6 is a timing diagram illustrating a case where the send bits of DI1 and DI3 are 0 in the case of FIG. 5, where the front part is cross switching and the rear part is pass switching.

According to the present invention as described above, it is possible to implement a shared memory structure, whereby the memory can be effectively used even when a burst of ATM cell input occurs in a specific port.

Claims (3)

In a switch for routing data to shared memory using a sequential address generated through a shared first-in first-out (FIFO) memory-cyclic repetitive address generator (hereinafter referred to as an address generator), A routing controller configured to receive an address that is an output of the address generator, a routing bit for switching corresponding data, and generate a strobe signal for determining whether the data is stored in a shared FIFO memory; And And a data switching unit configured to switch corresponding data using the routing bits. The method of claim 1, The routing control unit Among the address signals generated through the address generator, the first and second address signals are input through the first input port I0 and the second input port I1, respectively, in response to the first routing control signal ROUT0. (A) If the input to the I0 port is 1 and the input to the I1 port is 0, Outputs the value input to the first input port (I0) to the first output port (O0), outputs the value input to the first input port (I0) to the second output port (O1), routing bit output port Output 1 as (R_BIT), (B) if the input to the I0 port is 0 and the input to the I1 port is 1, Outputs the value input to the first input port (I0) to the first output port (O0), outputs the value input to the second input port (I1) to the second output port (O1), routing bit output port A first unit address switch configured to output 0 as R_BIT; Among the address signals generated through the address generator, the third and fourth address signals are input through the first input port I0 and the second input port I1, respectively, in response to the first routing control signal ROUT0. A second unit address switch configured to output in the same manner as the first unit address switch; A first input port is connected to the first output port of the first unit address switch, and a second input port is connected to the first output port of the second unit address switch, in response to the second routing control signal ROUT1. A third unit address switch configured to output in the same manner as the first unit address switch; A first input port is connected to the second output port of the first unit address switch, and a second input port is connected to the second output port of the second unit address switch, in response to the second routing control signal ROUT1. A fourth unit address switch configured to output in the same manner as the first unit address switch; Accepts the routing bits output through the routing bit output ports of the first and second unit address switches as inputs, and generates first and second control signals for controlling the data switching unit in response to a first routing latch signal. A first routing bit latch unit; And Accepts the routing bits output through the routing bit output ports of the third and fourth unit address switches as inputs, and generates third and fourth control signals for controlling the data switching unit in response to a second routing latch signal. And a second routing bit latch unit. The method of claim 1, The data switching unit Among the data signals input from the outside, the first and second data signals are received through the first input port I0 and the second input port I1, respectively, and receive the first control signal from the first routing bit latch circuit. again, (A) If the input to the I0 port is 1 and the input to the I1 port is 0, Outputs the value input to the second input port I1 to the first output port O0, and outputs the value input to the first input port I0 to the second output port O1, (B) if the input to the I0 port is 0 and the input to the I1 port is 1, A first unit data switch configured to output a value input to the first input port I0 to the first output port O0 and to output a value input to the second input port I1 to the second output port O1. ; Among the data input from the outside, the third and fourth data signals are received through the first input port I0 and the second input port I1, respectively, and in response to the second control signal from the first routing bit latch circuit. A second unit data switch configured to output in the same manner as the first unit data switch; A first input port is connected to a first output port of the first unit data switch, a second input port is connected to a first output port of the second unit data switch, and a first input port from the second routing bit latch circuit is used. A third unit data switch outputting the third unit data switch in the same manner as the first unit data switch; A first input port is connected to a second output port of the first unit data switch, a second input port is connected to a second output port of the second unit data switch, and a first input port from the second routing bit latch circuit is used. And a fourth unit data switch outputting the same in the same manner as the first unit data switch in response to a control signal. 4.