KR19980027432A - 2 channel image effect processing device and method - Google Patents

Abstract

The present invention relates to a two-channel image effect processing apparatus having a variable input filter and a trail effect function, and a method thereof. In particular, in the effect processing of a video image obtained through a camera or the like, an effect processing function independent of two input image screens and A variable input filter function to enhance the image quality and a function of processing various trail effects that leave traces when moving the effect screen are added so that two video signals can be processed independently in one device, and one if necessary. It can process various effects by processing two-stage video signals independent of video signals, and can effectively eliminate the vibration caused when the screen is reduced, improving the image quality, and various trails when the effect screen is moved. The effects can be processed to produce high quality broadcast screens.

Description

2 channel image effect processing device and method

1 is a block diagram of a conventional image effect processing apparatus

2 is an overall block diagram of an apparatus of the present invention.

3 is a conceptual diagram of the variable input filter among the inventions (a)-(c)

4 is a view illustrating an exemplary embodiment of a variable input filter unit of the present invention.

5 is another exemplary embodiment of the variable input filter unit of the present invention.

6 is a diagram illustrating an output state of a control signal output from a memory controller of FIG. 5.

7 is a basic view of the trail effect processing unit of the present invention apparatus

8 is a detailed view of a trail control signal generator and a trail key processor of the trail effect processor;

9 is an operation table for each trail mode

10 is a basic flow chart for explaining the method of the present invention.

11 is a detailed flow chart for trail key generation and storage subroutines in the method of the present invention.

12 is a detailed flowchart of the trail image data storage subroutine of the present invention method

Explanation of symbols on the main parts of the drawings

1, 7: first and second digital decoder 2: microcomputer

3, 8: first and second variable input filter unit 4, 10: first and second effect processing unit

5, 9: first and second input effect unit 6: trail effect processing unit

11: channel mixer 12: multiplexer

13: output effect section 14: digital encoder

41: source memory 42: interpolator

43: effect address generator 44: target memory

300: vertical filter unit

301 and 302: first and second 1H delay circuits

303-305, 310-312: First to Sixth (A + B) / 2 Average

306, 313: multiplexer 307: horizontal filter unit

308 and 309: first and second 1D delay circuits

314: control signal generator 401: high speed memory

402: Memory control unit 403: Data processing unit

601: trail control signal generator 602: trail key processor

603: buffer and latch portion

604: trail image data memory section 702: latch

703: calculator 704: control signal generator

705: random signal mixer 706: random signal generator

707: trail key memory 708: address generator

709: Trail Key Data Latch

The present invention relates to a two-channel image effect processing apparatus having a variable input filter and a trail effect function and a method thereof.

More specifically, in the effect processing of a video screen obtained through a camera or the like, an independent effect processing function for two input video screens, a variable input filter function for improving the image quality, and various trail effects that leave a trace when moving the effect screen are processed. The present invention relates to a two-channel image effect processing apparatus and a method thereof.

The image effect processing apparatus is mainly used to obtain a desired image screen by converting a predetermined screen into various sizes and shapes when switching screens in broadcasting production in a broadcasting station.

In order to process and synthesize the independent effects on two video screens, two independent video effect processing units and a video synthesizing unit are required in a single device. In the case of image reduction, a shaking phenomenon called an aliaser appears. In order to eliminate it, the variable input filtering process according to the reduction ratio should be performed.

In addition, when moving the effect screen requires a variety of trail effect processing of various shapes.

1 is a conceptual diagram of a conventional image effect processing, comprising: a decoder 101 for converting an input composite video signal into R, G, and B signals under the control of a microcomputer 106; An analog type input filter unit 102 for anti-aliasing the R, G, and B signals converted by the decoder unit 101; An effect processor (103) for applying an effect to the R, G, and B signals anti-aliased by the input filter (102); An output processor 104 for processing additional effects on the screen output from the fraud effect processor 103; An encoder unit 105 for converting the R, G, and B signals into a composite signal; It consisted of the microcomputer 106 which performs the overall control function of a system by a predetermined program.

However, the image effect processing device having such a configuration can only process one video signal in one device and cannot process two video signals. Therefore, in order to effect process two video signals, it is independent. There was a problem that two effect processors and a separate image synthesizer had to be used.

In addition, since an analog filter is used as an input filter, it cannot be changed according to the reduction rate, or digital filtering is performed using multiple stages of memory, which increases the production cost of the product due to complicated circuits and increases the failure rate. There is a problem in that it is not possible to process trail effects of various modes such as a maintenance mode, a sequential reduction mode, and a random mode because only simple trail effect processing is possible.

It is an object of the present invention to process two video signals independently in one equipment, and if necessary, two channels capable of processing various effects by processing two video signals independent of one video signal. An image effect processing apparatus is provided and a method thereof.

Another object of the present invention is to provide an aliasing phenomenon (ie, a shaking phenomenon) generated when a screen is reduced through a variable filter unit using two 1H delay circuits or a high-speed memory, and a trail effect processing unit capable of processing various trail effects. The present invention provides a two-channel image effect processing apparatus and method capable of efficiently eliminating and simultaneously improving image quality and processing various trail effects when the effect screen is moved.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram showing the overall block diagram of the present invention, which is a first digital device for converting a composite video signal and a key signal input to the channel A into R, G, B, and K signals under the control of the microcomputer 2; A decoder 1; R, G, B, K anti-aliased by the first variable input filter unit 3 for anti-aliasing the R, G, B, K signal converted by the first digital decoder 1 according to the reduction ratio. A first input effect unit 5 for processing crop and boarder effects of the input signal; The digital image data input from the first input effect unit 5 is stored in the source memory 41, and then by the source memory address generated by the effect address generation unit 43 controlled by the microcomputer 2. The image data in the source memory 41 is read out and generated by the effect address generator 43 under the control of the microcomputer 2 through an interpolator 42, which is generated by the target memory address. A first effect processor 4 for storing and performing image effect processing; A second digital decoder 7 which converts a composite video signal and a key signal input to the channel B under the control of the microcomputer 2 into R, G, B, and K signals; A second variable input filter unit (8) for anti-aliasing the R, G, B, and K signals converted by the second digital decoder (7) according to the reduction ratio; A first input effect unit (9) for processing cropping and more effects of the R, G, B, and K input signals anti-aliased by the second variable input filter unit (8); A multiplexer (12) for selectively inputting image signals output from the first effect processor (4) and the first input effect controller (9) to the second effect processor (10); Like the first effect processor 4, the source memory 41, the effect address generator 43 controlled by the microcomputer 2, the interpolator 43 and the target memory 44 is provided to the channel B. A second effect processor 10 for effect-processing the input video signal or effect-processing the video signal of channel A, which is primarily effected through the first effect processor 4; A channel mixer 11 for mixing the video signal effected in the channel A and the video signal effected in the channel B as controlled by the microcomputer 2; A trail effect processor (6) for performing various trail processes to leave a trajectory when moving in an image signal output through the channel mixer (11); An output effect unit 13 for processing a mosaic effect and a posterization effect on the image signal trailed by the trail effect processor 6; The digital encoder 14 converts the digital R, G, and B video signals and the key signals output from the output effect unit 13 into analog composite signals and key signals and outputs them.

4 is a detailed block diagram of the first and second variable input filter units 3 and 8 of the apparatus of the present invention, and the vertical filter unit 300, the horizontal filter unit 307, and the microcomputer 2 The control signal generator 314 may generate a control signal and generate a predetermined control signal.

At this time, the vertical filter unit 300 includes a first 1H delay circuit 301 for delaying the input image data by 1H under the control of the control signal generator 314; A second 1H delay circuit 302 for delaying the image data output from the first 1H delay circuit 301 by 1H again under the control of the control signal generator 314; A first (A + B) / 2 averager 303 for obtaining an average of the signal H1 not passing through the delay circuit and the signal H2 passing through the first 1H delay circuit 301; A second (A + B) / 2 averager (304) for obtaining an average of the signals (H2, H3) passing through the first and second 1H delay circuits (301, 302); A third (A + B) / 2 averager (305) for obtaining an average of the output signals of the first and second (A + B) / 2 averagers (303, 304); The signal H2 delayed by the first 1H delay circuit 301 and the average value obtained through the first (A + B) / 2 averager 303 and the third (A + B) / 2 average Any one of the average values obtained through the instrument 305 is characterized by consisting of a multiplexer 306 under the control of the microcomputer 2 to select and output to the horizontal filter unit 307.

The horizontal filter unit 307 may further include: a first 1D delay circuit 308 for delaying image data input from the vertical filter unit 300 by 1D; A second 1D delay circuit (309) for delaying the image data output from the first 1D delay circuit (308) by 1D again; A fourth (A + B) / 2 averager 310 for obtaining an average of a signal input from the vertical filter unit 300 and not passing through the delay circuit and a signal passing through the first 1D delay circuit 308; ; A fifth (A + B) / 2 averager (311) for obtaining an average of signals passing through the first and second 1D delay circuits (308, 309); A sixth (A + B) / 2 averager (312) for obtaining an average of the output signals of the fourth and fifth (A + B) / 2 averagers (301,311); The 1D delayed signal through the first 1D delay circuit 308 and the fourth (A + B) / 2 averager 310 are obtained through the fourth (A + B) / 2 averager 310. The multiplexer 313 selectively outputs any one of the average value and the average value obtained through the sixth (A + B) / 2 averager 312 under the control of the microcomputer 2.

In configuring the first and second variable input filter parts 3 and 8, there is another method, which is used instead of the two 1H delay circuits and the control signal generator used in the variable input filter part shown in FIG. As shown in FIG. 5, one high speed memory 401, a memory control section 402 and a data processing section 403 are used.

That is, a high speed memory 401 which reads and stores 2H delayed image data and 1H delayed image data during one clock period output from the memory control unit 402 instead of the two 1H delay circuits and the control signal generator; A memory controller 402 for generating a clock pulse of a predetermined period in the high speed memory 401; A signal separated into 1H delayed data (H2), 2H delayed data (H3), and a signal (H1) that does not pass through the delay circuit are combined with a first second (A + B) / 2 averager (303, 304) and a multiplexer. The same effect can be obtained even through the data processing unit 403 outputted to 306.

On the other hand, Figure 7 shows a block diagram of the trail effect processor 6 of the present invention, the control signal and trail image data memory for various trail key processing from the key signal input through the channel mixer 11 A trail control signal generator 601 for generating a control signal; A trail key processor 602 for processing a trail key output from the trail control signal generator 601 and outputting a key signal; A buffer and latch unit (603) for storing R, G, and B image data input through the channel mixer (11); A trail image data memory unit 604 is controlled by a trail key output from the trail control signal generator 601 to store image data output from the buffer and latch unit 603.

8 is a detailed block diagram of the trail control signal generator 601 and the trail key processor 602, and includes a latch 702 for stabilizing a key signal input from the channel mixer 11; ; The key signal inputted through the latch 702 and the key signal immediately read from the trail key memory 707 and passed through the latch 709 and the control signal generated by the control signal generator 704 by the control signal generator 704 are used for the key signal. An operator 703 for calculating a value; The calculator 703, the trail key memory 707, the address generator 708, the trail key data latch 709, and the random signal generator 706 are controlled by the control value of the microcomputer 2 and the key value immediately before one field. A control signal generator 704 for generating a predetermined control signal for controlling the signal; A random signal generator 706 for generating a signal for a random trail; A random signal mixer (705) for mixing a random signal with the key value calculated by the calculator (703); A trail key memory 707 for storing one field of key data; The address generator 708 generates an address of the trail key memory 707.

On the other hand, the method of the present invention, as shown in Figure 10, the trail key generation and storage to generate and store the trail effect by the input key and the trail key memory in accordance with the trail mode; A basic feature is that the trail image data storage subroutine stores the image data according to the trail mode and the input key.

At this time, the trail key generation and storage subroutine initializes the trail key memory 707, reads key data KA one field before from the key memory, and is input from the latch 702 as shown in FIG. Reading a key KB and determining whether a mode designated by a user is a trail mode; Outputting the key (KB) input from the latch 702 as it is, if not in the trail mode, and storing the same in a key memory; If it is not the sequential reduction mode, it is determined whether the key (KB) inputted to operate in the trail holding mode is 0. If the key is 0, the key (KB) read out from the key memory is output as it is and stored in the key memory. Outputting the key (KB) if the key is not 0 and storing the key in the key memory; Determining whether to operate in a random mode in the sequential reduction mode as a result of the detection; As a result of the detection, if it is not a random mode, it is determined whether the input key (KB) is 0 to operate in the sequential reduction mode, and if it is not 0, the input key (KB) is output as it is, stored in the key memory, and the input key ( Determining whether the key (KB) before one field read from the key memory is 0 when KB) is 0; As a result of the above detection, if the key KA before 1 field is 0, KA = KB = 0, so KB is output as it is and stored in the key memory.If the key (KB) before 1 field is not 0, 1 is subtracted from the value of KA. Storing the key in the memory; As a result of the detection, it is determined whether the input key (KB) is 0 in the random mode, and if it is not 0, the input key (KB) is output as it is and stored in the key memory. Determining whether the key (KB) before the read one field is zero; As a result of the above determination, if the key (KB) before 1 field is 0, KA = KB = 0, so KB is output as it is and stored in the key memory.If the key (KA) before 1 field is not 0, the random signal is mixed with the value of KA. Storing in a key memory; When the above processes are completed, it is determined whether or not it is the last address, and if it is not the last address, the address is increased to continue reading data from the key memory, and if the last address, the operation is terminated.

In addition, the trail image data storing subroutine may include: initializing the trail image data memory address and reading a key KB input from the latch 702 to determine whether the trail image data is in the trail mode; Determining whether the key (KB) is zero or not in the trailing mode if the data is stored in the video memory unconditionally as a result of the determination; If the key (KB) is input as 0, it is not stored, but if it is not 0, it is stored in a memory, and then it is determined whether it is the last address.

Referring to the effects of the present invention as follows.

First, in the image effect processing apparatus of the present invention, the composite video signal and the key signal input to the channel A are converted into R, G, B, and K digital signals through the first digital decoder 1, and then the first according to the reduction ratio. The anti-aliasing process is performed through the variable input filter unit 3 and then transferred to the first input effect unit 5.

Therefore, the first input effect unit 5 processes crop and boarder effects of the input signal and transfers them to the first effect processor 4, so that the source memory in the first effect processor 4 is processed. And a target memory 44 to store the incoming digital image data in the source memory 41 and to the source memory address by the source memory address generated by the effect address generator 43 controlled by the microcomputer 2. 41 is stored in the target memory 44 by the target memory address generated by the effect address generator 43 controlled by the microcomputer 2 through the interpolator 42 to perform image effect processing. .

The image data processed in this way is input to the trail effect processor 6 via the channel mixer 11 or to the multiplexer 12 (ie, MUX) installed in front of the second effect processor 10 of the channel B. Lose.

On the other hand, the composite image signal and the key signal input to the channel B is the second effect through a second digital decoder 7, the second variable input filter unit 8 and the second input effect unit 9 in the same manner. It is input to the multiplexer 12 in front of the processing unit 10.

At this time, the second effect processor 10 of the channel B has a two-stage effect processing function for processing the image signal input to the channel B or effect processing the image signal processed in the channel A again.

In addition, the channel mixer 11 mixes the video signal effected in channel A and the video signal effected in channel B as controlled by the microcomputer 2 and inputs it to the trail effect processor 6.

Therefore, the trail effect processing unit 6 performs various trail processing to leave the trajectory when moving, and transmits the output effect 13 to the output effect unit 13, thereby processing the mosaic effect and the posterization effect. The digital encoder 14 converts the digital R, G, and B video signals into analog composite signals and outputs them.

On the other hand, Figure 3 (a)-(c) shows a conceptual diagram of the first and second variable input filter unit (3, 8), (a) shows the filter when the vertical, horizontal reduction ratio of the screen is 0.6 or more When no processing is performed, the center pixel is affected by surrounding pixels. (B) is a table showing the influence of peripheral pixels when the vertical and horizontal scaling ratio of the screen is 0.4 or less and 0.6 or less. When the vertical and horizontal reduction rate of the screen is less than 0.4, the table shows the influence of peripheral pixels.

In other words, when the reduction ratio is small, the screen is stabilized by reducing the high frequency component so as to be influenced by the surrounding pixels. Make it look

Therefore, the input signal must be filtered in accordance with the reduction ratio. In the case of (c), two 1H delay circuits and two 1D delay circuits are required to process data around 8 pixels in real time.

4 is a detailed block diagram of the first and second variable input filter units 3 and 8 capable of satisfying the above conditions. First, the vertical filter unit 300 will be described. The signal H1 not passed, the signal H2 passed through the first 1H delay circuit 301, and the signal H3 passed through two stages to the second 1H delay circuit 302 are generated. 314 generates a predetermined control signal for controlling the first and second 1H delay circuits 301 and 302.

In the above description, the signal H1 not passing through the delay circuit, the signal H2 passing through the first 1H delay circuit 301 and the signal H3 passing through the second 1H delay circuit 302 are first through first. 3 (A + B) / 2 are passed through the averager 303, 034, 305 is input to the multiplexer 306, wherein the signal input to the multiplexer 306 is a signal that does not pass through the averager, the first ( A + B) / 2 a signal that passes only the averager 303, and a signal that passes through the first to third (A + B) / 2 averagers 303, 304, and 305, respectively, having a vertical reduction ratio of 0.6 or more and less than 0.6. The signal is used at 0.4 or less and less than 0.4, and is selected by the microcomputer 315 according to the reduction ratio and transmitted to the horizontal filter unit 307.

In addition, the horizontal filter unit 307 has the same structure as the vertical filter unit 300, but a 1D delay unit is used instead of two 1H delay units, and there is no delay circuit controller.

Looking at such a horizontal filter unit 307, first the signal does not pass through the delay circuit, the signal passed through the first 1D delay circuit 308, the signal passed to the second 1D delay circuit 309 is generated These signals are passed through the fourth to sixth (A + B) / 2 averagers 310, 311, and 312 to the selector, i.e., the multiplexer 313.

In this case, the signal transmitted to the multiplexer 313 is a signal that does not pass through the averagers, a signal that passes only the fourth (A + B) / 2 averager 310, and fourth to sixth (A + B) / 2. The signals have passed through the averagers 310, 311, and 312, respectively, and are used at horizontal reduction ratios of 0.6 or more, less than 0.6 or less, 0.4 or more and less than 0.4, respectively, and are selected and output by the microcomputer 315 according to the reduction ratio.

Therefore, it can be applied independently according to the vertical reduction rate and the horizontal reduction rate.

Meanwhile, the first and second variable input filter units 3 and 8 may be configured by another method. In order to perform the same functions as those of the variable input filter unit of FIG. Instead of the delay circuits 301 and 302 and the control signal generator 314, a high speed memory 401, a memory controller 402, and a data processor 403 are used to change the configuration circuits to change the speed of the memory. Accordingly, two or more 1H delay circuits can be replaced, and adopting such a scheme makes expansion easier than the above-described configuration.

As described above, the variable input filter unit using the high speed memory is the same as that of the fifth diagram. The memory control unit 402 reads the 2H delayed data and the 1H delayed data for one clock period, and stores the input data in the memory 401. The data processing unit 403 controls the signals separated into 1H delayed data H2, 2H delayed data H3, and the signal H1 not passing through the delay circuit to the first to third (A + B) / 2 send to the averagers 303, 304, 305 and multiplexer 306.

Looking at the control signal output from the memory control unit 402, since 2H delayed data and 1H delayed data must be read and written currently inputted during one clock period, for example, when 1H is composed of 858 pixels, Is generated repeatedly from 0 to 1716. If the data of current address 0 is read, the contents become data before 1716 (2H) and written as the current data.

The data at address 858 reads out data before 858 pixels (1H).

In the next clock, 1H delayed data and 2H delayed data are generated by reading the data at address 1 (data before 2H), writing the current data, and reading the data at address 859 (data before 1H).

On the other hand, the trail effect processing unit 6 is composed of a trail memory using a high-speed memory and the associated control unit, and the movement mode remains in the trace mode is not erased, the sequential reduction mode that is sequentially erased from the old part in time, and random It works in three ways: random mode that disappears.

As shown in FIG. 7, the trail effect processor 6 includes a trail control signal generator 601 for generating various train key processor control signals and a trail image data memory control signal from the input key signal, and a trail key. A trail key processing unit 602 for processing the data, a buffer and latch unit 603 for receiving R, G, and B image data, and a trail image data memory unit 604 for storing image data controlled by the trail key. It is.

The trail control signal generator 601 and the trail key processor 602 will be described in detail with reference to FIG. 8.

First, since the latch 702 stabilizes an input key signal and outputs the same to the calculator 703, the calculator 703 is read from the key signal KB and the trail key memory 707 input through the latch and latched. The key KA immediately before the one field passed through 709 is input and controlled by the control signal generated by the control signal generator 704 to calculate the value of the key signal.

Of course, the control signal generator 704 is based on the control value of the microcomputer 2 and the key value immediately before one field, and the operator 703, the trail key memory 707, the address generator 708, and the trail key. The control signal for controlling the data latch 709 and the random signal generator 706 is generated.

In addition, since the random signal generator 706 under the control of the control signal generator 704 generates a signal for a random trail to the random signal mixer 705, the random signal mixer 705 uses the calculator 703. The random signal is mixed with the calculated key value and outputted.

The trail key memory 707 stores key data for one field under the control of the control signal generator 704, and the address generator 708 stores a predetermined address in the trail key memory 707. Will be generated.

Meanwhile, an operation state of each trail mode performed by the trail effect processor 6 will be described with reference to the table shown in the ninth road.

First, if the trail mode is 0, the trail effect is not processed. If the trail mode is 1, the decrease mode is 0, the operation mode is maintained. Therefore, if the input key value is not 0, the trailing key memory 707 is used. If the input key is 0, the value (KA) read from the key memory is stored again.

If the random mode is 0 when the trailing mode is 0 and the random mode is 0, it is a sequential decreasing mode.If the input key (KB) is not 0, it is stored in the trail key memory and the input key (KB) is 0 and read from the key memory. If the calculated value KA is not 0, it is stored as the value of KA-1.

In addition, if the decrement mode is 1 and the random mode is 1, the random mode is 1, so if the input key (KB) is not 0, it is stored in the trail key memory 707 and the input key (KB) and the value read from the key memory (KA) are 0. If 0 is stored, and if the input key KB is 0 or the value KA read from the key memory is not 0, the KA is stored in the trail key memory 707 via the random signal mixer 705.

As shown in FIG. 10, the present invention supports the above-mentioned contents. As shown in FIG. 10, trail key generation and storage of a trail effect generated by an input key and a trail key memory according to a trail mode, and a trail mode, and a trail mode And a trail image data storage subroutine for storing image data according to an input key.

At this time, the trail key generation and storage subroutine first initializes the trail key memory, reads the key data KA one field before from the trail key memory 707, and then latches the latch 702. Read key (KB) input through

After that, it is determined whether the mode designated by the user is a trail mode, and if it is not a trail mode, the key (KB) is output as it is and stored in the trail key memory, and when the trail mode is operated, it is determined that the mode is a sequential reduction mode. If it is 0, judge whether the input key (KB) is 0, and if it is 0, output the key (KA) read from the key memory as it is and store it in the key memory.If the input key (KB) is not 0, the input key (KB) ) And print it out to the key memory.

However, when operating in the sequential reduction mode, it is determined whether to operate in the random mode and operates in the sequential reduction mode as it is not in the random mode. Therefore, it is determined whether the input key (KB) is 0. If the key (KB) is 0, it is judged whether the key (KA) before the 1 field read from the key memory is 0. If the key is 0, KA = KB = 0. If the key KA before 1 field is not 0, 1 is subtracted from the KA value and output to the key memory.

On the other hand, when operating in the random mode, it is determined whether the input key (KB) is 0, and if it is not 0, the input key (KB) is output as it is and stored in the key memory. It is judged whether the read key (KB) before 1 field is 0. If 0, KA = KB = 0. Therefore, KB is output as it is and stored in key memory.If the key (KB) before 1 field is not 0, random signal is used for the value of KA. Then store the data in the key memory and determine whether it is the last address. If it is not the last address, increase the address and continue reading data from the key memory again.

In addition, as shown in FIG. 12, the trail image data storage subroutine initializes the trail image data memory address, reads the key KB input through the latch 702, and unconditionally stores the key image in the video memory. In case of trail mode, it is determined whether the input key (KB) is 0 or not. If it is 0, it is not stored. If it is not 0, it is stored in memory. And when it is finished, it can finish various trail effects when moving the effect screen.

As described above, according to the present invention, two video signals can be processed independently in one device, and if necessary, two video signals can be processed independently of one video signal. It can be processed, and it can effectively eliminate the vibration caused when the screen is reduced, which can improve the image quality, and can process various trail effects when moving the effect screen, thus producing high quality broadcast screens. .

Claims (10)

A first digital decoder 1 for converting a composite video signal and a key signal into the R, G, B, and K signals under the control of the microcomputer 2; A first variable input filter unit (3) for anti-aliasing the R, G, B, and K signals converted by the first digital decoder (1) according to a reduction ratio; A first input effect unit (5) for processing crop and boarder effects of the R, G, B, and K input signals anti-aliased by the first variable input filter unit (3); Source memory addresses generated by the effect address generation unit 43, which stores the image data in the source memory 41 by digital input from the first input effect unit 5, and is then controlled by the microcomputer 2; The target memory 44 by reading the image data in the source memory 41 by means of the target memory address generated by the effect address generating unit 43 under the control of the microcomputer 2 via the interpolator 42. A first effect processor (4) for storing the same in a) and performing image effect processing; A second digital decoder 7 for converting a composite video signal and a key signal into the R, G, B, and K signals under the control of the microcomputer 2; By the second variable input filter section 8 and the second variable input filter section 8 which anti-alias the R, G, B, K signals converted by the second digital decoder 7 according to the reduction ratio. A second input effect unit 9 for processing cropping and border effects of the anti-aliased R, G, B, and K input signals; A multiplexer (12) for selectively inputting image signals output from the first effect processor (4) and the second input effect controller (9) to the second effect processor (10); Like the first effect processor 4, the source memory 41, the effect address generator 43 controlled by the microcomputer 2, the interpolator 43 and the target memory 44 is provided to the channel B. A second effect processor 10 for effect-processing the input video signal or effect-processing the video signal of channel A, which is primarily effected through the first effect processor 4; A channel mixer 11 for mixing the video signal effected in the channel A and the video signal effected in the channel B as controlled by the microcomputer 2; A trail effect processor (6) for performing various trail processes to leave a trajectory when moving in an image signal output through the channel mixer (11); An output effect unit 13 for processing a mosaic effect and a posterization effect on the image signal trailed by the trail effect processor 6; Two-channel video effect processing, characterized in that it comprises a digital encoder 14 for converting the digital R, G, B video signal and the key signal output from the output effect unit 13 into an analog composite signal and a key signal for output. Device. The control apparatus of claim 1, wherein the first and second variable input filter units 3 and 8 receive a predetermined control signal under the control of the vertical filter unit 300, the horizontal filter unit 307, and the microcomputer 2. The two-channel image effect processing apparatus, characterized in that consisting of a control signal generator 314 for generating. The trail control signal generator of claim 1, wherein the trail effect processor 6 generates a trail signal processing control signal and a trail image data memory control signal from a key signal input through the channel mixer 11. 601); A trail key processor 602 for processing a trail key output from the trail control signal generator 601 and outputting a key signal; A buffer and latch unit (603) for storing R, G, and B image data input through the channel mixer (11); Characterized in that the trail image data memory unit 604 is controlled by the trail key output from the trail control signal generator 601 to store the image data output from the buffer and latch unit 603 Channel image processing device. 3. The vertical filter unit (300) of claim 2, further comprising: a first 1H delay circuit (301) for delaying the input image data by 1H under the control of the control signal generator (314); A second 1H delay circuit 302 for delaying the image data output from the first 1H delay circuit 301 by 1H again under the control of the control signal generator 314; A first (A + B) / 2 averager 303 for obtaining an average of the signal H1 not passing through the delay circuit and the signal H2 passing through the first 1H delay circuit 301; A second (A + B) / 2 averager (304) for obtaining an average of the signals (H2, H3) passing through the first and second 1H delay circuits (301, 302); A third (A + B) / 2 averager (305) for obtaining an average of the output signals of the first to second (A + B) / 2 averagers (303, 304); A signal H2 delayed by the first 1H delay circuit 301 and the average value obtained through the first (A + B) / 2 averager 303 and a third (A + B) / 2 averager And a multiplexer (306) which selects and outputs any one of the average values obtained through (305) to the horizontal filter unit (307) under the control of the microcomputer (2). 3. The horizontal filter unit (307) according to claim 2, further comprising: a first 1D delay circuit (308) for delaying image data input from the vertical filter unit (300) by 1D; A second 1D delay circuit (309) for delaying the image data output from the first 1D delay circuit (308) by 1D again; A fourth (A + B) / 2 averager 310 for obtaining an average of a signal input from the vertical filter unit 300 and not passing through the delay circuit and a signal passing through the first 1D delay circuit 308; ; Fourth and fifth averaged output signals of the fifth (A + B) / 2 averagers 310 and 311 that average the signals that have passed through the first and second 1D delay circuits 308 and 309. (A + B) / 2 averager 311; The sixth (A + B) / 2 averager (312); The 1D delayed signal through the first 1D delay circuit 308, the average value obtained through the fourth (A + B) / 2 averager 310, and the sixth (A + B) / 2 averager 312 And a multiplexer (313) for selectively outputting any one of the average values obtained through the control of the microcomputer (2). 3. The memory device of claim 2, wherein the vertical filter unit (300) comprises: a high speed memory (401) for reading and storing image data delayed by 2H and image data delayed by 1H during one clock period output from the memory controller 402; A memory controller 402 for generating a clock pulse of a predetermined period in the high speed memory 401; The signal separated by the 1H delayed data (H2), the 2H delayed data (H3), and the signal (H1) which does not pass the delayed code are compared with the first and second (A + B) / 2 averagers (303, 304). A data processor 403 for outputting to the multiplexer 306; A first (A + B) / 2 averager 303 for obtaining an average of the undelayed signal H1 and the signal H2 passing through the data processor 403; A second (A + B) / 2 averager (304) for obtaining an average of two signals (H2, H3) passing through the data processor (403); A third (A + B) / 2 averager 305 for calculating an average of the output signals of the first and second (A + B) / 2 averagers 303 and 304; The signal H2 delayed by the data processor 403, the average value obtained through the first (A + B) / 2 averager 303, and the third (A + B) / 2 averager 305 And a multiplexer (306) which selects and outputs any one of the average values obtained through the microcomputer (2) to the horizontal filter unit (307) under the control of the microcomputer (2). 4. The trail control apparatus according to claim 3, wherein the trail control signal generator (601) and the trail key processor (602) comprise: a latch (702) for stabilizing a key signal input from the channel mixer (11); The key signal inputted through the latch 702 and the key signal just read from the trail key memory 707 and passed through the latch 709 and the control signal generated by the control signal generator 704 by the control signal generated by the control signal generator 704. An operator 703 for calculating a value; The calculator 703, the trail key memory 707, the address generator 708, the trail key data latch 709, and the random signal generator 706 are controlled by the control value of the microcomputer 2 and the key value immediately before one field. A control signal generator 704 for generating a predetermined control signal for controlling; A random signal generator 706 for generating a signal for a random trail; A random signal mixer (705) for mixing a random signal with the key value calculated by the calculator (703); A trail key memory 707 for storing one field of key data; And an address generator (708) for generating an address of the trail key memory (707). Trail key generation and storage for generating and storing a tray effect by an input key and a trail key memory according to a trail mode; And a trail image data storage subroutine for storing image data according to a trail mode and an input key. 10. The method of claim 8, wherein the trail key generation and storage subterminus initializes the trail key memory 707, reads the key data KA one field before from the key memory, and inputs the key from the latch 702. Determining whether the mode designated by the user is a trail mode after reading the KB); Outputting the key (KB) input from the latch 702 as it is, if not in the trail mode, and storing it in the key memory, and determining whether the mode is a sequential reduction mode in the trail mode; If it is not the sequential reduction mode, it is determined whether the key (KB) inputted to operate in the trail holding mode is 0. If the key is 0, the key (KB) read out from the key memory is output as it is and stored in the key memory. Outputting the key (KB) if the key is not 0 and storing the key in the key memory; Determining whether to operate in a random mode in the sequential reduction mode as a result of the detection; As a result of the detection, if it is not in random mode, it is determined whether the input key (KB) is 0 in order to operate in sequential reduction mode, and if it is not 0, the input key (KB) is output as it is, stored in the key memory, and the input key ( Determining whether the key (KB) before one field read from the key memory is 0 when KB) is 0; As a result of the above detection, if the key KA before 1 field is 0, KA = KB = 0. Therefore, KB is output as it is and stored in the key memory.If the key (KB) before 1 field is not 0, 1 is subtracted from the value of KA. The assumption of storing the key memory; Determining whether the input key KB is 0 in the random mode, and determining whether the key KA in the field 1 read from the key memory is 0 when the key KB is 0 when not in the random mode; ; As a result of the above determination, if the key KA before 1 field is 0, KA = KB = 0, so the KB is output as it is and stored in the key memory. If the key KA before 1 field is not 0, the random signal is mixed with the value of KA. Storing in a key memory; When the above processes are completed, it is determined whether the address is the last address, and if it is not the last address, the process of reading data from the key memory continues by increasing the address and ending the operation if the last address is completed. Way. 9. The method of claim 8, wherein the trail image data storage subroutine comprises: initializing a trail image data memory address and reading a key (KB) input from a latch (702) to determine whether the trail mode is in a trail mode; Determining whether the key (KB) is zero or not in the trailing mode if the data is stored in the video memory unconditionally as a result of the determination; If the key (KB) is 0, it is not stored. If it is not 0, it is stored in memory. If it is not the last address, it is determined that it is the last address. Channel image processing method.