KR19980022229A - Driving Method of Flash Memory Device - Google Patents

Abstract

The present invention relates to a method of driving a flash memory device that prevents a disturb phenomenon in which an unselected memory cell is programmed by a lowered channel voltage when programming a selected memory cell. A first memory string, a first string and a second string in which a plurality of source line select transistors are sequentially connected in series, and a plurality of bit lines selected respectively connected to gates of the plurality of bit line select transistors of the first and second strings Lines, a plurality of word lines connected to control gates of the memory cells of the first and second strings, and a plurality of source lines respectively connected to gates of the plurality of source line select transistors of the first and second strings, respectively. Consists of a selection line, a plurality of non- A first string and a second string in which a line select transistor, a plurality of unit memory cells, and a plurality of source line select transistors are sequentially connected in series, and connected to gates of the plurality of bit line select transistors of the first and second strings, respectively. A plurality of bit line select lines, a plurality of word lines connected to control gates of the memory cells of the first and second strings, and gates of the plurality of source line select transistors of the first and second strings, respectively. Another string block composed of a plurality of source line selection lines connected to each other is configured to be symmetrical by sharing bit line contacts to which one end of the first and second strings of the string block are connected, and through the bit line contacts, respectively. A first line connected with one end of the first and second strings of the other string block, The string block and the other string are respectively connected to source line contacts to which one end of two strings of the other string block symmetrically configured by sharing the bit line contacts of one string block and its neighboring string blocks are connected. A second line connected to the other end of the first and second strings of the block, two of the other string blocks symmetrically configured by sharing the bitline contacts of another neighboring string block and another neighboring string block; A drive of a flash memory device in which one end of a string is connected to a bit line contact, the string block and another string block are formed in bulk, and the string block and the other string block are two-dimensionally arranged to form a memory cell array. A method, comprising: applying an erase voltage to the bulk, the string block and another string. An erase operation is performed by applying a voltage equal to the erase voltage to a plurality of bit line select lines and a plurality of source line select lines configured in each block, and 0 V to a selected word line among a plurality of word lines of the string block, First, supply voltages are supplied to the first and second lines, and a plurality of bit line select lines, the plurality of source select lines, and the plurality of word lines configured to each of the string block and the other string blocks, respectively. After precharging the channel region of the memory cell by applying a period of time, the program voltage Vpgm is applied to the selected word line of the plurality of word lines of the string block and the plurality of word lines of the other string block. An unselected wordline of a block and a plurality of bitline select lines of the string block and another string block. After applying a voltage Vpass lower than the program voltage and higher than the supply voltage, the channel region of the memory cell connected to the selected word line is self-boosted above the precharge voltage, and then, among the first and second strings of the string block. To discharge the boosted voltage of the memory cell of the selected string, 0V is applied to the unselected strings of the plurality of source line select lines of the string block and 0V to the plurality of bit line select lines, and among the first and second lines. The program operation is performed by applying 0V to the source line of the selection bit line. By such a method, it is possible to prevent the disturb phenomenon in which the unselected memory cells are programmed by the lowered channel voltage when programming the selected memory cells.

Description

Driving Method of Flash Memory Device

The present invention relates to a method of driving a flash memory device, and more particularly, to a method of driving a flash memory device which prevents a disturb phenomenon in which an unselected memory cell is programmed by a lowered channel voltage when programming a selected memory cell. It is about.

Recently, nonvolatile memory devices capable of electrically erasing and rewriting data have become increasingly integrated and large in capacity. In general, a cell transistor constituting a nonvolatile memory device has a floating gate and a control gate, and is divided into a NOR type and a NAND type according to a connection type.

The NOR type nonvolatile memory device is configured such that several memory cells are connected to one bit line in parallel by sharing one bit line contact and a source line with two memory cells facing each other. In addition, a channel hot electron method is used to store data in a NOR type nonvolatile memory device, and a Fowler-Nordheim tunneling method is used to erase data. The memory device is disadvantageous for high integration by using a large cell current for such an operation, but has an advantage of easily coping with high speed.

In the NAND type nonvolatile memory device, two cell strings share one bit line contact and a source line, and one cell string is configured such that a plurality of cell transistors are connected in series with the bit line. In the NAND type nonvolatile memory device, FN tunneling is generated between a substrate and a floating gate according to a voltage applied to a control gate or a substrate to store and erase data. A NAND type nonvolatile memory device uses a small cell current. Therefore, there is an advantage in high integration.

In conclusion, since the NAND type nonvolatile memory cell has a higher degree of integration than the NOR type, the NAND type memory is preferable for increasing the capacity of the memory device.

1 illustrates a vertical structure of a unit string of a conventional single bit line NAND flash memory device.

Referring to FIG. 1, a process of forming a conventional single bit line NAND flash memory device is as follows.

After the n-well (3) (or p-well in the n-type substrate) is formed on the p-type substrate 1, the p-well 5 (hereinafter pocket) in the n-well (3) ) is denoted p-well). Next, an active region and a field insulating region (not shown) are formed on a bulk in which the pocket p-well 5 is formed by a general LOCOS technique, and the like for entering and entering electrons for storing and erasing data of a cell. Tunnel oxide (not shown) is formed in the active region of about 80 to 100 kHz. Thereafter, the floating gate polysilicon 7 is formed for each cell, and the oxide-nitride-oxide (ONO) film 9 is formed about 150 kV to 200 kV as an interpoly insulating film. Subsequently, a stack structure of polycide 11 is formed for the word line and the select line used as the control gate of the cell, and ion implantation of the source / drain 13 is performed. metal) wiring 15 is formed.

In the NAND type flash memory device, the operation of a unit cell utilizes the movement of electrons by F-N tunneling through tunnel oxide. When an operating voltage is applied between the control gate and the bulk silicon (pocket p-well in which the cell array is formed), the ratio of the capacitors (capacitor, Ci) composed of an interpoly insulating film between the control gate and the floating gate is determined. As a result, a constant voltage is induced to the floating gate. In other words, Vf = (Ci * Vpgm) /

At the time of (Ct + Ci) and erasing, a voltage of Vf = (Ct * Vers) / (Ct + Ci) is derived. Here, Vf is a voltage induced to the floating gate, Vpgm is a program voltage applied to the control gate, and Vers is an erase voltage applied to the control gate.

Accordingly, due to the voltage between the floating gate and the bulk silicon, the movement of electrons by F-N tunneling through the tunnel oxide occurs.

The reason why the cell array is formed in the pocket p-well 5 is to separate the voltage of about 20V applied to the bulk during the erase operation of the cell from the bulk operation region of the peripheral circuit.

2 is a circuit diagram of a conventional single bit line NAND flash memory device of FIG. Here only two strings 20 are shown connected to each of the two bit lines B / L1 and B / L2.

Referring to FIG. 2, a bit line select line SSL is connected to a gate to connect the bit lines B / L1 and B / L2 and the source line CSL with the unit cells MC1 to MC16. A unit string is formed by connecting a plurality of unit cells MC1 to MC16 in series between the line select transistor M1 and a source line select transistor M2 having a source line select line GSL connected to a gate. In addition, the unit string 10 is connected in parallel to each of the bit lines B / L1 and B / L2.

3 is a timing diagram illustrating a method of driving the above-described single bit line NAND flash memory device. Referring to FIG. 3, the operation of the conventional single bit line NAND flash memory device of FIG. 2 will be described.

A program operation for storing electrons in a floating gate of a cell may include a program voltage Vpgm at a word line W / L3 of a selected cell, for example, cell A of FIG. 2, and an unselected word line W / Ln, n 1 to 16, n ≠ 3) and the Vpass voltage to the bit line select line SSL, the ground voltage (0V) to the select bit line B / L1 and the source line select line GSL, and the unselected bit line ( By applying the Vpi voltage to B / L2). Accordingly, the program is made by injecting electrons from the bulk silicon into the floating gate through the tunnel oxide by the program voltage Vpgm of the selected cell A.

At this time, of the cells connected to the select word line W / L3, the cell B connected to the unselected bit line B / L2 is not programmed for the following reason. That is, since the Vpass voltage is applied to the bit line selection line SSL and the unselected word line W / Ln, where n is 1 to 16 and n ≠ 3, the Vpi voltage applied to the unselected bit line B / L2. This is induced in the channel of the cell B, and accordingly the electric field due to the Vpgm voltage of the word line W / L3 is reduced so that the tunneling of the electrons is suppressed and thus not programmed.

The erase operation for removing electrons in the floating gate of the cell is performed by applying a ground voltage to the selected word line W / L3 and applying an erase voltage Vers to the bulk silicon. Accordingly, the electrons of the floating gate are removed by the electric field caused by the erase voltage Vers, and the hole is injected, thereby erasing.

In addition, the read operation of reading data from a cell includes a cell having a Vth of +1 V when electrons are stored in the floating gate of the cell, and a Vth of a cell when a hole is stored in the floating gate of the cell. Use -3V. That is, the read operation reads data of logic 0 or logic 1 by applying a ground voltage (0V) to the selection word line W / L3 according to the presence or absence of a current path through the selection cell.

In case of using the operation scheme of the conventional single bit line NAND flash memory device described above, in the high density flash memory device, Vpi is applied to the bit line to prevent program disturb. The voltage must be a high voltage higher than the supply voltage (Vcc). Therefore, in order to generate a high voltage Vpi voltage, a technique of charge pumping a supply voltage Vcc using a capacitor is typically used.

At this time, since the size of the required capacitor is determined according to the bit line capacitance, if the bit line capacitance increases due to high integration, the size of the capacitor for charge pumping must also increase. As a result, the chip area occupied by the charge pumping capacitor is increased, and the time for charging the bit line to Vpi becomes long, resulting in a long program time.

A self-boosting technique to solve this problem was published in 1995 in ISSCC pp128-129 A 3.3V 32Mb nand flash memory with incremental step pulse programming scheme.

4A and 4B are timing diagrams illustrating a method of driving the conventional single bit line NAND flash memory device of FIG. 2 when using a self-boosting technique. 4A is an operation condition at the time of a program operation, and FIG. 4B is an operation condition at the time of a read operation.

Referring to FIG. 4A, a self-boosting technique may include a supply voltage Vcc at an unselected bit line B / L2 and a bit line select line SSL, a Vpgm at a select word line W / L3 during programming, Vpass is applied to the unselected word line (W / Ln, n is 1 to 16, n ≠ 3), and a ground voltage (0V) is applied to the select bit line (B / L1), bulk silicon, and source line select line (GSL). The self-boosting Vpi voltage is applied to the channel of the unselected string by applying.

In the case of using the self-boosting technique, since a high voltage of more than the supply voltage Vcc is applied only to the word line, only a charge pumping capacitor for generating a high voltage to be applied to the word line is required. Accordingly, the self-boosting technique has a charge pumping capacitor in comparison with the prior art which requires a charge pumping capacitor for generating a high voltage to be applied to a word line and a charge pumping capacitor for generating a high voltage to be applied to a bit line. The chip area that is occupied is reduced, and the time for charging the bit line to Vpi is also reduced.

FIG. 5 illustrates a layout of a conventional single bit line NAND flash memory device of FIG. 2. Here, the same reference numerals are given to the same components as those of FIG. 2.

Referring to FIG. 5, in the conventional single bit line NAND type flash memory device, since it is difficult to form the bit line a by a general metal process due to high integration, a poly pad layer is formed in the contact (b) region. There is a need for a modified process that uses, which has the problem of adding process steps.

In order to solve this problem, a shared bit line cell technology in which two neighboring strings share one bit line is disclosed in EEPROM device with multiple of memory strings made of US Pat. No. 4,962,481. It has been proposed in floating gate transistors connected in series.

Fig. 6 shows a circuit diagram of a NAND type flash memory device using the conventional shared bit line and self-boosting technique described in the above patent. Here only two string blocks 30 are shown connected to each of the two bit lines B / L1 and B / L2.

Referring to FIG. 6, two strings of the string block 30, that is, the first and second strings 30a and 30b are shared in one bit line. The first string 30a is formed by sequentially connecting first and second bit line select transistors M1 and M2, a plurality of unit memory cells MC1 to MC16, and a first source line select transistor M5 in series. Each bit line is connected between the bit lines B / L1 and B / L2 and the source line CSL. In addition, the second string 30b may be sequentially connected to third and fourth bit line select transistors M3 and M4, a plurality of unit memory cells MC17 to MC32, and a second source line select transistor M6 in series. And is connected between the bit lines B / L1 and B / L2 and the source line CSL.

7A to 7C are timing diagrams illustrating a method of driving a NAND type flash memory device using the shared bit line and the self-boosting technique of FIG. 6. Here, FIG. 7A is a driving condition in the erase operation, FIG. 7B is a driving condition in the program operation, and FIG. 7C is a driving condition in the read operation.

Referring to FIGS. 7A to 7C, the operation of a NAND flash memory device using the shared bit line and the self-boosting technique of FIG. 6 will be described.

In the erase operation, the electrons of the floating gate of the cell connected to all the word lines W / L1 to W / L16 in the string including the selected cell C are erased. Referring to FIG. 7A, in the erase operation, an erase voltage Vers of about 20 V is applied to a bulk in which a cell array is formed, and a ground voltage 0 V is applied to word lines W / L 1 to W / L16 of a selected string. Is applied, and the erase voltage Vers is applied to the bit line select lines SSL1 and SSL2 and the source line select line GSL. At this time, the word lines (not shown), bit lines B / L1, B / L2, and common source line CSL of the unselected string are floated. Accordingly, due to the voltage difference between the erase voltage Vers applied to the bulk and the ground voltage 0 V applied to the word lines of the selected string, the electrons of the floating gate are erased through the tunnel oxide so that the threshold voltage of the cell is-. As low as 3V.

The program operation includes a precharge operation for precharging an unselected bit line to prevent a disturb phenomenon in which an unselected cell is programmed during programming, a program operation, and a program operation to determine whether the selected cell is programmed. This is done by a program verify operation that leads the cell.

Referring to FIG. 7B, in the program operation, the supply voltage Vcc is first applied to the bit lines B / L1 and B / L2, and the supply voltage Vcc is supplied to all the word lines W / L1 to W / L16. The voltage applied to the bit lines B / L1 and B / L2 is precharged to the channel of the cell by applying a Vpass voltage higher than the voltage Vcc and lower than the program voltage Vpgm. Subsequently, the program voltage Vpgm is applied to the selection word line W / L2, the ground voltage (0 V) is applied to one of the bit line selection lines, and the ground voltage is applied to the selection bit line B / L1. The precharge voltage induced in the channel of the cell C is discharged through the bit line B / L1 to maintain 0V. In addition, electrons are injected from the bulk into the floating gate through the tunnel oxide by the program voltage Vpgm of about 18V applied to the selection word line W / L2, thereby changing the threshold voltage of the selection cell C to about 1V. do.

At this time, the unselected cells connected to the select word line W / L2 are stressed. However, these unselected cells are electrically connected to the bit lines B / L1 and B / L2 and the source line CSL by voltages applied to the bit line select lines SSL1 and SSL2 and the source line select line GSL. Separated and floated, and in this floated state by the Vpass and Vpgm voltages applied to the unselected word line (W / Ln, n is 1 to 16, n ≠ 2) and the selected word line (W / L2). The channel voltage of the unselected cells is self boosted above the supply voltage Vcc. Thus, since a predetermined self-boosted voltage is maintained in the channel of the unselected cells during the program time, tunneling from bulk is prevented from being programmed in the unselected cell. Thereafter, the program verify operation for reading each cell to find out whether the selected cell has been programmed is the same as the read operation described below, and thus will be omitted.

Referring to FIG. 7C, the read operation for reading the state of the cell data includes about 0.7 V on the bit line B / L1, the bit line select line SSL1, and the unselected word line W / Ln, where n is 1. To 16, n ≠ 2, supply voltage Vcc to source line select line GSL, ground line to bit line B / L2, bit line select line SSL2, and select word line W / L2. By applying. At this time, when the threshold voltage of the selected cell is programmed to be 0V or more, the current of the bit line does not flow through the cell. When the threshold voltage of the selected cell is erased to 0V or less, the bitline current flows through the cell. . Accordingly, the cell data is stored in the page buffer (not shown), and the stored data are sensed and amplified in the sense amplifier sequentially sequentially bit by bit.

FIG. 8 shows a layout of a NAND type flash memory device using the shared bitline and self-boosting technique of FIG. 6. Here, the same reference numerals are given to the same components as those of FIG. 6, and only one string block connected to one bit line is illustrated.

In the above-described conventional shared bit line NAND flash memory device, since two neighboring strings share one bit line, the density can be improved, and a self-boosting program method and a sensing scheme using a page buffer can be employed. There is an advantage.

However, there is a problem that the resistance of the source line is increased because the length of the active region forming the source line is increased and the width is decreased according to the high integration. Accordingly, the cell current is reduced by the source line bias during the read operation, thereby causing a malfunction.

9 is a circuit diagram illustrating another example of a NAND flash memory device using a shared bit line and a self-boosting technique, and FIG. 10 is a layout of the NAND flash memory device of FIG. 9. . Here, only two string blocks are shown, and only one string block is described because a plurality of string blocks are arranged in two dimensions.

9 and 10, each string block 40 includes a first string 40a and a second string 40b, and the first string 40a includes a first bit line select transistor M1, A plurality of unit memory cells MC1 to MC16 and a plurality of source line select transistors M2 and M3 are sequentially connected in series, and the second string 40b includes a second bit line select transistor M4 and a plurality of The unit memory cells MC17 to MC32 and the plurality of source line select transistors M5 and M6 are sequentially connected in series.

One end of the first and second strings 40a and 40b is connected to the first line L1 through a bit line contact C1, and the other end thereof is connected to a second line (C2) through a source line contact C2. L2), and the first line L1 is connected to one end of two strings through a source line contact of a neighboring string block, and the second line L2 is a bit of a neighboring string block (not shown). It is connected to one end of two adjacent strings through a line contact.

Here, the first and second bit line select transistors M1 and M4 and the source line select transistors M2 and M6 may be configured as enhancement type NMOS transistors, and the first and second bit line select transistors may be used. Bit line select lines SSL are connected to the gates of M1 and M4, and source line select transistors M3 and M5 are formed of a depletion type NMOS transistor.

In addition, word lines W / L1 to W / L16 are connected to control gates of the plurality of unit memory cells MC1 to MC16 of the first and second strings 40a and 40b, respectively. The first source line select line GSL1 is connected to the gates of M2 and M5, and the second source line select line GSL2 is connected to the gates of the other source line select transistors M3 and M6.

In the bit line contact C1, a PNP type bipolar transistor BP is formed to amplify a cell current. The base is connected to one end of the bit line select transistors M1 and M4, and the emitter is connected to the first line (1). It is connected to L1), and the collector is connected to the P-type bulk in which the string block is formed.

FIG. 11 is a vertical cross-sectional view taken along line AA ′ of FIG. 10, wherein reference numeral 21 is a P-type substrate, 23 is an n-well, 25 is a pocket p-well, M1 is a first bit line select transistor, and MC1 to MC16 are shown in FIG. Unit memory cells, M2 and M3 are source line select transistors, 27 a floating gate, 29 a control gate, 31 a source or drain, 33 a second line, 35 an emitter of a bipolar transistor, 37 a base of a bipolar transistor , 39 is the first line. Here, the impurity of the base 37 of the bipolar transistor is of the same type as that of the source or drain 31, and the concentration of the base 37 is ion implanted to be lower than the concentration of the source or drain 31.

12A through 12C are timing diagrams illustrating a method of driving the flash memory device illustrated in FIGS. 9 and 10.

Referring to FIG. 12A, an erase operation for erasing electrons in a memory cell to set the threshold voltage Vth in the cell to about -3V selects an erase voltage Vers of about 20V in the bulk in which the memory cell array is formed. Line SSL alc The same voltage as the erase voltage Vers is applied to the plurality of source line select lines GSL1 and GSL2, and 0V is applied to the select word line W / L2 connected to the select cell D. In this case, a voltage equal to the erase voltage Vers is applied or floated to the unselected word lines W / Ln, where n is 1 to 16 and n ≠ 2, and the first and second lines L1, Float L2).

By doing so, electrons in the floating gate of the memory cell selected by the selection word line W / L2 are moved to bulk and erased, so that the threshold voltage of the selected memory cell becomes -3V.

Next, referring to FIG. 12B, when selecting and programming a cell located in the second string 40b of FIG. 9, for example, cell D, the first line L1 operates as a bit line and the second line L2. This source line will operate.

First, the supply voltage Vcc is applied to the first and second lines L1 and L2, the bit line select line SSL, and the plurality of source line select lines GSL1 and GSL2, and all the word lines W / L1. To a plurality of memory cells MC1 to MC16 and MC17 to MC32 by applying a voltage Vpass higher than the supply voltage Vcc or the supply voltage Vcc and lower than the program voltage Vpgm to W / L16 for a predetermined time. Precharge the channel region.

Next, among the plurality of word lines W / L1 to W / L16, a program voltage Vpgm of about 18V is applied to the selected word line W / L2, and the unselected word lines W / Ln and n are 1 to 1, respectively. At 16, n ≠ 2, the Vpass is continuously applied to self-boost the channel region of the memory cell connected to the selected word line W / L2 above the precharge voltage. Herein, the voltage Vpass lower than the program voltage Vpgm is applied to the unselected word lines W / Ln, where n is 1 to 16 and n ≠ 2, whereby the selection string, that is, the second string 40b of the second string 40b is applied. Unselected cells are prevented from being programmed.

Next, a voltage applied to the bit line select line SSL and the first source line select line GSL1 to discharge the boosted voltage to the selection string, that is, the memory cell of the second string 40b, is supplied to the supply voltage Vcc. By lowering to 0V, only the second string 40b is connected to the source line, that is, the second line L2. In this case, the source line selection transistor M2 is turned off by 0V applied to the first source line selection line GSL1, so that the first string 40a is not connected to the second line L2.

Subsequently, the channel voltage of the second string 40b is discharged to the second line L2 by lowering the voltage applied to the second line L2 operating as the source line from the supply voltage Vcc to 0V. As a result, electrons are injected from the bulk into the floating gate through the tunnel oxide film by the program voltage Vpgm applied to the selection word line W / L2 to be programmed. Thus, the threshold voltage of the selected cell D is shifted by about + 1V. At this time, in the first string 40a, the boosted channel voltage reduces the voltage difference from the program voltage Vpgm applied to the selection word line W / L2, thereby preventing unwanted cells from being programmed.

In addition, referring to FIG. 12C, the read operation includes supply voltages to the bit line SSL, the second source line select line GSL2, and the unselected word line W / Ln, where n is 1 to 16 and n ≠ 2. (Vcc), a voltage of about 1.5V is applied to the first line (L1), 0V to the second line (L2), the selection word line (W / L2) and the first source line selection line (GSL1). Apply.

Accordingly, when the selection cell D is erased (threshold voltage is about -3V), the cell current flows through the source line, that is, the second line L2, and the selection cell is programmed (threshold voltage + 1V). In this case, no cell current flows through the second line L2. At this time, the sense amplifier (not shown) senses the voltage value of the bit line, that is, the first line L1, and reads the cell data.

Since the PNP type bipolar transistor BP is formed in the bit line contact C1, when the cell current flows through the source line, that is, the second line L2, the cell current is increased by the base current of the bipolar transistor BP. do. Accordingly, the collector current amplified by the gain of the bipolar transistor BP flows through the bit line, that is, the first line L1, and thus the speed of sensing by the sense amplifier is increased, and the memory cell in the unit string is increased. The number can be increased.

However, the voltage boosted to the channel when one string is conventionally composed of 16 memory cells Vchannel = {(Vpass * Cr ') * 15+ (Vpgm * Cr') * 1} / 16 [At this time, Cr ' = Ct /

(Ct + Cchannel), Ct = {(Cinterpoly cap. * Ctunnel oxide cap.) / (Cint-erpoly cap. + Ctunnel oxide cap.)} Of the unit cell, and Cchannel is the Cchannel cap. + Cj− of the unit cell. unction cap. (about 1/2 of the source / drain junction). In contrast, when the unit string consists of 32 memory cells, the voltage induced in the channel during programming Vchannel = {((Vpass * Cr ') * Since 31+ (Vpgm * Cr ') * 1} / 32, the ratio of applying the program voltage (Vpgm) of about 18V to the Vpass voltage of about 10V is applied to the boosted word line voltage compared to the 16-stage cell. Relatively low.

Therefore, the boosted channel voltage decreases as the number of cells in the string increases, which causes a problem in that the unselected cell is programmed due to a lowered channel voltage during programming.

Accordingly, the present invention proposed to solve the above-described problem, to provide a method of driving a flash memory device that can prevent the disturb phenomenon that the unselected memory cells are programmed by a lower channel voltage when programming the selected memory cells. Its purpose is to.

1 is a vertical cross-sectional view of a unit string of a conventional single bit line NAND flash memory device.

FIG. 2 is a circuit diagram of the single bit line NAND flash memory device of FIG. 1. FIG.

3 is a timing diagram illustrating a method of driving a single bit line NAND flash memory device of FIG. 1;

4A through 4B are timing diagrams illustrating a method of driving the single bit line NAND flash memory device of FIG. 2 when using the self-boosting technique.

5 is a layout of the single bit line NAND flash memory device of FIG.

6 is a circuit diagram illustrating an example of a NAND type flash memory device using a conventional shared bit line and a self-boosting technique.

7A through 7C are timing diagrams illustrating a method of driving a NAND flash memory device using the shared bit line and the self-boosting technique of FIG. 6.

8 is a layout of a NAND type flash memory device using the FIG. 6 shared bit line and self-boosting technique.

9 is a circuit diagram showing another example of a NAND type flash memory device using a conventional shared bit line and a self-boosting technique.

10 is a layout of a NAND-type flash memory device using the FIG. 9 shared bit line and self-boosting technique.

11 is a vertical cross-sectional view taken along a line A-A 'of a NAND-type flash memory device using the shared bitline and self-boosting technique of FIG.

12A through 12C are timing diagrams illustrating a method of driving a NAND flash memory device using the shared bit line and the self-boosting technique of FIG. 9.

13 is a circuit diagram showing the configuration of a NAND-type flash memory device according to an embodiment of the present invention.

FIG. 14 is a timing diagram illustrating a method of driving a NAND flash memory device according to an exemplary embodiment of FIG. 13.

(Configuration)

According to a feature of the present invention for achieving the above object, the string block, the first string and the second string in which a plurality of bit line selection transistors, a plurality of unit memory cells, a plurality of source line selection transistors are sequentially connected in series And a plurality of bit line selection lines respectively connected to gates of the plurality of bit line selection transistors of the first and second strings, and a plurality of words connected to control gates of the respective memory cells of the first and second strings. A line and a plurality of source line selection lines respectively connected to gates of the plurality of source line selection transistors of the first and second strings, and like the string block, a plurality of bit line selection transistors and a plurality of unit memory cells A plurality of source line select transistors are sequentially connected in series A first string and a second string, a plurality of bit line select lines connected to gates of the plurality of bit line select transistors of the first and second strings, respectively, and control of each memory cell of the first and second strings Another string block including a plurality of word lines connected to gates and a plurality of source line selection lines connected to gates of the plurality of source line selection transistors of the first and second strings, respectively, may be used. The first line connected to one end of the first string and the second string of the string block and the other string block, respectively, is configured symmetrically by sharing a bit line contact to which one end of two strings are connected. Two strings of other string blocks that are symmetrically configured by sharing the bitline contacts of the string block and its neighboring string blocks. A second line connected to a source line contact to which one end of the string is connected, and a second line connected to the other end of the first and second strings of the string block and another string block through a source line contact, and another neighboring string. A bitline contact of a block and another neighboring string block is shared to a bitline contact to which one end of two strings of another string block symmetrically configured is connected, the string block and the other string block being formed in bulk A method of driving a flash memory device in which a string cell and another string block are two-dimensionally arranged to form a memory cell array, the method comprising: erasing an erase voltage to the bulk and a plurality of bit lines configured in the string block and the other string block, respectively A voltage equal to the erase voltage on a selection line and the plurality of source line selection lines; The erase operation is performed by applying a voltage to a selected word line of the plurality of word lines of the string block, and first, supply voltages to the first and second lines, and a plurality of string blocks and other string blocks respectively. Precharges the channel region of the memory cell by applying a supply voltage Vcc to a plurality of bit line selection lines, the plurality of source selection lines and the plurality of word lines for a predetermined time, and then The program voltage Vpgm is applied to a selected word line and a plurality of word lines of the other string block among the word lines, and the program is selected to a non-selected word line of the string block and a plurality of bit line select lines of the string block and another string block. A channel of a memory cell connected to the selected word line by applying a voltage Vpass that is lower than the voltage and higher than the supply voltage. After self-boosting the inverse above the precharge voltage, the non-selection of the plurality of source line select lines of the string block to discharge the boosted voltage of the memory cells of the selected string of the first and second strings of the string block. The program operation is performed by applying 0V to a string and a plurality of bit line select lines, and 0V to a source line of a selected bit line among the first and second lines.

In a preferred embodiment of this method, when one of the first and second lines operates as a bit line, the other operates as a source line.

In a preferred embodiment of this method, during the erase operation, a voltage equal to the erase voltage is applied to an unselected word line among a plurality of word lines of the string block and another string block.

In a preferred embodiment of this method, in the erase operation, the first line and the second line are floated.

(Action)

By such a method, it is possible to prevent the disturb phenomenon in which the unselected memory cells are programmed by the lowered channel voltage when programming the selected memory cells.

(Example)

Best Mode for Carrying Out the Invention Embodiments of the present invention will be described in detail below with reference to FIGS. 13 and 14.

In FIG. 13, the same reference numerals are given to components that perform the same functions as the components of the flash memory device illustrated in FIGS. 1 to 11.

13 is a circuit diagram of a NAND flash memory device according to a preferred embodiment of the present invention.

In a flash memory device according to an embodiment of the present invention, a plurality of string blocks are arranged two-dimensionally, and another string block is symmetrically shared by sharing bit line contacts of the plurality of string blocks two-dimensionally arranged, respectively. In the present invention, only one string block and the other string block symmetrically configured by sharing the bit line contact of the one string block will be described.

Referring to FIG. 13, each string block 50 of a flash memory device according to an embodiment of the present invention includes a first string 50a and a second string 50b.

The first string 50a includes a first bit line select transistor M1, a plurality of unit memory cells MC1 to MC16, and a plurality of source line select transistors M2 and M3 in series. The second string 50b includes a second bit line select transistor M4, a plurality of unit memory cells MC17 to MC32, and a plurality of source line select transistors M5 and M6, which are sequentially connected in series.

In addition, each of the other string blocks 50 'symmetrically configured by sharing a bit line contact C1 connected to one end of two strings 50a and 50b of each of the string blocks 50 is similar to the first string 50a'. ) And a second string 50b '.

The first string 50a 'includes a first bit line select transistor M1', a plurality of unit memory cells MC1 'through MC16', and a plurality of source line select transistors M2 'and M3'. The second string 50b 'includes a second bit line select transistor M4', a plurality of unit memory cells MC17 'through MC32', a plurality of source line select transistors M5 ', M6 ') is configured by serially connecting.

One end of the first and second strings 50a and 50b of the string block 50 is connected to the first line L1 through a bit line contact C1, and the other end is connected to a source line contact C2. The first and second strings 50a 'and 50b of another string block 50', which are connected to the second line L2 and share a bit line contact C1 of the string block 50 and are symmetrically configured. One end of ') is connected to the first line L1 through a bit line contact C1' and the other end is connected to a second line L2 through a source line contact C2 '.

In addition, the first line L1 connected to the bit line contacts C1 and C1 'of the string block 50 and the other string block 50' is a source line of a neighboring string block of the string block 50. A source line contact C2 of the string block 50 and the other string block 50 'is connected to one end of two strings through a source line contact of a neighboring string block of the other string block 50'. , C2 ', the second line L2 connects the bit line contact of another neighboring string block of the string block 50 and the bit line contact of another neighboring string block of the other string block 50'. Through one end of the two strings.

The first and second bit line select transistors M1 and M4 of the string block 50 and the first and second bit line select transistors M1 'and M4' of the other string block 50 'are enhanced. It is composed of a type NMOS transistor, and bit line select lines SSL and SSL 'are connected to gates of the first and second bit line select transistors M1, M1', M4, and M4 '.

The first source line selection lines GSL1 and GSL1 'are connected to gates of the source line selection transistors M2, M2', M5, and M5 'of the string block 50 and the other string block 50'. The second source line select lines GSL2 and GSL2 'are connected to gates of the other source line select transistors M3, M3', M6, and M6 ', and the source line select transistors M2, M2', M6, and M6 are connected to the gates of the source line select transistors M3, M3 ', M6, and M6'. ') Is composed of an enhancement NMOS transistor, and the source line select transistors M3, M3', M5, and M5 'are composed of an enhancement NMOS transistor and a deflection type NMOS transistor having a different threshold voltage.

In addition, PNP-type bipolar transistors BP are formed in the bit line contacts C1 and C1 'of the string block 50 and the other string block 50' to amplify the cell current. The base is connected to one end of the bit line select transistors M1, M4, M1 ', and M4' of the string block 50 and the other string block 50 ', and the emitter is connected to the first line L1. The collector is connected to the bulk in which the string block is formed.

FIG. 14 illustrates a method of driving a flash memory device according to an exemplary embodiment of FIG. 13. Here, since the erase operation and the read operation are the same as those of the conventional bipolar bit line cells as shown in FIG. 9, only the program operation will be described.

The program operation includes the operation of precharging the bit line and the operation of programming the memory cell at the same time as discharging the precharge voltage of the selected bit line.

First, the precharge operation may include all bit lines B / L1, B / L2, B / L3, and B / L4, word lines W / L1 to W / L16, and bit lines of the string block 50. FIG. The supply voltage Vcc is applied to the selection line SSL and the source line selection lines GSL1 and GSL2, and at this time, another string block 50 'symmetrically configured by sharing a bit line contact with the string block 50. By applying the supply voltage Vcc to the bit line selection line SSL ', the word line W / Ln', and the source line selection lines GSL1 'and GSL2', the word line of the selection string is shared. A channel region connected to different bit line selection lines sharing the channel region and the bit line contact is also precharged below the supply voltage.

Next, a program voltage Vpgm of about 18V is applied to the selected word line W / L2, and a Vpass voltage of about 10V is applied to an unselected word line W / Ln, where n is 1 to 16 and n ≠ 2. The Vpass voltage is applied to the bit line select lines SSL and SSL ', and the program voltage to the unselected word line W / Ln of another string block 50' connected to the bit line by the bit line select line SSL '. Boost the channel region above the precharge voltage by applying a constant voltage between (Vpgm) or the program voltage (Vpgm) and Vpass voltage.

In this case, the boosting voltage Vchannel induced in the channel region is represented by the following equation.

Wherein Cr '= Ct / (Ct + Cchannel), Ct = (Cinterpoly cap. * Ctunnel oxide cap.) / (Cinterpoly cap. + Ctunnel oxide cap.), And Cchannel = (Cchannel cap.) / (Cjunction cap.) And the Cjunction cap. Is about one half of the source-drain junction.

As shown in Equation 1, the boosting voltage is applied to the n-type base of the bipolar transistor formed in the bit line, and a reverse bias is applied between the p-type emitter and the p-type collector so that the bit line is applied. The discharge phenomenon does not occur, and the voltage induced in the channel of the selection bit line cannot be increased further due to Vpass of the bit line selection lines SSL and SSL '.

Subsequently, 0V is applied to the source line selection lines GSL1 'and GSL2', the source line selection line GSL1, and the bit line selection lines SSL and SSL ', and operates as a source line of the selected cell. When 0 V is applied to the line L2, that is, B / L1, the channel region of the selected cell is discharged to 0 V, and electrons are tunneled from the bulk by the program voltage Vpgm of the selected word line W / L2. It is programmed by injection into the floating gate through. Thus, the threshold voltage of the selected cell E is shifted by about + 1V.

In this case, since the boosted channel voltage reduces the voltage difference with the program voltage Vpgm applied to the selection word line W / L2, unwanted cells are prevented from being programmed.

By this method, by using the increased read current by applying the bipolar bit line, the unselected cells in the program operation when increasing the number of cells connected per unit string from 16 to 32 or more than 64 conventionally This can greatly reduce stress.

Claims (4)

The string block includes a first string and a second string in which a plurality of bit line selection transistors, a plurality of unit memory cells, and a plurality of source line selection transistors are sequentially connected in series, and a plurality of bit lines of the first and second strings. A plurality of bit line select lines respectively connected to gates of a selection transistor, a plurality of word lines connected to control gates of respective memory cells of the first and second strings, and a plurality of sources of the first and second strings A plurality of source line selection lines connected to gates of the line selection transistors, and a plurality of bit line selection transistors, a plurality of unit memory cells, and a plurality of source line selection transistors are sequentially connected in series like the string block. A first string and a second string, and the first and second strings A plurality of bit line selection lines respectively connected to gates of the plurality of bit line selection transistors, a plurality of word lines connected to control gates of the memory cells of the first and second strings, and the first and second strings Another string block composed of a plurality of source line select lines respectively connected to the gates of the plurality of source line select transistors of the plurality of source line select transistors is configured to be symmetrical by sharing bit line contacts to which one end of the first and second strings of the string block are connected; The first line connected to one end of the first string and the second string of the string block and the other string block through the bit line contact, respectively, share the bit line contacts of the neighboring string block and the neighboring string block symmetrically. Each of the two strings of the other string block that is configured is connected to a source line contact to each other. And a second line connected to the other end of the first and second strings of the string block and another string block via a source line contact is a bit line of another neighboring string block and another neighboring string block. A contact is connected to a bitline contact to which one end of two strings of another string block symmetrically configured is connected, the string block and the other string block are formed in bulk, and the string block and the other string block are two-dimensionally A method of driving a flash memory device in which an array of memory cells is arranged, wherein the erase voltage is applied to the bulk, and the plurality of bit line selection lines and the plurality of source line selection lines respectively configured in the string block and the other string block are arranged in the memory cell array. A voltage equal to an erase voltage is selected from a plurality of word lines of the string block; An erase operation is performed by applying 0 V to a draw line, and first, supply voltages to the first and second lines, a plurality of bit line select lines, the plurality of source select lines configured in each of the string block and the other string block, After precharging a channel region of a memory cell by applying a supply voltage Vcc to the plurality of word lines for a predetermined time period, a plurality of selected word lines and a plurality of other string blocks among the plurality of word lines of the string block are precharged. The program voltage Vpgm is applied to the number of word lines, and the voltage Vpass lower than the program voltage and higher than the supply voltage is applied to unselected word lines of the string block and a plurality of bit line select lines of the string block and other string blocks. After self-boosting the channel region of the memory cell connected to the selected word line above the precharge voltage, One of the first and second strings of the string block corresponds to an unselected string of the plurality of source line select lines of the string block and 0V to the plurality of bit line select lines to discharge the boosted voltage of the memory cells of the selected string. The method of claim 1, wherein a program operation is performed by applying 0 V to a source line of a selected bit line among the first and second lines. The method of claim 1, wherein when one of the first and second lines operates as a bit line, the other operates as a source line. The method of claim 1, wherein, during the erase operation, a voltage equal to the erase voltage is applied to an unselected word line among a plurality of word lines of the string block and another string block. The method of claim 1, wherein the first line and the second line are floated during the erase operation.