KR19980019711A - Method of manufacturing nonvolatile semiconductor memory device - Google Patents

Abstract

The present invention relates to a nonvolatile semiconductor memory device in which a floating gate for storing data and a control gate capable of controlling and biasing the stacked gate are stacked, wherein the length of the source junction overlapped below the floating gate in the semiconductor substrate is the floating of the drain junction. Shorter than the gate overlap, the thickness of the gate bird's beak in the region where the floating gate overlaps the source and drain is made thicker in the drain region than the source region.

Description

Method of manufacturing nonvolatile semiconductor memory device

The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a method of manufacturing a high speed flash memory device.

A semiconductor memory device, particularly a flash memory device that writes data by injecting electrons into a floating gate defined as a floating node by an electrical signal, or erases data by emitting electrons from a floating gate. The operation of is performed by applying a high voltage generated at a circuit pumped from a single power supply of 5V or 3.3V applied to an external node to each node of 쎌. In general, a program operation of injecting electrons into a floating gate of a noah type flash memory applies a voltage of about 6V to a drain and a voltage of about 10V to a control gate that controls the floating gate. The potential of the common source line and bulk is grounded, and the high voltages applied to the drain and control gates cause the memory cell's operating mode to saturate and flow from the source region to the drain. In the electron, hot electrons having high energy in the depletion region near the drain are injected into the floating gate to be programmed, thereby increasing the threshold voltage of the memory 쎌. In addition, the erasing operation for erasing data in the memory cell is performed by removing electrons from the floating gate, which is generally performed in bulk or sector units. A high voltage of about 12V is applied to a common source line, and the control gate is 0V. Electrons in the floating gate are emitted to the source region by an electric field through a tunneled tunnel oxide where the region and the floating gate overlap. In order to prevent a punch through phenomenon when the high voltage is applied to the source junction, the drain junction should be a floating node. The high voltage is applied to the source junction to erase the data of the memory cell. In the region where the source junction and the floating gate overlap, a thin tonel oxide film generates only a band-to-band tunnel current between the layers. Rather, most of the electrons in the electron-hole pairs generated during operation are lost to the source, but the hole is trapped in the oxide film, which lowers or damages the potential barrier, which causes a problem of inferior reliability. . In order to overcome this problem, a low voltage of about 5V is applied to the source junction and a negative bias of about -10V is applied to the control gate to erase data of the memory chip. Since it is applied, there is an advantage that the capacity generated in the internal pumping circuit can be reduced, and since the turnnel current between the film and the film is also reduced, damage to the turnnel oxide film during the erase operation is also reduced. Since the erase operation by the above two methods is performed through the high concentration source junction and the floating gate through the turnnel oxide film in the overlapped region, the degree of overlap may cause a significant problem in the erase operation. In particular, when the overlap of source junctions is less, the spread of the erased pins becomes severe. Among them, when the over erased pins are over erased, the misreading is sensed as ON on reading the data. Will cause problems. The programming and erasing operation of the noah type flash memory chip is performed quickly. When a voltage of a predetermined level generated in an internal circuit is applied to each node of the memory chip, a floating gate and a control gate are applied. If the thickness of the Interpoly Oxide Nitride Oxide Layer (hereinafter referred to as "Oeno Film") is thin or can increase the dielectric capacity by increasing the area, the program speed can be improved. It is a reality that it is difficult to change the dielectric capacity of the interpoly because the increase in area is almost fixed in the design of the fin. Then, there may be a method of increasing the thickness of the tunneling oxide or reducing the area of the active region in which the tunneling oxide is grown. However, increasing the thickness of the tunneling oxide film has a problem in that the overall thickness of the tunneling oxide film is problematic because it decreases the speed of the erase operation performed by the Fowler-Nordheim (F-N) turnneling. 1 is a vertical sectional view of a flash memory chip according to the prior art. Referring to FIG. 1, a turnnel oxide film 11 is formed on a well 10 formed by doping impurities on a semiconductor substrate or a substrate, a floating gate 13 is formed on an upper surface of the turnnel oxide film 11, and an upper surface of the floating gate 13 is formed. An ohno film 15 having a three-layer structure of an oxide film / nitride film / oxide film is formed, and a control gate 17 formed of polyside is formed on an upper surface thereof. Thereafter, patterning is performed using dry etching, and oxide layers 21 and 31 are simultaneously formed on the wells 10 at both edges of the patterned turnnel oxide layer 11 at predetermined thicknesses, and are opposite to the wells 10 over the entire surface. High concentration ion implantation with impurities. As a result, the source region 20 and the drain region 30 are formed.

SUMMARY OF THE INVENTION An object of the present invention is to improve the program and erase speed of a memory chip and to distribute the threshold voltage of the erased chip in a NOR flash memory device of a stack type, in particular, in which one transistor consists of one chip in a high-speed flash memory device. The present invention provides a method of manufacturing a nonvolatile semiconductor memory device which can improve over erasing by making uniform.

Another object of the present invention is that the gate bird's beak in the region where the source and drain junctions are asymmetric and each of the source and drain regions overlap with the floating gate is thicker and closer to the drain junction than the source junction. The present invention provides a method of manufacturing a nonvolatile semiconductor memory device capable of increasing program efficiency and improving the speed of erasing and the threshold voltage distribution of erasing voltage.

1 is a vertical sectional view of a flash memory shock according to the prior art;

Figure 2 is a vertical sectional view of a flash memory cap in accordance with an embodiment of the present invention.

3A to 3E are cross-sectional views of a process according to the process sequence of FIG. 2.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings. In addition, it should be noted that the same components and parts in the drawings represent the same reference signs wherever possible. In addition, it should be noted that in the following embodiments, only parts necessary for understanding the operation according to the present invention will be described, and descriptions of other parts will be omitted so as not to obscure the subject matter of the present invention.

2 is a vertical sectional view of a flash memory chip according to an embodiment of the present invention. Referring to FIG. 2, a first insulating layer, such as a turnnel oxide layer 11, is formed on a P-type well 10, and a first conductive layer, eg, a floating gate 13, is formed of polysilicon on an upper surface thereof. A second insulating layer, for example, an interlayer insulating layer (OHN film) 15, is formed on the upper portion thereof, and a second conductive layer, for example, a control gate 17, is formed of polycide on the upper surface thereof, and the turnnel oxide layer is formed. A first diffusion region and a second diffusion region, for example, a source region 20 and a drain region 30, are formed below both edges of 11, respectively. It should be noted that the third insulating film 21 and the fourth insulating film 31, which are portions overlapping with the source region 20 and the drain region 30 of the turnnel oxide film 11, are formed to be 150 and 600, respectively. A detailed process will now be described with reference to FIGS. 3 (a) (e).

3A to 3E are cross-sectional views of a process according to the process procedure of FIG. 2. Here, the back and forth process steps that may proceed regardless of the present invention are omitted. Referring to FIGS. 3A to 3E, FIG. 3A illustrates a well 10 for controlling a threshold voltage of a memory cell on a first conductive type, for example, a semiconductor substrate doped with an impurity of a dopant or a well 10 having the same impurity as the substrate. Impurities of the same form Ion implantation at a concentration of about 90 nm, and then a thin first insulating layer, for example, a turnnel oxide layer 11, is grown, and a first conductive layer, for example, is floated by stacking first polycrystalline silicon doped with POCL (Phosphorus Oxychloride). A gate 13 is formed, and then a second insulating film, for example, an interlayer insulating film 15 having a three-layer structure of oxide, nitride, and oxide, that is, an ohno-film structure, for example, an interlayer insulating film 15 is laminated, and then the fockle is doped. Second polycrystalline silicon and tungsten silicide ( ) Are sequentially stacked to form a polycide, thereby forming a second conductive layer, for example, a control gate 17. FIG. 3B illustrates a state in which the control gate 17, the interlayer insulating layer 15, and the floating gate 13 are dry-etched by self-aligning by using a photo mask process. 3C shows an upper surface of a region where a drain is to be formed by applying a photoresist, for example, a photoresist (hereinafter, referred to as PR) 19 as a mask to a portion except a region where a drain is to be formed using the photomask process after the dry etching. A diagram showing a process of ion implantation in. Here, the impurity to be implanted is a arsenic (As) ion of yen type, and the amount of implanted Injection is high enough. The electric field strengthening due to the increase in the concentration of the junction in contact with the well 10 may maximize the generation of hot carriers during the program operation of the memory cell, thereby enhancing the program efficiency. FIG. 3D is a view showing that the third insulating film and the fourth insulating film 21 and 31 are simultaneously formed by a reoxidation process at a low temperature (about 859 ° C.) after ion implantation with a high concentration of impurities in the drain region. Here, a thick oxide film of about 600 (the fourth insulating film) is grown on the drain region 30, and a relatively thin oxide film of about 150 (here, the third insulating film) is formed on the source region 20. FIG. 3E is a view showing a state in which high concentration of arsenic ions are injected into the entire surface of the resultant of FIG. 3D and subjected to high temperature heat treatment. In this case, the source junction and the drain junction are asymmetric and overlap each other with the floating gate 13. Subsequently, although not shown, a subsequent process of stacking an interlayer insulating film made of a high temperature oxide film (HTO) and BPSG (Borophosphosilicate Glass) and opening a contact hole to connect a metal wiring is performed.

According to the present invention, the drain region is ion-implanted at a high concentration, and the oxide film formed on the drain region is formed thicker than the oxide film formed on the source region, and the length of the drain region overlapping the floating gate, that is, the length of the drain junction, is increased. The length of the source region overlapping with the length of the source junction, i.e., the length of the source junction, is longer than that of the source junction, thereby improving fast programming and erasing characteristics, and improving the threshold voltage distribution of the erase pulse.

Claims (17)

A nonvolatile semiconductor memory device in which a first conductive layer for storing data located on a semiconductor substrate or a well of a first conductive type and a second conductive layer for controlling and biasing the same are stacked. A first insulating film formed on the upper surface of the semiconductor substrate or the well to a predetermined thickness; A first conductive layer formed adjacent to the first insulating layer and an upper surface thereof; A second insulating film formed by interviewing the first conductive layer and the second conductive layer; A third insulating film and a fourth insulating film formed on an upper surface of the semiconductor substrate or the well and extending to both edges of the first insulating film to be differentially formed into a first thickness and a second thickness; And a first diffusion region and a second diffusion region formed in the semiconductor substrate under the third insulating layer and the fourth insulating layer, respectively, and having a predetermined distance differentially crossing the lower portion of the first insulating layer. Semiconductor memory device. The nonvolatile semiconductor memory device of claim 1, wherein the first conductive type is a shaped body. The nonvolatile semiconductor memory device of claim 1, wherein the first diffusion region and the second diffusion region are diffusion regions of impurities opposite to the first conductivity type. The nonvolatile semiconductor memory device of claim 1, wherein the third insulating layer and the fourth insulating layer are formed in a bird's beak shape. The nonvolatile semiconductor memory device of claim 1, wherein the first and second diffusion regions are a source region and a drain region, respectively. The nonvolatile semiconductor memory device of claim 1, wherein the second thickness is thicker than the first thickness. The nonvolatile semiconductor memory device of claim 1, wherein the second thickness is four times the first thickness. The nonvolatile semiconductor memory device of claim 1, wherein a distance between the first diffusion region and the second diffusion region is longer than that of the first diffusion region. In the method of manufacturing a nonvolatile semiconductor memory device, Forming a semiconductor substrate of the first conductivity type or an impurity well of the same conductivity type as the substrate; Forming an active region and a separation region on a surface of the semiconductor substrate; Implanting impurities of a first conductivity type into the isolation region and growing a field oxide film; Implanting impurities of a second conductivity type into the active region to adjust the threshold voltage of the memory cell; Forming a first insulating film through deposition; Laminating with first polycrystalline silicon on the first insulating film to form a first conductive layer, Forming a second insulating layer on the first conductive layer by depositing the same and then laminating a second conductive layer by heat-treating a second conductive polycrystalline silicon and tungsten silicide; Simultaneously etching the second conductive layer, the second insulating layer, and the first conductive layer; Implanting ion into a high concentration of second conductive ions using a photosensitive film as a mask on one of the active regions to form a second diffusion region, Simultaneously forming a third insulating film and a fourth insulating film with asymmetrical differential thicknesses by reoxidation after removing the photoresist film; And implanting a high concentration of the second conductivity type ions into the front surface to form a first diffusion region, and performing a high temperature heat treatment. 10. The method of claim 9, wherein the second diffusion region is formed before the formation of the first diffusion region. 10. The method of claim 9, wherein the first conductive type is an etched type. 10. The method of claim 9, wherein the first diffusion region and the second diffusion region are regions diffused with impurities of a type opposite to that of the first conductivity type. 10. The method of claim 9, wherein the third insulating film and the fourth insulating film are formed in a buzz bead. 10. The method of claim 9, wherein the first diffusion region and the second diffusion region are source and drain regions, respectively. 10. The method of claim 9, wherein the second thickness is thicker than the first thickness. 10. The method of claim 9, wherein the second thickness is four times the first thickness. The method of claim 9, wherein the second diffusion region has a longer crossover distance between the first diffusion region and the second diffusion region than the first diffusion region.