KR19980015972A - Method for manufacturing nonvolatile semiconductor memory device - Google Patents

Abstract

The present invention relates to a semiconductor memory device, and more particularly, to a method of manufacturing a nonvolatile semiconductor memory device, and a method of manufacturing a nonvolatile semiconductor memory device for reducing a thermal cycle to improve over-erase characteristics. According to an aspect of the present invention, there is provided a method of manufacturing a volatile semiconductor memory device, including: forming a first conductive type semiconductor substrate or a first conductive type well formed on a semiconductor substrate with a first insulating film and a floating gate sequentially Forming a second insulating film and a control gate on the floating gate in sequence; forming a control gate in a self-aligned manner to form a drive in region after the second conductive type impurity is ion- And a step of growing an oxide film on the semiconductor substrate or the well through a thermal oxidation process performed at a temperature at which the ion implanted impurity is electrically activated.

Description

Method for manufacturing nonvolatile semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a method of manufacturing a nonvolatile semiconductor memory device.

A nonvolatile semiconductor memory device, for example, a flash EEPROM, is a memory device in which data is not permanently stored, even when an electrical signal is not applied, or a program or erase of data by an electrical signal. (Charge) of electrons or discharges of electrons to the floating gate defined as a floating node. The operation of the flash memory cell can be divided into three modes. In the first program operation, a signal of a level boosted by an internal circuit of about 6V is applied to the drain of the cell, and when a high level voltage of about 12V is applied to the control gate, The cell is in the saturation region and moves upward in the direction of high energy generated near the drain. In the second erase operation, the electrons are drawn from the floating gate to the source or the substrate of the cell, and the threshold voltage of the cell is weakened, so that the appropriate potential between the source and the gate or the gate and the substrate is applied. The third read operation is turned on or off according to the current conduction according to the threshold voltage of the memory cell and is read as data 1 or 0.

In these operations, the erase operation causes electrons to be discharged from the floating gate to the source or the substrate, thereby lowering the threshold voltage of the cell. The scattering of the threshold voltage after erasing has a Gaussian distribution, And a cell having a negative threshold voltage exists. This causes an error to be read into the on-cell regardless of the state of the selected cell during the read operation. Also, since a normally-conducting cell is present, a problem arises that an appropriate level of voltage is not applied to the drain of the cell during the program operation.

A split gate type cell structure has been proposed in order to solve the problem of a so-called over-erase cell having a negative threshold voltage. However, this is a cell structure that prevents a malfunction of the over-erased cell and does not reduce over-erase itself.

The over-erase technology known so far relates to the quality of the floating gate made of polysilicon, and the grain size of the polysilicon has a great influence on the distribution of the threshold voltage of the erased cell.

FIG. 1 is a view showing a layout showing a NOR type cell of a general nonvolatile semiconductor memory device, and FIG. 2 is an equivalent circuit diagram of FIG.

In the NOR type cells M1M4, a channel is connected in series between the bit line BL and the ground power supply, and a gate is connected to the word line WL. Such a NOR type cell has a higher driving current than a NAND type cell and exhibits a fast operating speed.

FIGS. 3A to 3E are diagrams sequentially showing process sectional views of a memory cell of a nonvolatile semiconductor memory device cut in a direction A to A 'in FIG. 1 according to the related art.

3A, a first insulating layer 302 and a floating gate 303 (not shown) are formed on a portion of a first conductivity type well (not shown) formed in a semiconductor substrate 301 of a first conductivity type or a semiconductor substrate 301, And then a second insulating film 304 and a control gate 305 are sequentially formed on the floating gate 303. Then, As shown in FIG. 3B, the control gate 305 is ion-implanted (306) with a second conductivity type impurity by self-alignment, and then an oxide film 307 is formed in the oxidizing atmosphere After forming the drain 308 and the source 308 in the drive-in as shown in FIG. 3D, the floating gate 303 and the side surface of the control gate 305, as shown in FIG. 3E, And a spacer 309 including a part of the oxide film 307 are formed.

4A is a view showing the size of a polygrain according to an annealing temperature after annealing a floating poly with polysilicon. The grain size is rapidly increasing between 950 and 1050 degrees. As the polygrain size of the floating gate increases, a local segregation of Ph is generated to lower the resistance to poly at the edge of the grain. The segregated Ph diffuses into the polysilicon / gate oxide film and reacts with Si02 to form an oxide layer Ph-rich SiO2: Oxide ridge). FIGS. 4B and 4C show that Ph is segregated at the polysilicon-gate oxide film interface depending on the grain size.

Since the oxide layer (Ph-rich SiO2) formed at the polysilicon / gate oxide film interface lowers the barrier by Ph or functions as a trap region of electrons, it partially speeds up the erase rate at the time of erasing, Distribution.

4c schematically illustrates formation of an oxide valley (400) within the energy band of the gate oxide due to Ph at the interface between the polysilicon grain and the gate oxide film. When the particle size is large, the number of oxide valleys is reduced. This is because some memory cells have a higher erase speed than other memory cells and do not achieve uniform erase Vth distribution.

In the actual flash memory fabrication process, the polysilicon of the floating gate may be said to exhibit the over-erase phenomenon due to the increase in the grain size of the polysilicon due to the thermal cycle in the subsequent heat treatment process. To prevent this, It is necessary to optimize or minimize the heat treatment, oxidation, and drive-in process of the substrate. In addition, since the flash memory cell charges or discharges electrons through the gate oxide film, a technique of growing a gate bird's beak through reoxidation to increase the reliability of the gate oxide film during the manufacture of a memory cell is generalized .

However, the re-oxidation or heat treatment process can not avoid increasing the grain size of the polysilicon that constitutes the floating gate during oxidation.

Accordingly, it is an object of the present invention to provide a method of manufacturing a nonvolatile semiconductor memory device for reducing a thermal cycle to improve an over-erase characteristic.

It is another object of the present invention to provide a method of manufacturing a nonvolatile semiconductor memory device which can reduce the time required to obtain gate buzzbills or reduce the temperature.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a layout showing a NOR type cell of a general nonvolatile semiconductor memory device; FIG.

Fig. 2 is an equivalent circuit diagram of Fig. 1; Fig.

3 is a view sequentially showing process cross-sectional views of a nonvolatile semiconductor memory device implemented according to a conventional technique;

Fig. 4 is a diagram showing the segregation of Ph according to the size of the polygrain of the floating gate and the grain size thereof according to the annealing temperature in the prior art. Fig.

5 is a view sequentially showing process cross-sectional views of a nonvolatile semiconductor memory device implemented according to the present invention;

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Also, it should be noted that the same components and parts of the drawings indicate the same reference numerals as possible whenever possible.

FIGS. 5A through 5E sequentially show process cross-sectional views of a memory cell of a nonvolatile semiconductor memory device cut in a direction A to A 'in FIG. 1 according to an embodiment of the present invention.

5A, a first insulating layer 302 and a floating gate 303 (not shown) are formed on a portion of a first conductivity type well (not shown) formed in a semiconductor substrate 301 of a first conductivity type or a semiconductor substrate 301 And then a second insulating film 304 and a control gate 305 are sequentially formed on the floating gate 303. Then, 3B, a process of forming a drive inductor 308 in a nitrogen N2 atmosphere by ion-implanting an impurity of the second conductivity type by self-aligning the control gate 305, An oxide film 307 is grown on the semiconductor substrate or the well through a thermal oxidation process performed at a temperature at which impurities are electrically activated, for example, at a temperature between 800 DEG C and 900 DEG C, and the floating gate 303 and the control The memory cell is fabricated by the process of forming the spacer 309 including the side surface of the gate 305 and a part of the oxide film 307. [

The second insulating layer 304 may be formed of a silicon oxide layer formed by a thermal oxidation process, a silicon nitride layer formed by a chemical vapor deposition process, and a second insulating layer formed by a thermal oxidation process. It is an insulating film of ONO structure made of a silicon oxide film. Further, the floating gate 303 and the control gate 305 are formed by a process of depositing polycrystalline silicon. The first conductivity type described above is a conductive type formed by a feature type impurity and the second conductivity type is a conductive type formed by a yen type type impurity.

The oxide film thickness after the reoxidation of the high concentration N + ion implanted region in the memory cell processed in the process sequence shown in the present invention is formed to be twice as thick as the oxide film thickness of the memory cell which has been processed in the conventional process under the same conditions. This indicates that, even if the reoxidation is carried out at the same temperature and at the same time, progressing to the process sequence shown in the present invention can reduce the time or temperature for obtaining a specific gate buzz big.

As described above, the present invention has an advantage that it is possible to reduce the time for obtaining the gate buzz big or reduce the temperature. The present invention also has the advantage of reducing the grain size of the floating gate by reducing the thermal cycle of the subsequent heat treatment process, thereby improving over-age characteristics.

Claims (4)

A method of manufacturing a nonvolatile semiconductor memory device, comprising: Sequentially forming a first insulating film and a floating gate on a portion of a well of a first conductivity type formed in a semiconductor substrate of a first conductivity type or a semiconductor substrate, Sequentially forming a second insulating film and a control gate on the floating gate, Implanting impurities of a second conductivity type into the control gate by self-alignment and forming a drive-in impedance; And growing an oxide film on the semiconductor substrate or the well through a thermal oxidation process performed at a temperature at which the ion implanted impurity is electrically activated. 2. The method of claim 1, further comprising forming a spacer including a side surface of the floating gate and the control gate and a portion of the oxide film. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the temperature at which the thermal oxidation process is performed is a temperature between 800 캜 and 900 캜. The nonvolatile semiconductor memory device according to claim 1, wherein the second insulating film is an insulating film of ONO structure formed of a silicon oxide film formed by a thermal oxidation process, a silicon nitride film formed by chemical vapor deposition, and a silicon oxide film formed through a thermal oxidation process A method of manufacturing a semiconductor memory device.