KR102766867B1 - Apparatus and Method for time synchronization in linkage with master clock - Google Patents

Abstract

A master clock-linked time synchronization device capable of improving the synchronization precision of oscillation pulses within each facility and ensuring continuity and stability even when a temporary problem occurs in communication with a master clock is disclosed. The time synchronization device is characterized by including a receiver which generates a first reference clock signal, a clock signal generator which generates a second reference clock signal which is heterogeneous with the first reference clock signal, a selector which selects the first reference clock or the second reference clock signal, a comparator which compares the first reference clock or the second reference clock with a current synchronous clock signal which is generated in advance, a controller which generates a control output signal for synchronous control according to a result of the comparison, a converter which converts the control output signal into a numerical value-to-voltage value to generate a converted output value, and an oscillator which simultaneously synchronizes a phase and a frequency with the converted output value to generate a final synchronous clock signal.

Description

{Apparatus and Method for time synchronization in linkage with master clock}

The present invention relates to a time synchronization technology, and more specifically, to a time synchronization device and method that enable operation of a signal sampling operation in an optimized form to simultaneously synchronize phase and frequency with a master clock to achieve master clock-tracking time synchronization within an internal oscillator.

First, let me explain the key terms:

- Time synchronization: aligning the time of multiple devices (clients) to a single reference time (time server)

- Intelligent Electronic Device (IED):

It is a power system protection device that generally receives analog signals such as transmission and distribution lines, generators, load voltage and current, processes the signals to detect whether an accident has occurred in the power system, and in the event of an accident such as a short circuit, ground fault, or open circuit, it quickly separates the faulty line from the healthy line to minimize damage.

In addition, it provides a function that facilitates fault analysis and device operation history inquiry by storing event occurrence information such as relay element operation due to accident occurrence, status change of input/output contacts, and changes in various device settings along with occurrence time information.

MU(Merging Unit): An analog-to-digital signal conversion and transmission device that samples analog input signals in the field, converts them into digital values according to the IEC 61850 standard, and transmits them.

Time Synchronization Device: A device that periodically synchronizes the time of power facilities and other systems, such as protection control automation systems, to a standard time. Generally, the time is synchronized to the Global Positioning System (GPS).

The conventional method in the power equipment field is to connect signal lines to the digital signal conversion unit built into the IED (Intelligent Electronic Device) to convert analog signals (current, voltage, phase) into digital signals and output them inside the IED.

As various protection control automation facilities in the substation sector are digitized, the facilities are simplified, and the reliability of operation and the usability of various information are further increased. In order to efficiently respond to the expanding power supply and demand, intelligent power grids are gradually being introduced. To this end, the communication method of the power system that constitutes the monitoring, protection, and control automation substations domestically and internationally is trending toward being built as an international standard based on IEC 61850.

The acquired data such as SV (Sampled Value) and status signal value received by the IED from the MU (Merging Unit) are shared between IEDs, and the IED transmits reports, status values, etc. to the upper operating device (Station Control) and GW (Gate Way).

Sampling values such as voltage, current, etc. must match the time or phase information exactly to perform accurate protection control and monitoring functions. To this end, all devices (110, 130, 140) required within the system are synchronized in time through a clock unit (Substation Clock) (120). A drawing showing this is shown in Fig. 1.

Recently, it is being converted to a form of implementation in which digital conversion is performed directly from the signal source in the field using a process bus. At this time, digital data is transmitted from the IED (130) to remote access (230) and the network (220) based on the IEC 61850-9-2 (Sampled Value, SV) standard.

The merging unit (MU) (140) converts the signal source on site into a digital value and extracts and outputs SV data. The merging units (140) installed at different locations must be synchronized with the master clock (master clock, main clock source) (210-1, 210-2). A drawing showing this is shown in Fig. 2.

If the time synchronization does not meet the normal range, errors will occur due to sampling time mismatch when converting analog signals to digital when the phase of voltage data and current data measured on the same line is processed within each MU. This will cause malfunction of substation automation equipment.

Meanwhile, in the case of the existing time synchronization method, a fixed oscillator is located inside the clock device to generate a sampling clock inside the IED built-in ADC (Analog to Digital Converter) device or MU. A synchronization signal from the master clock (main clock source) is received through this oscillator to correct the time difference with the internal fixed oscillator.

In addition, in the method of utilizing a time difference signal as a sampling reference point, if the synchronization signal of the master clock is momentarily lost, in a large-scale network system, sampling of major signals such as voltage and current is performed by relying on an internal fixed-type oscillator that is not synchronized with the master clock during that period. In this case, if the time synchronization error increases, problems occur in the protective control function.

At this time, the standard related to the accuracy of the internal error of the fixed oscillator is IEC (International Electrotechnical Commission) 61850, which stipulates the time synchronization accuracy of electronic devices on the transmission path, such as MU and IED, which are SV (Sampled Value) output devices, as approximately 1 [μsec] in the international standard. However, since it implements its own hardware performance, it is impossible to operate high-precision equipment through continuous linkage with the master clock, so there is a disadvantage that the time synchronization error may increase.

Meanwhile, when multiple devices are connected to a bus-type network, there is no manufacturing guide in the relevant standards such as IEC for electronic devices on multiple transmission paths. Therefore, protection control requirements for protecting power facilities such as substations are not provided, which is a limitation for implementing an effective network system.

Meanwhile, the phase/time information due to the delay between the reference PPS signal (or IEEE 1588 PTP signal) transmitted every second from the GPS (Global Positioning System) receiver and the output clock of the self-locking oscillator is compared to perform compensation for the difference. After that, a sampling clock signal is provided to synchronize with the reference PPS, but there is a disadvantage in that it is difficult to periodically synchronize when the reference signal is lost.

In addition, the operating characteristics of existing equipment do not cause problems in general operating environments (or equipment conditions) where the equipment or system configuration is simple or where the master clock providing the reference clock is not lost (interrupted). However, if the PPS signal, which is the reference clock, is lost or the network system configuring the equipment has a complex structure, it is difficult to maintain precision in synchronizing with other devices in the network system, which makes it difficult to perform accurate protection control monitoring functions.

In other words, the core of the time synchronization of existing equipment is the structure that provides a sampling clock signal to improve the clock precision by compensating for the difference in time delay between devices. However, when the master clock is lost or a system with a complex structure is applied, there is a problem that it is difficult to maintain the time synchronization precision.

That is, in a system based on existing international standards (IEC), as the scale of the system increases, the topology (structure) of the network system becomes more complex and the number of component devices increases, making it difficult to properly synchronize time between IEDs, MUs, and other equipment within a substation, which may cause malfunctions in the protection, control, and monitoring system of power equipment.

In addition, when the master clock, which is the reference clock, is lost, the oscillator error inside the device increases over time, which reduces the precision of signal sampling and causes the system to malfunction.

1. Republic of Korea Patent Registration No. 10-1698227 (Registration Date: January 13, 2017)

The present invention has been proposed to solve the problems according to the above background technology, and its purpose is to provide a master clock-linked time synchronization device and method capable of improving the synchronization precision of oscillation pulses within each facility and ensuring continuity and stability even when a temporary problem occurs in communication with a master clock.

In addition, the present invention provides a master clock-linked time synchronization device and method capable of maintaining the precision of the clock for time synchronization at a stable, high precision by using PID (Proportional Integral Derivative Control) control and voltage conversion technology of the control output value, a voltage-controlled oscillator, etc., to implement high precision of the reference clock sampled during time synchronization operation in a large-scale network system application of the protection control automation system of power facilities such as substations. Another purpose of the present invention is to provide a master clock-linked time synchronization device and method capable of maintaining the precision of the clock for time synchronization at a stable, high precision by using PID (Proportional Integral Derivative Control) control and the voltage conversion technology of the control output value.

In addition, another purpose of the present invention is to provide a master clock-linked time synchronization device and method that enable operation of a high-reliability time synchronization system.

The present invention provides a master clock-linked time synchronization device capable of improving the synchronization precision of oscillation pulses within each facility and ensuring continuity and stability even when a temporary problem occurs in communication with a master clock to achieve the task presented above.

The above visual synchronization device,

A receiver generating a first reference clock signal;

A clock signal generator that generates a second reference clock signal that is heterogeneous with the first reference clock signal;

A selector for selecting the first reference clock signal or the second reference clock signal;

A comparator for comparing a current synchronous clock signal generated in advance with the first reference clock or the second reference clock;

A controller that generates a control output signal for synchronous control according to the above comparison result;

A converter that converts the above control output signal into a numerical value-to-voltage value and generates a converted output value; and

It is characterized by including an oscillator that simultaneously synchronizes phase and frequency with the above-mentioned conversion output value to generate a final synchronous clock signal.

At this time, the first reference clock signal is generated using a GPS (Global Positioning System) signal, and the second reference clock signal is characterized in that it is extracted from PTP (Precision Time Protocol) communication.

In addition, the PTP communication is characterized as IEEE 1588 PTP communication.

In addition, the comparator is characterized in that it extracts a differential value between the first reference clock signal or the second reference clock signal and the self-voltage control oscillation clock signal of the oscillator when the first reference clock signal or the second reference clock signal is not input for a specific time.

In addition, the differential value is characterized in that it is calculated through a TOF (Time of Flight) differential comparison so that the error between the first reference clock signal or the second reference clock signal and the self-voltage control oscillation clock signal of the oscillator (380) is minimized.

In addition, the control output signal is characterized in that it is produced using a PID (Proportional Integral Derivative Control) control function.

In addition, the conversion output value is characterized in that it is produced through numeric to voltage conversion (NVC) by calculating the average value and the effective value of the control value for a certain period immediately before losing the first reference clock signal or the second reference clock signal.

Additionally, the first reference clock or the second reference clock signal is characterized in that it is PPS (Pulse Per Second).

On the other hand, another embodiment of the present invention provides a master clock-linked time synchronization method, characterized by including: (a) a step of a receiver generating a first reference clock signal; (b) a step of a clock signal generator generating a second reference clock signal which is heterogeneous with the first reference clock signal; (c) a step of a selector selecting the first reference clock or the second reference clock signal; (d) a step of a comparator comparing the first reference clock or the second reference clock with a current synchronous clock signal that is generated in advance; (e) a step of a controller generating a control output signal for synchronous control according to a result of the comparison; (f) a step of a converter converting the control output signal into a numerical value-to-voltage value to generate a converted output value; and (g) a step of an oscillator synchronizing a phase and a frequency simultaneously with the converted output value to generate a final synchronous clock signal.

In addition, the step (d) is characterized in that, if the first reference clock signal or the second reference clock signal is not input for a specific time, the comparator extracts a differential value between the first reference clock signal or the second reference clock signal and the self-voltage control oscillation clock signal of the oscillator.

According to the present invention, when operating an automated system for power facility protection, control, monitoring, etc., even if the synchronization signal with the master clock through the Global Positioning System (GPS) is lost, a synchronization optimization system is implemented that links the synchronization state within the device to the master clock, thereby enabling transmission and/or operation of a high-precision synchronization signal to a data sampling unit.

In addition, another effect of the present invention is that, in terms of time synchronization in a packet transmission method using IEEE 1588 PTP (Precision Time Protocol), when configuring a serial network using T/C (Time/Clock), it is not limited to the maximum 15 nodes (750 ns) of the existing technology, and configuring 20 to 30 or more devices is possible, thereby facilitating the design, implementation, and operation of a network system for protection and control automation of large-scale power facilities.

In addition, another effect of the present invention is that even if various clock devices (TC (Tranparent Clock), BC (Boundary Clock), OC (Ordinary Clock)), switches, etc. are installed in a network system, it is possible to maintain high-precision sampling synchronization without error (phase, time) by providing optimized synchronization signals for current and voltage data values between other devices in the network, such as IEDs and MUs.

In addition, another effect of the present invention is that by applying a high-precision time synchronization algorithm linked to a master clock, temporary malfunctions due to increased time synchronization error and major accidents caused by these can be prevented when operating a system applying existing technology, thereby maximizing the operational reliability of a substation protection control automation system, and in the future, effective application of an intelligent application system and advancement and efficiency improvement of an operating system can be expected.

In addition, another effect of the present invention is that it can effectively achieve phase analysis, protection control, and fault analysis functions of various power facilities such as distributed power sources, system analysis, and power plants/substations by providing more precise time synchronization technology compared to existing facilities.

Figure 1 is a diagram showing the main components of a typical substation automation system.
Figure 2 is a schematic diagram of the configuration of a protection control automation system applied to a general power facility process bus network.
FIG. 3 is a block diagram of a master clock-linked time synchronization device according to an embodiment of the present invention.
Figure 4 is a flowchart showing a visual synchronization process according to one embodiment of the present invention.

The present invention can have various modifications and various embodiments, and specific embodiments are illustrated in the drawings and specifically described in the detailed description. However, this is not intended to limit the present invention to specific embodiments, but should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

When describing each drawing, similar reference numerals are used to refer to similar components.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only to distinguish one component from another.

For example, without departing from the scope of the present invention, the first component could be referred to as the second component, and similarly, the second component could also be referred to as the first component. The term "and/or" includes any combination of a plurality of related listed items or any item among a plurality of related listed items.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense, unless expressly defined in this application.

Hereinafter, a master clock-linked time synchronization device and method according to an embodiment of the present invention will be described in detail with reference to the attached drawings.

FIG. 3 is a block diagram of a master clock-linked time synchronization device (300) according to an embodiment of the present invention. Referring to FIG. 3, the master clock-linked time synchronization device (300) may include a receiver (320) that generates a first reference clock signal, a clock signal generator (330) that generates a second reference clock signal that is different from the first reference clock signal, a selector (340) that selects the first reference clock or the second reference clock signal, a comparator (350) that compares the first reference clock or the second reference clock with a current synchronous clock signal generated in advance from an oscillator (380), a controller (360) that generates a control output signal for synchronous control according to the comparison result, a converter (370) that converts the control output signal into a numerical value-to-voltage value to generate a converted output value, and an oscillator (380) that simultaneously synchronizes the phase and frequency with the converted output value to generate a final synchronous clock signal.

The receiver (320) receives a GPS signal from a GPS (Global Positioning System) satellite (310) and generates a first reference clock signal (PPS: Pulse Per Second).

The clock signal generator (330) selects a PPS signal extracted from 1588 PTP (Precision Time Protocol) communication, which is an Ethernet protocol, to generate a second reference clock signal.

The selector (340) performs the function of selecting the first reference clock signal or the second reference clock signal. In detail, in receiving the master time synchronization signal, it performs the function of selecting the time synchronization signal required by the user's selection by receiving the PPS signal from the GPS receiver or the IEEE1588 PTP signal through the Ethernet network.

The reference clock (PPS) branched from the front of the comparator (350) A signal provided from the master clock via GPS, which is always provided in the normal operation (non-fault) state of the master clock. A synchronous clock via comparison/control/conversion/oscillator, etc., is a clock signal generated to have the function of replacing the reference clock when the reference clock is not provided. Therefore, the reference clock is a clock signal provided to the internal time synchronization module of each electronic device when the master clock is operating/provided normally.

The comparator (350) performs a function of comparing the first reference clock signal or the second reference clock signal with the current synchronous clock signal output from the oscillator (380).

When a reference time synchronization signal (PPS) (i.e., a first reference clock signal or a second reference clock signal) from a master clock (i.e., a receiver (320) or a clock signal generator (330)) is not input and is lost for a long period of time (e.g., 10 minutes), a function is performed to compare the reference time synchronization signal with an output clock signal (i.e., a current synchronization clock signal) from a numerically controlled oscillator (NCO) (380) to extract a differential value between the reference signal and the clock signal. Strictly speaking, a function is performed to extract a differential value between the reference time synchronization signal (PPS) of the master clock and its own voltage controlled oscillator (VCO) clock signal.

The master clock's reference clock and the electronic device's own synchronous clock are both composed of 10MHz square waves, and the time of the highest priority rising edge is recorded in 1-second units. The time difference between the rising edge of the reference clock and the rising edge of the synchronous clock is calculated as the difference value, and this difference value can be defined as the phase difference.

The comparison can be a TOF (Time of Flight) differential comparison that compares the differential values so that the error between the reference master clock and the self-voltage control oscillation clock signal is minimized. In other words, the differential value can be calculated through a TOF (Time of Flight) differential comparison.

The controller (360) performs a function of generating a control output signal for synchronous control according to the comparison result. In detail, a PID (Proportional Integral Derivative Control) control function is performed to implement high precision of a reference clock signal sampled during time synchronization operation output from the comparator (350).

In detail, when the phase value of the synchronous clock is ahead or behind the reference clock, this occurs when the frequency of the synchronous clock of the electronic device is not exactly approximately 10 MHz. Therefore, when the synchronous clock is less than/more than 10 MHz by a software control command, the voltage frequency is extracted through a comparator (350) and the size of the difference value (i.e., the phase difference) is considered to derive the control output value through increase/decrease control using a PID controller for the voltage frequency numerical value, and this output value is converted into a voltage value through a converter and then a high-precision square wave is generated through an oscillator. The difference value through PID control is no longer expanded but gradually converges to a smaller value.

The converter (370) performs a function of converting a control output signal into a numeric-voltage value and generating a converted output value. In detail, even if an external PPS signal (i.e., a reference clock signal (PPS)) from a receiver (320) or a clock signal generator (330) is lost, the converter performs a function of controlling a numerically controlled oscillator (NCO) (380) through a numeric to voltage conversion (NVC: Numeric to Voltage Conversion) by calculating an average value and an effective value of a stable control value for a certain period of time immediately before losing the reference clock signal (PPS).

In detail, the conversion output value is produced through numeric to voltage conversion (NVC) by calculating the average value and effective value of the control value for a certain period of time immediately before losing the first reference clock signal or the second reference clock signal.

The oscillator (380) performs the function of generating a final synchronous clock signal by synchronizing the phase and frequency simultaneously with the conversion output value. In general, it performs the function of receiving a synchronizing signal from a master clock (a master clock source) and correcting the time difference with the internal fixed oscillator. In one embodiment of the present invention, it is characterized by providing a sampling clock signal having an oscillation function capable of phase control and frequency control to synchronize with a reference PPS.

In addition, the oscillator (380) performs a function to support comparing the clock signal of the oscillator output terminal with the reference clock, comparing the phase/time information due to the delay between them, and performing compensation for the difference. That is, the differential value between the first reference clock signal or the second reference clock signal and the self-voltage control oscillation clock signal of the oscillator (380) is compensated to generate a final synchronous clock signal.

FIG. 4 is a flow chart showing a time synchronization process according to an embodiment of the present invention. Referring to FIG. 4, a configuration is provided that can select a PPS signal transmitted from a GPS receiver (320) as a reference clock and a PPS signal extracted from 1588 PTP communication, which is an Ethernet protocol, and a high-precision time synchronization clock is provided in the signal sampling stage, thereby enabling the operation of a high-efficiency, high-performance protection control automation system.

Despite the guidance of new international standards such as IEEE PTP, when utilizing IEEE PTP and TC (Transparent Clock) in a system where devices such as MU (Merging Unit), switches, and IED (Intelligent Electronic Device) are connected within a single ring, the number of devices inevitably increases to implement an effective protection and control automation system, which in turn increases the time synchronization error, which acts as a constraint on the connection of multiple devices or the configuration of a network system.

The configuration of nodes utilizing IEEE 1588 PTP and TC is a measure to satisfy the maximum limit of precision error (1 μs) within the device, and is stipulated as a limit of approximately 750 ns considering the margin, so the number of serially configured nodes (devices) within the network is limited to approximately 15. This will soon act as a constraint for the design and configuration of an effective network system.

Recently, IEEE 1588 PTP (Precision Time Protocol), which is being widely applied to global digital substations, is being effectively utilized in network systems as a time synchronization method for distributing reference time information through Ethernet networks within substations.

In cases where precision is insufficient, IEC 61588 and IEEE perform time synchronization with the master clock using the IEEE 1588-PTP-based time synchronization method to process the time synchronization signal of the MU to compensate for this. The following table compares the characteristics of the time synchronization technology applied with PTP.

PTP(Precision Time Protocol) NTP(Network Time Protocol) IRIG-B Precision 1 microsecond 1 millisecond 1 microsecond Visual motivation
Operating structure Master-Slave Server-client Master-Slave Hardware Support
Need or not necessary otiosity necessary Visual motivation
Network configuration LAN(Local Area Network) WAN(Wide Area Network) Dedicated Cable

NTP is a network protocol for time synchronization between computer systems over packet-switched, variable-latency data networks.

IRIG-B, commonly known as IRIG Time Code, is a standard format for transmitting timing information.

Referring to FIG. 4, a reference time synchronization signal and a signal of an output clock of a voltage controlled oscillator from a numerically controlled oscillator (NCO) are mutually compared to extract a difference value between the reference signal and the clock signal (step S420).

Thereafter, in order to implement high precision of the reference clock signal sampled during time synchronization operation, a PID (Proportional Integral Derivative Control) control function is performed (step S430). In detail, a numerically controlled oscillator (NCO: Numerically Controlled Oscillator) that performs a numerical control-based oscillation function with a structure capable of frequency control according to calculated values, a TOF differential comparator, a PID controller, etc. are used to drive a high precision time synchronization algorithm.

In normal operation, when the master clock is operating normally, the built-in time synchronization device of each device has a function that has an algorithm that continuously matches the phase and frequency of the numerically controlled oscillator (NCO) with the input clock from the master clock for a specific period of time through PID control.

In this case, when the time synchronization signal from the master clock is lost, the clock control signal output from the voltage-controlled oscillator (VCO) inside the numerically controlled oscillator (NCO) is averaged for a certain period of time immediately before losing the time synchronization. Afterwards, by utilizing this to stably maintain this value (holding), the synchronized signal is continuously transmitted to the data sampling section even during the time synchronization loss period, enabling high-precision time synchronization operation.

Thereafter, the average value and effective value of the stable control values for a certain period of time immediately before losing the signal are calculated to control the numerical control oscillator (NCO) (380) through numerical to voltage conversion (NVC) (step S440).

Afterwards, finally, the clock signal of the oscillator output terminal is compared with the reference clock, and the phase/time information due to the delay between them is compared, and compensation is performed for the difference to generate and output the final synchronous clock signal (step S450).

Therefore, even if an external PPS signal is lost, the average value and effective value of the stable control value for a certain period of time immediately before the signal is lost are calculated and provided to a numeric to voltage converter (NVC) to control the numerically controlled oscillator (NCO) (380).

Accordingly, it is possible to continuously maintain a state in which the clock frequency or phase does not change, so that operation is possible while minimizing problems with time synchronization errors with the master clock even in a state in which there is no reference PPS from the master.

By having a configuration that can select a PPS signal transmitted from a GPS receiver (320) as a reference clock and a PPS signal extracted from 1588 PTP communication, which is an Ethernet protocol, a high-precision time synchronization clock is provided at the signal sampling stage, enabling the operation of a high-efficiency, high-performance protection control automation system.

In addition, the steps of the method or algorithm described in connection with the embodiments disclosed herein may be implemented in the form of program instructions that can be executed by various computer means, such as a microprocessor, a processor, a CPU (Central Processing Unit), and the like, and recorded on a computer-readable medium. The computer-readable medium may include program (instruction) codes, data files, data structures, etc., alone or in combination.

The program (command) code recorded on the above medium may be specially designed and configured for the present invention, or may be known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium may include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs, DVDs, and Blu-rays, and semiconductor memory devices specially configured to store and execute program (command) codes such as ROMs (Read Only Memory), RAMs (Random Access Memory), and flash memories.

Here, examples of program (instruction) code include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter, etc. The above-mentioned hardware device can be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

110: Station controller 120: Clock unit
130: IED(Intelligent Electronic Device) 140: Merging Unit
210-1,210-2: Master Clock
220: Network 230: Remote Access
300: Master clock-linked time synchronization device
310: GPS(Global Positioning System) satellite
320: Receiver 330: Clock signal generator
340: Selector 350: Comparator
360: Controller 370: Converter
380: Generator

Claims (16)

A receiver (320) generating a first reference clock signal;
A clock signal generator (330) that generates a second reference clock signal that is different from the first reference clock signal;
A selector (340) for selecting the first reference clock or the second reference clock signal;
A comparator (350) for comparing a current synchronous clock signal generated in advance with the first reference clock or the second reference clock;
A controller (360) that generates a control output signal for synchronous control according to the above comparison result;
A converter (370) that converts the above control output signal into a numerical value-voltage value and generates a converted output value; and
It includes an oscillator (380) that simultaneously synchronizes the phase and frequency with the above conversion output value to generate a final synchronous clock signal;
A master clock-linked time synchronization device characterized in that, even when the synchronization signal with the master clock, which is the receiver (320) or clock signal generator (330), is lost, the comparator (350) extracts the difference value between the first reference clock signal or the second reference clock signal and the self-voltage control oscillation clock signal of the oscillator (380) if the first reference clock signal or the second reference clock signal from the master clock is not input for a specific period of time in order to link the synchronization state within the device with the master clock.
In paragraph 1,
A master clock-linked time synchronization device, characterized in that the first reference clock signal is generated using a GPS (Global Positioning System) signal, and the second reference clock signal is extracted from PTP (Precision Time Protocol) communication.
In the second paragraph,
A master clock-linked time synchronization device characterized in that the above PTP communication is IEEE 1588 PTP communication.
delete In paragraph 1,
A master clock-linked time synchronization device characterized in that the above differential value is calculated through a TOF (Time of Flight) differential comparison so as to minimize an error between the first reference clock signal or the second reference clock signal and the self-voltage control oscillation clock signal of the oscillator (380).
In paragraph 1,
A master clock-linked time synchronization device, characterized in that the above control output signal is produced using a PID (Proportional Integral Derivative Control) control function.
In paragraph 1,
A master clock-linked time synchronization device characterized in that the above-mentioned conversion output value is produced through numeric to voltage conversion (NVC) by calculating the average value and the effective value of the control value for a certain period immediately before losing the first reference clock signal or the second reference clock signal.
In paragraph 1,
A master clock-linked time synchronization device, characterized in that the first reference clock or the second reference clock signal is PPS (Pulse Per Second).
(a) a step in which the receiver (320) generates a first reference clock signal;
(b) a step in which a clock signal generator (330) generates a second reference clock signal that is different from the first reference clock signal;
(c) a step of selecting the first reference clock or the second reference clock signal by the selector (340);
(d) a step of comparing a current synchronous clock signal generated in advance with the first reference clock or the second reference clock by a comparator (350);
(e) a step in which the controller (360) generates a control output signal for synchronous control according to the comparison result;
(f) a step of the converter (370) converting the control output signal into a numerical value-voltage value to generate a converted output value; and
(g) a step of generating a final synchronous clock signal by synchronizing the phase and frequency simultaneously with the above conversion output value by the oscillator (380);
Step (d) above,
A master clock-linked time synchronization method characterized in that, even when the synchronization signal with the master clock, which is the receiver (320) or the clock signal generator (330), is lost, the comparator (350) extracts the difference value between the first reference clock signal or the second reference clock signal and the self-voltage control oscillation clock signal of the oscillator (380) if the first reference clock signal or the second reference clock signal from the master clock is not input for a specific period of time in order to link the synchronization state within the self-device with the master clock.
In Article 9,
A master clock-linked time synchronization method, characterized in that the first reference clock signal is generated using a GPS (Global Positioning System) signal, and the second reference clock signal is extracted from PTP (Precision Time Protocol) communication.
In Article 10,
A master clock-linked time synchronization method characterized in that the above PTP communication is IEEE 1588 PTP communication.
delete In Article 9,
A master clock-linked time synchronization method, characterized in that the above differential value is calculated through a TOF (Time of Flight) differential comparison so as to minimize an error between the first reference clock signal or the second reference clock signal and the self-voltage control oscillation clock signal of the oscillator (380).
In Article 9,
A master clock-linked time synchronization method, characterized in that the above control output signal is produced using a PID (Proportional Integral Derivative Control) control function.
In Article 9,
A master clock-linked time synchronization method characterized in that the above-mentioned conversion output value is produced through numeric to voltage conversion (NVC) by calculating the average value and the effective value of the control value for a certain period immediately before losing the first reference clock signal or the second reference clock signal.
In Article 9,
A master clock-linked time synchronization method, characterized in that the first reference clock or the second reference clock signal is PPS (Pulse Per Second).