KR102696749B1 - A quantum computing simulation method providing software development kit by using quantum library and a server performing thereof - Google Patents

Abstract

The technical idea of the present invention relates to a quantum computing simulation method for providing a software development kit by utilizing a quantum library, and a server for performing the same. The quantum computing simulation method performed by a server according to one embodiment of the present disclosure may include the steps of: loading a quantum library including quantum devices; designing a quantum circuit based on the quantum library; selecting a simulator among a plurality of candidate simulators by analyzing the quantum circuit; obtaining a result of simulating the quantum circuit using the selected simulator; and transmitting the quantum circuit to a quantum computer based on the simulation result.

Description

{A QUANTUM COMPUTING SIMULATION METHOD PROVIDING SOFTWARE DEVELOPMENT KIT BY USING QUANTUM LIBRARY AND A SERVER PERFORMING THEREOF}

The present invention relates to a quantum computing simulation method that provides a software development kit utilizing a quantum library and a server that performs the same.

A quantum computer is a computing device that performs information processing based on the principles of quantum mechanics. Unlike general digital computing, it utilizes quantum states (superpositions) called quantum bits or qubits.

Quantum computers use the phenomenon of entanglement to control the interaction between multiple qubits, which allows them to perform parallel calculations. This characteristic can provide superior performance than traditional computing methods in solving certain problems.

The development of quantum computing technology is facing various technical difficulties and challenges, and currently, research is mainly conducted at the laboratory level. The main reason for this problem is that it costs hundreds of millions of dollars per hour to utilize a quantum computer. Therefore, the need for a software development kit to design and simulate quantum circuits on a classical computer has arisen before utilizing a quantum computer.

An object of the present invention is to provide a quantum simulation method that provides a software development kit for a user to design and simulate quantum circuits by utilizing a quantum library.

Another object of the present invention is to provide a plurality of simulators utilized for simulation of quantum circuits, and to provide a quantum simulation method that suggests an optimal simulator among the plurality of simulators.

A quantum computing simulation method performed by a server according to one embodiment of the present disclosure may include: loading a quantum library including quantum devices; designing a quantum circuit based on the quantum library; selecting a simulator among a plurality of candidate simulators by analyzing the quantum circuit; obtaining a result of simulating the quantum circuit using the selected simulator; and transmitting the quantum circuit to a quantum computer based on the simulation result.

In one embodiment, the quantum circuit may include a first quantum line representing a quantum state of a first qubit; a second quantum line representing a quantum state of a second qubit; and a quantum gate performing an operation on at least one of the first qubit and the second qubit.

In one embodiment, the quantum gate may include a Pauli gate that swaps a state probability corresponding to '0' or '1' of a qubit, or changes a probability amplitude or a probability phase; a Hadamard gate that fixes a qubit in a superposition state of '0' and '1'; a CNOT gate that entangles a plurality of qubits; a SWAP gate that swaps states of a plurality of qubits; a Topoli gate that inverts a state of a third qubit based on states of the first qubit and the second qubit; and a Fredkin gate that swaps states of the second qubit and the third qubit based on the state of the first qubit.

In one embodiment, the step of selecting a simulator may include the steps of: obtaining a simulator list including information about the plurality of candidate simulators; and suggesting an optimal simulator among the plurality of candidate simulators based on the quantum circuit.

In one embodiment, the step of presenting the optimal simulator may include: a step of identifying quantum elements included in the quantum circuit; a step of first filtering candidate simulators supporting the identified quantum elements based on the simulator list; a step of identifying the number of qubits required to configure the quantum circuit; a step of second filtering candidate simulators supporting the identified number of qubits among the first-filtered candidate simulators based on the simulator list; and a step of presenting the second-filtered candidate simulator to the user.

In one embodiment, the step of presenting the second filtered candidate simulator to the user may include the steps of: obtaining a gate-by-gate processing time DB presented for each of the filtered candidate simulators; calculating a simulation time for simulating gates included in the quantum circuit using the gate-by-gate processing time DB for each of the filtered candidate simulators; and presenting an optimal simulation to the user using the simulation time.

In one embodiment, the step of calculating the simulation time may include the step of distinguishing gates connected to a plurality of quantum lines among the gates included in the quantum circuit; and the step of determining the sum of processing times corresponding to the gates connected to the plurality of quantum lines as the simulation time using the processing time DB for each gate.

In one embodiment, the step of calculating the simulation time may include: a step of distinguishing parallel-connected quantum elements by analyzing the quantum circuit; a step of obtaining simultaneous processing times of the parallel-connected gates by using the gate-specific processing time DB; and a step of determining the sum of the simultaneous processing times of the parallel-connected gates and the remaining processing time as the simulation time.

In one embodiment, the step of presenting the second filtered candidate simulator to the user may include the steps of: obtaining a gate-by-gate processing time DB presented for each of the filtered candidate simulators; calculating a simulation time for simulating gates included in the quantum circuit using the gate-by-gate processing time DB for each of the filtered candidate simulators; and presenting the simulation time for each of the filtered candidate simulators to the user.

In one embodiment, the step of presenting the optimal simulator may include: a step of confirming quantum elements included in the quantum circuit; a step of first filtering candidate simulators supporting the confirmed quantum elements based on the simulator list; a step of confirming the minimum number of qubits required to configure the quantum circuit; a step of second filtering candidate simulators supporting the confirmed number of qubits among the candidate simulators filtered first based on the simulator list; a step of obtaining an output type for which a simulation result is desired to be obtained from the user; a step of third filtering candidate simulators supporting the output type among the candidate simulators filtered second based on the simulator list; and a step of presenting the candidate simulator filtered third to the user.

A server for providing a user with a software development kit to simulate a quantum circuit according to one embodiment of the present disclosure includes: a memory storing at least one command constituting the software development kit; and a processor providing the user with a software development environment utilizing the at least one command; wherein the processor may be characterized by loading a quantum library including quantum devices from the memory, designing a quantum circuit based on the quantum library, selecting a simulator among a plurality of candidate simulators by analyzing the quantum circuit, obtaining a result of simulating the quantum circuit using the selected simulator, and transmitting the quantum circuit to a quantum computer based on the result of the simulation.

According to the technical idea of the present invention, by utilizing a quantum library prepared in advance in designing a quantum circuit and performing a simulation of the designed quantum circuit using an optimal simulator among a plurality of simulators, it is possible to design an optimal quantum circuit before utilizing a quantum computer, and as a result, it is possible to efficiently utilize a quantum computer, which is a limited and high-value resource.

FIG. 1 is a block diagram illustrating a quantum computing system according to an exemplary embodiment of the present disclosure.
FIG. 2 is a flowchart illustrating a quantum computing simulation method according to an exemplary embodiment of the present disclosure.
FIG. 3 is a diagram illustrating a quantum circuit according to an exemplary embodiment of the present disclosure.
FIG. 4 is a flowchart illustrating a quantum computing simulation method according to an exemplary embodiment of the present disclosure.
FIG. 5 is a flowchart illustrating a quantum computing simulation method according to an exemplary embodiment of the present disclosure.
FIG. 6 is a table showing a list of simulators according to an exemplary embodiment of the present disclosure.
FIG. 7 is a flowchart illustrating a quantum computing simulation method according to an exemplary embodiment of the present disclosure.
FIG. 8 is a table showing a processing time DB per gate according to an exemplary embodiment of the present disclosure.
FIG. 9a is a diagram illustrating a quantum circuit according to an exemplary embodiment of the present disclosure.
FIG. 9b is a diagram illustrating a quantum simulator decision step according to an exemplary embodiment of the present disclosure.
FIG. 10 is a flowchart illustrating a quantum computing simulation method according to an exemplary embodiment of the present disclosure.
FIG. 11 is a block diagram illustrating a computing system according to an exemplary embodiment of the present disclosure.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. The advantages and features of the present invention and the method for achieving them will become clear with reference to the embodiments described in detail below together with the attached drawings. However, the technical idea of the present invention is not limited to the following embodiments, but can be implemented in various different forms, and the following embodiments are provided only to complete the technical idea of the present invention and to fully inform a person having ordinary skill in the art to which the present invention belongs of the scope of the present invention, and the technical idea of the present invention is defined only by the scope of the claims.

When adding reference signs to components of each drawing, it should be noted that identical components are given the same signs as much as possible even if they are shown on different drawings. In addition, when describing the present invention, if it is determined that a specific description of a related known configuration or function may obscure the gist of the present invention, the detailed description is omitted.

Unless otherwise defined, all terms (including technical and scientific terms) used in this specification can be used in a meaning that can be commonly understood by a person of ordinary skill in the art to which the present invention belongs. In addition, terms defined in commonly used dictionaries are not to be ideally or excessively interpreted unless explicitly specifically defined. The terminology used in this specification is for the purpose of describing embodiments and is not intended to limit the present invention. In this specification, the singular also includes the plural unless specifically stated in the phrase.

In addition, when describing components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and the nature, order, or sequence of the components are not limited by the terms. When it is described that a component is "connected," "coupled," or "connected" to another component, it should be understood that the component may be directly connected or connected to the other component, but another component may also be "connected," "coupled," or "connected" between each component.

As used herein, the terms "comprises" and/or "comprising" do not exclude the presence or addition of one or more other components, steps, operations and/or elements.

Components included in one embodiment and components that include common functions may be described using the same names in other embodiments. Unless otherwise stated, descriptions made in one embodiment may be applied to other embodiments, and specific descriptions may be omitted within the overlapping scope or within the scope that can be clearly understood by a person skilled in the art.

Hereinafter, some embodiments of the present invention will be described in detail with reference to the attached drawings.

Hereinafter, the present invention will be described in detail with reference to preferred embodiments of the present invention and the attached drawings.

FIG. 1 is a block diagram illustrating a quantum computing system according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1, a quantum computing system (1) may include a server (10), a user terminal (20), and a quantum computer (30). The server (10) may include a quantum SDK module (100) and a quantum simulator module (200). The quantum SDK module (100) and the quantum simulator module (200) may be implemented as a software module or a hardware module, and may be operated by one server or two or more servers. The server (10) may perform the entire quantum computing simulation based on a control signal (CTRL) received from the user terminal (20), and may collectively refer to a server and an operating computer that operates the server, and may be implemented in a cloud in one example. In one embodiment, the server (10) may transmit data to the user terminal (20) using an application program such as a website or an application.

The user terminal (20) can be operated by a user who designs a quantum circuit, simulates the designed quantum circuit, and then wants to perform calculations using an actual quantum computer (30), and can include various terminal devices capable of communication, such as a cellular phone, a smart phone, a laptop, a personal computer (PC), a navigation system, a personal communication system (PCS), a global system for mobile communications (GSM), a personal digital cellular system (PDC), a personal handyphone system (PHS), a personal digital assistant (PDA), an international mobile telecommunication (IMT)-2000, a code division multiple access (CDMA)-2000, a W-Code Division Multiple Access (W-CDMA), a wireless broadband internet (Wibro) terminal, a smart pad, a tablet PC, etc.

Each component of the quantum computing system (1) can be connected to communicate with each other wired or wirelessly, and in the case of being connected wired, each component included in the quantum computing system (1) can communicate using a serial method, and in the case of being connected wirelessly, each component included in the quantum computing system (1) can communicate with each other using a wireless communication network, and the wireless communication network includes a local area network (LAN), a wide area network (WAN), the Internet (WWW: World Wide Web), a wired and wireless data communication network, a telephone network, a wired and wireless television communication network, 3G, 4G, 5G, 3GPP (3rd Generation Partnership Project), 5GPP (5th Generation Partnership Project), LTE (Long Term Evolution), WIMAX (World Interoperability for Microwave Access), Wi-Fi, the Internet, LAN (Local Area Network), Wireless LAN (Wireless Local Area Network), WAN (Wide Area Network), PAN (Personal Area Network), RF (Radio Frequency), This includes, but is not limited to, Bluetooth networks, NFC (Near-Field Communication) networks, satellite broadcasting networks, analog broadcasting networks, and DMB (Digital Multimedia Broadcasting) networks.

The quantum SDK module (100) can provide a software development kit for designing quantum circuits to users based on the quantum library (QL). The software development kit (SDK) is a collection of software development tools developed to design and simulate quantum circuits. The SDK includes APIs (application programming interfaces), libraries, development tools, documentation, example codes, etc. that support users to easily and quickly develop quantum circuits. This allows users to build applications without having to deeply understand the basic settings or functions of the platform, and simplifies and accelerates the development process.

A quantum library (QL) may include various types of information for designing quantum circuits, such as quantum elements such as quantum gates, quantum wires, and information about a simulator. A quantum SDK module (100) provides a quantum library (QL) to a user terminal (20), and transmits a quantum circuit (QC) designed under the control of the user terminal (20) to a quantum simulator module (200) for simulation.

The quantum simulator module (200) is a software or hardware system designed to simulate the operating principles of quantum computing or quantum algorithms, and may include a software-based quantum simulator and a hardware-based quantum simulator, and may include, for example, a Qasm simulator, a Statevector simulator, a Unitary simulator, a QPlayer simulator, an optical-based simulator, a superconducting circuit simulator, etc. The quantum simulator module (200) may include a plurality of simulators, and may include, for example, a first simulator (SM1) and a second simulator (SM2).

The quantum simulator module (200) can simulate a quantum circuit (QC) by utilizing a simulator selected by the quantum SDK module (100) among a plurality of simulators (SM1, SM2) and transmit a result value (Res) to the quantum SDK module (100). The result value (Res) can include various types of data, and in one example, can include a quantum bit stream, a state vector, an expected value, and a gradient value of a parameter. The quantum SDK module (100) can present the result value (Res) to the user terminal (20), and the user terminal (20) can adaptively modify the quantum circuit (QC) based on the result value (Res). If the result value (Res) is suitable, the user terminal (20) can request the quantum SDK module (100) to perform a calculation using a quantum computer (30), and the quantum SDK module (100) can transmit a quantum circuit (QC) to the quantum computer (30) and provide the corresponding result value to the user terminal (20).

According to the technical idea of the present disclosure, a quantum SDK module (100) provides a user terminal (20) with an SDK that makes it easy to design a quantum circuit (QL) by utilizing a quantum library (QL), and can perform a simulation by utilizing a simulator suitable for the quantum circuit (QL) among a plurality of simulators, and as a result, the user can adaptively modify the quantum circuit (QL) until a suitable result value is obtained, thereby obtaining an optimal quantum circuit (QL). In addition, by utilizing a simulator to design an optimal quantum circuit (QL), it is possible to obtain a desired result value while utilizing a limited and expensive quantum computer (30) to a minimum.

According to one embodiment of the present disclosure, a quantum SDK module (100) is implemented by a server (10), so that a user can utilize the SDK on the web, and thus, a user can easily design a quantum circuit (QC) without installing a separate application program, and as a result, the user's ease of utilizing the SDK can be increased.

In this specification, the operation of the quantum computing system (1) and the components included therein may mean an operation performed by a processor included in each component based on a computer program including at least one command stored in a storage device included in each component, and the storage device may include a non-volatile memory, a volatile memory, a flash memory, a hard disk drive (HDD), a solid state drive (SSD), or the like. In addition, the processor may include at least one of a Central Processing Unit (CPU), a Graphic Processing Unit (GPU), a Neural Processing Unit (NPU), a RAM, a ROM, a system bus, and an application processor.

FIG. 2 is a flowchart illustrating a quantum computing simulation method according to an exemplary embodiment of the present disclosure.

Referring to FIG. 2, the server (10) can load a quantum library (QL) (S100) and design a quantum circuit (QC) based on the quantum library (QL) in response to a control signal (CTL) of a user terminal (20) (S200).

The server (10) can analyze the quantum circuit (QC) and select one simulator from among multiple candidate simulators (S300). The server (10) can simulate the quantum circuit using the selected simulator (S400). The server (10) can transmit the quantum circuit (QC) to the quantum computer based on the simulation result (S500).

FIG. 3 is a diagram illustrating a quantum circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 3, a quantum circuit (QC) may include a plurality of quantum lines (ql0 to ql3) and a plurality of quantum gates. Each of the plurality of quantum lines (ql0 to ql3) may correspond to a qubit (q0 to q3) and represent an input and output for a quantum gate. The quantum gate may include a Pauli gate including an I gate (gi), an X gate (gx), a Y gate (gy), and a Z gate (gz). The I gate, or identity gate, is a gate that does not change a qubit in quantum computing. This gate is used when no operation is to be applied in a quantum circuit. The I gate is expressed as a 2x2 identity matrix, which maintains the state of the qubit as it is. The matrix representation of the I gate is as shown in Mathematical Formula 1.

The X gate (gx) plays a role similar to the classical NOT gate. This gate flips the state of a quantum bit. That is, the matrix representation of the X gate is as shown in mathematical expression 2.

The Y gate (gy) applies a complex phase transformation to the qubit. The Y gate (gy) is also a combination of the X gate (gx) and the Z gate (gz), and can change the phase of the quantum state through this gate. The matrix representation of the Y gate is as shown in mathematical expression 3.

The Z gate (gz) changes the phase only for the "1" state. The Z gate (gz) leaves the "0" state as is and adds a phase of π to the "1" state. This acts to invert the phase of the qubit. The matrix representation of the Z gate (gz) is as follows:

Hadamard gate (gh) is one of the important single-qubit transformation gates used in quantum computing. This gate is used to transform qubits into superposition states, and provides the basis for quantum parallelism and entanglement. Hadamard gate (gh) can be expressed as the following mathematical expression 5.

The CNOT (Controlled-NOT) gate (gcn) is one of the two-qubit gates. The CNOT gate (gcn) is a conditional gate that applies a NOT operation (X gate) to one qubit (target qubit) depending on the state of the other qubit (control qubit). The state of the target qubit is inverted only when the control qubit is in the "1" state. When the control qubit is in the "0" state, the target qubit is not changed.

The swap gate (gsw) is a two-qubit gate used to swap the states of two qubits. The swap gate (gsw) is used to swap information between two qubits, which allows the positions of the qubits to be adjusted within a quantum circuit. When applied to a two-qubit system, the swap gate transfers the state of the first qubit to the second qubit, and the state of the second qubit to the first qubit. The swap gate (gsw) can be expressed as shown in the following mathematical expression (6).

The Fredkin gate (gfk), or Controlled-SWAP (CSWAP) gate, is a three-qubit gate consisting of a control qubit and two target qubits. The states of the two target qubits are swapped only when the control qubit is in the "1" state. When the control qubit is in the "0" state, the target qubit is not changed. The Fredkin gate (gfk) is used in quantum computing in particular to perform conditional swap operations.

The Toffoli gate (GTF), or Controlled-Controlled-NOT (CCNOT) gate, is a three-qubit gate consisting of two control qubits and one target qubit. It performs a NOT operation on the target qubit only when both control qubits are in the "1" state. In all other cases, the target qubit is left unchanged. The Toffoli gate (GTF) can be used to perform the classical "AND" operation in quantum computing, and is essential for complex conditional operations and quantum algorithms.

The measurement gate (gm) is a gate that measures the state of the qubit of the corresponding quantum line.

According to the technical idea of the present disclosure, various gates and quantum lines illustrated in FIG. 3 can be provided to a user terminal (20) by a quantum library (ql), and the user terminal can design a desired quantum circuit (QC) by using the quantum library (ql). Although representative gates are illustrated in FIG. 3, this is only an example, and more diverse quantum gates than the illustrated type can be included in the quantum library (ql), and more or less qubits than the illustrated number of qubits (4) can be provided by the SDK.

FIG. 4 is a flowchart illustrating a quantum computing simulation method according to an exemplary embodiment of the present disclosure. Specifically, FIG. 4 illustrates the simulator selection step (S300) of FIG. 2 in detail.

Referring to FIG. 4, the server (10) can obtain a simulator list including information on candidate simulators (S310). In one example, the simulator list can include information on support gates, the number of supported qubits, and output types for each of multiple simulators.

The server (10) can filter a plurality of candidate simulators based on the quantum circuit (S320). In one embodiment, the server (10) can filter suitable candidate simulators based on information about the gates included in the quantum circuit, the number of qubits utilized, and the output type desired by the user.

The server (10) can calculate the simulation time for the filtered candidate simulators by utilizing the processing time DB for each gate (S330). In one example, the processing time DB for each gate can include information on the processing time for processing a simulator for a specific gate for each simulator, and the server (10) can check the gates included in the quantum circuit and calculate the time required to simulate the quantum circuit for each simulator.

The server (10) can present the optimal simulator to the user by utilizing the simulation time (S340). The server (10) can present simulation times for the filtered candidate simulators and present the fastest simulator among them as the optimal simulator.

Depending on the simulation methodology, various simulators can be used to simulate quantum circuits (QC), and each simulator may have different supported gates, supported qubits, output types, and processing times.

According to one embodiment of the present disclosure, the server (10) can provide a software development environment that allows a user to utilize multiple simulators using one SDK, and thus, the user can perform various simulations using one SDK rather than utilizing individual SDKs to utilize multiple simulators.

In addition, according to one embodiment of the present disclosure, the server (10) can filter simulators capable of simulation by analyzing a quantum circuit, and calculate the expected simulation time of the filtered simulator based on the processing speed per gate, thereby suggesting a suitable simulator to the user, and as a result, the convenience of the user's SDK utilization can be increased.

FIG. 5 is a flowchart illustrating a quantum computing simulation method according to an exemplary embodiment of the present disclosure. Specifically, FIG. 5 illustrates in detail a step (S320) of filtering a plurality of candidate simulators of FIG. 4.

Referring to FIG. 5, the server (10) can verify quantum elements included in a quantum circuit (QC) (S321). The quantum elements can include quantum gates and qubits (or quantum lines). The server (10) can first filter candidate simulators that support the verified quantum elements based on the simulator list (S322). In one example, the simulator list can include information about the quantum elements, number of qubits, output types, etc. supported by each simulator.

The server (10) can check the number of qubits required to configure a quantum circuit (S323). The server (10) can secondarily filter candidate simulators that support the number of qubits confirmed based on the simulator list (S324).

The server (10) can obtain the output type desired for obtaining the simulation result from the user (S325). The server (10) can perform a third filtering of candidate simulators that support the output type confirmed based on the simulator list (S326).

According to one embodiment of the present disclosure, the server (10) can filter out a suitable simulator from among a plurality of candidate simulators based on the supported quantum elements, the number of supported qubits, and the supported output type, thereby eliminating simulators that cannot simulate quantum circuits in advance, and preventing various types of resource waste that may occur when a user utilizes a simulator that cannot simulate.

FIG. 6 is a table showing a list of simulators according to an exemplary embodiment of the present disclosure.

Referring to FIG. 6, the simulator list (SL) may include information about the number of gates and qubits supported by each simulator and the output type.

In one example, the first simulator (SM1) can support I gate (gi), X gate (gx), Y gate (gy) and Topoli gate (gtf), and can support up to four qubits, and the output can be supported as a bit stream of the qubits. The bit stream output can include a bit string of the length of the number of qubits, or a statistical distribution of measured results from multiple measurements of the same circuit.

In one example, the second simulator (SM2) can support Hadamard gate (gh), CNOT gate (gcn), and swap gate (gsw), support up to 16 qubits, and the output can be supported as a state vector.

In one example, the third simulator (SM3) can support Fredkin gate (gfk), Toffoli gate (gtf), and can support up to 4 qubits, and the output can be supported as an expected value. The expected value can represent the average value for the probability distribution of the measurement results.

In one example, the fourth simulator (SM4) can support X gate (gx), Hadamard gate (gh) and CNOT gate (gcn), supports up to 8 qubits, and the output can be supported as a gradient value for the parameter.

The list of simulators illustrated in Fig. 6 is an example in which the support gates, support qubits, and output types are arbitrarily set for convenience of explanation, and the support gates, support qubits, and output types can be set in various ways for each simulator.

Fig. 7 is a flowchart illustrating a quantum computing simulation method according to an exemplary embodiment of the present disclosure. Specifically, Fig. 7 illustrates in detail the step (S330) of calculating the simulation time of Fig. 4.

Referring to FIG. 7, the server (10) can obtain a processing time DB for each gate presented for each filtered candidate simulator (S331). The server (10) can calculate a simulation time for simulating gates included in a quantum circuit by utilizing the processing time DB for each gate for each filtered candidate simulator (S332). In one embodiment, the server (10) can obtain a processing time for each quantum element included in a quantum circuit from the processing time DB for each gate, and calculate a simulation time by adding them up.

The server (10) can present the optimal simulator using the simulation time (S333). In one embodiment, the server (10) can present the simulator with the shortest simulation time as the optimal simulator. In another embodiment, the server (10) can present the simulation time for each simulator to the user.

According to one embodiment of the present disclosure, the server (10) can distinguish a simulator having the fastest gate processing speed among various simulators through a simple operation, and consequently guide a user to select the most suitable simulator.

FIG. 8 is a table showing a processing time DB per gate according to an exemplary embodiment of the present disclosure.

Referring to FIG. 8, the first processing time DB (GDB1) may represent the time it takes for the first simulator (SM1) to simulate each gate, and the second processing time DB (GDB2) may represent the time it takes for the second simulator (SM2) to simulate each gate.

In the example of Fig. 8, the first simulator (SM1) may take a first time (t1) to process the X gate, a second time (t2) to process the Hadamard gate (gh), a third time (t3) to process the Fredkin gate (gfk), and a fourth time (t4) to process the X gate (gx) and the Hadamard gate (gh) connected in parallel or series at once.

Similarly, the second simulator (SM2) may take a fifth time (t5) to process the X gate, a sixth time (t6) to process the Hadamard gate (gh), a seventh time (t7) to process the Fredkin gate (gfk), and an eighth time (t8) to process the X gate (gx) and the Hadamard gate (gh) connected in parallel or in series together.

The server (10) can analyze the quantum circuit to identify the quantum gates included in the quantum circuit, and calculate the simulation time by adding the processing time for each identified gate. According to one embodiment of the present disclosure, by analyzing the quantum circuit and calculating the simulation time based on the result, the simulation time can be predicted through a relatively simple operation, and as a result, the user can be guided to select the fastest simulator.

In addition, according to one embodiment of the present disclosure, by separately managing the time for gates connected in parallel, it is possible to predict a processing time most similar to an actual simulation.

FIG. 9a is a diagram illustrating a quantum circuit according to an exemplary embodiment of the present disclosure, and FIG. 9b is a diagram illustrating a quantum simulator decision step according to an exemplary embodiment of the present disclosure.

Referring to Fig. 9a, the quantum circuit (QC) includes a parallel-connected X gate (gx), a Hadamard gate (gh), a CNOT gate (gcn), and a Frederick gate (gfk), utilizes four qubits, and requires an expected value as an output type.

Referring to FIG. 9b, the server (10) may first filter candidate simulators that support X gate (gx), Hadamard gate (gh), CNOT gate (gcn), and Frederick gate (gfk) among a plurality of candidate simulators (SM1 to SM8) based on the simulator list. In addition, the server (10) may second filter candidate simulators that support four qubits based on the simulator list. Finally, the server (10) may third filter candidate simulators that support expected value as an output type to determine the first simulator (SM1) and the fourth simulator (SM4).

The server (10) can calculate the expected simulation times of the first simulator (SM1) and the fourth simulator (SM4) using the processing time DB per gate. In one example, the first simulator (SM1) can be recorded in the processing time DB per gate as taking 3 minutes to process the parallel-connected X gate (gx) and the Hadamard gate (gh), taking 7 minutes to process the CNOT gate (gcn), and taking 5 minutes to process the Frederick gate (gfk), and the server (10) can calculate 15 minutes as the expected simulation time by adding the processing times. Similarly, the fourth simulator (SM4) can be recorded in the processing time DB for each gate as taking 2 minutes to process the parallel-connected X gate (gx) and Hadamard gate (gh), 4 minutes to process the CNOT gate (gcn), and 3 minutes to process the Frederick gate (gfk), and the server (10) can calculate 9 minutes as the expected simulation time by adding the processing times. As a result, the server (10) can present the fourth simulator (SM4) with the fastest simulation time as the optimal simulator to the user.

According to one embodiment of the present disclosure, by checking a simulator that can be simulated through filtering and measuring the simulation time for the simulator, resources that would otherwise be wasted by unnecessarily calculating simulation times for simulators that cannot be simulated can be saved. In addition, by simply calculating the simulation time and presenting it to the user, the user can perform simulations by utilizing only the optimal simulator instead of unnecessarily utilizing multiple simulators, and as a result, the convenience of utilizing the SDK for the user can be increased.

FIG. 10 is a flowchart illustrating a quantum computing simulation method according to an exemplary embodiment of the present disclosure. Specifically, FIG. 10 illustrates one embodiment of a simulation time calculation step (S332) of FIG. 7.

Referring to Fig. 10, the server (10) can distinguish gates connected to multiple quantum lines among the gates included in the quantum circuit (S332_1). The server (10) can use the processing time DB for each gate to ignore gates connected to only one quantum line and determine the simulation time using only the sum of the processing times corresponding to gates connected to multiple quantum lines (S332_2).

In some embodiments, the processing speed for gates that connect multiple quantum lines (e.g., CNOT gate, SWAP gate, Fredkin gate, Topoli gate) may take relatively longer than the processing time for gates that connect only one quantum line (e.g., X gate, Y gate, Z gate, Hadamard gate).

According to one embodiment of the present disclosure, the time for calculating the simulation time is reduced by ignoring the gates connected to a single quantum wire that has relatively little deviation and can be processed in a short time, and only using the gates connected to a plurality of quantum wires that take a relatively long time to predict the simulation time, and the simulator can be recommended to the user by utilizing fewer resources.

FIG. 11 is a block diagram illustrating a computing system according to an exemplary embodiment of the present disclosure.

Referring to FIG. 11, the computing system (1000) may comprise a server (10) or a user terminal (20), and may include a processor (1100), a memory device (1200), a storage device (1300), a power supply (1400), and a display device (1500). Meanwhile, although not shown in FIG. 11, the computing system (1000) may further include ports that may communicate with a video card, a sound card, a memory card, a USB device, or the like, or communicate with other electronic devices.

In this way, the processor (1100), the memory device (1200), the storage device (1300), the power supply (1400), and the display device (1500) included in the computing system (1000) can perform a quantum computing simulation method by configuring any one of the servers (10) according to the embodiments of the technical idea of the present invention. Specifically, the processor (1100) can perform the operation method of the virtual private network operation system (10) described above in FIGS. 1 to 10B by controlling the memory device (1200), the storage device (1300), the power supply (1400), and the display device (1500).

The processor (1100) can perform specific calculations or tasks. According to an embodiment, the processor (1100) can be a microprocessor, a central processing unit (CPU). The processor (1100) can communicate with a memory device (1200), a storage device (1300), and a display device (1500) through a bus (1600), such as an address bus, a control bus, and a data bus. According to an embodiment, the processor (1100) can also be connected to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

The memory device (1200) can store data required for the operation of the computing system (1000). For example, the memory device (1200) can be implemented as DRAM, mobile DRAM, SRAM, PRAM, FRAM, RRAM, and/or MRAM. The storage device (1300) can include a solid state drive, a hard disk drive, a CD-ROM, etc. The storage device (1300) can store programs, application data, system data, operating system data, etc. related to the quantum computing simulation method described above in FIGS. 1 to 10b.

The display device (1500) can be used as an output means for notifying a user and can display information about a quantum computing simulation method to the user. The power supply device (1400) can supply an operating voltage necessary for the operation of the computing system (1000).

As described above, exemplary embodiments have been invented in the drawings and specifications. Although specific terms have been used in this specification to describe the embodiments, these have been used only for the purpose of explaining the technical idea of the present invention and have not been used to limit the meaning or the scope of the present invention described in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Accordingly, the true technical protection scope of the present invention should be determined by the technical idea of the appended claims.

Claims (11)

In a quantum computing simulation method performed by a server,
A step of loading a quantum library containing quantum elements;
A step of designing a quantum circuit based on the above quantum library;
A step of selecting a simulator among a plurality of candidate simulators by analyzing the above quantum circuit;
A step of obtaining a result of simulating the quantum circuit by utilizing the selected simulator;
A step of transmitting the quantum circuit to a quantum computer based on the simulation results;
The steps for selecting the above simulator are:
A step of obtaining a simulator list including information on the plurality of candidate simulators; and
A step of presenting an optimal simulator among the plurality of candidate simulators based on the quantum circuit;
The steps of presenting the above optimal simulator are:
A step of verifying quantum elements included in the above quantum circuit;
A step of first filtering candidate simulators supporting the confirmed quantum device based on the above simulator list;
A step of checking the number of qubits required to configure the above quantum circuit;
A step of secondarily filtering candidate simulators that support the confirmed number of qubits among the candidate simulators that have been filtered first based on the above simulator list;
A step for obtaining the output type desired to obtain simulation results from the user;
A step of thirdly filtering candidate simulators that support the output type among the second-filtered candidate simulators based on the above simulator list; and
A quantum computing simulation method, comprising the step of presenting the third filtered candidate simulator to a user.
In the first paragraph,
The above quantum circuit,
A first quantum line representing the quantum state of the first qubit;
a second quantum line representing the quantum state of the second qubit; and
A quantum computing simulation method comprising: a quantum gate performing an operation on at least one of the first qubit and the second qubit.
In the second paragraph,
The above quantum gate is,
Pauli gate, which swaps the state probability corresponding to '0' or '1' of a qubit, or changes the probability amplitude or probability phase;
Hadamard gate, which fixes a qubit in a superposition of '0' and '1';
CNOT gate that entangles multiple qubits;
A swap gate that swaps the states of multiple qubits;
A Topolli gate that inverts the state of the third qubit based on the states of the first and second qubits; and
A quantum computing simulation method comprising a Fredkin gate that swaps the states of a second qubit and a third qubit based on the state of a first qubit.
delete delete In the first paragraph,
The step of presenting the above second filtered candidate simulator to the user is:
A step of obtaining a processing time DB for each gate presented for each of the filtered candidate simulators;
For each of the above filtered candidate simulators, a step of calculating a simulation time for simulating gates included in the quantum circuit using the gate-specific processing time DB; and
A quantum computing simulation method, comprising: a step of presenting an optimal simulation to the user by using the above simulation time;
In Article 6,
The steps for calculating the above simulation time are:
A step of distinguishing gates connected to multiple quantum lines among the gates included in the quantum circuit;
A quantum computing simulation method, comprising: a step of determining the sum of processing times corresponding to gates connected to the plurality of quantum lines as the simulation time using the processing time DB for each gate;
In Article 7,
The steps for calculating the above simulation time are:
A step of distinguishing parallel-connected quantum elements by analyzing the above quantum circuit;
A step of obtaining the simultaneous processing time of the parallel-connected gates by using the processing time DB for each gate; and
A quantum computing simulation method, comprising: a step of determining the sum of the simultaneous processing times of the parallel-connected gates and the remaining processing times as the simulation time;
In the first paragraph,
The step of presenting the above second filtered candidate simulator to the user is:
A step of obtaining a processing time DB for each gate presented for each of the filtered candidate simulators;
For each of the above filtered candidate simulators, a step of calculating a simulation time for simulating gates included in the quantum circuit using the gate-specific processing time DB; and
A quantum computing simulation method, comprising: a step of presenting the simulation time for each of the filtered candidate simulators to the user;
In the first paragraph,
The steps of presenting the above optimal simulator are:
A step of verifying quantum elements included in the above quantum circuit;
A step of first filtering candidate simulators supporting the confirmed quantum device based on the above simulator list;
A step of checking the minimum number of qubits required to configure the above quantum circuit;
A step of secondarily filtering candidate simulators that support the confirmed number of qubits among the candidate simulators that have been filtered first based on the above simulator list;
A step of obtaining an output type for which a simulation result is desired from the above user;
A step of thirdly filtering candidate simulators that support the output type among the second-filtered candidate simulators based on the above simulator list; and
A quantum computing simulation method, comprising the step of presenting the third filtered candidate simulator to a user.
For a server that provides users with a software development kit to simulate quantum circuits,
A memory storing at least one command constituting the software development kit; and
A processor providing a software development environment to the user by utilizing at least one of the above instructions;
The above processor,
Load a quantum library containing quantum elements from the above memory,
Design a quantum circuit based on the above quantum library,
By analyzing the above quantum circuit, a simulator is selected from among multiple candidate simulators,
Obtain the results of simulating the quantum circuit using the selected simulator,
Based on the above simulation results, the quantum circuit is transmitted to a quantum computer,
Obtain a list of simulators containing information about the above multiple candidate simulators,
Verify the quantum elements included in the above quantum circuit,
Based on the above simulator list, candidate simulators supporting the above-mentioned confirmed quantum devices are first filtered,
Check the number of qubits required to construct the above quantum circuit,
Based on the above simulator list, candidate simulators that support the above-mentioned number of qubits are secondarily filtered among the candidate simulators that have been first filtered,
Obtain the output type that you want to obtain the simulation results from the above user,
Based on the above simulator list, candidate simulators that support the above output type are filtered out among the candidate simulators that have been filtered out in the second stage, and
A server characterized in that it presents the above 3rd filtered candidate simulator as the optimal simulator to the user.