KR102678340B1 - Interactive dram signal analyzer and method for analyzing and calibrating dram signal in real time using the same - Google Patents

Abstract

According to the present invention, in an interactive DRAM signal analyzer, a signal input/output unit configured to receive command signals and data transmitted from a System On Chip (SoC) including at least one processor through a memory subsystem, and a memory subsystem. A signal analysis processing unit configured to generate a correction command based on analysis of the command signal and data received from the system, wherein the signal analysis processing unit transfers the first command signal and data received from the memory subsystem to the DRAM memory, Receive an uncorrected command signal and data fed back from the DRAM memory, generate a first correction command based on signal analysis of the uncorrected command signal and data, transmit the first correction command to the memory subsystem, and transmit the first correction command to the memory subsystem. An interactive DRAM signal analyzer can be provided, configured to transfer a second command signal and data corrected based on a first correction command from the system to the DRAM memory.

Description

Interactive DRAM signal analyzer and real-time DRAM signal analysis and correction method using the same {INTERACTIVE DRAM SIGNAL ANALYZER AND METHOD FOR ANALYZING AND CALIBRATING DRAM SIGNAL IN REAL TIME USING THE SAME}

The present invention relates to an interactive DRAM signal analyzer capable of analyzing and correcting DRAM (Dynamic Random Access Memory) signals and a method of analyzing and correcting DRAM signals in real time using the same. More specifically, the present invention provides a DRAM signal analyzer that can access and analyze command signals or data related to DRAM memory at the shortest distance through interaction with a transmitter such as a SoC (System On Chip), real-time DRAM signal analysis using the same, and It's about the correction method.

In the case of an oscilloscope, a conventional signal measurement equipment, when measuring input/output (I/O) located on a printed circuit board (PCB) for debugging signal and data processing between the transmitting end and the receiving end, such as SoC (System On Chip), the measuring equipment and There is a problem that signal integrity and short delay time cannot be guaranteed due to the physical distance between PCBs and differences in logical and physical elements between signals to be measured.

Oscilloscopes, the existing signal measurement equipment, are optimized only for signal and voltage level monitoring and do not have signal integrity assistance or phase correction functions between signals. Therefore, from the user's perspective, the measured signal is monitored and the user determines the integrity and phase of the signal. There are time constraints and technical challenges that require iterating circuits and digital designs to support compensation functions.

Recently, as deep learning application technology requires computationally intensive applications and high memory frequencies, there are technical difficulties in measuring and correcting signals and data during the data transfer process between deep learning application and memory, and from the user's perspective, it is difficult to Measuring equipment technology requires a lot of time and technology consumption to solve data and signal processing problems that occur during the transmission process.

As ultra-high-speed frequency memories such as LPDDR5X and LPDDR6 emerge in the future, signal equipment such as existing oscilloscopes must also sufficiently support high bandwidth. To prevent bottlenecks when measuring signals, a probe that can guarantee the frequency bandwidth supported by the oscilloscope used is required. Equipment is also needed, and in terms of price, there is a problem in that purchasing such high-end equipment costs tens of times more than the existing cost.

Therefore, an interactive DRAM signal analyzer that analyzes high-frequency signals between a transmitting end such as SoC and a receiving end such as DRAM through a method different from the conventional method and includes a correction function between signals to assist signal integrity, and DRAM signal analysis using the same. and a correction method are required.

(Patent Document 0001) Republic of Korea Patent No. 10-0864633

The present invention provides the same ball map structure as DRAM memory, enabling signals to be measured at the shortest distance from the PCB and memory, preventing signal distortion and ensuring integrity when measuring signals, and performing signal measurement directly inside the device. The purpose is to provide an interactive DRAM signal analyzer that can improve measurement signal quality without the need for additional devices such as probes.

In addition, the present invention improves signal accuracy through signal phase difference analysis at the receiving end through interaction between a transmitting end such as a SoC and a receiving end such as a DRAM signal analyzer, improves signal quality through voltage analysis at the receiving end, and improves signal quality at the receiving end. The purpose is to provide an interactive DRAM signal analyzer that can improve data accuracy through protocol analysis between signals and increase memory use efficiency through customized response according to the phase difference, voltage, and protocol analysis received from the transmitter and receiver. Do this.

In addition, the purpose of the present invention is to provide an interactive DRAM signal analyzer that facilitates debugging and result analysis by distinguishing signals from a DRAM memory mounted on a PCB from before and after correction and monitoring them in real time.

In addition, the purpose of the present invention is to provide an interactive DRAM signal analyzer capable of setting an optimal DRAM operating environment by enabling debugging and verification of normal operation before integrating DRAM on a PCB.

The problems to be solved by the present invention are not limited to the contents mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

In one embodiment of the present invention, in an interactive DRAM signal analyzer, a signal input/output unit configured to receive command signals and data transmitted from a System On Chip (SoC) including at least one processor through a memory subsystem. ; and a signal analysis processor configured to generate a correction command based on analysis of the command signal and data received from the memory subsystem, wherein the signal analysis processor generates a first command signal and data received from the memory subsystem. transmitting to a DRAM memory, receiving the uncorrected command signal and data fed back from the DRAM memory, generating a first correction command based on signal analysis of the uncorrected command signal and data, and executing the first correction command It may be configured to transmit a second command signal and data corrected based on the first correction command from the memory subsystem to the DRAM memory.

Additionally, the signal input/output unit may be packaged to have the same ball map as the DRAM memory. Additionally, the signal input/output unit may be configured to support a plurality of DRAM memories.

Additionally, the first correction command may be related to correction of at least one of the phase difference of the signal, the voltage level of the signal, and the memory protocol.

Additionally, the signal analysis processor may be configured to receive a corrected command signal and data from the DRAM memory and determine whether the memory is operating normally based on signal analysis of the corrected command signal and data.

Additionally, when the signal analysis processor determines that the memory is operating normally based on signal analysis of the corrected command signal and data, it may be configured to transmit a normal operation signal to the SoC and the user terminal.

In addition, when the signal analysis processing unit determines that the memory is not operating normally based on signal analysis of the corrected command signal and data, a second correction command is generated based on signal analysis of the corrected command signal and data. and may be configured to transmit the second correction command to the memory subsystem.

In addition, signal analysis of the uncorrected command signal and data includes analyzing the phase difference between the command signal and the data, analyzing the skew (SKEW) between the data based on the command signal, determining whether it complies with the standard memory protocol, and analyzing the voltage level of the signal. may include.

Additionally, the memory subsystem may include a memory controller, and the memory subsystem may be configured to receive the first correction command and correct a protocol between a command signal and data using the memory controller.

Additionally, the memory subsystem includes a physical layer, and the memory subsystem may be configured to adjust inter-data skew (SKEW) and correct voltage levels using a training algorithm using the physical layer.

In another embodiment of the present invention, in a real-time DRAM signal analysis and correction method using an interactive DRAM signal analyzer, instructions transmitted from a SoC (System On Chip) including at least one processor by a signal input/output unit Receiving signals and data through a memory subsystem; and generating, by a signal analysis processing unit, a correction command based on analysis of the received command signal and data, wherein the first command signal and data received from the memory subsystem are generated by the signal analysis processing unit. transferring to the DRAM memory; The signal analysis processor receives the uncorrected command signal and data fed back from the DRAM memory, generates a first correction command based on signal analysis of the uncorrected command signal and data, and executes the first correction command. delivering to the memory subsystem; and transmitting, by the signal analysis processor, a second command signal and data corrected based on the first correction command from the memory subsystem to the DRAM memory. can do.

According to the present invention, a DRAM signal analyzer capable of accessing and analyzing command signals or data related to DRAM at the shortest distance through interaction between a transmitting end such as a SoC and a receiving end such as a DRAM analyzer, and a DRAM signal analysis and correction method using the same. can be provided.

In addition, according to the present invention, it is possible to provide a DRAM signal analyzer that can stabilize memory operation by providing precise signal, power, protocol analysis, debugging, and verification environment in situations where memory operation verification is difficult due to the emergence of ultra-high frequency memory. You can.

In addition, according to the present invention, it is possible to monitor waveform properties such as voltage level, time interval, and signal integrity to improve the function of the DRAM circuit, and signal integrity is maintained through interaction between the transmitting end (SoC) and the receiving end (DRAM analyzer). A device including a phase correction function between signals for assistance can be provided.

In addition, according to the present invention, it is possible to provide a DRAM signal analysis and correction device and a method using the same that facilitate debugging and result analysis by distinguishing signals from a DRAM memory mounted on a PCB from before and after correction and monitoring them in real time.

The effects of the present invention are not limited to the contents mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

Figure 1 is a conceptual diagram to explain the problems of analyzing DRAM-related signals using an oscilloscope, a conventional signal measurement device.
2A and 2B are conceptual diagrams for explaining the operation and configuration of a DRAM signal analyzer configured to analyze and correct DRAM-related signals according to an embodiment of the present invention.
Figure 3 is a block diagram for explaining the configuration of a DRAM signal analyzer according to an embodiment of the present invention.
FIG. 4 is a flowchart illustrating a method of analyzing and correcting DRAM-related signals through interaction between a SoC and a DRAM signal analyzer according to an embodiment of the present invention.
FIG. 5 is a flowchart illustrating a method of analyzing and correcting a DRAM-related signal in a signal analysis processor of a DRAM signal analyzer according to an embodiment of the present invention.
Figure 6 is an exemplary diagram showing a screen on which analysis results of a DRAM signal analyzer are displayed in real time on a user terminal according to an embodiment of the present invention.
Figure 7 is a flowchart illustrating a method of monitoring signals before and after correction in real time using a DRAM signal analyzer according to an embodiment of the present invention.

Hereinafter, with reference to the attached drawings, the present invention will be described in detail so that those skilled in the art can easily practice it. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein.

The terminology used herein is for describing embodiments and is not intended to limit the invention. As used herein, singular forms also include plural forms, unless specifically stated otherwise in the context.

As used herein, “comprises”, “comprising” refers to the presence or absence of one or more other components, steps, operations and/or elements. Addition is not ruled out.

Additionally, when describing the present invention, if it is determined that a detailed description of related known technologies may obscure the gist of the present invention, the detailed description will be omitted.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the attached drawings. The configuration of the present invention and its operational effects will be clearly understood through the detailed description below.

Figure 1 is a conceptual diagram to explain the problems of analyzing DRAM-related signals using an oscilloscope, a conventional signal measurement device.

Referring to FIG. 1, in the case of the oscilloscope 10, which is an existing signal measurement equipment, a separate device is used to analyze signal and data processing between a transmitting end such as the SoC 21 and a receiving end such as a DRAM placed at the location where the memory 22 is integrated. Probe equipment is required, and the integrity of the signal cannot be guaranteed due to delay time when analyzing signals due to differences in physical distance and logical elements between the measurement equipment and the printed circuit board (PCB) 20. A problem arises. In addition, after manufacturing the PCB 20, a measurement device such as an oscilloscope 10 cannot be directly connected to the ball map of the memory from the transmitting end to the receiving end to debug the memory operation, so a sub board 11 is required as a separate interface means for measurement. .

Here, a test vector or data to be used as input to the SoC 21 is transmitted through the user terminal 30, and input data and test are generally transmitted through software or an application of the user terminal 30. Vectors, etc. are transmitted to the SoC (21), and the data flow and results during the transmission process can be confirmed through the oscilloscope (10).

At this time, from the user's perspective, it takes a lot of time and technical difficulties exist because the user must monitor the signal measured by the oscilloscope 10 and continuously repeat the circuit and digital design to support signal integrity and phase correction functions. .

In this way, when using the oscilloscope 10, a conventional signal measurement equipment, when measuring input/output (I/O) located on the printed circuit board (PCB) 20 for debugging of signal and data processing between the transmitting end and the receiving end, the measuring equipment There is a problem that signal integrity and delay time cannot be guaranteed due to the physical distance between the device and the PCB and differences in logical and physical elements between the signals to be measured.

2A and 2B are conceptual diagrams for explaining the operation and configuration of a DRAM signal analyzer configured to analyze and correct DRAM-related signals according to an embodiment of the present invention.

Referring to FIG. 2A, the DRAM signal analyzer 100 is packaged to have the same ball map as a memory device such as the DRAM memory 220, and thus has the same physical specifications as the DRAM memory, so that the DRAM memory 220 can be stored on the PCB 200. It may be configured to be mounted in a mounting position or to be mounted together with the DRAM memory 220, for example, by being coupled to the DRAM memory 220 while the DRAM memory 200 is mounted. Accordingly, the DRAM signal analyzer 100 can measure signals at the shortest distance from the PCB 200 and the DRAM memory 220, thereby preventing signal distortion and ensuring integrity, and the data transmitted through the DRAM memory 220 inside the device is guaranteed. By enabling direct measurement of signals, there is no need for additional devices such as conventional probe equipment and signal quality can be improved. For example, the DRAM signal analyzer 100 has the same ball map as the DRAM memory 220, so that the DRAM memory 220 is mounted at the location where the DRAM memory 220 is integrated on the PCB 200, as shown in FIG. 2A. It can be placed together and connected to transmit and receive signals with the SoC 210. Here, SoC 210 is an integrated circuit (IC) that integrates computer components into a single chip. Typical computer components of a SoC include a central processing unit (CPU), memory, input/output ports, and auxiliary storage, and DRAM memory. It is an entity such as a master or host that uses (220) and runs specific applications. Here, the SoC can perform various signal processing functions and may include a special processor or co-processor, such as a graphics processing unit (GPU). In addition, although one SoC 210 is shown in FIG. 1 for convenience, multiple SoCs 210 and multiple DRAM signal analyzers 100 connectable thereto may be used.

The configuration of the DRAM signal analyzer 100 and the DRAM memory 220 indicated by a dotted line in FIG. 2A is shown so that the DRAM signal analyzer 100 corresponds to one memory of the DRAM memory 220 and supports only one memory. As shown in 2b, the DRAM signal analyzer 100 supports a plurality of DRAM memories 220 mounted on the PCB 200, so that it can be designed to verify and correct signals from a plurality of memories simultaneously with one analyzer. At this time, if the number of ball maps of each DRAM memory 220 is, for example, 60, the ball map of the DRAM signal analyzer 100 configured to support a plurality of memories may be configured to have a total of 240 ball maps of 60 x 4, and the DRAM The connection of the signal analyzer 100 can be configured to reflect the gap between independently installed memories. As such, according to an embodiment of the present invention, a plurality of memory channels can be supported using one DRAM signal analyzer 100, thereby enabling verification and correction of a plurality of memories.

Through circuit technology that allows analysis of transmission and reception signal characteristics through the DRAM signal analyzer 100, the user can interact between a transmitting end such as the SoC 210 and a receiving end such as the DRAM signal analyzer 100 through the user terminal 300. Based on the analysis function, it can be configured to increase memory use efficiency through customized results according to the phase difference, voltage, and protocol analysis of the DRAM signal. A more detailed configuration of the DRAM signal analyzer 100 will be described below.

Figure 3 is a block diagram for explaining the configuration of a DRAM signal analyzer according to an embodiment of the present invention.

The DRAM signal analyzer 100 may include a signal input/output unit 110, a signal analysis processor 120, and a DRAM model 130.

First, the signal input/output unit 110 receives command signals and data transmitted from the SoC 210 including at least one processor through a memory subsystem, etc. and processes them between the DRAM signal analyzer 100 and the memory subsystem. It may be configured to transmit and receive data. Here, the signal input/output unit 110 is packaged to have the same ball map as the DRAM memory device and has the same hardware specifications as the DRAM, so that the DRAM signal analyzer 100 is the same as the memory device such as the DRAM memory 220. By being configured to be placed and mounted on the DRAM memory 220 on the PCB 200, it can be configured to enable signal measurement directly on the PCB 200. Additionally, the signal input/output unit 110 may be configured to support a plurality of DRAM memories.

The signal analysis processor 120 may be configured to generate a correction command based on analysis of command signals and data received from a memory subsystem including a memory controller. Here, the command signal is, for example, a signal requesting to read data or write data to a specific address of the memory, and data refers to data transmitted and received when executing a specific application from the SoC 210 point of view. You can save or load it accordingly. For example, when running an AI application, data necessary for learning or data for which computational processing has been completed can be used. Additionally, since such a command signal must be sent in a protocol format suitable for the corresponding memory, it can be transmitted to a memory subsystem that can process the protocol.

Here, the memory subsystem receives a memory access request from an entity that reads and writes data to a memory physically connected to another chip, such as the SoC 210, and stably provides memory driving instructions and data. It is transmitted to the memory or DRAM signal analyzer 100, and refers to a driving auxiliary system of the memory system consisting of a memory controller (controller), physical layer (PHY), input/output (IO), etc. for reading, writing, and preserving memory data. .

In addition, the DRAM model 130 may be configured to operate like DRAM and output command signals and data based on the command signal and data received from the signal analysis processor, and the DRAM model 130 has the same role as DRAM. It is modeled in software, and although it is not an actual DRAM, it plays a role in interfacing with a virtual DRAM. Through that role, it can communicate between DRAMs in advance to debug and prevent problems caused by differences in protocols, timing, skew, etc. It is designed to compensate for existing problems. Here, DRAM may include, for example, DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR (Low Power Double Data Rate) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, RDRAM (Rambus Dynamic Random Access Memory), etc. It can also be implemented in various forms such as SDRAM (Static DRAM), high bandwidth memory (HBM), or Processor In Memory (PIM), but is not limited to these.

Here, the signal analysis processor 120 transfers the first command signal and data received from the memory subsystem to the DRAM memory 140 when the DRAM memory 220 is installed, and when the DRAM memory 220 is not installed, the signal analysis processor 120 transfers the first command signal and data received from the memory subsystem to the DRAM memory 140. In each case, it transmits to the DRAM model 130, and in each case, receives uncorrected (uncompensated) command signals and data fed back from the DRAM memory 220 or the DRAM model 130, and receives the uncorrected command signals and data. Generate a first correction instruction based on signal analysis, transmit the first correction instruction to the memory subsystem, and receive a second instruction signal and data calibrated based on the first correction instruction from the memory subsystem. It may be configured to be delivered back to the DRAM memory 220 or the DRAM model 130. Here, signal analysis of the uncorrected command signal and data includes analysis of the phase difference between the command signal and data, analysis of skew (SKEW) between data based on the command signal, determination of whether it complies with the standard memory protocol, and analysis of the voltage level of the signal. It can be included. Additionally, the first correction command signal may be related to calibration of at least one of the phase difference of the signal, the voltage level of the signal, and the memory protocol.

In addition, the signal analysis processing unit 120 receives the corrected command signal and data from the actually installed DRAM memory 220 or the DRAM model 130, and based on signal analysis of the corrected command signal and data, the memory It may be configured to determine whether it is operating normally.

At this time, when the signal analysis processing unit 120 determines that the memory is operating normally based on signal analysis of the corrected command signal and data, the SOC 210 performs the requested operation, and the SoC 210 and the user terminal 300 ) may be configured to transmit a normal operating signal to the device.

In addition, when the signal analysis processor 120 determines that the memory is not operating normally based on signal analysis of the corrected command signal and data, a second correction command is generated based on signal analysis of the corrected command signal and data. and is configured to transmit the second correction command to the memory subsystem. Through this operation, the corrected command signal and data are once again transmitted to the DRAM memory 220 or the DRAM model 130 and the signal analysis processor 120. By receiving and analyzing the signal, signal analysis and correction work can be repeated.

Additionally, the memory subsystem may include a memory controller, and the memory subsystem may be configured to receive a correction command using the memory controller and correct a protocol between the command signal and data. Additionally, the memory subsystem includes a physical layer, and the memory subsystem may be configured to adjust inter-data skew (SKEW) and correct voltage levels using a training algorithm using the physical layer.

FIG. 4 is a flowchart illustrating a method of analyzing and correcting DRAM-related signals through interaction between a SoC and a DRAM signal analyzer according to an embodiment of the present invention.

Figure 4 shows a process in which the SoC 210, which is a transmitting end, and the DRAM signal analyzer 100, which is a receiving end including a signal analysis processor 120, transmit and receive signals through the memory subsystem 211, and the DRAM memory 220 It shows a method of analyzing and correcting the signal while monitoring it in real time by transmitting and receiving signals and data with the actually installed memory.

First, DRAM-related command signals and data can be transmitted from the SoC 210 to the memory subsystem 211 (S201).

The memory subsystem 211 may generate command signals and data based on the first phase, voltage, and memory protocol and transmit them to the signal analysis processor 120 through the signal input/output unit 110 of the DRAM signal analyzer 100. (S202) At this time, the memory subsystem 211 transmits the command signal and data through the training algorithm, but the command signal and data based on the first phase, voltage, and memory protocol produce results output through the DRAM memory 220. Since it has not been corrected, it means uncorrected (raw) command signals and data.

The signal analysis processing unit 120 transmits command signals and data to the actually installed DRAM memory 220 (S203), and the DRAM memory 220 is configured to feed back and output the input signal as it is, where the first phase, Based on the voltage and memory protocol, uncorrected command signals and data can be output and transmitted to the signal analysis processor 120 (S204). Here, the command signal and data output from the DRAM memory 220 are transmitted to the DRAM memory 220. ) refers to the output produced after reacting through .

The signal analysis processing unit 120 analyzes uncorrected command signals and data received from the DRAM memory 220, for example, phase differences between signals, voltage differences between signals, and signals that do not conform to the standard memory protocol. A self-generated correction command based on the result of signal analysis can be transmitted to the memory subsystem 211 (S205). In this way, the signal analysis processor 120 analyzes the phase difference between the command signal and data at the receiving end, and executes the command. Phase difference of the signal and voltage level of the signal to improve signal accuracy and signal quality based on signal-based skew analysis between data, voltage level analysis, protocol analysis between interface signals, impedance analysis of the signal for power integrity, etc. , you can create correction commands for signal correction such as impedance and memory protocol.

The memory subsystem 211 converts the command signal and data back to the signal analysis processor 120 based on the second phase, voltage, and memory protocol generated by applying the training algorithm and interpretation of the correction command received from the signal analysis processor 120. ). (S206)

The signal analysis processor 120 may transmit the command signal and data corrected by the correction command back to the DRAM memory 220 (S207).

The DRAM memory 220 is configured to feed back and output the signal received through correction as is. At this time, differently from step S204, the corrected command signal and data can be output and transmitted to the signal analysis processor 120 (S208).

The signal analysis processor 120 may determine whether the operation is normal based on the corrected command signal and data fed back from the DRAM memory 220, and may transmit the corrected command signal and data to the memory subsystem 211. ( S209)

At this time, if the signal analysis processor 120 determines that the memory is operating normally based on signal analysis of the corrected command signal and data, the command requested by the SoC 110 is normally transmitted to the SoC 210 and the user terminal 300. It is configured to transmit a processed normal operation signal, and the user can check whether the memory is operating normally and receive verified data through the user terminal 300.

At this time, if the signal analysis processing unit 120 determines that the memory is not operating normally based on signal analysis of the corrected command signal and data, the second correction command is issued again based on signal analysis of the corrected command signal and data. By generating and transmitting the second correction command to the memory subsystem 120, processes S206 to S209 can be repeated.

In the present invention, through the interaction between the DRAM signal analyzer 100 and the SoC 110, the transmitting end (SoC) recommands and corrects the signal based on the signal analysis result and correction command received from the receiving end (DRAM signal analyzer). The optimization algorithm for this purpose can be delivered to the receiving end so that the receiving end can comply with the memory protocol and operate in accordance with the memory standard. In addition, the transmitting end can transmit the optimal register set to the receiving end based on a training algorithm that analyzes and adjusts itself to adjust the phase difference between signals by analyzing the phase difference of the signal received from the receiving end. In addition, the transmitting end can transmit the optimal register set to the receiving end based on a training algorithm that analyzes and adjusts itself to adjust the voltage level by analyzing the voltage level received from the receiving end.

FIG. 5 is a flowchart illustrating a method of analyzing and correcting a DRAM-related signal in a signal analysis processor of a DRAM signal analyzer according to an embodiment of the present invention.

Referring to FIG. 5, the signal analysis processing unit 120 of the DRAM signal analyzer 100 may receive uncorrected (non-compensated) command signals and data from the actually installed DRAM memory 220 (S510).

The signal analysis processing unit 120 analyzes the phase difference between the command signal and the data (S520), performs skew analysis between the data based on the command signal (S530), and performs a standard memory protocol.

You can check compliance (S540) and perform voltage level analysis of the uncorrected signal (S550).

Based on the signal analysis results, the signal analysis processor 120 may generate a correction request command requesting correction of the command signal and data, and transmit it to the memory subsystem 211 (S560).

The memory controller in the memory subsystem 211 may receive a correction request command and perform protocol correction between signals and data (S570).

Additionally, the PHY (physical layer) within the memory subsystem 211 can adjust skew between data and correct voltage levels through its own training algorithm (S580).

The signal analysis processor 120 may receive the corrected command signal and data from the memory subsystem 220 and transmit the corrected command signal and data to the DRAM memory 220 (S590).

The signal analysis processor 120 may receive the corrected command signal and data fed back from the DRAM memory 220, and determine whether data is received normally and whether the memory is operating normally (S600).

If the signal analysis processing unit 120 determines that the memory is operating normally based on signal analysis of the corrected command signal and data, the command requested by the SoC 110 is normally processed by the SoC 110 and the user terminal 300. It can be configured to transmit a normal operation signal (S610).

If the signal analysis processing unit 120 determines that the memory is not in normal operation based on signal analysis of the corrected command signal and data, it may be configured to return to step S510 and repeat the signal analysis and correction operations in steps S510 to S600. there is.

Figure 6 is an exemplary diagram showing a screen on which analysis results of a DRAM signal analyzer are displayed in real time on a user terminal according to an embodiment of the present invention.

Referring to FIG. 6, the user can compare data before and after correction using the DRAM signal analyzer 100 through the user terminal 300. For example, the uncorrected signal and data 610 are displayed on the left, The corrected signal and data 620 can be configured to be displayed on the right. Accordingly, it is possible to provide a DRAM signal analysis and correction method that is easy for debugging and result analysis by monitoring the signal in the DRAM memory 220 directly mounted on the PCB in real time before and after correction.

Figure 7 is a flowchart illustrating a method of monitoring signals before and after correction in real time using a DRAM signal analyzer according to an embodiment of the present invention.

First, the signal analysis processor 120 of the DRAM signal analyzer 100 can receive uncorrected signals and data from the installed DRAM memory 220 (S710).

The signal analysis processor 120 of the DRAM signal analyzer 100 can transmit uncorrected signals and data to the user terminal 300 that is communicatively connected (S720).

The user can monitor uncorrected signals and data using a software application linked to the signal analysis processor 120 through the user terminal 300 (S730).

A correction process is performed through the signal analysis processor 120 and the memory subsystem 211, and the corrected signal can be transmitted to the DRAM memory 220 based on the signal analysis results (S740).

The signal analysis processor 120 may receive the corrected signal and data from the DRAM memory 220 (S750).

The signal analysis processor 120 may transmit the corrected signal and data to the user terminal 300 (S760).

The user can monitor the correction signal in real time using an application linked to the signal analysis processor 120 through the user terminal 300 (S770).

In this way, the user can monitor and check the signal before and after correction in real time. (S780)

The embodiments disclosed in the specification of the present invention are merely examples, and the present invention is not limited thereto. The scope of the present invention should be interpreted in accordance with the scope of the patent claims below, and all technologies within the equivalent scope thereof should be interpreted as being included in the scope of the present invention.

100: DRAM signal analyzer
110: signal input/output unit
120: signal analysis processing unit
130: DRAM model
210: SoC
211: memory subsystem
220: DRAM memory
300: User terminal

Claims (11)

In an interactive DRAM signal analyzer,
A signal input/output unit configured to receive command signals and data transmitted from a System On Chip (SoC) including at least one processor through a memory subsystem; and
A signal analysis processor configured to generate a correction command based on analysis of the command signal and data received from the memory subsystem.
Including,
The signal analysis processing unit,
Transferring the first command signal and data received from the memory subsystem to the DRAM memory,
Receive an uncorrected command signal and data fed back from the DRAM memory, generate a first correction command based on signal analysis of the uncorrected command signal and data, and transmit the first correction command to the memory subsystem; ,
and transmitting a second command signal and data corrected based on the first correction command from the memory subsystem to the DRAM memory. The interactive DRAM signal analyzer according to claim 1, wherein the signal input/output unit is packaged to have the same ball map as the DRAM memory. The interactive DRAM signal analyzer according to claim 2, wherein the signal input/output unit is configured to support a plurality of DRAM memories. The interactive DRAM signal analyzer of claim 1, wherein the first correction instruction relates to correction of at least one of a phase difference of the signal, a voltage level of the signal, and a memory protocol. The method of claim 1, wherein the signal analysis processor is configured to receive a corrected command signal and data from the DRAM memory and determine whether the memory is operating normally based on signal analysis of the corrected command signal and data. In,Interactive DRAM Signal Analyzer. The method of claim 5, wherein when the signal analysis processing unit determines that the memory is in normal operation based on signal analysis of the corrected command signal and data, it is configured to transmit a normal operation signal to the SoC and the user terminal. Interactive DRAM signal analyzer. The method of claim 5, wherein when the signal analysis processing unit determines that the memory is not operating normally based on signal analysis of the corrected command signal and data, the second operation is performed based on signal analysis of the corrected command signal and data. An interactive DRAM signal analyzer configured to generate a correction instruction and transmit the second correction instruction to the memory subsystem. The method of claim 1, wherein the signal analysis of the uncorrected command signal and data includes analyzing the phase difference between the command signal and the data, analyzing skew (SKEW) between the data based on the command signal, and determining whether the signal complies with a standard memory protocol. An interactive DRAM signal analyzer, comprising voltage level analysis. The method of claim 1, wherein the memory subsystem includes a memory controller, and the memory subsystem is configured to receive the first correction command using the memory controller and correct a protocol between a command signal and data. In,Interactive DRAM Signal Analyzer. The method of claim 1, wherein the memory subsystem includes a physical layer, and the memory subsystem is configured to adjust inter-data skew (SKEW) and correct voltage level using a training algorithm using the physical layer. , Interactive DRAM Signal Analyzer. In a real-time DRAM signal analysis and correction method using an interactive DRAM signal analyzer,
Receiving, by a signal input/output unit, a command signal and data transmitted from a System On Chip (SoC) including at least one processor through a memory subsystem; and
Generating, by a signal analysis processor, a correction command based on analysis of the received command signal and data.
Including,
transmitting, by the signal analysis processor, a first command signal and data received from the memory subsystem to a DRAM memory;
The signal analysis processor receives the uncorrected command signal and data fed back from the DRAM memory, generates a first correction command based on signal analysis of the uncorrected command signal and data, and executes the first correction command. delivering to the memory subsystem; and
Transferring, by the signal analysis processor, a second command signal and data corrected based on the first correction command from the memory subsystem to the DRAM memory.
A real-time DRAM signal analysis and correction method further comprising: