KR102668839B1 - Display device - Google Patents

Abstract

A display of an electronic device includes a plurality of separate transparent electrode blocks configured to provide one or more auxiliary features, such as touch recognition. Signal paths between transparent electrode blocks and drivers for auxiliary features are implemented with a plurality of conductive lines arranged beneath one or more planarization layers. Conductive lines implementing the signal paths are routed across the display area, directly towards the non-display area where the drive-integrated circuits are located.

Description

Display device {DISPLAY DEVICE}

This disclosure relates generally to electronic devices, and more specifically to electronic devices having displays and methods of manufacturing the same.

Electronic devices often include displays. For example, mobile phones and portable computers include displays for providing information to a user. In addition to displaying information, displays may support various auxiliary features. For example, a touch screen allows a user to interact with a display by simply touching a graphical interface displayed on the screen with a finger, stylus (pen), or other object. Touch screens, with their ease of use and flexibility of operation, are one of the most common user interaction mechanisms used in various flat panel displays such as liquid crystal displays (LCD) and organic light emitting diodes (OLED).

Typically, a separate substrate provided with a matrix of touch-driving lines and touch-sensing lines, which may be referred to as a touch panel, is overlaid or covered on the display panel to provide a touch-sensing function. However, placing a separate touch panel on the display panel increases the thickness and weight of the display panel. Similar problems may arise from adding separate components or substrates to displays for these auxiliary features, such as tactile feedback or pressure sensing functionality. As such, attempts have been made to integrate components associated with these auxiliary features within the stacks of layers that form the display panel.

However, integrating components related to auxiliary features (e.g., touch sensor, touch pressure sensor, tactile feedback sensor) into the display panel complicates the operation of the display panel and may even adversely affect display quality. there is. Conductive lines that transmit signals to and from display areas within the display panel, for example for the implementation of touch-sensing, touch-pressure sensing or tactile feedback mechanisms, are subject to unwanted parasitics with other components of the display panel. Capacitance may be created, which may cause visual artifacts (e.g., uneven tilting angles of liquid crystal molecules, line dimming, moire effects, etc.).

The present disclosure generally relates to display panels provided with auxiliary functions such as touch-sensing function, touch pressure sensing function and tactile feedback function, and more specifically, to a segment arranged over the display area of the display panel for such auxiliary functions. It relates to the configuration of segmented electrode blocks.

In the display panel, some elements used in connection with display functions may be configured to recognize touch inputs on the screen. For example, some drivers, such as gate drivers, data drivers, and touch drivers, may be configured to operate display pixels and provide signals to recognize touch inputs made on the screen. Additionally, some electrodes and/or conductive layers of the display pixels used to display images on the display panel may serve as part of a touch sensor.

In this way, the display panel can be provided with lower weight, thinner profile, and manufactured using fewer components in fewer manufacturing steps.

When implementing a touch sensor within a display panel, fine-tuning of both the touch-sensing function and the display function can be a difficult task. Among various types of LCD display panels, electrodes for generating electric fields that control the orientation of liquid crystal molecules are provided on the same side as the liquid crystal layer, so the arrangement of components for both functions is of the in-plane-switching (IPS) type. and fringe-field-switching (FFS) type LCD display panels.

Accordingly, a plurality of transparent electrode blocks (i.e., portions) provided on the display area of the display panel are provided in the display panel, and each transparent electrode block communicates with the touch driver through a signal path formed by at least one common signal line. It is configured to do so. Common signal lines are placed on the substrate and the common signal lines are covered with a lower planarization layer. A lower planarization layer is provided over the plurality of common signal lines with a thickness sufficient to provide a planar surface over the common signal lines. A plurality of gate lines, a plurality of data lines and a plurality of thin-film-transistors (TFTs) are provided on the flat surface provided by the lower planarization layer, and they form an array of pixel circuits within the display area. That is, the gate lines and data lines define a matrix of pixel regions, and a pixel circuit is provided with one or more TFTs in each pixel region. Accordingly, the substrate provided with the array of TFTs may be referred to as the TFT substrate or TFT backplane of the display panel.

The lower planarization layer must be formed of a material capable of maintaining a flat surface over the common signal lines and withstand the various processes associated with forming components thereon. For example, the lower planarization layer can be made of photoresist so that the lower planarization layer can withstand annealing processes, plasma treatments and other processes performed during the formation of the TFT array, electrodes and various other components positioned on the lower planarization layer. It must have sufficient thermal stability, mechanical stability, chemical durability and resistance to strippers/developers. For this purpose, the lower planarization layer may comprise a SOG layer formed from an organosiloxane hybrid layer based on Si-O monomers and polymers. More specifically, the lower planarization layer may include a hybrid polysiloxane polymer layer, and the hybrid polymer contains organic components including alkyl groups and aryl groups.

A top planarization layer is provided over the array of gate lines, data lines and TFTs. A plurality of transparent electrode blocks (eg, segmented portions of a common electrode) and a plurality of pixel electrodes are provided on the top planarization layer. Pixel electrodes are provided on a pixel basis, but each transparent electrode block is shared by a group of pixels.

Each of the transparent electrode blocks is configured to communicate with the touch driver through a signal path implemented with one or more common signal lines. Because some transparent electrode blocks are spaced farther from the touch driver than other transparent electrode blocks, the signal path for some transparent electrode blocks may be a parallel-connected signal path, implemented as a set of a plurality of common signal lines.

In some embodiments, signal paths for connecting each of the transparent electrode blocks to the touch driver may include a plurality of parallel-connected signal paths. For example, a first parallel-connected signal path and a second parallel-connected signal path may be provided in the display panel. The first parallel-connected signal path is implemented with a first set of a plurality of common signal lines. The second parallel-connected signal path is implemented with a second set of a plurality of common signal lines, distinct from the first set of common signal lines.

In some embodiments, one of the first parallel-connected signal path and the second parallel-connected signal path may be implemented with fewer common signal lines than the other signal path. A transparent electrode block connected to a signal path implemented with a smaller number of common signal lines may be located closer to the touch driver than a transparent electrode block connected to a signal path implemented with a larger number of common signal lines. For example, the second set of common signal lines implementing the second parallel-connected signal path may have more common signal lines than the total number of common signal lines included in the first set of common signal lines implementing the first parallel-connected signal path. It may also include a small number of common signal lines. The transparent electrode block connected to the second parallel-connected signal path may be located closer to the touch driver than the transparent electrode block connected to the first parallel-connected signal path.

In some embodiments, the common signal lines of the first set of common signal lines are interconnected in parallel with each other by an interconnection line provided below the lower planarization layer. Similarly, the common signal lines of the second set of common signal lines are interconnected in parallel with each other by interconnection lines provided below the lower planarization layer.

In some embodiments, at least one of the first parallel-connected signal path and the second parallel-connected signal path includes a main portion and a tail portion. The tail portion of the signal path is implemented with fewer common signal lines than the number of common signal lines implementing the main portion of the signal path. That is, the main part of the signal path may be implemented as an entire set of common signal lines, and the tail part of the signal path may be implemented as a subset of common signal lines from the set of common signal lines that implement the signal path.

In some embodiments, the tail portion of the first parallel-connected signal path or the tail portion of the second parallel-connected signal path may be configured as an independent parallel-connected signal path provided at an end of the main portion. In this case, the signal path includes a main parallel-connection and a tail parallel-connection.

In some embodiments, at least one of the first parallel-connected signal path and the second parallel-connected signal path includes a main section and a tail section, the tail section having a first section underlying one of the data lines and the data lines. Includes a second section placed one below the other. The first section and the second section of the tail portion may be connected in series. In this case, the signal path includes a main parallel-connection and a tail series-connection.

In some embodiments, transparent electrode blocks may be configured to implement a self-capacitance touch recognition system in a display panel. In this configuration, common signal lines forming a signal path connected to one of the transparent electrode blocks are routed under and across the other transparent electrode blocks such that each transparent electrode block is individually controlled by a touch driver. do.

In some other embodiments, transparent electrode blocks can be configured to implement a mutual-capacitance touch recognition system within a display panel. In this configuration, one or more common signal lines forming a signal path to one of the transparent electrode blocks are routed below and across the other transparent electrode blocks. The signal paths can optionally be grouped together to control optional groups of transparent electrode blocks, some of the optional groups serving as touch-actuating regions and some of the optional groups serving as inter-capacitance touch recognition systems. It serves as a touch-sensing area.

In some embodiments, the connection between the signal path and the transparent electrode block is through a bypass line. Common signal lines forming the signal path are formed from a first metal layer, which is deposited on the substrate. Bypass lines may be provided by the second metal layer M2 forming gate lines. A third metal layer M3 may be provided at the source/drain of the data lines and TFTs. In this setup, bypass lines are provided between the lower and upper planarization layers. Accordingly, the bypass line is connected to the common signal line through the lower contact hole through the lower planarization layer, and to the transparent electrode block through the upper contact hole through the upper planarization layer.

In some embodiments, common signal lines may be arranged in the same direction (eg, Y-axis) as the data lines. In these embodiments, each of the common signal lines may be arranged beneath one of the corresponding data lines. Bypass lines may be arranged in the same direction (eg, X-axis) as the gate lines.

In some embodiments, the display panel may further include a plurality of dummy lines. The dummy lines are formed from the same metal layer as the common signal lines and are covered below the lower planarization layer. The dummy lines are arranged in the same direction as the common signal lines. That is, dummy lines are placed along the data lines. In this case, each dummy line may be arranged to at least partially overlap one of the data lines.

In one aspect, a touch screen device is provided. In one embodiment, a touch screen device includes a plurality of pixels operated by a pixel electrode and a common electrode. The common electrode is divided into a plurality of separate parts of common electrode blocks. Each of the common electrode blocks is shared by a group of pixels. The touch screen device further includes a plurality of TFTs coupled to a plurality of pixels. TFTs are located on the lower planarization layer. A touch screen device also includes a touch driver. Also included in the touch screen device are a plurality of common signal lines disposed beneath the lower planarization layer.

The plurality of common electrode blocks include a first group of common electrode blocks and a second group of common electrode blocks. The signal paths for each and all of the common electrode blocks of the first group are implemented with the same number of common signal line(s). Similarly, the signal paths for each and all of the common electrode blocks of the second group are implemented with the same number of common signal line(s). However, the number of common signal lines used to implement the signal path for the common electrode blocks of the first group is equal to the number of common signal lines used to implement the signal path for the common electrode blocks of the second group Different. That is, each of the signal paths for the first group of common electrode blocks may be formed of a first number of common signal lines, and each of the signal paths for the second group of common electrode blocks may be formed of a second number of common signal lines. It may also be formed as a set of signal lines.

In some embodiments, at least some of the signal paths for the first group of common electrode blocks may include a main parallel-connection and a tail. The main parallel-connection is implemented as an entire set of common signal lines of the first number forming the signal path, while the tail part is implemented as a subset of common signal lines from the set of first number of common signal lines.

In some embodiments, at least some of the signal paths for the second group of common electrode blocks may include a main parallel-connection and a tail. The main parallel-connection is implemented as an entire set of common signal lines of the second number forming the signal path, while the tail part is implemented as a subset of common signal lines from the set of the second number of common signal lines.

Among the common signal lines of the first number of set of common signal lines, the subset of common signal lines used to implement the tail portion of each signal path is the remainder of the common signal lines of the first number of set of common signal lines. longer than Similarly, among the common signal lines of the second number of sets of common signal lines, the subset of common signal lines used to implement the tail portion of each signal path is the common signal of the second number of sets of common signal lines. longer than the rest of the lines.

In another aspect, an electronic device having a display is provided. In one embodiment, the electronic device has a display area provided with a plurality of pixels. A thin film transistor (TFT) array layer is arranged within the display area to control a plurality of pixels. At the top of the TFT array layer, a plurality of individual transparent electrode blocks are arranged to overlap a plurality of pixels in the display area. The electronic device also includes a driver configured to transmit signals to and from the plurality of individual transparent electrode blocks. A plurality of common signal lines located below the TFT array layer are further included in the electronic device. A plurality of common signal lines implement a plurality of signal paths between each of the plurality of transparent electrode blocks and the driver. Among the plurality of signal paths, one or more signal paths are provided with a main parallel-connection implemented as a set of a plurality of common signal lines and a tail part implemented as a subset of common signal lines from the set of the plurality of common signal lines. .

Additional features of the present invention, its characteristics and various advantages will become more apparent from the accompanying drawings and the detailed description of the preferred embodiments below.

1A and 1B are perspective views of example electronic devices, such as a laptop computer with a display and a small electronic device with a display, according to an embodiment of the present disclosure.
2 is a schematic diagram of an example electronic device with a display, according to an embodiment of the present disclosure.
3A is a schematic illustration of an example display panel having a plurality of transparent electrode blocks, where each of the transparent electrode blocks is connected to a common signal line and configured to operate in a self-capacitance touch sensor, according to an embodiment of the present disclosure. .
3B is a schematic illustration of an example display panel having a plurality of transparent electrode blocks, where each of the transparent electrode blocks is connected to a common signal line and configured to operate in a mutual-capacitance touch sensor, according to an embodiment of the present disclosure. .
4 is a timing diagram showing example timing of signals applied to pixel electrodes and transparent electrode blocks of pixels during display periods and during touch sensing periods, according to an embodiment of the present disclosure.
FIG. 5A is a timing diagram illustrating example timing of a signal used to provide multiple touch scanning intervals within a single frame, according to an embodiment of the present disclosure.
FIG. 5B is a diagram illustrating how the total duration of a single frame can be divided and allocated to accommodate multiple display sections and multiple touch scanning sections, according to an embodiment of the present disclosure.
FIG. 6A is a schematic diagram illustrating an example configuration of common signal lines and bypass lines in display panels, according to an embodiment of the present disclosure.
FIG. 6B is a cross-sectional view illustrating an example configuration for connecting a common signal line to a transparent electrode block through a bypass line, according to an embodiment of the present disclosure.
FIG. 6C is a schematic illustration showing the order in which metal layers form common signal lines, bypass lines, gate lines of a TFT, data lines, and source/drain, according to an embodiment of the present disclosure.
7A and 7B illustrate cross-sectional views of a display panel during manufacturing steps, according to an embodiment of the present disclosure.
8A is a cross-sectional view of an example embodiment in which at least some common signal lines are in direct contact with common electrode blocks through contact holes made through the upper planarization layer and the lower planarization layer in the SL-VCOM contact area.
FIG. 8B illustrates a cross-sectional view of the SL-VCOM contact area shown in FIG. 8A during manufacturing steps, according to an embodiment of the present disclosure.
9A is a top view and cross-sectional side view illustrating an exemplary configuration of a common signal line provided below a coplanar structure TFT, according to an embodiment of the present disclosure.
FIG. 9B is a cross-sectional side view of an example configuration of common signal line, bypass line, and transparent electrode blocks, according to an embodiment of the present disclosure.
10A is a top view of an example configuration of metal line traces in a non-display area of a display panel, according to an embodiment of the present disclosure.
10B is a cross-sectional side view of an example configuration of metal line traces in a non-display area of a display panel, according to an embodiment of the present disclosure.
11A is a circuit diagram of an example stage of a gate driver circuit for a display, according to an embodiment of the present disclosure.
FIG. 11B is a top and cross-sectional view of a capacitor provided in the stage of FIG. 11A, according to an embodiment of the present disclosure.
FIG. 12A is a circuit diagram of an example compensation circuit that may be provided in embodiments configured with an intra-frame pause driving scheme, according to an embodiment of the present disclosure.
FIG. 12B is a timing diagram of an example operation of a gate driver provided with the compensation circuit of FIG. 12A, according to an embodiment of the present disclosure.
Figure 13 is a schematic diagram showing an example configuration of common signal lines and their connections to transparent electrode blocks, according to an embodiment of the present disclosure.
14A to 14F respectively illustrate example configurations of common signal lines for implementing signal paths between common electrode blocks and a driver, according to embodiments of the present disclosure.
15A illustrates an example configuration of common signal lines in a bypass section.
15B illustrates another example configuration of common signal lines in a bypass section.
Figure 16 is a schematic illustration showing an example configuration of a masking layer, according to an embodiment of the present disclosure.
17A-17E illustrate various example configurations of a masking layer, according to embodiments of the present disclosure.
18A-18C illustrate example configurations of common signal lines with light shielding, according to an embodiment of the present disclosure.
FIG. 19A illustrates an example configuration for connection of a bypass line and a transparent electrode block in a BL-VCOM contact area, according to embodiments of the present disclosure.
19B illustrates a schematic cross-sectional view in the BL-VCOM contact area during manufacturing, according to an embodiment of the present disclosure.
20A illustrates an example configuration of a set of bypass lines for connecting a plurality of common signal lines (or dummy lines) to a common electrode block.
20B illustrates an example configuration of a set of bypass lines for connecting a plurality of common signal lines (or dummy lines) to a common electrode block.
20C shows one of the bypass lines extending toward the first side of the common signal line (or dummy line) and the other of the bypass lines extending toward the second side of the common signal line (or dummy line). , illustrates an example configuration of a set of bypass lines for a common electrode block.
FIG. 20D illustrates an example configuration of a set of bypass lines for a common electrode block, where a common signal line is provided with a plurality of contacts, each of which is routed to different pixel regions.
21A and 21B illustrate an example configuration of a display panel in the area between two adjacent transparent electrode blocks.

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numbers will be used throughout the drawings to refer to the same or similar parts.

Exemplary embodiments may be described herein with reference to a Cartesian coordinate system, where the x-direction and y-direction can be equated to the horizontal (row) direction and the vertical (column) direction, respectively. However, those skilled in the art will understand that references to specific coordinate systems are merely for clarity purposes and do not limit the orientation of the structures to a specific direction or specific coordinate system.

[Example Electronic Devices with Display]

Electronic devices may include displays used to display images to a user. Exemplary electronic devices provided with displays are shown in FIGS. 1A and 1B.

1A shows how the electronic device 10 may have the shape of a laptop computer with an upper housing (UH) and a lower housing (LH). Components such as a keyboard (INP1) and a touch pad (INP2) may be provided in the electronic device 10. The electronic device 10 may have a hinge structure (HNG) that allows the upper housing (UH) to rotate about a rotation axis (AX) related to the lower housing (LH). The display panel (PNL) may be mounted within the upper housing (UH), the lower housing (LH), or both the upper housing (UH) and the lower housing (LH). The upper housing (UH), which may sometimes be referred to as a display housing or lid, may be placed in a closed position by rotating the upper housing (UH) about the axis of rotation (AX) toward the lower housing (LH). . When the display panel PNL is mounted from the upper housing UH to the lower housing LH, the display panel PNL may be a foldable display. Additionally, the upper housing (UH) and lower housing (LH) may each include a separate display panel (PNL).

Figure 1b shows the electronic device 10 provided in the form of a small device, such as a mobile phone, a music player, a gaming device, a control console unit of a car, or other small device. In a configuration for this type of electronic device 10, the housing 12 may have opposing front and back sides. The display panel (PNL) may be mounted on the front of the housing (HS). The display panel (PNL) may, as the case may be, have a display cover layer or other outer layer containing openings for components such as buttons (BT), speakers (SPK) and cameras (CMR).

The configuration for electronic device 10 shown in FIGS. 1A and 1B is merely exemplary. Typically, electronic device 10 may be a laptop computer, a computer monitor, including an embedded computer, a tablet computer, a mobile phone, a media player, or other portable or small electronic device, a smaller device such as a wrist-watch device, a pendant, etc. The device, or other wearable or miniature device, television, computer display other than an embedded computer, gaming device, navigation device, electronic equipment having a display, is embedded in an embedded system such as a kiosk or a system mounted in a car (e.g. , dashboard, central console and control panel), or other electronic equipment.

The display panel (PNL) may include a touch-sensitive display that includes a layer with an array of transparent electrode blocks that serve as a touch sensor. The display panel PNL may be a touch-sensitive display comprising a layer with an array of transparent electrode blocks that act as a touch sensor capable of measuring the pressure of touch inputs. The display panel (PNL) may be a touch-sensitive display that includes a layer having an array of transparent electrode blocks that provide tactile feedback in response to touch inputs.

Displays for electronic device 10 are generally formed from light-emitting diodes (LEDs), organic LEDs (OLEDs), plasma cells, electrowetting pixels, electrophoretic pixels, and liquid crystal display (LCD) components. may include image pixels, or image pixels formed from other suitable image pixel structures.

Embodiments of the present disclosure relate to LCDs, particularly in-plane-switching (IPS) mode LCDs and fringe-field-switching (FFS) mode LCDs, with common electrodes and pixel electrodes arranged on one of the substrates surrounding the liquid crystal layer. ) mode is described in the context of LCD. However, the features described herein have technical similarities in that the display carries signals from the driver of the display device and has a plurality of conductive lines connected to an array of transparent electrode blocks located below and/or above the array of TFTs. If so, it should be understood as a technology that can be applied to various other types of displays that include these features. That is, the features described in this disclosure can also be adopted in display technologies other than LCD displays, such as organic-light-emitting-diode (OLED) displays, electro-luminescent displays, etc.

For example, in an OLED display, a plurality of conductive lines may be located on one side of the TFT array, and the conductive lines may be connected to an array of transparent electrode blocks provided on the other side of the TFT array. Transparent electrode blocks provided on the other side of the TFT array may serve as touch sensors to provide touch recognition functionality. As mentioned above, the function of the array of transparent electrode blocks provided on the TFT array is not limited to touch sensing, and may be used for various other functions such as touch-pressure sensing function, tactile feedback function, etc. As such, it should be noted that the terms “transparent electrode blocks” and “common electrode blocks” are used interchangeably in this disclosure.

[Example display panel]

Figure 2 schematically illustrates the configuration of a display panel (PNL) according to an embodiment of the present invention. Referring to FIG. 2 , the display panel PNL includes a plurality of display pixels P connected to a plurality of data lines DL and a plurality of gate lines GL. The data driver (DD) and gate driver (GD) are provided in an area outside the display area, which may be referred to as a non-active area (i.e., non-display area). The data driver (DD) and gate driver (GD) provide data signals and gate signals to the data lines (DL) and gate lines (GL), respectively, in order to drive the display pixels (P) of the display area. It is composed.

Pixels containing electrodes or other capacitive elements may be used for display functions and touch-sensing functions. In an LCD, for example, a layer of liquid crystal molecules (i.e., a liquid crystal layer) is sandwiched between two substrates, and one of the two substrates generates electric fields to control the amount of light passing through the layer of liquid crystal molecules. The pixel electrode and the common electrode provided in are provided with a data voltage and a common voltage, respectively. Light passing through the liquid crystal layer also passes through color filters and a black matrix provided on one of the substrates to represent images on the screen. In the display panel PNL shown in FIG. 2, the common electrode VCOM is subdivided into a plurality of common electrode blocks (marked B1 to B12). For simpler explanation, only B1 to B9 are shown in Figure 2. However, the common electrode VCOM may be provided with a larger number of separate parts of common electrode blocks.

Each of the display pixels P includes a TFT having a gate, source, and drain. Each display pixel (P) includes a capacitor formed of a pixel electrode (PXL) and a common electrode (VCOM). The gate of the TFT is connected to the gate line (GL), the source of the TFT is connected to the data line (DL), and the drain of the TFT is connected to the pixel electrode (PXL) of each pixel.

The touch driver (TD) transmits touch-sensing related signals to and from each of the common electrode blocks through a plurality of common signal lines (SL) in order to use the common electrode blocks when sensing touch inputs on the display panel (PNL). It is configured to transmit and receive messages. Transparent electrodes provided in the display panel (PNL) other than the common electrode (VCOM) may be subdivided into a plurality of segmented blocks, and to the touch driver (TD) via a plurality of common signal lines (SL) and the touch driver. It should be understood that it may be configured to transmit and receive touch-sensing related signals from (TD).

In an OLED display panel, a plurality of separate transparent electrode blocks arranged across the display area of the OLED display panel may also be configured to communicate with a touch driver (TD) via common signal lines (SL).

In some embodiments, the data driver (DD), gate driver (GD), and touch driver (TD) may all be provided on the substrate of the display panel (PNL). In some other embodiments, some of these drivers are on a separate printed circuit board coupled to the substrate of the display panel (PNL) via suitable interface connection means (e.g., pads, pins, connectors, etc.). may be provided. Although the data driver (DD), gate driver (GD), and touch driver (TD) are each illustrated as separate components in Figure 2, some or all of these drivers may be integrated together into a single component. For example, the touch driver (TD) may be provided as part of the data driver (DD). In these cases, some of the signals related to the touch sensing function communicated between the touch driver (TD) and the plurality of common electrode blocks may be transmitted through the data driver (DD). Additionally, the data driver (DD) and the touch driver (TD) may be provided on the same printed circuit board, connected to common signal lines (SL) and data lines (DL) provided on the board of the display panel (PNL). there is.

3A and 3B illustrate example configurations of transparent electrode blocks (ie, common electrode blocks) and lines for transparent electrode blocks for implementing a touch sensor within the display panel (PNL). In particular, FIG. 3A illustrates an example configuration of common electrode blocks B1 to B9 and common signal lines SL for a self-capacitance touch recognition system. In the self-capacitance touch recognition system, each of the common electrode blocks B1 to B9 functions as a touch sensing electrode with unique coordinates, and therefore the change in capacitance read from each of the common electrode blocks corresponds to the touch on the display panel PNL. It can be used to detect the location of inputs. To achieve this, each common electrode block is provided with an individual signal path to the touch driver (TD) implemented as a common signal line (SL). That is, each common signal line (SL) is connected to only one common electrode block, but each common electrode block is connected to a plurality of common signal lines (SL) forming a signal path between the common electrode block and the touch driver (TD). It may be connected to .

FIG. 3B illustrates an example configuration of common electrode blocks B1 to B9 and common signal lines SL for a mutual-capacitance touch recognition system in the display panel PNL. Unlike self-capacitance touch recognition systems, mutual-capacitance touch recognition systems rely on changes in capacitance between a pair of touch-actuating electrodes and touch-sensing electrodes to detect the location of touch inputs on the display panel (PNL). Accordingly, in a mutual-capacitance touch recognition system, common electrode blocks are selectively grouped together such that some groups of common electrode blocks serve as touch-actuating electrodes and some other groups of common electrode blocks serve as touch-sensing electrodes. . To this end, the common signal lines SL are formed by groups of common electrode blocks arranged in one direction (e.g., X-direction) collectively forming touch-driving electrodes (e.g., TX1 to TX3). And, groups of common electrode blocks arranged in different directions (eg, Y-direction) may be grouped together to collectively form touch-sensing electrodes (eg, RX1).

Common signal lines (SL) connected to the corresponding common electrode blocks are routed directly through the active area (i.e. display area) of the display panel (PNL) and outside the active area to form TX lines or RX lines. are grouped together in As an example, the common signal lines SL from the common electrode blocks B1 and B3 are grouped together as illustrated in FIG. 3B such that the first touch drive line TX1 is formed in the X-direction. Similarly, common electrode blocks B4 and B6, and common signal lines SL from common electrode blocks B7 and B9 are grouped together to form touch-drive lines TX2 and TX3, respectively. do. The touch-sensing line RX is formed in the Y-direction by grouping the common signal lines SL from the common electrode blocks B2, B5, and B8. The TX lines TX1-TX3 may be arranged in the same direction as the gate lines GL (e.g., X-direction), and the touch-sensing line RX is aligned with the data lines DL (Y-direction). direction) may be arranged in the same direction. In this way, a mutual capacitance is formed at the intersection between the TX lines and the Rx lines.

In FIGS. 3A and 3B, only nine common electrode blocks are shown for simpler explanation. However, it should be understood that the number of common electrode blocks provided in the display panel PNL is not so limited, and the common electrode of the display panel PNL may be additional parts of the common electrode blocks. As a non-limiting example, the display panel (PNL) may include 36 x 48 common electrode blocks. Additionally, it should be noted that the size of individual display pixels may be much smaller than the size of individual units of the touch sensing area to be provided within the display panel (PNL). That is, the size of each common electrode block may be larger than the size of an individual display pixel. Thus, a group of pixels may share a single common electrode block, but each of these pixels is provided with an individual pixel electrode. In a non-limiting example, a single common electrode block may be shared by pixels arranged in 45 rows by 45 columns (each pixel containing red, green, and blue sub-pixels).

[Touch scan operation]

FIG. 4 illustrates example signals applied to common electrode blocks through common signal lines SL during a display period and a touch-sensing period according to an embodiment of the present disclosure. Since the common electrode blocks are also used as touch electrodes, they transmit signals related to display functions during a specific period and receive signals related to touch sensing during a specific period. That is, one frame section defined by a vertical synchronization (sync) signal includes a display section and a touch-sensing section.

A display period may be just a portion of one frame period. In the display period, gate signals and data signals are provided to the gate lines GL and data lines DL, respectively, to charge new image data to the pixels. The remaining frame intervals can be used to scan common electrode blocks to identify touch inputs on the screen as well as to prepare pixels to receive the next image data. For example, each frame is 16.6 ms when the display panel is configured to operate at a frequency of 60 frames per second. Within 16.6 ms, approximately 12 ms can be dedicated to the display period. The remainder can be used to perform touch-sensing functions and to prepare the pixels to receive new frames of image data.

Accordingly, during the display period, the common voltage signal is transmitted from the data driver DD to the common electrode blocks. During the touch scan period, a touch-driving signal is transmitted from the touch driver (TD) to the common electrode blocks through the common signal lines (SL).

In some embodiments, the common voltage signal may be in the form of a pulse signal that swings between positive and negative voltages to perform LCD inversion. In some embodiments, the common voltage signal is supplied to the common electrode blocks through common signal lines SL. Alternatively, in some other embodiments, the common voltage signal may be supplied to the common electrode blocks through a dedicated common voltage signal line (SL) rather than the common signal line (SL). Additionally, in some embodiments, the common signal lines SL may be auxiliary for supplying the common voltage signal to the common electrode blocks, in addition to signal lines dedicated to supplying the common voltage signal to the common electrode blocks. It can also serve as a means.

[Intra-Frame Pause touch scanning scheme]

In some embodiments, the display panel PNL may be configured to perform a touch scan operation at least twice within a single frame. That is, the display section within the frame may be divided into at least two separate display sections, and the middle touch scan section may be located between the two separate display sections of the same frame. 5A illustrates an example Intra Frame Pause (IFP) driving scheme, which may be used in embodiments of a display panel (PNL) of the present disclosure. Accordingly, the intra-frame touch scan operation is performed at least once between two separate display periods of the same frame and at least once more during a blanking period before the next frame begins. During the intermediate touch scan period located between two separate display periods, the scan signal is not provided on the gate lines GL. This gate driving scheme may also be referred to as IFP “intra-frame pause” driving.

Referring to FIG. 5A, the frame includes a first display section and a second display section separated by an IFP touch scan section. The blanking section follows the second display section. During the first display period, scan signals are sequentially provided to the gate lines GL1 to GL(m). After the scan signal is supplied to the gate line GL(m), an intra-frame touch scan operation starts on the display panel PNL. Supplying the scan signal to the gate lines (GL(m+1) to GL(end)) is restarted after completion of the intra-frame touch scan operation. Once the scan signal is supplied to all gate lines GL, another touch scan operation is performed during the blanking period. In some cases, an additional display section and an additional intra-frame touch scan section may be provided within a single frame to increase the touch scan resolution of the display panel (PNL).

In the example shown in FIG. 5B, a display panel with 2048 gate lines GL may be driven at 120 Hz (120 frames per second). By having 2048 gate lines, a single frame can include a first display period and a second display period each of which is 1024H long. The IFP touch scan section between the first display section and the second display section may be 182H long, and the blanking section following the second display section may be 800H long.

In this example, the length of the first display period and the length of the second display period are the same. However, it should be understood that the length of the first display section and the length of the second display section may be different from each other. In other words, the number of gate lines to which scan signals are provided during the first display period may be different from the number of gate lines to which scan signals are provided during the second display period.

As will be described in more detail below, temporarily stopping the scan signal output on the same gate line every frame requires specific parts of the gate driver (GD) (e.g., specific stages of the shift register, specific transistor(s), etc.) may accelerate the deterioration. Accordingly, in some embodiments, the length of the first display period and the length of the second display period may vary between two different frames. As an example, the first display period during the first frame may be longer than the second display period (i.e., a greater number of gate lines during the first display period than the number of gate lines to which the scan signal is supplied during the second display period. scan signal is supplied to). In the second frame, the first display period may be shorter than the second display period (i.e., fewer gate lines are scanned during the first display period than the number of gate lines to which the scan signal is supplied during the second display period. signal supplied).

When the common electrode blocks are configured as a self-capacitance touch recognition system, touch-drive pulses are provided to each of the common electrode blocks, and signals from each of the common electrode blocks determine whether a touch input is registered to a particular common electrode block. analyzed to make a decision. More specifically, in a self-capacitance touch recognition system, charging or discharging touch-drive pulses on common electrode blocks can be used to determine touch inputs on the common electrode blocks. For example, a change in capacitance value during a touch input changes the time for the voltage to drop on the common electrode block. These changes on each of the common electrode blocks can be analyzed to determine the location of the touch input on the display panel (PNL).

When the common electrode blocks are configured as a mutual-capacitance touch recognition system, groups of common electrode blocks consisting of touch-driving lines (TX) are provided with touch-driving pulses, and groups of common electrode blocks consisting of touch-sensing lines (RX) are provided. Groups of common electrode blocks are provided with a touch reference voltage signal. A touch input made on the display panel (PNL) changes the capacitive coupling at the intersection of the touch-driving line (TX) and the touch-sensing line (RX), and the current carried by the touch-sensing line (RX) changes. Raw information or information in partially processed form may be used to determine the positions of touch inputs on the display panel (PNL). The touch driver (TD) performs this operation at high speed for each intersection of the TX and RX lines to provide multipoint sensing.

In the example shown in FIG. 3B, each of the TX lines is defined by a group of common electrode blocks arranged in a row (X-direction), and each of the RX lines is defined by a group of common electrode blocks arranged in a column (Y-direction). Defined as a group. The number of TX lines and RX lines within the display panel (PNL) may be adjusted according to the arrangement and sizes of common electrode blocks within the active area.

The arrangement of the common electrode blocks is not limited as shown in FIG. 3B and may be arranged in various other ways depending on the desired layout of the TX lines and RX lines of the display panel (PNL). The number of TX lines implemented with common electrode blocks arranged in a single row as well as the number of RX lines implemented with common electrode blocks arranged in a single column may vary depending on various factors. For example, based on the size of the display panel (PNL) as well as the touch scanning frequency and accuracy, common electrode blocks arranged in a single row can be used to provide a plurality of TX lines, and common electrode blocks arranged in a single column can be used to provide multiple TX lines. Can be used to provide multiple RX lines.

Additionally, the RX line of the mutual-capacitance touch recognition system may be formed of common electrode blocks that are larger than the common electrode blocks that form the TX lines. For example, instead of using a plurality of common electrode blocks arranged in the column direction to form the RX line, a single large common electrode block extending across the active area in the column direction (i.e., Y-direction) serves as the RX line. can be used

To improve touch-sensing accuracy at the edges of the display panel (PNL), a common signal line from common electrode blocks located at each of the outermost ends of the active area (i.e., left end and right end) The lines SL may be grouped together such that RX lines are formed at the outermost ends of the active area. In this way, touch inputs made with objects having a touch point much smaller than the typical size of a finger (eg, 2.5Φ) can be recognized at the edges of the display panel PNL.

To further improve the performance of the touch-sensing capability, the width of the common electrode blocks serving as RX lines at the outermost end of the display panel (PNL) is changed to the width of other touch-sensing blocks in different areas of the display panel (PNL). It may be different from . Configuring common electrode blocks as RX lines at the outermost ends of the display panel (PNL) enables more accurate touch input recognition even from the very ends of the active area. However, this means that the positions of the common electrode blocks serving as TX lines will be shifted from the edges by the width of the common electrode blocks serving as RX lines. Additionally, each TX line does not extend completely across the RX lines located at the edges. Accordingly, the width of the common electrode blocks at the edges may be narrower than the width of the common electrode blocks in other areas of the active area. For example, the width of the common electrode blocks measured in the X-direction may be half that of the common electrode blocks located elsewhere.

To improve touch-sensing accuracy at the top edge and bottom edge of the display panel (PNL), the common electrode blocks at the top edge and bottom edge of the display panel (PNL) have other common electrodes in different areas of the display panel (PNL). Compared to blocks, they may have a reduced width when measured in the Y-direction. In this way, narrower TX lines can be provided at the top and bottom edges of the display panel (PNL).

Regardless of the type of touch recognition system implemented in the display panel (PNL), each of the common electrode blocks is connected to at least one common signal line (SL). The common signal lines SL extend parallel to each other and are routed out of the active area in the same direction as the data lines DL. Arranging the common signal lines (SL) parallel to each other and routed across the active area toward the drivers eliminates the need for space in the non-display area of the display panel to route the common signal lines (SL). and thus reduce the size of the bezel.

Each of the common signal lines (SL) connected to the corresponding common electrode block proceeds across the active area of the display panel (PNL) toward the non-display area and bypasses the common electrode blocks connecting other common signal lines. )do. For example, in order to reach a non-display area where the drivers are located without contacting the common electrode blocks B4 and B7 at the root, the common signal line SL connected to the common electrode block B1 is connected to the common electrode block B1. fields (B4 and B7) are routed across below.

The common signal lines SL cannot be located directly above the surface of the common electrode blocks. If the common signal lines SL are routed on the surface of the common electrode blocks, the common signal lines SL will contact a plurality of common electrode blocks along the path to the non-display area. This will disturb the intrinsic coordinates of the common electrode blocks of the self-capacitance touch recognition system or disrupt the formation of TX/RX lines in the mutual-capacitance touch recognition system.

Additionally, when the common signal lines SL are located in the same layer as the pixel electrode PXL, the coupling created between the common signal lines SL and the pixel electrode PXL is When used to adjust common electrode blocks during this touch-sensing period, it may cause various display defects. Therefore, locating the common signal lines SL in the same layer as the pixel electrodes PXL makes it difficult to reduce the space between the common electrode blocks and the pixel electrode PXL, resulting in lower storage capacitance. . Additionally, an unwanted fringe field may be generated when the common signal lines SL are located in the common electrode layer or the pixel electrode layer. These fringe fields can affect liquid crystal molecules and cause unwanted light leakage. Accordingly, in order to route the common signal lines SL across the active area of the display panel PNL, the plane level of the common signal lines SL must be different from the plane levels of the pixel electrode and the common electrode blocks.

Placing common signal lines (SL) between a layer of pixel electrodes and a layer of common electrode blocks poses similar problems. In this configuration, an insulating layer must be provided between the layer of common electrode blocks and the layer of common signal lines (SL). The thickness of the insulating layer interposed between the pixel electrodes and the common electrode blocks is limited in IPS mode LCD devices or FFS mode LCD devices, as it cannot be greater than the thickness of the insulating layer between the layer of pixel electrodes and the layer of common electrode blocks. Therefore, the thickness of the common signal lines SL is limited.

For example, when the thickness of the insulating layer interposed between the pixel electrode and the common electrode blocks is about 3000 Å, when the common signal lines SL are located between the common electrode blocks and the pixel electrode, the common signal lines (SL) The thickness of SL) is limited to approximately 2500 Å. Since thickness is one of the factors that affect the line resistance of the common signal lines (SL), the limit on the thickness of the common signal lines (SL) is the limit of the signals between the driver and the common electrode blocks. During transmission, this significantly limits the performance of the common signal lines (SL), especially when the size of the display area in the device becomes larger.

For the reasons mentioned above, the common signal lines SL are located below the array of TFTs so that they are sufficiently spaced apart from the pixel electrode and common electrode blocks provided above the array of TFTs. This setting provides more freedom when increasing the width and thickness of the common signal lines (SL). For this purpose, one or more planarization layers are provided between the common signal lines SL and the common electrode blocks, and the common signal lines SL are connected through the planarization layer to the corresponding common electrode blocks through contact holes. . In these settings, each of the common signal lines (SL) connected to the common electrode block can be routed across the active area without contacting other common electrode blocks located along its route. The common signal lines SL may simply bypass the common electrode blocks along the path to the touch driver TD in the active area.

[Bypass lines]

In some embodiments, the common signal lines SL are connected to corresponding common electrode blocks through bypass lines connected to both the common signal lines SL and the common electrode blocks through contact holes in the planarization layers. connected.

FIG. 6A is a top view of an example configuration of common signal lines (SL) and bypass lines (BL) in a matrix of pixel areas in the display panel (PNL) according to an embodiment of the present disclosure. Referring to FIG. 6A , the data lines DL and the gate lines GL are arranged to intersect each other, defining a matrix of pixel areas of the display area of the display panel PNL. The common signal lines SL are arranged to extend in the same direction as the data lines DL. Each of the common signal lines SL is positioned to at least partially overlap the data line DL to minimize reduction of the aperture ratio of the pixel areas due to the common signal lines SL. As will be described below, the dummy line (DML) may be located under some data lines (DL) instead of the common signal line (SL).

A TFT is provided in each pixel area. The TFT may be formed with a bottom gate structure with the source and drain provided on opposite sides of the semiconductor layer (SEM). This TFT structure is sometimes referred to as an inverted staggered structure or a back-channel etched structure. The source electrode of the TFT extends from or is otherwise connected to the data line DL, and the drain is connected to the pixel electrode PXL (not shown in Figure 6A) provided in the corresponding pixel area. The pixel electrode PXL is provided with a plurality of slits to generate an electric field together with an overlapping common electrode block (not shown).

Common signal lines SL are located below the TFTs of the pixels, and each of the common electrode blocks is connected through contact holes (i.e., lower contact hole: CTL; upper contact hole: CTU) through planarization layers formed on the TFTs. It is connected to one of the corresponding common signal lines (SL). In this configuration, each common signal line (SL) is connected to at least one bypass line (BL) connected to a corresponding common electrode block.

The bypass line BL is arranged in the same direction as the gate line GL such that the bypass line BL extends from one pixel area to another pixel area in the same column. That is, the connection between the bypass line (BL) and the common signal line (SL) may be made through a contact hole provided in one pixel area, and the connection between the bypass line (BL) and the common electrode block may be made through a contact provided in another pixel area. This can be done through a hole. As shown in FIG. 6A, the useful aperture ratio in the pixel areas is the bypass lines (BL) and the common signal lines (SL) and contact holes (CTL) for connecting the common electrode blocks to the bypass lines (BL). , CTU).

6B is a cross-sectional view showing an example configuration for connecting a common signal line to a common electrode block through a bypass line BL. FIG. 6C shows metal layers to form the common signal lines (SL), bypass lines (BL), gate lines (GL), data lines (DL) of the display panel (PNL), and the source/drain of the TFT. Illustrates the order in which they are placed on top of each other. In this disclosure, metal layers are referenced according to the order in which each of the metal layers is located on the substrate.

Referring to FIGS. 6B and 6C, the common signal lines SL are formed using the first metal layer on the substrate. The metal layer used to form the common signal lines SL is referred to as the first metal layer M1 because it is the first metal layer disposed on the substrate, and for convenience of explanation, the other metal layer on the first metal layer M1 is the first metal layer M1. In order from the first metal layer (M1), they are referred to as the second metal layer (M2), the third metal layer (M3), etc. The second metal layer M2 may be referred to as a gate metal layer and the third metal layer M3 may be referred to as a source/drain metal layer.

It should be noted that the term “first metal layer” need not mean a layer consisting of a single metal layer. Instead, the term “first metal layer” refers to a metal layer or stack of metal layers that may be formed on a surface and that is insulated from another layer of metal layer or stack of metal layers by an insulating layer. Similar to the first metal layer M1, other subsequent metal layers (e.g., second metal layer M2, third metal layer M3) in embodiments of the present disclosure are formed from a plurality of layers of different metals. It could be.

The metal layers forming the common signal lines (SL), gate lines (GL), bypass lines (BL), and data lines (DL) are metal layers such as copper, molybdenum, titanium, aluminum, and combinations thereof. It may be formed as a stack of In a suitable embodiment, the first metal layer (M1) may be in the form of a stack of a copper layer (Cu) and a molybdenum-titanium alloy layer (MoTi). The second metal layer (M2) may also be a stack of a copper layer (Cu) and a molybdenum-titanium alloy layer (MoTi). The third metal layer (M3) may be a stack of a molybdenum-titanium alloy layer (MoTi), a copper layer (Cu), and another molybdenum-titanium alloy layer (MoTi). The copper layer may be thicker than the molybdenum-titanium alloy layer of each of the metal layers.

[Lower flattening layer]

To provide an array of TFTs on the common signal lines SL, a lower planarization layer PLN-L is provided on the common signal lines SL. The thickness of the lower planarization layer (PLN-L) may vary depending on the thickness of the common signal lines (SL). For example, the thickness of the common signal lines SL may range from about 2500 Å to about 7500 Å, more preferably from about 3500 Å to about 6500 Å, and more preferably from about 4500 Å to about 5500 Å. In a specific example, the common signal lines SL are formed from a first metal layer M1 in the form of a stack of a copper layer (Cu) and a molybdenum-titanium alloy layer (MoTi), the thickness of the copper layer being about 4500 Å. to about 5500 Å, and the thickness of the molybdenum-titanium alloy layer (MoTi) may range from about 100 Å to about 500 Å.

The thickness of the lower planarization layer (PLN-L) covering the common signal lines (SL) ranges from about 0.5 μm to 4 μm, more preferably from about 0.5 μm to 3 μm, and more preferably from about 0.5 μm to 2 μm. It may be possible. The thickness of the planarization layer covering the common signal lines SL may vary based on various factors, such as dielectric properties, materials, manufacturing processes, etc.

An array of TFTs is fabricated on the lower planarization layer (PLN-L). It should be noted that the fabrication of TFTs involves high temperature processes and chemical treatments. The top planarization layer (PLN-U) disposed on the TFT is not directly affected by the processes and treatments involved in the manufacture of TFTs. Meanwhile, the lower planarization layer (PLN-L) provided below the TFTs is directly affected by the processes and treatments performed during the manufacturing of the TFTs, the electrodes of the lower planarization layer (PLN-L) and other components.

Accordingly, the lower planarization layer (PLN-L) is provided with photoresist strippers/developer so that the lower planarization layer can withstand the processes and treatments performed in the formation of the array of TFTs, electrodes and various other components implementing the pixel circuit. It must have sufficient thermal stability, mechanical stability, chemical durability and resistance to various substances.

For example, while manufacturing a TFT with an oxide semiconductor layer such as indium-gallium-zinc-oxide (IGZO), some processes may be performed above about 350°C. Fabrication of TFTs with a poly-silicon semiconductor layer may require processes performed at much higher temperatures. As such, the lower planarization layer (PLN-L) cannot be formed of photo-acrylic, which is generally used as a planarization layer covering TFTs. Instead, the lower planarization layer (PLN-L) is used to cover the common signal lines (SL) and to provide a flat surface to the TFTs to be fabricated on the planarization layer, while maintaining the optical properties and physical structure to be used in the display panel (PNL). To provide a surface, it may be formed of a material that exhibits sufficient thermal stability.

In particular, the lower planarization layer (PLN-L) must maintain a flat surface on the common signal lines (SL) at a temperature of 350° C. or higher. More preferably, the lower planarization layer (PLN-L) may maintain a flat surface on the common signal lines (SL) at a temperature of 380° C. or higher. Stated differently, the lower planarization layer (PLN-L) may include a material that exhibits a thermal gravimetric analysis (TGA) of less than 1% for 30 minutes at 350°C (% weight loss at 350°C/30min). More preferably, the lower planarization layer (PLN-L) may comprise a material exhibiting a TGA of less than 0.1% at 380° C. for 30 minutes.

The lower planarization layer (PLN-L) must exhibit suitable optical properties even after the processes and treatments involved during the fabrication of TFTs. These are particularly desired properties for LCD panels because the light emitted from the light source passes through the lower planarization layer (PLN-L). In this regard, the average light transmittance of the lower planarization layer (PLN-L) is greater than 70%, more preferably greater than 80%, more preferably greater than 90% (measured for a thickness of 400 to 800 nm on soaked glass). %). Additionally, the refractive index of the material for forming the lower planarization layer (PLN-L) may be in the range of 1.4 to 1.6. In a specific example, a 400 nm thick soaked glass coated with a bottom planarization layer (PLN-L) exhibits an average light transmittance of about 91.24% to 91.25% even after being placed at 380° C. for 30 minutes. Additionally, the lower planarization layer (PLN-L) exhibits a refractive index of 1.49 at a thickness of 633 nm.

The lower planarization layer (PLN-L) must also exhibit sufficient chemical durability to withstand chemical treatments during the fabrication of TFTs, electrodes and other components on the lower planarization layer (PLN-L). For example, the lower planarization layer (PLN-L) must exhibit sufficient chemical durability against deionized water (DI), isopropyl alcohol (IPA), and propylene glycol methyl ether acetate (PGMEA). In a specific example, the thickness of the lower planarization layer (PLN-L) (e.g., 1.3 μm) may vary by less than 10 Å when treated with DI water or IPA (70 °C/10 min) and PGMEA (RT/10 min). ) may change to less than 20 Å when processed.

The lower planarization layer (PLN-L) must also have sufficient resistance to photoresist strippers/developers used in the fabrication of the TFTs, electrodes and other components on the lower planarization layer (PLN-L). In certain instances, the thickness of the lower planarization layer (PLN-L) (e.g., 1.3 μm) may vary by less than 10 Å when treated with N-Methyl-2-pyrrolidone (NMP) (70 °C/10 min). and may change to less than 20 Å when treated with 2.38% tetra-methyl-ammonium hydroxide (TMAH) (RT/10min).

In some embodiments, the lower planarization layer (PLN-L) is formed of an organosiloxane hybrid layer based on Si-O monomer and polymer. In this disclosure, the hybrid polysiloxane polymer layer may simply be referred to as a SOG layer.

In embodiments in which the lower planarization layer (PLN-L) is formed of a SOG layer, the lower planarization layer may include a hybrid polysiloxane polymer layer, and the hybrid polymer includes an alkyl group and an aryl group, expressed in Formula 1 below: Contains organic components.

[Formula 1] (n and m refer to the number of repeating units)

The material (e.g., SOG layer) for forming the lower planarization layer (PLN-L) is also spun to cover the common signal lines (SL) and provide a planar surface on the common signal lines (SL). - Must be suitable for on-glass method, slit coating method, slot-die coating method or other suitable coating methods. In some embodiments, the viscosity profile of the material forming the lower planarization layer (PLN-L) ranges from 2.5 cps to 3 cps at 25°C, and more preferably ranges from 2.5 cps to 2.7 cps at 25°C. The density of the material forming the lower planarization layer (PLN-L) may be about 1.0 g/ml at 25°C. The curing process may be performed when the lower planarization layer (PLN-L) is coated over the common signal lines (SL).

Metallic ions from the first metal layer (M1) forming the common signal lines (SL) are removed from the lower planarization layer (PLN-L) by heat from the curing process of the lower planarization layer (PLN-L) and/or the annealing processes involved in TFT manufacturing. It may spread within (PLN-L). Similarly, metallic ions from the second metal layer (M2) forming the gate lines (GL) and bypass lines (BL) also form the lower planarization layer (PLN-L) due to the heat involved during the curing/annealing processes. It may spread internally. For example, diffusion of copper (Cu) into the lower planarization layer may occur when the first metal layer (M1) or the second metal layer (M2) includes copper (Cu). Additionally, metallic ionic impurities and/or moisture from the glass substrate may also diffuse into the lower planarization layer (PLN-L). These metallic ions and other impurities diffused into the lower planarization layer (PLN-L) can increase the dielectric constant of the lower planarization layer (PLN-L), which ultimately interferes with the touch-sensing performance of the display panel (PNL). (Resistance-Capacitance) Increases delay time.

Accordingly, in some embodiments, a passivation layer (PAS1) serving as a capping layer is provided below the lower planarization layer (PLN-L). In these embodiments, the passivation layer (PAS1) covers the common signal lines (SL) and the surface of the substrate. The passivation layer (PAS1) not only blocks metallic ions and other impurities from the common signal lines (SL) and the substrate, but also improves the adhesion of the lower planarization layer (PLN-L) to the substrate. Additionally, in some embodiments, the passivation layer (PAS2) may be provided on the lower planarization layer (PLN-L). In this case, the passivation layer PAS2 includes the lower planarization layer PLN-L and the second metal layer M2 (e.g., gate lines GL, It is interposed between bypass lines (BL)).

The passivation layers (PAS1 and PAS2) may be a silicon nitride layer, a silicon oxide layer, or stacks of these layers. In some suitable embodiments, the passivation layer (PAS1) below the lower planarization layer (PLN-L) and the passivation layer (PAS2) on the lower planarization layer (PLN-L) may be provided with substantially the same thickness and may be provided with the same organic layer. It may also be formed from a material. For example, both the passivation layer PAS1 and the passivation layer PAS2 may be silicon nitride layers with a thickness of about 1000 Å to about 3000 Å. In some suitable embodiments, the lower planarization layer (PLN-L) having a thickness of 17,000 Å may be provided with a passivation layer (PAS1) and a passivation layer (PAS2) each having a thickness of 2000 Å.

The passivation layer (PAS2) not only acts as a capping layer, but also protects the lower planarization layer (PLN-L) from unwanted evaporating gases/smoke/fumes (e.g. hydrogen gas) from the lower planarization layer (PLN-L). It can provide protection for components located on PLN-L). In this way, the material and composition of the passivation layer (PAS2) between the lower planarization layer (PLN-L) and the array of TFTs may vary depending on the semiconductor layer (i.e., active layer) of the TFTs on the lower planarization layer (PLN-L). You can. For example, in some embodiments, the passivation layer PAS2 may be formed of a silicon nitride layer when the TFTs thereon use a metal oxide semiconductor (eg, IGZO). In some embodiments, the passivation layer PAS2 is between the lower planarization layer PLN-L and the conductive lines of the second metal layer M2, for example, the gate lines GL and the bypass lines BL. Please note that it may be provided to .

The common signal lines (SL) are disposed under the lower planarization layer (PLN-L), and the gate lines (GL) and the gates (G) of the TFTs are disposed on the lower planarization layer (PLN-L) with a second metal layer ( It is formed as M2). The bypass lines BL are also formed from the second metal layer M2 provided on the lower planarization layer PLN-L. A semiconductor layer (eg, oxide, LTPS, a-Si) is formed on the gate insulating layer (GI) to provide a channel (ACT) for the TFT. The data line DL connected to the source S of the TFT is formed of the third metal layer M3.

To provide a flat surface on which to place the common electrode blocks, a top planarization layer (PLN-U) is provided over the TFTs and bypass lines (BL). The drain (D) of the TFT contacts the pixel electrode (PXL) through a contact hole in the upper planarization layer (PLN-U). As shown, a passivation layer (PAS3) formed of an inorganic material such as SiNx and/or SiOx may be interposed between the upper planarization layer (PLN-U) and the third metal layer (M3). Another passivation layer (PAS4) is interposed between the pixel electrodes (PXL) and the common electrode blocks provided on the upper planarization layer (PLN-U).

A contact bridge may be present in the upper contact hole (CTU) to connect the bypass line (BL) and the corresponding common electrode block. More specifically, the contact bridge is formed of the third metal layer (M3) on the contact area of the bypass line (BL) (i.e., BL-VCOM contact area), and the upper contact hole ( CTU).

Each of the common signal lines SL is connected to one of the common electrode blocks by one or more bypass lines BL. In this regard, one end of the bypass line (BL) is connected to the common signal line (SL) through the lower contact hole (CTL) through the lower planarization layer (PLN-L) in the SL-BL contact area. The other end of the bypass line (BL) is connected to the common electrode block through the top contact hole (CTU) through the top planarization layer (PLN-U) in the BL-VCOM contact area. As shown in FIG. 6B, a contact bridge formed of the same metal layer as the source/drain metal of the TFT (i.e., the third metal layer M3) may be interposed between the bypass line BL and the common electrode block. The common electrode block may be in contact with the contact bridge through the upper contact hole (CTU) to electrically connect the common electrode block and the bypass line (BL). However, it should be noted that the contact bridge need not provide a connection between the bypass line (BL) and the common electrode block. Likewise, in some other embodiments, the bypass line BL may directly contact the common signal line SL through the lower contact hole CTL without an interconnecting contact bridge.

Each of the common signal lines SL includes a routing portion extending below the data line DL and a contact portion protruding from the routing portion toward the lower contact hole CTL. The ends of the contact portion in the SL-BL contact area may be enlarged to ensure the contact area size through the lower contact hole (CTL). Similarly, the ends of the bypass line (BL) corresponding to the SL-BL contact area and the BL-VCOM contact area may be wider than the interrim section of the bypass line (BL). Although only one common signal line (SL) is shown as a contact in FIG. 6C, contacts of other common signal lines (SL) may be located in different rows of pixel portions.

[Example Manufacturing Steps/Masks]

7A and 7B illustrate an example method of manufacturing a TFT substrate of a display panel (PNL) according to an embodiment of the present disclosure. Referring to FIGS. 7A and 7B , in step 1, the first metal layer M1 is disposed on the lower substrate and common signal lines SL are formed on the lower substrate. Although not shown in the drawing, the first metal layer M1 may have conductive lines and/or pads formed in a non-display area of the display panel PNL, depending on the case.

In step 2, the lower planarization layer (PLN-L) is disposed on the common signal lines (SL). As shown, the passivation layer PAS1 may be provided on the common signal lines SL and on the surface of the lower substrate. The lower contact hole (CTL) is formed in the SL-BL contact area where the connection between the common signal line (SL) and the bypass line (BL) is made. In this way, the connection portion of the common signal line (SL) is exposed through the lower contact hole (CTL) in the SL-BL contact area.

In some cases, some portions of the lower substrate within the non-display area may not be covered by the lower planarization layer (PLN-L). For example, in some embodiments, drivers (e.g., gate driver (GD), data driver (DD), touch driver (TD)) connect flexible printed circuit boards (FPCBs) in non-display areas. Metal traces (eg, metal lines and pads) for processing may be located on the lower substrate that is not covered under the lower planarization layer (PLN-L).

The curing process may be performed once the lower planarization layer (PLN-L) is coated over the common signal lines (SL). As the curing temperature increases, the coefficient of thermal expansion (CTE) for the lower planarization layer (PLN-L) (eg, SOG layer) decreases. The lower planarization layer (PLN-L) may deteriorate when cured at temperatures that cause dissociation of Si-O bonds. Additionally, the hardness and modulus of the lower planarization layer (PLN-L) increase as the curing temperature increases, which may make it easier for cracks to occur in the lower planarization layer (PLN-L). As such, in suitable embodiments, the curing temperature may range from 350°C to 400°C. However, it should be understood that the curing temperature is not limited thereto and may vary depending on the material of the lower planarization layer (PLN-L).

In step 3, the second metal layer M2 forms gate lines GL and bypass lines BL on the lower planarization layer PLN-L. Similar to the first metal layer (M1), the second metal layer (M2) may also form metal traces in the non-display area, the metal traces being arranged to contact the metal traces formed by the first metal layer (M1). It may be possible. If the lower planarization layer (PLN-L) is present in the non-display area between the metal traces of the first metal layer (M1) and the second metal layer (M2), the metal traces contact through the lower planarization layer (PLN-L) Contact may be made through holes.

As mentioned above, the passivation layer PAS2 may be provided on the lower planarization layer PLN-L before disposing the gate lines GL and bypass lines BL. In some embodiments, the lower contact holes (CTL) for connecting the common signal lines (SL) and the bypass lines (BL) are formed when the passivation layer (PAS2) is located on the lower planarization layer (PLN-L). It may be formed later.

Alternatively, in some other embodiments, the lower contact holes (CTL) of the SL-BL contact regions have a lower planarization layer (PLN-L) for improved protection against hydrogen fume (H+) from the lower planarization layer (PLN-L). It may be formed before forming the passivation layer (PAS2) on the PLN-L). More specifically, the lower contact holes (CTL) may be formed before positioning the passivation layer (PAS2) on the lower planarization layer (PLN-L). In this way, the passivation layer PAS2 is positioned on the lower planarization layer PLN-L, which already has contact holes formed therein, so that the side wall surfaces in the lower contact holes CTL can be covered with the passivation layer PAS2. there is.

It should also be noted that there may be free/unbound hydrogen (H) species within the passivation layer (PAS2) (eg Si3N4). These hydrogen species may interfere with TFT performance, especially if the TFT to be placed on the lower planarization layer (PLN-L) includes a metal oxide semiconductor (eg, IGZO). As such, in embodiments in which the passivation layer (PAS2) is present on the lower planarization layer (PLN-L), the curing process may be performed after forming the passivation layer (PAS2) on the lower planarization layer (PLN-L). It may be possible. In this way, free/unbound hydrogen (H) species in the passivation layer (PAS2) can be reduced during the curing process.

In step 4, a gate insulating layer (GI) is provided on the gate lines (GL) and bypass lines (BL). On top of the gate insulating layer (GI), a semiconductor layer (SEM) (eg, IGZO) is disposed. Subsequently, a contact hole is formed to penetrate the gate insulating layer (GI) and the semiconductor layer (SEM) to expose a portion of the bypass line (BL) in the BL-VCOM contact area.

In step 5, the third metal layer M3 is disposed on the semiconductor layer SEM and is formed similarly to the semiconductor layer SEM to form the source/drain of the data lines DL and TFTs. Accordingly, the semiconductor layer SEM under the source/drain of the TFTs as well as under the data lines DL remains intact even after the formation of the third metal layer M3.

The bypass line BL in the BL-VCOM contact area may be damaged during formation of the third metal layer M3.

Photoresist may cover the BL-VCOM contact area during formation of the third metal layer M3. As a result, the third metal layer M3 under the photoresist in the BL-VCOM contact area remains intact on the bypass line BL, as shown in FIG. 7A. In this case, the electrical connection between the bypass line BL and the common electrode block is made through a portion of the third metal layer M3 remaining in the BL-VCOM contact area, referred to in the present disclosure as a contact bridge.

In step 6, another passivation layer (PAS3) is formed on the source/drain and data lines (DL) of the TFTs. Next, an upper planarization layer (PLN-U) is provided on the passivation layer (PAS3) to provide a flat surface over the TFTs and data lines (DL). Since the upper planarization layer (PLN-U) is provided on top of the TFTs and the data lines (DL), the thermal stability of the material forming the upper planarization layer (PLN-U) is lower than that of the lower planarization layer (PLN-L). It doesn't have to be as big as that. Accordingly, the upper planarization layer (PLN-U) may be formed of photo-acrylic. The upper contact holes (CTU) are formed through the upper planarization layer (PLN-U), exposing the passivation layer (PAS3) in the drain region of the TFTs and the BL-VCOM contact region.

In step 7, the passivation layer (PAS3) is removed from the BL-VCOM contact area to expose the contact bridge at the BL-VCOM contact area. At this time, the passivation layer (PAS3) of the SD-PXL contact area of the TFT may remain in the upper contact hole (CTU).

In step 8, a transparent conductive layer, such as an indium-tin-oxide (ITO) layer, is formed on the upper planarization layer (PLN-U) to serve as a common electrode (VCOM) of the display panel (PNL). As described above, the common electrode VCOM is patterned into a plurality of separate portions, i.e., common electrode blocks.

In step 9, another passivation layer (PAS4) is provided on the common electrode blocks and the top planarization layer (PLN-U). Passivation layer PAS4 may also cover surfaces inside the contact holes. For example, the passivation layer (PAS4) is the exposed passivation layer (PAS3) below the top contact hole (CTU) in the SD-PXL contact area, and part of the common electrode block within the top contact hole (CTU) in the BL-VCOM contact area. It can also cover conductive lines/pads in non-display areas. Passivation layer PAS4 may then be etched in selective areas to expose the surface underneath. As shown, the passivation layer (PAS4) may be etched together with the passivation layer (PAS3) inside the upper contact hole (CTU) in the SD-PXL contact area to expose the drain of the TFT.

In step 10, another transparent conductive layer (eg, ITO) is disposed on the passivation layer (PAS4), forming pixel electrodes (PXL). As the SD-PXL contact area of the TFT is exposed, the transparent conductive layer comes into contact with the drain of the TFT. In some cases, the transparent conductive layer may also be exposed on conductive lines/pads located within the non-display area.

In some embodiments, the common signal lines SL may directly contact corresponding common electrode blocks. Since the common signal line (SL) is directly connected to the corresponding common electrode block without using the bypass line (BL), any side effects that may arise from using the bypass line (BL) (e.g. , loss of aperture ratio in pixels) can also be solved.

[Common signal line-transparent electrode block direct contact]

FIG. 8A illustrates an example configuration of a common signal line (SL) and a common electrode block that penetrate the upper planarization layer (PLN-U) and the lower planarization layer (PLN-L) and directly contact each other. Considering the step coverage of the common electrode block (e.g., ITO), the contact hole (CT) is not insulated and faces the common signal line (SL) so that the common electrode block and the common signal line (SL) can be electrically connected. It becomes narrower from the top to the bottom. More specifically, the upper portion (U) of the contact hole (CT) in the upper planarization layer (PLN-U) is larger than the middle portion (M) of the contact hole (CT) in the passivation layer (PAS3) and the gate insulating layer (GI). It can be wide. In addition, the middle portion (M) of the contact hole (CT) in the passivation layer (PAS3) and the gate insulating layer (GI) may be wider than the lower portion (L) of the contact hole (CT) in the lower planarization layer (PLN-L). there is. In some embodiments, a portion of the contact hole in the gate insulating layer GI may also be wider than a portion of the contact hole in the passivation layer PAS3. In suitable embodiments, the width D2 of the contact hole CT in the gate insulating layer GI and the passivation layer PAS3 is greater than the width D3 of the contact hole CT in the lower planarization layer PLN-L. It may be wider than at least 2 ㎛.

Additionally, the gate insulating layer may have a protrusion such as a ledge within the contact hole CT. The ledge creates a contact hole (CT) when a portion of the gate insulating layer (GI) is etched in a first round of the etching process and another portion of the gate insulating layer is etched in a second round of the etching process that is different from the first round of the etching process. ) is formed within. The first round of the etching process passes through only a portion of the passivation layer (PAS3) and the gate insulating layer (GI), leaving the gate insulating layer (GI) within the contact hole still covering the lower planarization layer (PLN-L). can be formed. Then, another round of the etching process is performed to form a contact hole completely through the gate insulating layer (GI), which will leave a ledge of the gate insulating layer within the contact hole (CT).

The manufacturing method is as follows. In step 1, a plurality of common signal lines SL are formed from the first metal layer M1. In step 2, the common signal lines SL are covered with the lower planarization layer PLN-L, and then the lower planarization layer PLN-L is cured. Similar to the previous example using the bypass line BL, passivation layers PAS1 and PAS2 may be provided on the upper and lower surfaces of the lower planarization layer PLN-L, respectively. In step 3, the second metal layer M2 forms gate lines GL and a gate electrode on the lower planarization layer PLN-L, and then the gate insulating layer GI is deposited. In step 4, a semiconductor layer (SEM) is deposited on the gate insulating layer (GI) and an annealing process is performed. Next, a semiconductor layer (SEM) is formed. In step 5, the third metal layer M3 forms the source/drain electrodes and data lines DL of the TFT. In step 6, another passivation layer (PAS3) is provided on the source/drain electrodes and data lines (DL), and then another annealing process is performed. In step 7, a top planarization layer (PLN-U) is deposited to provide a flat surface over the TFTs, and a contact hole (CT) penetrates the top planarization layer (PLN-U) to open the SL-VCOM contact region. is formed

FIG. 8B is a schematic illustration to explain an exemplary manufacturing method of the display panel (PNL) in which the common signal lines (SL) and the common electrode blocks are in direct contact with each other. Referring to FIG. 8B, photoresist PR may be provided on the upper planarization layer PLN-U, as shown in (A) of FIG. 8B. Next, a photo/development process is performed to create contact holes through the passivation layer (PAS3) and the gate insulating layer (GI). It should be understood that a gate insulating layer (GI) may need to be provided on some parts of the display panel (PNL) at least temporarily during manufacturing. For example, the gate insulating layer GI may provide temporary protection for metal trace lines in a non-display area of the display panel PNL. In these cases, the gate insulation layer (GI) may remain on the SL-VCOM contact area. For example, the passivation layer PAS3 may be overetched, but the surface of the lower planarization layer PLN-L is not exposed, as shown in (B) of FIG. 8B.

After forming a contact hole through the passivation layer (PAS3) and the gate insulating layer (GI), another photoresist deposition and development process can be performed, and the lower planarization layer (PLN-L) in the SL-VCOM contact area is As shown in (C) of 8b, it may be etched to expose the common signal line (SL). As shown in (D) of FIG. 8B, after stripping the photoresist, a transparent electrode layer (e.g., ITO) is created through the upper planarization layer (PLN-U) and the lower planarization layer (PLN-L). It can be deposited to directly contact the common signal line (SL) through a contact hole.

In this exemplary method, formation of a contact hole (CT) through the lower planarization layer (PLN-L) is performed after annealing processes. That is, all thermal expansion of the lower planarization layer (PLN-L) occurred when the contact hole (CT) was formed through the lower planarization layer (PLN-L). Therefore, even if the bypass line BL is not used, a stable connection between the common signal line SL and the common electrode block is possible.

[Co-planner structure TFT]

In some embodiments, the TFTs on the lower planarization layer may have a coplanar structure, where the gate, source, and drain are provided on the same side of the semiconductor layer (SEM). 9A illustrates a top and cross-sectional view of a coplanar TFT, which may serve as an example embodiment of the present disclosure. FIG. 9B is a cross-sectional view illustrating the connection between the common signal line SL and the common electrode block according to an embodiment of the present disclosure.

Referring to FIGS. 9A and 9B , the common signal line SL is formed of the first metal layer M1 and is covered under the lower planarization layer PLN-L. Similar to the display panel (PNL) with the inverted staggered structure TFTs shown in FIG. 6B, passivation layers (PAS1 and PAS2) are provided on the lower and upper surfaces of the lower planarization layer (PLN-L) It could be. The lower contact hole (CTL) is formed to penetrate the lower planarization layer (PLN-L) to open a portion of the contact portion of the common signal line (SL).

A semiconductor layer (SEM) (eg IGZO, poly-silicon) is provided on the lower planarization layer (PLN-L). A light shield (LS) may be provided to suppress light-induced threshold voltage shift of the TFT. In this regard, the light shielding portion LS may be formed of the first metal layer M1 below the lower planarization layer PLN-L. As shown in FIG. 9A, a portion of the common signal line (SL) may protrude toward the active area of the TFT to serve as a light shield (LS) (see plan view). In this way, both the common signal lines (SL) and the light shields (LS) can be provided from a single metal layer, reducing the manufacturing time and cost of the display panel (PNL).

In some cases, the buffer layer (BUF) may be provided between the semiconductor layer (SEM) and the lower planarization layer (PLN-L). In this regard, the buffer layer BUF may be provided in addition to a passivation layer (not shown) provided on the lower planarization layer PLN-L. Similar to the passivation layers below and above the lower planarization layer (PLN-L), the buffer layer (BUF) may be formed of a silicon nitride layer, a silicon oxide layer, or a combination thereof. If the semiconductor layer (SEM) to be provided on the buffer layer (BUF) is a metal oxide semiconductor such as IGZO, the silicon oxide layer may be composed of the outermost layer (that is, a layer interfacing with the semiconductor layer) of the buffer layer (BUF). According to the above-described configuration, it is possible to shield the semiconductor layer (SEM) from free/unbound hydrogen from any silicon nitride layer present beneath the semiconductor layer. For example, a passivation layer formed of a silicon nitride layer may be provided above or below the lower planarization layer (PLN-L), and a buffer layer (BUF) formed of a silicon oxide layer may be provided on the passivation layer.

A gate insulating layer (GI) is provided on the semiconductor layer. Subsequently, the second metal layer M2 forms the gate line GL and the gate electrode of the TFTs on the gate insulating layer GI. An annealing process and/or plasma treatment is performed on the semiconductor layer. Additionally, the third metal layer M3 forms the data lines DL and source/drain electrodes of the TFTs. An interlayer dielectric layer (ILD) is provided to insulate the source/drain electrodes and the gate electrode from each other. The upper planarization layer (PLN-U) is disposed on the above-described coplanar type TFTs, and a plurality of transparent electrode blocks are provided on the upper planarization layer (PLN-U). Each of the plurality of transparent electrode blocks may serve as a common electrode (VCOM) during operation of the display panel (PNL). The plurality of transparent electrode blocks may also serve as a touch sensor during operation of the display panel (PNL).

Each of the transparent electrode blocks is connected to at least one common signal line (SL) below the lower planarization layer. In some embodiments in which coplanar type TFTs are provided, the bypass lines (BL) are connected to the common signal lines (BL) below the lower planarization layer (PLN-L) and the common electrode on the upper planarization layer (PLN-U). It can also be used to connect blocks. The bypass lines BL may be formed of the second metal layer M2. Alternatively, in some other embodiments, the bypass lines BL may be formed of the third metal layer M3.

Additionally, in embodiments in which the semiconductor layer (SEM) is formed of a metal oxide layer such as IGZO, the metal oxide pattern formed from the lower contact hole (CTL) and the upper contact hole (CTU) serves as a bypass line (BL). It could be a challenging line. That is, the bypass lines BL are formed into a conductive path (i.e., signal) by a suitable doping process, including, but not limited to, plasma enhanced chemical vapor deposition (PECVD), hydrogen plasma treatment, argon plasma treatment, etc. /conductive path), it can be formed as a metal oxide layer.

It should be understood that these heavily doped metal oxide paths may be provided in various other parts of the display panel (PNL). For example, conductive lines in the non-display area of the display panel PNL may be formed from doped metal oxide patterns. Additionally, in some embodiments, the gate driver (GD) of the display panel (PNL) is a gate-in-panel (GIP) implemented using a plurality of TFTs formed directly in a non-display area of the display panel (PNL). It may also be provided in the form In embodiments where a GIP type gate driver (GD) is provided, some nodes within the circuitry of the GIP may be formed with highly doped metal oxide patterns.

It should be noted that the TFTs implementing the GIP circuit are not limited to oxide TFTs, and the GIP circuit may also be implemented using LTPS TFTs. That is, both oxide TFTs and LTPS TFTs may be provided on the TFT substrate of the display panel PNL. As an example, pixel circuits in the display area of the display panel (PNL) may be implemented with oxide TFTs, and driving circuits in the non-display area (e.g., buffer, shift register, multiplexer, GIP, etc.) may be implemented with LTPS. It can also be implemented with TFTs. A pixel circuit implemented with oxide TFTs will provide a higher voltage holding ratio than LTPS TFTs, which helps conserve power while the display is used in applications that do not require high frame rates (i.e., frames per second). This may be advantageous when temporarily reducing the frame rate of the display. Driving circuits implemented with LTPS TFTs will be advantageous for high-frequency driving of various components such as touch drivers, especially when the IFP touch scanning scheme is used.

Additionally, a combination of both oxide TFTs and LTPS TFTs may be used to implement pixel circuits and/or driver circuits. For example, while LTPS TFTs are used to implement the remainder of the GIP circuit, oxide TFTs may be used to fabricate the IFP compensation circuit (described in detail below). If storage capacitors are used within the pixel circuit and/or drive circuit, the transistors connected to the terminals of these storage capacitors may be oxide TFTs, although LTPS TFTs are used in other parts of the circuit. As will be described in more detail below, the IFP compensation circuit includes a storage capacitor, and the transistors connected to the terminals of the storage capacitor may be oxide TFTs while LTPS TFTs are used in other parts of the GIP circuit.

In non-display areas where common signal lines are not routed, oxide TFTs and LTPS TFTs may be provided in different layers from each other. For example, LTPS TFTs may be provided under the lower planarization layer (PLN-L) and oxide TFTs may be provided on the lower planarization layer (PLN-L), or vice versa. Accordingly, in embodiments where both oxide TFTs and LTPS TFTs are provided, the pixel circuits and/or driving circuits of the display panel (PNL) have nodes and/or electrodes formed with a doped metal oxide pattern (i.e., metal oxide TFTs). It may also include a conductive line formed of a semiconductor layer. In embodiments where a combination of oxide TFTs and LTPS TFTs are provided on a TFT substrate (TFT backplane), the TFTs can be provided in any coplanar structure and inverted staggered structure. In some cases, oxide TFTs or LTPS TFTs may be implemented in a coplanar structure, while other TFTs may be provided in an inverted staggered structure.

Additionally, in some embodiments where coplanar type TFTs are provided, the common signal lines SL are connected to the common electrode blocks through a contact hole through the upper planarization layer (PLN-U) and the lower planarization layer (PLN-L). You can also contact them directly.

[Non-display area: SOG open area]

In some embodiments, an FPCB with a driver IC (D-IC) and/or driver may be connected to an interface provided within a non-display area of the display panel (PNL). 10A and 10B each illustrate a schematic illustration of an exemplary configuration of an interface for a driver of a non-display area of the display panel (PNL).

Referring to FIG. 10A, some parts of the non-display area are provided with the lower planarization layer (PLN-L) and other parts of the non-display area do not have the lower planarization layer (PLN-L). For simpler explanation, the part of the non-display area provided with the lower planarization layer (PLN-L) may be referred to as the “SOG area”, and the part of the non-display area without the lower planarization layer (PLN-L) may also be referred to as “SOG open area.”

If an interface is provided on the lower planarization layer (PLN-L), the lower planarization layer (PLN-L) may be damaged when attaching the D-IC or removing the D-IC for repair. As such, it is desirable for the interface for the D-IC to be located in the SOG open area in the non-display area.

To provide an interface to the SOG open area, a plurality of metal line traces are routed from the SOG area to the SOG open area. As shown, the metal line traces routed to the SOG open area may be metal line traces formed from the first metal layer M1. Each of the metal line traces exposed in the SOG open area may include a portion configured as a bump (eg, pad) that is part of the interface. In some embodiments, the bumps may be formed from multiple metal layers. For example, the second metal layer M2 may be disposed on bump portions of the metal line traces formed with the first metal layer M1. Of course, additional metal layers may be provided on top of the bump portions of the underlying metal layer. In suitable embodiments, the metal line traces routed from the SOG area to the SOG open area may be a common signal line (SL), and the touch drive IC or FPCB provided with the touch driver is attached to the bumps provided in the SOG open area.

Referring to FIG. 10B , in some embodiments, metal line traces routed from the SOG area to the SOG open area may be formed of the second metal layer M2. In this case, the common signal lines SL may be routed to the SOG area of the non-display area, and the metal line traces formed in the second metal layer M2 may be routed from the SOG area to the SOG open area. The common signal lines SL in the SOG area may contact metal line traces formed of the second metal layer M2 through lower contact holes CTL provided in the SOG area. The metal line traces of the second metal layer M2 of the SOG open area may include portions configured as bumps for connecting a touch drive IC and/or an FPCB with a touch driver. This configuration requires that contact holes (i.e., jumping holes) be formed in the non-display area, but the common signal lines SL will not be damaged during formation of the second metal layer M2. In some suitable embodiments, the data link lines that are fanned out, i.e. spread out, from the data driver DD may be routed from the SOG open area to the SOG area as shown in FIG. 10B. Here, the data link lines may be formed of the second metal layer (M2) or the third metal layer (M3), or may simply be routed on the lower planarization layer (PLN-L) in the SOG area. The metal line traces, connected to the common signal lines (SL) through the bottom contact hole (CTL) in the non-display area, may be a touch link line connected to the touch driver IC. In this setup, the data link lines connected to the data driver (DD) may be fanned out across the common signal lines (SL) located below the lower planarization layer (PLN-L), which (PNL) enables reduced bezel design of devices.

[Gate-In-Panel: GIP]

The gate driver (GD) of the display panel (PNL) may be provided in a gate-in-panel (GIP) type implemented with a plurality of TFTs formed directly in a non-display area of the display panel (PNL). In some embodiments, the TFTs of the GIP circuit may be formed on the lower planarization layer, similar to the array of TFTs in the display area of the display panel PNL. In these embodiments, conductive lines for supplying external signals to the GIP circuit may be provided beneath the lower planarization layer (PLN-L). For example, the plurality of external signal lines may also be connected to the ratio of the display panel (PNL) when forming the first metal layer (M1) on the substrate to provide common signal lines (SL) across the display area of the display panel. -Can be formed within the display area.

FIG. 11A illustrates an example configuration of a stage of an example GIP circuit, which may be provided within a display panel (PNL). As shown in FIG. 11A, external signal lines provided to the GIP circuit may include various clock signal lines, power signal lines (eg, VSS, VDD), reset signal lines, etc. These external signal lines are routed within the non-display area of the display panel (PNL). More specifically, the external signal lines may be formed of the first metal layer (M1) or may be provided below the lower planarization layer (PLN-L). In this way, external signal lines may be routed down a plurality of TFTs in the non-display area that implement the shift register of the GIP circuit. External signal lines may be connected to each node of the GIP circuit through contact holes through the lower planarization layer (PLN-L). In some embodiments, a signal line for transmitting a common voltage signal may be routed within a non-display area beneath the GIP circuit. Routing at least some of the external signal lines directly below the GIP circuitry reduces the bezel size even further.

[Example Capacitor Configuration]

In some embodiments, capacitors included in the GIP circuits may be implemented as a metal layer beneath the lower planarization layer (PLN-L). For example, each stage of the shift register of the GIP circuit includes a pull-up TFT (T6) configured to output a scan signal to the output terminal (Vgout(N)). The pull-up TFT (T6) has a gate connected to the Q-node, a first terminal connected to a voltage source (CLK), and a second terminal connected to the output terminal (Vgout(N)) of each stage. Therefore, the pull-up TFT (T6) is controlled by the voltage on the Q-node.

A capacitor (CAP) may be connected between the gate and the second terminal of the pull-up TFT (T6). During the operation of the shift register, the voltage at the Q-node is raised to a higher voltage by bootstrapping of the capacitor (CAP) connected between the Q-node and the output terminal, thus fully turning on the pull-up TFT (T6). do.

The capacitor CAP may be configured as a parasitic capacitor formed in an overlapping area between the gate and source of the pull-up TFT T6, each formed of the second metal layer M2 and the third metal layer M3. The dimensions of the capacitor (CAP) within the GIP circuit may be quite large. Accordingly, the dimensions of the capacitor CAP may be reduced to reduce the size of the GIP circuit in the non-display area of the display panel PNL.

To this end, the first metal layer M1 may form an additional metal layer under the lower planarization layer PLN-L to implement the capacitor CAP. As shown in FIG. 11B, the capacitor CAP is a first capacitor plate CP1 formed of a first metal layer M1, in which the first capacitor plate CP1 and the third capacitor plate CP3 are electrically connected to each other. ), the second capacitor plate CP2 formed of the second metal layer M2, and the third capacitor plate CP3 formed of the third metal layer M3. The third capacitor plate CP3 may be connected to the first capacitor plate CP1 through the lower planarization layer PLN-L and the contact hole CTL. As shown, a contact bridge formed from the second metal layer M2 may be provided to electrically connect the first capacitor plate CP1 and the third capacitor plate CP3. Of course, the contact bridge formed from the second metal layer (M2) is insulated from the second capacitor plate (CP2). By stacking three metal plates, a more compact size capacitor can be provided without sacrificing total charge storage or resistance-capacitance. This ultimately promotes GIP circuits of more compact size.

In some embodiments, the thickness of the lower planarization layer (PLN-L) interposed between the first metal plate (CP1) and the second metal plate (CP2) increases the amount of capacitance that can be stored in the capacitor (CAP). It can be decreased to increase. To this end, a half-tone mask may be used when forming the lower contact hole (CTL) through the lower planarization layer (PLN-L). More specifically, when forming the lower contact hole (CTL), photoresist may be placed on the lower planarization layer (PLN-L), and the photoresist may be developed by using a half-tone mask. The photoresist on the lower planarization layer (PLN-L) in the first metal plate (CP1) may have a reduced thickness. Accordingly, the thickness of the lower planarization layer (PLN-L) in the capacitor (CAP) can also be reduced when a dry-etching process to create the lower contact hole (CT) is performed. A similar process can be used to form various other capacitors described in this disclosure.

It should be noted that the shift register of the GIP circuit may include capacitors other than those described above. Similar to the capacitor (CAP) connected between the Q-node of the stage and the output terminal (Vgout (N)), other capacitors are also connected to the first capacitor plate (CP1), the second capacitor plate (CP2) and the third capacitor plate ( It may be in the form of a stack of CP3).

[IFP compensation circuit]

As described above, in some embodiments, the display panel (PNL) may be configured to operate with an intra-frame-pause (IFP) touch scan scheme to provide improved touch scan resolution.

In the GIP circuit, each stage of the shift resist outputs a scan signal on a gate line (GL) connected to the output terminal of the stage. Additionally, the scan signal from one stage is supplied as a start signal to another stage of the shift register so that the stage receiving the start signal operates to output the scan signal on the connected gate line GL. Accordingly, the scan signal is supplied on all gate lines GL in sequential order for each frame.

However, when the IFP scheme is used, the sequential output of the scan signal on the gate lines GL is temporarily paused while the touch scan operation is performed. That is, one stage of the shift register is prevented from outputting a scan signal until the intra-frame touch scan operation is completed. In order to resume outputting the scan signal from the last gate line (GL) to which the scan signal was provided, the Q-node must be charged to a high state. One way to restart operation of the shift register is to hold the Q-node high while the IFP touch scan operation is performed. That is, the Q-node of the stage that received the start signal from the previous stage may simply remain in the high state. However, in this case, the pull-up TFT connected to the high state Q-node to extend the interval may deteriorate faster than other TFTs in the GIP circuits.

Accordingly, in some embodiments, the display panel PNL may include a GIP circuit with a compensation circuit configured for an IFP driving scheme. By storing the voltage of the Q-node in the storage capacitor during the IFP scan operation and recharging the Q-node with the stored voltage after the IFP touch scan operation, the compensation circuit causes the Q-node to discharge while the IFP touch scan operation is performed. .

FIG. 12A is a schematic circuit diagram illustrating an example configuration of a compensation circuit that may be provided in one or more stages of a GIP circuit. It should be noted that the compensation circuit shown in Figure 12A is only part of the stage, and therefore the circuitry of the stage is not limited to pull-up transistors, but will include a variety of other transistors, including pull-up transistors. For example, the compensation circuit of Figure 12A can be added to the circuitry of the stage shown in Figure 11A.

Referring to FIG. 12A, the compensation circuit includes a first transistor (TIFP1), a second transistor (TIFP2), a third transistor (TIFP3), and a fourth transistor (TIFP4). The first transistor TIFP1 is connected between the Q-node and the low voltage line VSS, and the gate of the first transistor TIFP1 is connected to the node to which the IFP signal is supplied. The second transistor TIFP2 is connected between the high voltage line VDD and the gate of the fourth transistor TIFP4, and the gate of the second transistor TIFP2 is also connected to the high voltage line VDD. The third transistor TIFP3 is connected between the gate of the fourth transistor TIFP4 and the low voltage line VSS, and the gate of the third transistor TIFP3 is connected to the node to which the IFP signal is supplied. The second transistor (TIFP2) and the third transistor (TIFP3) are connected in series between the high voltage line (VDD) and the low voltage line (VSS), and operate as an inverter of the compensation circuit that controls the fourth transistor (TIFP4).

The fourth transistor (TIFP4) has a first terminal (TM1) connected to the storage capacitor (CIFP), a second terminal (TM2) connected to the Q-node, and connected in series between the high voltage line (VDD) and the low voltage line (VSS). It has a gate connected to the node between the second transistor (TIFP2) and the third transistor (TIFP3). The compensation circuit includes a storage capacitor (CIFP) connected between the first terminal (TM1) of the fourth transistor (TIFP4) and the low voltage line (VSS).

In operation, the Q-nodes of one stage are charged in response to a start signal from the previous stage (or via an external start signal line). As mentioned, the stage is provided with a compensation circuit. Accordingly, IFP signals are supplied to this stage, indicating the start and end of the IFP touch scan operation. In response to the low level IFP signal, the voltage of the Q-node is stored in the storage capacitor (CIFP). As shown in Figure 12b, the Q-node discharges in response to a high level IFP signal. When the IFP signal switches back to a low level, the Q-node of this stage is charged with the voltage stored in the storage capacitor (CIFP) and outputs a scan signal. In this way, the Q-node can be discharged during the period for performing the IFP touch scan operation, minimizing degradation of the pull-up transistor.

It should be noted that in some embodiments, the start timing of an IFP touch scan operation within a frame may be fixed. That is, the display panel (PNL) may be configured to start the IFP touch scan operation after the scan signal is supplied to each of the pre-specified number of gate lines (GL) in the frame. That is, one or more of the pre-specified stages of the shift register may be configured to be stopped to synchronize with the IFP touch scan operation. In these embodiments, compensation circuitry may be added to the circuitry of pre-specified stages configured to be stationary during an IFP touch scan operation.

In some other embodiments, the start timing of the IFP touch scan operation within a frame may vary. For example, the timing of the IFP signal hitting the high stage may vary between any two display periods within a single frame. Because the timing of the IFP signal varies, the stage that is stopped during the IFP touch scan operation also varies. As such, the stage to be stopped during an IFP touch scan operation may be one of pre-specified stages (ie, a plurality of stages in a pre-specified range). The display panel (PNL) may be configured such that the timing of the high level IFP signal varies for each frame. In these cases, the high level IFP signal may be supplied to a different stage of the set of stages pre-specified to receive the high level IFP signal. In these embodiments, compensation circuitry may be provided on all stages of a pre-specified set of stages that may receive a high level IFP signal.

Similar to the bootstrapping capacitor (e.g., CAP) discussed with reference to FIG. 11A, the storage capacitor (CIFP) of the compensation circuit includes a first metal plate (CP1) formed of a first metal layer (M1), a second metal layer It may also be implemented as a second metal plate (CP2) formed of (M2) and a third metal plate (CP3) formed of a third metal layer (M3). As mentioned above, the second metal plate CP2 is interposed between the first metal plate CP1 and the third metal plate CP3 and is connected to the first metal plate CP1. In this setup, at the end of the IFP touch scan operation, an increased amount of Charge may be stored in a storage capacitor (CIFP).

[Dummy line configuration]

To implement a touch sensor within the display panel (PNL) by using segmented portions of transparent electrodes (e.g., segmented portions of a common electrode), each of the individual portions having at least one common signal. It must be connected to the line (SL). Accordingly, the minimum number of common signal lines SL required for the display panel will be equal to the number of common electrode blocks. However, it should be understood that the display panel PNL may be provided with a much larger number of common signal lines SL than is minimally required within the display panel PNL. Additional common signal lines (SL) are provided in the display panel (PNL) so that a plurality of common signal lines (SL) can be connected to a single common electrode block to provide a low-resistance connection between the common electrode block and the driver.

In some cases, a common signal line (SL) may be provided below each of all data lines (DL) to implement a self-capacitance touch sensor system, a mutual-capacitance touch sensor system, or It may also be connected to common electrode blocks to provide various other functions (eg, touch pressure sensor system, localized tactile feedback system, etc.).

By using the common signal line (SL) located below all data lines (DL), uniformity of capacitance between the data line (DL) and the common signal line (SL) across the display panel (PNL) may be achieved. . However, portions of the common signal line (SL) routed under common electrode blocks that are not connected to a specific common signal line (SL) increase unwanted capacitance in these common electrode blocks. In this way, dummy lines (DML) that are not directly connected to the touch driver (TD) may be provided in place of unnecessary parts of the common signal lines (SL). That is, in order for the data lines DL to have uniform data line capacitance, as shown in FIG. 6A, all data lines DL of the display panel are connected to the common signal line SL or the dummy line DML. To overlap, dummy lines DML may be provided in the display panel PNL. Since the dummy lines (DML) do not need to be connected to the common electrode blocks, the total number of bypass lines (BL) required in the display panel (PNL) can be greatly reduced, which means that the pixels in the display panel (PNL) will improve their opening rate.

It should be understood that both a common signal line (SL) and a dummy line (DML) may lie beneath a single data line (DL). In other words, the conductive line formed from the first metal layer M1, routed along the data lines DL, may be separated into a plurality of insulated portions, one portion having a common signal connected to the touch driver TD. It acts as a line (SL), and the other part acts as a dummy line (DML). For example, the common signal line (SL) may extend below the data line (DL) and may be connected to the common electrode block. The common signal line (SL) will terminate at a point connected to the common electrode block. From there, a conductive line insulated from the common signal line (SL) may extend below the data line (DL) as a dummy line (DML).

Floating dummy lines (DML) may cause static electricity during manufacturing of the display panel (PNL). As such, in some embodiments, the dummy lines DML may be connected to a voltage source, such as a common voltage source, a DC voltage source, or a ground voltage source. The common signal line (SL) divided into a plurality of parts under the same data line (DL) may include insulated dummy line (DML) parts that cannot extend to a voltage source located outside the display area. Accordingly, in some embodiments, some dummy lines DML may be connected to common electrode blocks through bypass lines BL. In these cases, the dummy line (DML) represents a set of common signal lines (SL) or a plurality of common electrode blocks that individually communicate with the touch driver (TD) through one common signal line (SL). There should be no interconnection. Dummy lines (DML) are connected to common electrode blocks in order to implement specific features defined by common signal lines (SL), unless the connection to the common electrode blocks changes the electrical connection map of the common electrode blocks. can be connected

13 illustrates an example configuration of a display panel (PNL) provided with a plurality of insulated dummy lines (DML), wherein the dummy lines (DML) are selectively connected to corresponding common electrode blocks among the common electrode blocks. do. Connection between the dummy lines (DML) and the common electrode block may be made through the bypass line (BL) in the same manner as the common signal lines (SL). As shown, when connected to common electrode blocks, the dummy lines DML are not floating. However, the insulated dummy lines (DML) do not interconnect different common electrode blocks. Even if the dummy lines DML are not directly connected to each upper touch driver TD, the dummy lines DML may serve as a current path to relay signals within a single common electrode block.

In the example shown in FIG. 13 , each of the dummy lines DML is connected to the common electrode block through a plurality of bypass lines BL located at different positions of the common electrode block. It should be understood that the common signal lines SL may also be connected to a plurality of bypass lines BL connected to different positions of the same corresponding common electrode block.

Referring again to the example shown in FIGS. 6A to 6C, the contact portion of the common signal line SL is shown extending into a pixel area immediately adjacent to the routing portion of the common signal line SL. However, the configuration of the contact portion is not limited to this, and the contact portion may extend into other pixel areas. When the dummy lines (DML) are disposed in the display panel (PNL), the dummy lines (DML) below each of the data lines (DL) have a common signal line (SL) to extend across the dummy lines (DML). It may also be provided in divided parts to provide a passage for the contact portion of.

As shown in FIG. 13, in embodiments in which dummy lines DML below some data lines DL are connected to common electrode blocks located above, the dummy lines DML are connected to the data lines DL. ) and a contact portion protruding from the routing portion to be connected to the bypass line BL. Contact portions of the dummy lines DML may also extend horizontally across a plurality of pixel areas. In this case, other dummy lines DML below the data lines DL may be provided in divided portions to provide a passage through which the contact portion of the dummy line DML traverses. It should be noted that the contact portion of the dummy line DML may contact these other dummy lines DML in such a way that the other dummy lines DML are not connected to a different common electrode block.

[Resistance-Capacitance Compensation]

Some common electrode blocks are located farther from the driver (eg, touch driver (TD)) than other common electrode blocks and require a longer communication path to communicate with the touch driver (TD). In embodiments where the common electrode blocks are configured to communicate with the touch driver (TD), the length difference of the common signal lines (SL) forming the signal path is converted into a resistance-capacitance delay (RC delay) difference between the common electrode blocks, This will make it difficult to recognize touch inputs. To compensate for resistance differences between signal paths for common electrode blocks, some signal paths may be implemented with a larger number of common signal lines (SL) than others.

Accordingly, some common electrode blocks may be configured to communicate with the touch driver (TD) through a signal path consisting of a set of common signal lines (SL). A set of common signal lines may be connected in parallel with each other. That is, a parallel-connected signal path implemented with at least two common signal lines SL may be provided for at least some of the common electrode blocks.

Connecting a set of common signal lines (SL) in parallel to form a parallel-connected signal path can be accomplished in a variety of ways. In some embodiments, parallel connection of the set of common signal lines (SL) can be achieved by simply forming the interconnection line with the first metal layer (M1) during the formation of the common signal lines (SL) at the first location. there is. That is, a metal line may be formed from the first metal layer M1 to extend over selective locations of the set of common signal lines SL and interconnect to form a parallel-connected signal path. In this case, the interconnection line may be arranged to at least partially overlap the gate line GL to minimize the impact the interconnection line may have on the aperture ratio of the pixel regions. A parallel-connected signal path implemented as a set of parallel-connected common signal lines (SL) may be connected to the common electrode block using any of the configurations described in this disclosure.

In some other embodiments, a commonly shared bypass line (BL) between the sets of common signal lines (SL) serves as a means for creating a parallel-connection for the set of common signal lines (SL). can do. In another embodiment, each of the set of common signal lines (SL) may be individually connected to the same common electrode block, in which case the common electrode block itself will create a parallel connection between the set of common signal lines (SL).

The more common signal lines (SL) there are in a parallel connected signal path, the lower the resistance of the signal path. Accordingly, some parallel-connected signal paths may include a greater number of common signal lines than other signal paths. For example, a set of common signal lines (SL) forming a parallel-connected signal path for a common electrode block located farther from the touch driver (TD) may be a set of common signal lines (SL) that form a parallel-connected signal path for a common electrode block located closer to the touch driver (TD). may be implemented with an additional number of common signal lines (SL) than the set of common signal lines (SL) that form a parallel-connected signal path for the signals. That is, the first parallel-connected signal path for the common electrode block can be implemented with N common signal lines (SL), and the second parallel-connected signal path for the other common electrode block can be implemented with M common signal lines. It can be implemented as: N may be greater than M when the common electrode block connected to the first parallel-connected signal path is located farther from the touch driver (TD) than the common electrode block connected to the second parallel-connected signal path.

FIG. 14A illustrates an example configuration of common signal lines SL for normalizing the resistance difference between common electrode blocks of the display panel PNL according to an embodiment of the present disclosure. In the display panel PNL, the common electrode blocks may be arranged in “X” rows and “Y” columns, for example, 48 rows x 36 columns. Additionally, the pixels may be arranged in “I” rows x “J” columns, for example, 45 rows x 45 columns. Each pixel may include three sub-pixels (RGB). However, it should be understood that the above-described arrangements of common electrode blocks and pixels are merely examples. The number of common electrode blocks, the number of pixels, the number of sub-pixels as well as their colors may vary in different embodiments of the present disclosure.

As mentioned, for at least some of the common electrode blocks, a signal path from the touch driver (TD) to each common electrode block may be implemented as a plurality of common signal lines (SL) connected in parallel. In the example shown in FIG. 14A, each of the signal paths for the common electrode blocks in the rows numbered 1 to 37 is implemented with at least two parallel-connected common signal lines SL. In some cases, such parallel connected signal paths may not be provided to common electrode blocks located relatively close to the touch driver (TD). In this way, the signal paths for the common electrode blocks numbered 38 to 48 in the same row are implemented as a signal path formed by a single common signal line (SL).

As mentioned above, some parallel connected signal paths may be implemented with an increased number of parallel-connected common signal lines (SL). However, it should be noted that the total number of common signal lines (SL) that can be located under each common electrode block may be limited. Accordingly, it may not be feasible to increase the number of common signal lines (SL) of each of all parallel-connected signal paths for the common electrode blocks of this row. Accordingly, in some embodiments, the same number of common signal lines (SL) as the signal path for other common electrode blocks, even though some common electrode blocks are located closer to the touch driver (TD) than other common electrode blocks. A signal path implemented as may be provided to some common electrode blocks. In these embodiments, the blocks of common electrodes arranged in each row may be divided into a plurality of groups of common electrode blocks, and the groups are defined based on the distance between the touch driver (TD) and the common electrode blocks. Here, signal paths for all common electrode blocks of the same group may be implemented with the same number of common signal lines (SL).

In the example shown in FIG. 14A, a single row of common electrode blocks includes five groups (N1, N2, N3, N4, and N5). The common electrode blocks of the first group N1 are located closer to the common electrode blocks of other groups. The common electrode blocks of the second group (N2) are located farther from the touch driver (TD) than the common electrode blocks of the first group (N1), but are not farther away than the common electrode blocks of the third group (N3). The common electrode blocks of the fourth group (N4) are located farther from the touch driver (TD) than the common electrode blocks of the third group (N3), but are not farther away than the common electrode blocks of the fifth group (N5).

In this setup, the difference in resistance of the signal paths from the touch driver (TD) to the common electrode blocks is compensated by adjusting the number of common signal lines (SL) that generate these signal paths. Likewise, the first group (N1), second group (N2), third group (N3), fourth group (N4) and fifth group (N5) of this row are from #38 to #48 and #27, respectively. It includes common electrode blocks #37, #18 to #26, #8 to #17, and #1 to #7. Since the first group N1 is closest to the touch driver TD, the signal path for each of the common electrode blocks of the first group N1 consists of a signal path implemented with a single common signal line SL. For the second group N2, the parallel connected signal path for each of the common electrode blocks consists of two parallel-connected common signal lines SL. For the third group N3, the parallel connected signal path for each of the common electrode blocks consists of three parallel-connected common signal lines SL. Additionally, for the fourth group N4, the parallel connection signal path for each of the common electrode blocks consists of four parallel-connected common signal lines SL. Finally, for each of the common electrode blocks of the fifth group N5, the parallel connection signal path consists of five parallel-connected common signal lines SL.

In the example of Figure 14A, the resistance difference between signal paths is compensated between groups of common electrode blocks in this row. However, there is still a resistance difference between common electrode blocks within the same group. When the number of common electrode blocks included in each group increases, the difference in resistance for the signal path between common electrode blocks of the same group may not be negligible. As such, in some embodiments, the signal path between the touch driver (TD) and the common electrode block may include a tail portion for secondary adjustment of the resistance of the signal path. The tail of the signal path can be adjusted to further normalize the resistance of the signal paths for common electrode blocks of the same group.

FIG. 14B is an exemplary configuration of tail portions for secondary adjustment of the resistance difference between signal paths for common electrode blocks. Signal path #1 may be a signal path connected to common electrode block #1 and signal path #7 may be a signal path connected to common electrode block #7. As shown, signal paths #1 and #7 include a main portion (M) and a tail portion (T). The tail section (T) may be another parallel connection signal path formed at the end of the parallel connection signal path of the main section (M), and only this parallel connection signal path of the tail section (T) is connected to the parallel connection of the main section (M). It is implemented with fewer common signal lines (SL) than the signal path.

In the example shown in FIG. 14B, the parallel connection signal path of the tail part (T) is formed by n-1 common signal lines (SL), and “n” forms the parallel connection signal path of the main part (M). Indicates the total number of common signal lines (SL) used to However, it should be understood that the number of common signal lines (SL) to form the parallel connection signal path of the tail portion (T) is not limited to n-1. As such, in some embodiments, the signal paths of the tail unit may be implemented as n-2, n-3, etc. In some cases, a parallel connection signal path may be provided with a tail portion (T) formed of a single common signal line (SL). For example, signal paths #27 and #37 connected to common electrode blocks #27 and #37 are formed of two parallel-connected common signal lines (SL), a parallel connected main portion (M) and a single common signal It includes a tail portion (T) formed of a line (SL).

In the example shown in FIG. 14B, all signal paths for the same group of common electrode blocks include a tail T. The tail portions (T) of these signal paths are implemented with the same number of common signal lines (SL). For example, the tail portions (T) of signal paths #1 to #7 are implemented with n-1 (i.e., 4 in this case) common signal lines (SL). For more precise adjustment, the tails T of some of the signal paths may be configured differently from the tails T of other signal paths. Using a different tail section (T) is particularly useful for signal paths of the same group of common electrode blocks, each of which has a main section (M) implemented with the same number of common signal lines (SL). You may. For signal paths of common electrode blocks of the same group, the tail portion T may not be significantly used to compensate for the resistance difference if all signal paths are provided with a tail portion T configured in exactly the same way as each other. there is.

Accordingly, in some embodiments, these signal paths are implemented with the same number of common signal lines (SL) even though the tail portion (T) of the signal paths may be implemented with a different number of common signal lines (SL). It includes main parts (M). Figure 14c illustrates an example configuration of signal paths with identical main portions (M) but provided with different tail portions (T). In the example shown in FIG. 14C, signal paths #1 to #7 may have a main portion M implemented with n (5 in the example of FIG. 14C) common signal lines SL. However, the tail portion (T) of signal path #1 may be implemented with n-1 (e.g., 4) common signal lines (SL) and the tail portion (T) of signal path #7 may be implemented with n-2 common signal lines (SL). It may be implemented with (for example, 3) common signal lines (SL).

14D illustrates an example configuration of signal paths for the same group of common electrode blocks. In some embodiments, among signal paths implemented with the same number of common signal lines SL, a tail portion T may be provided only to some signal paths. For example, although signal path #1 may not be provided with a tail portion (T), the main portion (M) for both signal path #1 and signal path #7 is provided with the same number of common signal lines (SL). It is implemented.

Additionally, in some embodiments, the length of the tail portion T may be adjusted to compensate for differences in resistance of signal paths. For example, the tail portion (T) of signal path #1 and the tail portion (T) of signal path #7 may be provided in different lengths as shown in FIG. 14E.

It may be difficult to adjust the resistance of the signal path using a tail implemented as a single common signal line (SL). For example, the length of a single common signal line (SL) for implementing the tail portion may not fit under the common electrode block to which the tail portion is to be connected. As such, in some embodiments, a tail portion T implemented with at least two common signal lines SL connected in a series configuration may be provided in some signal paths.

14F illustrates an example configuration of common signal lines (SL) for implementing a signal path using a series-connected tail. Referring to FIG. 14F, the signal path includes a parallel connected main section (M) and a series-connected tail section (T). The series-connected tail part T is implemented with at least two parts (labeled 1 and 2) which are formed from the first metal layer M1 and are conductive lines located below the different data lines DL. An interconnection line can be used to connect these two parts in series, creating a series-connected tail (T). In this regard, the total length of the series connected tail portion can be adjusted by adjusting the length of the respective parts (labeled 1 and 2). It should be noted that this series-connected tail section may also be provided for signal paths with a parallel main section implemented with three or more common signal lines (SL).

In the previous examples, each of the signal paths for the common electrode blocks of the first group N1, the group closest to the touch driver TD, was implemented with a single common signal line SL. With a single common signal line (SL), the resistance of the signal path is very dependent on the length of the common signal line (SL). Therefore, it may be difficult to normalize the resistance of the signal paths when the entire signal path is implemented with a single common signal line (SL). Accordingly, in some embodiments, all signal paths for common electrode blocks of the display panel PNL may be implemented with at least two common signal lines SL connected in parallel. In these embodiments, each of all signal paths between the common electrode block and the touch driver (TD) may include at least one parallel connection. Some signal paths may include a tail and some may not. For these signal paths including a tail portion (T), the tail portion (T) may be a single common signal line (SL), a plurality of common signal lines (SL) connected in a series configuration, or a plurality of common signals connected in parallel. It can be implemented with lines (SL).

As discussed above, dummy lines (DML) insulated from the common signal lines (SL) may be arranged below the data lines (DL). As shown in FIGS. 14B to 14E, dummy lines DML below the data lines DL may be insulated from the above-described parallel connection signal paths. Additionally, some common signal lines (SL) implementing parallel connected signal paths may continue to extend throughout the display area.

The signal paths for the common electrode blocks of other rows of common electrode blocks may also be configured similarly to the manner described above. However, it should be noted that the configuration of the signal paths for a row of common electrode blocks need not be the same for all rows of common electrode blocks. Some rows of common electrode blocks may have a signal path configuration that is different from the configuration of signal paths of other rows of common electrodes.

[Contact hole location]

As mentioned, the common signal lines SL are routed across the display area of the display panel PNL along the data lines DL. This causes the routing portion of the common signal line (SL) to at least partially overlap with the data line (DL) provided thereon. However, the contact portion that protrudes horizontally from the routing portion of the common signal line (SL) may not be covered below the data line (DL).

In addition, the bypass lines BL are formed of the second metal layer M2, which is the same as the non-transparent metal layer of the gate lines GL and the gate electrode of the TFTs. GL) cannot be positioned to overlap. In LCD devices, bypass lines BL block light from passing from a light source (eg, backlight), which will reduce the aperture of the pixels. Even for self-emissive displays such as OLED displays, bypass lines (BL) can reflect external light and make images on the screen difficult to see. Accordingly, the contact portion of the common signal line (SL) as well as the bypass lines (BL), the gate lines (GL) and the data lines (DL) are hidden under a masking layer (e.g., BM-black matrix). It is hidden under the masking layer (BM) in a similar way. The same is applied to the contact portion of the dummy lines (DML) and bypass lines (BL) connecting the dummy lines (DML) to the corresponding common electrode blocks.

Since the masking layer BM defines the aperture ratio of the pixels, covering the bypass lines BL causes a decrease in the aperture ratio of the pixels in which the bypass lines BL are arranged. Since at least one bypass line BL is required to connect the common signal line SL to the common electrode block, each pixel group sharing the common electrode block may include pixels having different aperture ratios. For example, the maximum aperture ratio of the pixel area having the lower contact hole (CTL) may be different from the maximum aperture ratio of the pixel area having the upper contact hole (CTU). Additionally, the maximum aperture ratio of the pixel regions across which the middle section of the bypass line BL lies may be different from the maximum aperture ratio of the pixel regions that accommodate the lower or upper contact holes. Additionally, some pixels may not accommodate either the contact holes or the bypass line (BL) and may have a maximum aperture ratio greater than that of other pixels. In this specification, pixels that have a reduced maximum aperture due to contact holes or bypass lines (BL) may be referred to as “bypass pixels.” The maximum aperture ratio is reduced by contact holes or bypass lines (BL). Pixels that are not reduced may be referred to as “normal pixels.”

Referring again to FIG. 6A, a lower contact hole (CTL) for connecting the common signal line (SL) to the bypass line (BL) is provided in one of the pixel areas, and the bypass line (BL) is connected to the common electrode block. Top contact holes (CTU) for connection are provided in different pixel areas. The lower contact hole (CTL) and upper contact hole (CTU) must be covered with a masking layer (BM). Accordingly, the pixels housing the lower contact hole (CTL) and the upper contact hole (CTU) have a reduced maximum aperture ratio than the pixels between these two pixels.

To improve efficiency, lower contact holes (CTL) and upper contact holes (CTU) may be provided on certain selected pixels. For example, a bottom contact hole (CTL) and a top contact hole (CTU) may be provided in blue pixel areas. The luminance of blue pixels tends to be lower than that of green or red pixels, even if they are provided in the same size. With a low brightness/size ratio, the actual amount of brightness reduced by placing contact holes is less in blue pixel areas compared to placing contact holes in red and green pixel areas. Accordingly, in some embodiments, the lower contact hole (CTL) and upper contact hole (CTU) on opposite ends of the bypass lines (BL) may be arranged within the blue pixel areas.

As shown in the examples of FIG. 6A, the blue pixel areas for accommodating the lower contact hole (CTL) and upper contact hole (CTU) to connect the bypass line (BL) may be pixels in the same row. Intermediate pixel areas between the blue pixel area with the bottom contact hole (CTL) and the blue pixel area with the top contact hole (CTU) in the same row are pixel areas of different colors, such as a red pixel area, a green pixel area and/or Contains a white pixel area.

A blue pixel area without contact holes may also be included among the intermediate pixel areas between two blue pixels containing contact holes. That is, the middle section of the bypass line (BL) between the blue pixel area with the lower contact hole (CTL) and the blue pixel area with the upper contact hole (CTU) is the lower contact hole (CTL) or the upper contact hole (CTU). ) may lie across one or more of the blue pixel areas that do not accommodate any.

It should be recalled that the bypass line BL and the gate lines GL are provided in the same plane and are not arranged to overlap each other. Likewise, the aperture ratio of the middle pixel regions is also reduced by the bypass lines BL extending between the lower contact hole CTL and the upper contact hole CTU. In order to minimize the number of bypass pixel areas, that is, pixel areas whose aperture ratio is reduced due to the bypass line BL, the length of the bypass line BL must be kept to a minimum. For this reason, the lower contact hole (CTL) and upper contact hole (CTU) for each of the bypass lines BL may be provided in the two closest blue pixel areas in the same row. That is, the blue pixel area where the upper contact hole (CTU) is formed may be the first blue pixel area in the same row, and is connected to the blue pixel area where the lower contact hole (CTL) is formed.

[Bypass common signal line]

To locate the SL-BL contact area and BL-VCOM area within the blue pixel areas, the common signal line (SL) down one data line (DL) may have to be partially bypassed down the other data line (DL). there is. For example, one or more common signal lines SL at the right end of the common electrode block may extend beyond the blue pixel area to accommodate the BL-VCOM contact area.

Figure 15a is a schematic illustration of common signal lines SL provided with a bypass section DT, according to an embodiment of the present disclosure. Referring to FIG. 15A, the common signal line (SL1) routed below the data line (DL1) is provided with a bypass section that is skewed toward the data line (DL2). In this way, the bypass section (DT) of the common signal line (SL1) runs down the data line (DL2). In the example of Figure 15A, the bypass section DT of common signal line SL1 is a single pixel long. That is, the bypass section DT of the common signal line SL1 extends in the Y-direction under the data line DL2 for a single pixel and then returns under the data line DL1. However, the length of the bypass section DT is not so limited. In some cases, the bypass section DT may continue for multiple pixels. However, in these cases the bypass section DT of the adjacent common signal lines SL2, SL3, etc. will also be extended further.

The shift in the lane between the two data ins (DL) occurs on a portion of the common signal line (SL) that intersects below the gate line (GL). In this regard, a slanting portion of the common signal line SL may be covered below the gate line GL. Since the common signal line (SL) carries the modulating pulse signal during the touch scanning period, the signal on the pixel electrode (PXL) may therefore be affected by the signal on the common signal line (SL) and cause unwanted visual artifacts on the screen. can cause them. Referring to FIG. 15B, the slanting portion of the common signal line (SL) may be routed at an angle so that the slanting portion does not go below the drain (D) that is not covered by the gate line (GL) of the TFT. Additionally, some portions of the common signal line SL may be routed in the X-direction along the gate line GL to cover below the gate line GL. Additionally, the slanting portion of the common signal line (SL) must be inclined to provide sufficient margin between the two bypass sections of the common signal lines (SL). In suitable embodiments, any two bypass sections of the common signal lines SL may be spaced apart from each other by more than 5 μm, more preferably by more than 6 μm.

[Aperture rate compensation]

Depending on size and location, there may be a significant difference in maximum aperture ratio between bypass pixels and regular pixels. A portion of the bypass line BL corresponding to contact holes for connecting the bypass line BL to the common signal line SL and the common electrode block may be larger than other portions of the bypass line BL. In this way, the contact holes of the lower planarization layer (PLN-L) for connecting the common signal line (SL) to the bypass line (BL) and the upper planarization layer (PLN-L) for connecting the common electrode block to the bypass line (BL) The pixels of the contact holes of the PLN-U) may have a maximum aperture ratio that is much smaller than that of the other bypass pixels between the two planarization layers. Differences in aperture ratios of pixels may be visually noticeable to the human eye, especially when pixels of different aperture ratios are arranged in a simple repeated pattern, for example as a moire pattern or dimming line.

Because differences in aperture ratios of pixels create a visually striking pattern, reducing the difference in aperture ratios of pixels will make the pattern less noticeable. Accordingly, in some embodiments, the masking layer BM may be configured to compensate for the loss of aperture ratio of the bypass pixels.

Referring to FIG. 16 , the masking layer BM includes a plurality of strips covering the data lines DL and gate lines GL. In the present disclosure, strips arranged in the vertical direction covering the data lines DL may be referred to as data BM strips. Strips arranged in the horizontal direction covering the gate lines GL and bypass lines BL may be referred to as gate BM strips. Additionally, the portion of each gate BM strip and each data BM strip corresponding to a pixel is referred to as a gate BM section and a data BM section, respectively. That is, a single gate BM strip includes multiple gate BM sections. Similarly, a single data BM strip includes multiple data BM sections. These BM strips and BM sections of BM strips are arranged to intersect each other to set the aperture ratio of the pixel areas, so they are commonly referred to as black matrix patterns.

[Simple BM pattern]

In some embodiments, the aperture ratio of all pixels may be formed the same as shown in FIG. 16. In this regard, the width of the gate BM strips may be set to the width of the gate BM strip for the pixel area with the smallest maximum aperture ratio. For example, gate BM strips for all pixel areas may be provided with sufficient width to cover the top contact hole (CTU) and bottom contact hole (CTL). In this way, the total aperture of all pixels will be reduced to the smallest aperture of the pixels, but there will be no aperture ratio mismatch between bypass pixels and normal pixels.

In some cases, simply reducing the aperture ratio mismatch between pixels housing contact holes and normal pixels may be sufficient to remove visually striking patterns to a certain level. In this way, it is also possible to have the width/orientation adjusted section within the strip span continuously over a limited number of pixels. For example, a continuous section of a gated BM strip spanning from a pixel with a bottom contact hole (CTL) to a pixel with a top contact hole (CTU) means that the maximum aperture ratio of some pixels in this particular section is greater than that of some other pixels in this section. It may be larger than the maximum aperture of the pixels, but may also have a single width and be oriented in the same way.

In some embodiments, the width of the gate BM sections can be adjusted to reduce aperture mismatch between pixel regions. For example, the widths of the gate BM sections corresponding to normal pixels may be wider than the widths of the gate BM sections corresponding to bypass pixels that accommodate a bottom contact hole or an upper contact hole. Additionally, the widths of the gate BM sections corresponding to the middle bypass pixels may be wider than the widths of the gate BM sections corresponding to the bypass pixels that accommodate the bottom contact hole or the top contact hole. Additionally, the widths of the gate BM sections corresponding to the bypass pixels accommodating the upper contact hole may be wider than the widths of the gate BM sections corresponding to the bypass pixels accommodating the lower contact hole. In this setup, the widths of the gate BM sections are adjusted to maximize the openings of the bypass pixels that accommodate the bottom and top contact holes, and then the widths of the gate BM sections corresponding to the other pixels are adjusted to maximize the openings of the gate BM sections that accommodate the bottom contact hole and the top contact hole. It is adjusted with reference to the openings of the bypass pixels having . This setup may provide a higher overall aperture ratio than previous embodiments. However, the positions of the openings for each pixel may be skewed from each other, which may be undesirable in some cases.

It should be noted that the width difference between different sections of the gate BM strips need not be large to make the aperture ratios of the pixels exactly the same. In the example shown in Figure 16, the aperture uniformity of the bypass pixels and normal pixels may strain the overall aperture of the pixels. Accordingly, in some embodiments, the aperture of the bypass pixels may be 80% to 95% of the aperture of a normal pixel. More preferably, the opening of the bypass pixels may be 85% to 95% of the opening of the normal pixel. Aperture mismatches at these levels may not be visually noticeable to the human eye, especially when coupled with some of the other features described in this disclosure.

[Asymmetric BM pattern]

However, in these settings, the overall luminance of the display panel PNL deteriorates to some extent. Accordingly, in some other embodiments, selective sections of the masking layer BM next to pixel regions of the bypass pixels may be configured to reduce the aperture ratio mismatch between the bypass pixels and normal pixels. ) may be presented more narrowly than other sections of the section. Additionally, selective sections of masking layer BM adjacent to pixel regions of bypass pixels may be spaced or skewed away from sections adjacent to normal pixels. In this way, the aperture ratio of the bypass pixels can be increased while reducing or maintaining the aperture ratio of the regular pixels. Accordingly, the difference between the aperture ratios of the bypass pixels and the normal pixels can be reduced while maintaining the overall luminance level of the display panel PNL.

For example, the width and/or orientation of sections of data BM strips and/or gate BM strips can be adjusted to compensate for the amount of aperture difference between bypass pixels and normal pixels. In BM strips and/or gated BM strips, these adjustments may be made pixel by pixel. That is, the width/orientation of the strips may be different between pixels with lower contact holes (CTL), pixels with upper contact holes (CTU), intermediate pixels, and normal pixels.

To reduce aperture mismatch between pixels, some sections within a data BM strip may be arranged asymmetrically from other sections of the same data BM strip. At a basic level, the sections of data BM strips that border bypass pixels may be narrower than those that border only regular pixels. In these configurations, sections of the data BM strips disposed between two regular pixels may be configured to be wider than other sections of the data BM strip. That is, if either of the pixels to the left or right of this section is a bypass pixel, the width of the data BM strip in this section may be narrower than the sections between the two normal pixels. In this way, the reduction in the aperture ratio of the bypass pixels due to the bypass lines BL can be compensated to some extent.

As shown in FIG. 17A, in some embodiments, sections of the data BM strip between two immediately adjacent regular pixels (e.g., section A) may be provided with a width “W,” which width is next to a first bypass pixel with a bottom contact hole (CTL), a second bypass pixel with a top contact hole (CTU), and any intermediate bypass pixels between the first and second bypass pixels. larger than the width of the sections of the data BM strip. That is, in each of the data BM strips, a first bypass pixel (e.g., section C), a second bypass pixel, or any intermediate bypass pixels between the first and second bypass pixels ( For example, data BM sections located next to section B) may be narrower than other data BM sections located between two immediately adjacent regular pixels (e.g., section A).

Additionally, in some embodiments, data BM sections neighboring the first bypass pixel, the second bypass pixel, or any intermediate pixels between the first and second bypass pixels have substantially the same width. may have, this width being narrower than the width of the data BM sections located between two immediately adjacent normal pixels. Accordingly, the differences in the width of the masking layer BM can compensate for the aperture ratio mismatch due to the arrangement of the bypass lines BL. However, it should be noted that the width differences between different sections of the data BM strips need not be large to ensure that the aperture ratios of the pixels are exactly the same. As mentioned above, in some embodiments, the aperture of the bypass pixels may be 80% to 95% of the aperture of a normal pixel. More preferably, the opening of the bypass pixels may be 85% to 95% of the opening of the normal pixel. This level of aperture mismatch may not be visually noticeable to the human eye, especially when coupled with some of the other features described in this disclosure.

As an example, the width of the sections of the data BM strip neighboring the bypass pixels may be about 5 to 6 μm, while the width of the sections between normal pixels may be about 7 to 8 μm. The width of the data lines and the width of the common signal line (SL) should be equal to or less than the width of any given section of the data BM strip. That is, the width of the data line DL and the width of the common signal line SL located below it may be set to the narrowest width of the data BM section next to the bypass pixels.

As mentioned above, pixel areas that accommodate contact holes may have their aperture ratios maximally deteriorated by the bypass line BL. Accordingly, in some embodiments, sections of data BM strips located next to pixel regions with lower contact holes (CTL) and pixel regions with upper contact holes (CTU) provide maximum compensation of aperture ratio to these pixels. It can be configured to provide. As such, in some embodiments, as shown in sections “A”, “B”, and “C” of FIG. 17B, some data BM sections are centered about the center of the data line DL located below. It may be configured to avoid this.

In FIG. 17B, the data BM sections between a pixel with a contact hole and a normal pixel may be configured asymmetrically from other sections of the data BM strip. Figures 17C-17E are cross-sectional views of sections “A”, “B” and “C” of Figure 17B, respectively. Referring to FIG. 17C, the width of the data BM sections between normal pixels (i.e., wider portions of the data BM strips) may be larger than the width of the data line DL and the common signal line SL below. Accordingly, the additional width of the data BM section may be distributed equally on both sides on the data line DL. As an example, if the data BM section between two regular pixels has an additional width of 3 μm, then a data BM section of 1.5 μm protrudes on each side of the data line (DL) and/or common signal line (SL). can do.

As described above, the data BM section neighboring the pixel with the contact hole is configured asymmetrically with respect to the other sections of the data BM strips. In this regard, the length that the data BM section protrudes toward a normal pixel beyond the edge of the data line DL may be greater than the length of the data BM section that protrudes toward a pixel with a contact hole. As shown in Figures 17D and 17E, the edge of the data BM section and the edge of the data line DL towards the pixel with the contact hole can be aligned accurately with the maximum aperture ratio for the pixel with the contact hole, otherwise They may be oriented perpendicular to each other. Additionally, in some embodiments, the length of the data BM section that protrudes beyond the edge of the underlying data line DL toward the pixel with the contact hole is shorter than the length of each data BM section that protrudes toward the intermediate bypass pixel. .

The BM section should cover both the data line (DL) and the common signal line (SL) below, so that the edges of the data BM section and the edges of the common signal line (SL) will be oriented towards the pixels having contact holes with each other. Be careful that it may happen. That is, the edge of the data BM section may be oriented with the edge of the data line DL or the edge of the common signal line SL, whichever is closer to the pixel having the contact hole.

Light from the light source may pass through a color filter layer, which sets the light emission from each pixel area. In some embodiments, the color filter layer and masking layer BM may be provided on a second substrate different from the first substrate on which the array of TFTs is located. Here, the color filter layer may be arranged so that the masking layer BM is provided farther from the first substrate than the color filter layer. Alternatively, the color filter layer and the masking layer BM may be provided on the second substrate, and may be arranged such that the masking layer BM is provided closer to the first substrate on which the array of TFTs is provided than the color filter layer. Light from the display can protrude from the first substrate and be extracted toward the second substrate, and a masking layer (BM) located closer to the first substrate than the color filter layer prevents light from one pixel from leaking to adjacent pixels. can help suppress.

In some embodiments, the masking layer BM may be provided closer to the light source than the color filter layer. Providing the masking layer (BM) closer to the light source allows more precise control of the angle of light from the light source to the color filter layer, which in turn suppresses light leakage and/or color washout problems in the reduced width masking layer. makes it possible. Therefore, a mismatch in aperture ratio between regular and bypass pixels can be addressed with asymmetric BM strips having a lower risk of these light leakage or color wash out problems.

[wavy bypass line]

In some embodiments, the position and shape of the bypass line BL may be adjusted to maximize the aperture ratio of the bypass pixels. Depending on the shape of the gate line GL, some portions of the bypass line BL may be arched toward the gate line GL while maintaining a minimum margin from the gate line GL. By eliminating the wasted space between the gate line (GL) and the bypass line (BL), the area that must be covered by the masking layer (BM) can be reduced for bypass pixels.

18A and 18B illustrate an example configuration of bypass line BL, which may be provided in display panel PNL for larger aperture ratio bypass pixels. When using both the gate line (GL) and the bypass line (BL) formed from the second metal layer (M2), they must be spaced apart from each other by a minimum margin (marked as G2G). As a non-limiting example, the minimum margin (G2G) between the gate line (GL) and the bypass line (BL) may be about 5 μm. As shown, the gate line GL includes a plurality of gate electrodes protruding from the main routing portion of the gate line GL toward the active channels of the TFTs. In each of the two adjacent gate electrodes, there is an indented open area to connect the drain of the TFT and the pixel electrode (PXL). In this way, the portion of the bypass line BL next to the entered open area may be arched out toward the entered open area until a minimum margin is reached.

Accordingly, the bypass line BL has a sine wave in which portions of the bypass line BL curve in and out. More specifically, portions of the bypass line (BL) are arched toward the recessed open area between the two gate electrodes, and portions of the bypass line (BL) are arched against the gate electrode portion of the gate line (GL). It arches in one direction. In the example shown in Figures 18A and 18B, both the SL-BL contact area and the BL-VCOM contact area are provided in the blue pixel areas. The bypass line BL lying between two of these blue pixel areas includes three arch-in portions and three arch-out portions. Additionally, the gate line GL located closest to the bypass line BL has a plurality of recessed open areas with openings facing the nearest bypass line BL. Each arch-in portion is provided between two immediately adjacent data lines DL. Each arch-out portion is provided between two immediately adjacent pixel regions. Accordingly, each arch-out portion of the bypass line BL is provided between two arch-in portions of the bypass line. Although this sinusoidal waveform is provided on the bypass line BL, all portions of the bypass line BL are spaced from the nearest gate line GL by at least the minimum margin G2G.

[Common signal line with light shielding]

Considering the minimum margin (G2G) between the gate line (GL) and bypass line (BL) discussed above, a larger aperture ratio can be achieved by reducing the size of the gate electrode. In embodiments where the TFTs of the display panel (PNL) are bottom gate inverted staggered TFTs, the gate electrode serves as a light shield (LS) for the active channel of the TFT. To act as a light shield (LS), the gate electrode may have to be provided with dimensions larger than those required to simply control the on/off state of the TFT. The additional length of the gate electrode outside the active edge of the TFT for light shielding purposes may be referred to as the gate shield (GS). However, the dimensions of the gate electrode, especially the size of the gate shield GS, can be reduced if the active of the TFT can be shielded from light in other structures.

Accordingly, in some embodiments, a light shielding unit LS may be provided on some common signal lines SL. More specifically, the light shielding portion LS may protrude from the routing portion of the common signal line SL. The light shielding portion LS protrudes from an end of the gate electrode facing the bypass line BL. In pixels provided with the light shield LS, the width of the gate shield GS may be reduced. That is, the light shielding portion LS formed of the first metal layer M1 is provided to compensate for the reduced width of the gate shield GS. When the width of the gate shield GS is reduced, the bypass line BL can be positioned further toward the gate line GL, which allows for a thinner gate BM in the bypass pixels.

As shown in FIG. 18A, since a general pixel has the largest aperture ratio even without a light shielding unit LS, a general pixel may not need a light shielding unit LS. In these cases, the gate electrode is provided with a gate shield GS of sufficient width. For example, the width of the gate shield GS in the Y-direction may be 4 μm or more.

A light shielding portion (LS) is provided on the common signal line (SL) between the normal pixel and the first blue pixel. The common signal line SL includes a connection portion protruding from the routing portion. In these cases, the connection can be enlarged, as shown in Figure 15a, and at the same time serve as a light shield LS.

A light shielding portion LS is also provided on each of the common signal lines SL located between the first bypass pixel and the last bypass pixel. Since these common signal lines SL do not have a connection, the light shielding portion LS of these common signal lines SL is not as large as the light shielding portion of the first bypass pixel.

FIG. 18B is an enlarged view showing an example configuration of common signal lines SL with a light shielding portion LS. As shown, the light shielding unit LS may be located next to the gate shield GS on the bypass line BL. The gate electrodes of bypass pixels still include gate shields (GS), but are much narrower than the gate shields (GS) of regular pixels. As described above, the reduced width of the gate shield GS of the bypass pixels shifts the boundary of the minimum margin G2G between the gate line GL and the bypass line BL, and thus the bypass line BL. ) can also be shifted from the gate line GL toward the gate line GL without violating the minimum margin G2G.

As shown, the width of the light shielding portion LS may be larger than the width of the gate shield GS provided in a general pixel. In this way, the light shielding unit LS compensates for the reduced width of the gate shield GS in the bypass pixels. In this regard, the light shield (LS) within the bypass pixel may be configured to provide much greater coverage than the gate shield (GS) of a normal pixel. That is, the distance between the active edge of the TFT and the edge of the light shielding portion LS on the bypass line BL side may be greater than the distance between the edge of the gate shield GS and the active edge of the TFT. Additionally, the light shield LS in the bypass pixels may be arranged to at least partially overlap the gate shield GS to ensure that external light does not reach the active side of the TFT. In some cases, a portion of the light shield LS may be positioned to partially overlap the active of the TFT.

In the example shown in FIG. 18B, the light shield LS is configured to reduce the width of the gate electrode and shift the bypass line BL for a larger aperture ratio of the bypass pixels. The light shield LS is arranged to reduce the gate shield in the vertical direction (i.e. Y-direction). However, in some embodiments, light shield LS may also be configured to reduce gate shield GS in the horizontal direction (ie, X-direction). As shown in FIG. 18C, the light shield LS may extend below the gate shield GS toward the drain-pixel contact hole in the recessed open area. In this setting, the light shield LS may not contribute much to the aperture ratio of the pixels. However, a reduced gate shield (GS) toward the drain-pixel contact hole can help further reduce the TFT's Cgs and kick back voltage (ΔVp).

[Contact Bridge]

As described above, in some embodiments, a contact bridge formed of the third metal layer M3 may be located in the BL-VCOM contact area. In these embodiments, the minimum margin between the contact bridge formed by the third metal layer M3 and other metal structures must be considered. For example, a minimum margin (denoted D2D) between the contact bridge and the drain electrode of the TFT must be maintained. Additionally, a minimum margin (D2D) must be maintained between the contact bridge and the data line (DL). The minimum margin D2D that must be maintained between the metal structures formed of the third metal layer M3 may be greater than the minimum margin G2G that must be maintained between the gate line GL and the bypass line BL. Likewise, even when a light shield (LS) is provided on the common signal line (SL) to reduce the width of the gate shield (GS), it is difficult to reduce the width of the gate BM in the BL-VCOM contact area. Due to the minimum margin (D2D) from the data lines (DL), the position of the top contact hole (CTU) within the bypass pixel may be limited.

Accordingly, in some embodiments, contact between the bypass line (BL) and the common electrode block in the BL-VCOM contact area is made without a contact bridge. FIG. 19A illustrates configurations of a BL-VCOM contact area using a contact bridge and a BL-VCOM contact area without a contact bridge. Connecting the bypass line (BL) and the common electrode block through the top contact hole (CTU) without using a contact bridge may be achieved by adjusting the order in which the contact holes are formed during manufacturing of the display panel (PNL).

19B shows exemplary manufacturing steps of a display panel (PNL) without a contact bridge according to an embodiment of the present disclosure. Briefly, the method is described starting with forming the second metal layer (M2) on the lower planarization layer (PLN-L). In step 1, the second metal layer M2 forms the gate lines GL and the bypass line BL. In step 2, a gate insulating layer (GI) and a semiconductor layer (SEM) are provided on the gate lines (GL). Unlike the previous example described with reference to FIGS. 7A and 7B , in this case, contact hole formation through the semiconductor layer (SEM) and gate insulator (GI) to expose the bypass line (BL) is postponed. The third metal layer M3 may be formed to provide the data lines DL and the source/drain of the TFT. However, in this embodiment, the contact bridge shown in FIGS. 7A and 7B is not formed within the BL-VCOM contact area. The formation of the semiconductor layer (SEM) may be performed together with the formation of the third metal layer (M3), or may be performed separately prior to the formation of the third metal layer (M3).

In this case, the contact bridge in the BL-VCOM contact area is no longer needed because the bypass line (GL) in the BL-VCOM contact area is covered under the gate insulation layer (GI). In step 3, a passivation layer (PAS3) is provided. As shown in FIG. 19B, the passivation layer (PAS3) is on the gate insulating layer (GI) in the BL-VCOM contact region. In step 4, an upper planarization layer (PLN-U) is provided so that the data lines (DL) and the source/drain of the TFTs are covered below the upper planarization layer (PLN-U). Subsequently, a contact hole is formed to penetrate the upper planarization layer (PLN-U). The upper contact hole (CTU) is formed to expose the BL-VCOM contact area. At this stage, the passivation layer (PAS3) and gate insulation layer (GI) still remain above the bypass line (BL) in the BL-VCOM contact area. Similarly, contact holes can be formed through the top planarization layer (PLN-U) to expose the drain region of the TFT. The drain region exposed through the contact hole of the upper planarization layer (PLN-U) may also be covered by the passivation layer (PAS3) and the gate insulating layer (GI).

After the formation of a contact hole through the upper planarization layer (PLN-U), in step 5, the passivation layer (PAS3) and the gate insulating layer (GI) in the drain region of the TFT and the BL-VCOM contact region are connected to the bypass line (BL). It can be etched simultaneously to expose. Once the bypass line is exposed, in step 6, a transparent electrode layer (eg, ITO) can be deposited to contact the bypass line (BL) through the top contact hole (CTU). In this way, direct contact between the bypass line BL and the common electrode block can be made without using a contact bridge formed from the third metal layer M3.

Without using a contact bridge in the BL-VCOM contact area, the bypass line (BL) can be positioned closer to the gate line (GL) as long as a minimum margin between the bypass line (BL) and the gate line (GL) is maintained. there is. As described above, the width of the gate shield GS can be reduced by providing a light shielding portion LS, which is formed from the first metal layer M1 and reduces the width of the gate BM. Additionally, the contact portion of the bypass line (BL) in the BL-VCOM contact area can be shifted left or right toward the data lines (DL), which enables efficient placement of the bypass line (BL) within the pixel area. do.

[Bypass Line Shifting]

Although aperture mismatch between pixels is the root cause of visual artifacts, it is the repeated arrangement of these pixels that makes visual artifacts prominent and noticeable to the human eye. It would be difficult to detect the relatively low brightness of a single isolated set of bypass pixels. However, multiple sets of bypass pixels arranged in a repeated pattern form low and high brightness areas within the matrix that are much more perceptible to the human eye. Some patterns are inevitable in the arrangement of bypass lines within the matrix, but may become less noticeable when the patterns become sufficiently complex.

Here, the basic idea is to provide variation in the arrangement of the bypass lines BL in the matrix of pixel areas rather than simply arranging the bypass lines BL in a linear order in the vertical or horizontal direction. Accordingly, in some embodiments, a set of bypass lines (BL) connected to a common electrode block is a set of bypass lines (BL) that are displaced from at least one other bypass line (BL) of the same set. Includes bypass line (BL). More specifically, the pixel area receiving the bottom contact hole (CTL) for a bypass line (BL) of a set of bypass lines (BL) is the bottom contact hole (CTL) for at least one other bypass line (BL) of the same set. They are arranged in different rows and different columns from the pixel area receiving the contact hole (CTL).

As described above, each common electrode block may be connected to a plurality of common signal lines SL as well as dummy lines DML. Additionally, a single common signal line or a single dummy line (DML) may be connected to the common electrode block by using a plurality of bypass lines (BL). In this way, the set of bypass lines (BL) connected to the common electrode block includes a single common signal line (SL), a plurality of common signal lines (SL), a single dummy line (DML), and a plurality of dummy lines (DML). ) or may be bypass lines (BL) connected to a combination thereof.

Figure 20A shows an example configuration of a set of bypass lines for an electrode block. In this example, SL#1 is connected to the common electrode block through two bypass lines (BL 1-1 and BL 1-2). Lower contact holes (CTL) for each of the bypass lines (BL 1-1 and BL 1-2) are provided in pixel areas of the same row. Similarly, SL#2 is connected to the common electrode block through two bypass lines (BL 2-1 and BL 2-2), and for each of the bypass lines (BL 2-1 and BL 2-2) Bottom contact holes (CTL) are provided in pixel areas in the same row. SL#1 and SL#2 may each be a common signal line (SL) or a dummy line (DML).

As shown, pixel areas having lower contact holes (CTL) for bypass lines (BL) connected to SL#1 and lower contact holes (CTL) for bypass lines (BL) connected to SL#2. ) are provided in different rows. Skewing the placement of contact holes for the bypass lines BL at least into different rows can help suppress visually striking patterns, such as moire effects.

As mentioned above, bottom contact holes (CTL) and top contact holes (CTU) may be provided within the blue pixel areas. Each of the upper contact holes (CTU) for the bypass lines (BL) is located in a blue pixel area, which may also be in the same row as the blue pixel housing the lower contact hole (CTL) for the respective bypass line (BL). It may be located. It should be noted that the row of pixel areas containing pixels receiving contact holes need not be formed in the entire blue pixel areas. Instead, it may be formed of pixel regions with many different colors, including blue pixel regions that accommodate contact holes.

20B illustrates another example configuration of a set of bypass lines BL connected to a common electrode block. Similar to the previous example, SL#1 and SL#2 are connected to the same common electrode through one or more bypass lines (BL). However, in this particular example, some bypass lines BL extend to the left, while some other bypass lines BL extend to the right of the underlying lines to which they are connected.

As an example, the bypass line (BL 1-1) connected to SL#1 is further provided on the right side of the lower contact hole (CTL) for the bypass line (BL 1-1) from the lower contact hole (CTL), Extends to the upper contact hole (CTU). The bypass line (BL 2-1) connected to SL#2 is connected to the upper contact hole (CTU) provided on the side of the lower contact hole (CTL) from the lower contact hole (CTL) to the bypass line (BL 2-1). extend to Although not shown in FIG. 20B, other bypass lines connected to SL#1 and SL#2 may also be configured in a similar manner to the bypass line BL 1-1 and bypass line BL 2-1.

Additionally, among the bypass lines connected to the same common signal line (SL), some of the bypass lines may be arranged to extend toward one side of the common signal line (SL) while some of the other bypass lines extend toward the other side. arranged to extend towards For example, as shown in FIG. 20C, bypass line BL 1-1 may extend toward the right side of SL#1, but bypass line BL 1-2 extends toward the left side of SL#1. extend towards That is, the lower contact hole (CTL) for the bypass line (BL 1-1) and the lower contact hole (CTL) for the bypass line (BL 1-2) are provided in the pixel area of the same row. Meanwhile, upper contact holes (CTU) for the bypass line (BL 1-1) and the bypass line (BL 1-2) are provided on opposite sides of SL#1. Because the bypass lines are formed in the second metal layer M2 (e.g., the gate metal layer), the bypass lines can extend horizontally across SL#1 (i.e., the first metal layer M1), The data line DL (i.e., the third metal layer M3) is located on top of it.

Although the bottom contact holes (CTL) for the bypass lines (BL) are shown as being provided in pixel areas of the same column, in some other embodiments, the bottom contact holes (CTL) for each of the bypass lines (BL) are shown. ) can be located in pixel areas of different rows, even when they are connected to the same common signal line (SL) (or the same dummy line (DML)).

20D illustrates another example configuration of bypass lines BL connected to the same common electrode block. Similar to the previous example, SL#1 is connected to the common electrode block through a plurality of bypass lines (BL). However, unlike previous examples, lower contact holes CTL for some bypass lines BL are provided in pixel areas spaced from the common signal line SL (or dummy line DML).

Referring to FIG. 20D, a lower contact hole (CTL) for connecting the bypass line (BL 1-1) to SL#1 is provided in the pixel area of column A. A lower contact hole (CTL) for connecting the bypass line (BL 1-2) to SL#1 is provided in the pixel area of column B. Additionally, a lower contact hole (CTL) for connecting the bypass line (BL 1-3) to SL#1 is provided in the pixel area of column C. For this purpose, SL#1 is provided with a plurality of contact parts protruding from the routing part of SL#1, and the contact parts extend to pixel areas in different rows where contact is made with corresponding bypass lines. In other words, some contact parts of SL#1 may have different lengths than other contact parts. As described above, the dummy line (DML) may be divided into a plurality of portions to provide a passage for the contact portions to traverse and reach the pixel regions where the lower contact hole (CTL) is located. In this configuration, some contacts will traverse more or fewer dummy lines (DML) than other contacts.

In FIG. 20D, bottom contact holes (CTL) for all bypass lines (BL) connected to SL#1 are provided in pixel areas of different rows. However, it should be understood that not all bottom contact holes (CTL) for bypass lines (BL) have to be provided in pixel areas of different rows. That is, some of the lower contact holes (CTL) for the bypass lines (BL) may still be provided in the same column as the lower contact holes (CTL) for the other bypass lines (BL).

Additionally, the contact portions of SL#1 may be arranged not only in the X-direction but also in the Y-direction. In these cases, a portion of the contact portion arranged in the Y-direction may extend down a data line different from the data line DL located on the routing portion of the common signal line SL.

Referring to the example shown in FIG. 20D, the routing unit of SL#1 extends below the data line. The contact parts protrude from the routing part in the X-direction. A portion of the contact portion in contact with the bypass line (BL 1-3) extends in the Y-direction below the data line and then reaches the pixel area where the lower contact hole (CTL) is located. The contact portion in contact with the bypass line (BL 1-3) will extend across the gate line (GL). Of course, the number of gate lines GL that the contact part intersects varies as much as the length that the part of the contact part extends in the Y-direction. Accordingly, some lower contact holes (CTL) may be provided in pixel areas of the same row even if the contact portions are provided in different lengths.

In Figure 20d, the contact parts of SL#1 protrude to the right of the routing part. However, it should be understood that some common signal lines (SL) or dummy lines (DML) may include contact portions that protrude in a different direction from other contact portions of the same line.

20A to 20D, the configuration of the bypass lines BL is described with reference to only a single common electrode block. However, it should be noted that the common electrode blocks of the display panel (PNL) do not need to be configured in the same way. That is, the configuration of the common signal lines SL and bypass lines BL in one common electrode block may be different from the configuration in another common electrode block. In this way, an entire more complex bypass line (BL) pattern can be provided on the display panel (PNL) so that it is difficult for the user to visually perceive the difference in aperture ratio caused by the bypass lines (BL).

[Shielded ITO]

21A and 21B illustrate an example configuration of the display panel (PNL) in the area between two adjacent common electrode blocks. Because the common electrode VCOM is divided into several common electrode blocks, a space (denoted COMM.Space in FIGS. 21A and 21B) exists between two adjacent common electrode blocks. In this space, the electric field to control the liquid crystal molecules may be disrupted due to the lack of a common electrode block, resulting in various visual defects. In this way, a portion of the transparent electrode formed similarly to the pixel electrodes (PXL) is “COMM.” Space”. This transparent electrode is referred to as “shielded ITO” or “shielded electrode” in this disclosure.

Referring to FIGS. 21A and 21B, the shielding electrode (i.e., ITO shield or shielding ITO) is connected to the COMM between common electrode block #1 and common electrode block #2. Extend along the space. In order to keep common electrode block #1 and common electrode block #2 separated from each other, a shielding electrode is formed from the transparent electrode layer of the pixel electrode (PXL). Accordingly, the passivation layer PAS4 is interposed between the shielding electrode and common electrode block #1 and common electrode block #2. However, the shielding electrode must be connected to either common electrode block #1 and common electrode block #2 to generate an electric field to control the liquid crystal molecules in COMM.Space. Accordingly, the shield electrode has a shield electrode contact portion extending on one of common electrode block #1 and common electrode block #2. In the embodiment shown in FIGS. 21A and 21B, the shield electrode contact portion is connected to the common electrode block #1 through a contact hole (shield contact hole) through the passivation layer (PAS4) in the shield electrode (i.e., ITO shield) contact area. Contact us. Of course, the configuration of the shielding electrode can be reversed and the shielding electrode can be connected to common electrode block #2.

Placing the shield electrode contact portion and the shield contact hole may affect the maximum aperture ratio of the pixel area. Accordingly, in some embodiments, the pixel housing the shield contact hole may be equipped with a comb-shaped pixel electrode (PXL) as shown in FIG. 21A to compensate for the aperture ratio (AR) affected by the shield electrode contact area. there is. That is, a pixel having at least a portion of the shielding electrode contact portion may have a pixel electrode PXL having a comb shape. In this case, one or more comb teeth of the comb-shaped pixel electrode (PXL) may be routed to the next shield contact and extend closer toward the gate line (GL) of an adjacent row of pixels, as shown in FIG. 21A. In the example shown in FIG. 21A , one of the comb teeth EXT that is longer than the other comb teeth of the comb-shaped pixel electrode PXL passes through the shield electrode contact portion of the shield electrode and extends toward the gate line GL. The additional length of the pixel electrode (PXL) allows the electric field to be generated over a larger area within the pixel area. In some embodiments, the comb teeth of the pixel electrode PXL passing through the shielding electrode contact portion may at least partially overlap the gate line GL as shown in FIG. 21A. In this setting, the extended comb teeth of the pixel electrode PXL can generate an electric field together with the common electrode block #1 provided below it, which contributes to minimizing the width of the gate BM. In some cases, comb-shaped pixel electrodes PXL may be provided in other pixels that do not accommodate the shielding electrode contact portion. In some embodiments, the shielding electrode contact portion may be positioned to at least partially overlap the gate line GL, as shown in FIG. 21A. This setting allows the pixel electrode (PXL) to cover a larger area within the pixel area, further increasing the size of the area available for generating an electric field that does not need to be hidden by the gate BM.

Embodiments have been described using common signal lines (SL) extending along below corresponding data lines (DL). However, the features described herein can also be used when the common signal lines SL are arranged to extend along below the gate lines GL. Additionally, embodiments have been described in the context of an LCD display panel with a pixel-top structure. However, the features described in this disclosure can be equally applied to a display panel with a VCOM-top structure in which the layer of common electrode blocks and the layer of pixel electrodes are located in the reverse order to the examples shown in the drawings of this disclosure. In embodiments with a VCOM-top structure, a contact hole in the BL-VCOM contact area or in the SL-VCOM contact area connects the common electrode block to the bypass line or directly to the common signal lines (SL) through the passivation layer (PAS4). ) is formed to connect to each.

In this disclosure, many features have been described with reference to an embodiment where a common signal line (SL) and a common electrode block are connected through a bypass line (BL). However, unless a particular feature is described as being exclusive to embodiments that use bypass lines, the features are those in which the common signal line (SL) and the common electrode block are connected to the upper planarization layer (PLN-U) and the lower planarization layer (PLN-U). -L) may be applicable to embodiments in which they are in direct contact with each other through a contact hole.

In this disclosure, all embodiments are described as having common signal lines (SL) and data lines positioned to overlap each other. The width of the common signal lines SL may be the same as the width of the data lines DL. However, it should be noted that the widths of the common signal lines SL and the widths of the data lines DL may be different from each other. Using a common electrode provided in a plurality of common electrode blocks, the field of the area between two adjacent common electrode blocks may be different from other areas on the common electrode block. As such, controlling the liquid crystal molecules over these areas may be difficult, and light from the backlight may leak into pixels near these areas.

Accordingly, the data line DL and the common signal line SL may be located in an area between two adjacent common electrode blocks. In this way, the data line (DL) and common signal line (SL) can be used to block light from the backlight. The width of the data lines DL and the width of the common signal lines SL may be adjusted according to the distance between two adjacent blocks. In this regard, increasing the width of the common signal lines (SL) can help reduce the resistance on the common signal lines (SL) and lower the RC delay. In embodiments that use common signal lines SL disposed below the data lines DL, the width of the common signal lines SL may be larger than the width of the data lines DL. Because the common signal lines (SL) are located farther from the common electrode blocks and pixel electrodes than the data lines (DL), managing the coupling capacitance is more important than the data lines (DL). ) may be easy for.

In embodiments described in this disclosure, the common signal lines SL are arranged below the data lines DL (or below the gate lines GL) and directly intersect the display area from the transparent electrode block. It is routed from the display area to a driver (e.g., touch driver (TD)). By routing the common signal lines SL directly across the display area, the size of the display area in terms of the panel can be reduced. Additionally, the thickness of the passivation layer between the pixel electrode PXL and the common electrode blocks may be kept to a minimum to increase the capacitance of the pixel. Because the common signal lines SL can be spaced further apart from the common electrode blocks, they can be provided with a targeted thickness to reduce RC delays during the touch-sensing period. Additionally, because the common electrode blocks are located above the common signal lines SL, a fringe field is not created between the common electrode blocks and the common signal lines SL. This effectively solves the light leakage problem caused by having the common signal lines (SL) in the same layer as the pixel electrode (PXL).

In embodiments of the present disclosure, the transparent electrode and common signal lines (SL) have been described with reference to a touch recognition capable LCD device. However, the use of the transparent electrode (eg, common electrode block) and common signal line (SL) is not limited to displaying images from the panel and identifying the location of touch inputs. The functions of the transparent electrode and common signal lines SL during different periods are not limited to activating pixels (eg, LCD pixels) as described above. In addition to the touch-sensing function, the common electrode blocks and common signal lines (SL) can be used to measure the amount of touch pressure on the screen, generate vibration on the screen, or actuate electro-active materials in the panel. It may be possible.

For example, some embodiments of the display panel (PNL) may include a layer of deformable material. Common electrode blocks may be positioned near or interfacing with the deformable material and loaded using voltage signals to measure electrical changes caused by deformation of the deformable material. In these cases, the common electrode blocks can measure the amount of pressure on the display panel (PNL) in addition to the location of touch inputs. In some embodiments, the deformable material may be electro-active materials, and the amplitude of the material and/or the frequency of the material may be controlled by electrical signals and/or electric fields. Examples of such deformable materials include piezoelectric ceramics, electro-active-polymers, etc. In these embodiments, the common electrode blocks can be used to bend the changeable material in targeted directions and/or vibrate at targeted frequencies, thereby providing a tactile and/or tactile effect on the display panel (PNL). Provide feedback.

Although various embodiments are described in terms of display pixels, those skilled in the art will understand that the term display pixels may be used interchangeably with the term display sub-pixels in embodiments where the display pixels are divided into sub-pixels. For example, some embodiments directed to RGB displays may include display pixels divided into red, green, and blue sub-pixels. That is, in some embodiments, each sub-pixel displays a red (R), green (G), or blue color (of the combination of all three R, G, and B sub-pixels forming one color display pixel). B) Can be sub-pixel.

It will be apparent to those skilled in the art that various modifications and changes may be made in the present invention without departing from its scope. Accordingly, this disclosure is intended to cover modifications and variations of the invention provided within the scope of the appended claims and their equivalents.

Claims (81)

a plurality of pixels, each pixel including a thin film transistor and a pixel electrode, the thin film transistor being interposed between a lower planarization layer and an upper planarization layer, and the pixel electrode being on the upper planarization layer;
touch driver;
a plurality of common signal lines under the lower planarization layer, the plurality of common signal lines connected to the touch driver;
A plurality of bypass lines between the lower planarization layer and the upper planarization layer, each bypass line directly contacting at least one of the plurality of common signal lines through the lower planarization layer and through a lower contact hole. bypass line of;
A common electrode layer on the upper planarization layer, the common electrode layer comprising separated portions of common electrode blocks, and at least one of the plurality of bypass lines through an upper contact hole in each of the common electrode blocks through the upper planarization layer. the common electrode layer connected to one; and
A masking layer comprising a plurality of data black matrix strips to cover data lines and gate black matrix strips to cover gate lines, wherein the plurality of bypass lines are hidden beneath the gate black matrix strips. A liquid crystal display device having a touch sensor, comprising a layer. According to claim 1,
wherein each of the plurality of bypass lines extends between a first bypass pixel receiving a lower contact hole and a second bypass pixel receiving an upper contact hole. delete According to claim 1,
Each of the plurality of common signal lines includes a routing portion and a contact portion contacting one of the plurality of common signal lines,
the routing portion is arranged to at least partially overlap one of the data lines,
The contact portion protrudes from the routing portion toward one of the plurality of pixels arranged adjacent to the data line that at least partially overlaps the routing portion of the common signal line, and each of the plurality of bypass lines is connected to the plurality of pixels. A liquid crystal display device having a touch sensor, which is in contact with the contact portion of one of the common signal lines. According to claim 4,
Some of the plurality of common signal lines have the contact portion protruding in a first direction, and other portions have the contact portion protruding in a second direction opposite to the first direction. According to claim 1,
At least some of the gate black matrix strips include one or more gate black matrix sections arranged asymmetrically to other gate black matrix sections of the same respective gate black matrix strip. According to claim 1,
At least some of the gate black matrix strips include one or more gate black matrix sections having a width different from the width of another gate black matrix section of the same respective gate black matrix strip. According to claim 1,
At least some of the plurality of data black matrix strips include one or more data black matrix sections arranged asymmetrically to other data black matrix sections of the same respective data black matrix strips. According to claim 1,
At least some of the plurality of data black matrix strips include one or more data black matrix sections having a different width than other data black matrix sections of the same respective data black matrix strip. According to claim 8,
The data black matrix section is sandwiched between two immediately adjacent normal pixels that do not have either the bottom contact hole or the top contact hole, and is located next to a bypass pixel that has either the bottom contact hole or the top contact hole. A liquid crystal display device with a touch sensor having a width greater than the width of the data black matrix section. According to claim 1,
the masking layer and the color filter layer are disposed on an inner surface of the first substrate facing an inner surface of the second substrate on which the plurality of common signal lines are disposed;
The masking layer is disposed on the color filter layer such that the masking layer is located closer to the lower one of the first substrate and the second substrate than the color filter layer. According to claim 2,
The opening of the first bypass pixel and the opening of the second bypass pixel are in a range of 80% to 95% of the opening of a normal pixel that does not accommodate both the lower contact hole and the upper contact hole. Display device. a thin film transistor array coupled to a plurality of data lines and a plurality of gate lines provided on a first substrate;
an upper planarization layer on the thin film transistor array;
a plurality of separated transparent electrode blocks on the upper planarization layer;
driver;
a lower planarization layer below the thin film transistor array;
A plurality of common signal lines disposed below the lower planarization layer and configured to form a plurality of signal paths, each of the plurality of signal paths connecting each of the plurality of separate transparent electrode blocks between the upper planarization layer and the lower planarization layer. the plurality of common signal lines connected to the driver through a bypass line interposed therein; and
a color filter layer and a masking layer comprising a plurality of data black matrix strips configured to cover the plurality of data lines and a plurality of gate black matrix strips configured to cover the plurality of gate lines to define a plurality of pixel regions within a display area. It includes a second substrate having,
wherein the bypass line is covered beneath the plurality of gate black matrix strips. delete delete delete delete delete delete delete a plurality of common signal lines on a substrate;
a lower planarization layer covering the plurality of common signal lines;
an array of thin film transistors on the lower planarization layer, the array of thin film transistors connected to a plurality of gate lines and a plurality of data lines on the lower planarization layer;
an upper planarization layer covering the array of thin film transistors; and
A plurality of transparent electrode blocks on the upper planarization layer, each of the plurality of transparent electrode blocks configured to communicate with a touch driver through a signal path implemented by at least one of the plurality of common signal lines. Contains,
The display panel of claim 1, wherein the signal path for at least one of the plurality of transparent electrode blocks is a parallel-connected signal path implemented as a set of common signal lines. According to claim 21,
The signal path for at least one of the plurality of transparent electrode blocks is a first parallel-connected signal path implemented with a first set of common signal lines, and the signal path for another one of the plurality of transparent electrode blocks is the first parallel-connected signal path. A display panel, wherein a second parallel-connected signal path is implemented with a second set of common signal lines distinct from the first set of common signal lines. According to claim 22,
The second set of common signal lines implementing the second parallel-connected signal path is less than the total number of common signal lines of the first set of common signal lines implementing the first parallel-connected signal path. A display panel comprising common signal lines. According to claim 23,
The display panel of claim 1, wherein the transparent electrode block connected to the second parallel-connected signal path is located closer to the touch driver than the transparent electrode block connected to the first parallel-connected signal path. According to claim 23,
The first set of common signal lines are interconnected in parallel with each other by an interconnection line provided below the lower planarization layer, and the second set of common signal lines are interconnected in parallel by another interconnection line provided below the lower planarization layer. Display panels, interconnected in parallel with each other. According to claim 23,
Further comprising a plurality of bypass lines,
The display panel of claim 1, wherein the signal path is connected to the corresponding plurality of transparent electrode blocks through at least one of the plurality of bypass lines. According to claim 24,
The first parallel-connected signal path and the second parallel-connected signal path each include at least one common signal line routed across an entire display area of the display panel. According to claim 26,
Each of the plurality of bypass lines is connected to the signal path through a lower contact hole through the lower planarization layer, and is connected to the transparent electrode block through an upper contact hole through the upper planarization layer. According to claim 21,
Further comprising a plurality of dummy lines arranged below the lower planarization layer,
Each of the plurality of dummy lines is configured to extend below one of the plurality of data lines,
A display panel, wherein at least one of the plurality of dummy lines is electrically connected to a voltage source. delete According to claim 22,
Further comprising a plurality of dummy lines arranged below the lower planarization layer,
The plurality of dummy lines include a first dummy line and a second dummy line,
the first dummy line extends below one of the plurality of data lines overlapping at least one of the common signal lines included in the first set of common signal lines,
The second dummy line extends under one of the plurality of data lines overlapping at least one of the common signal lines included in the second set of common signal lines. According to claim 22,
At least one of the first parallel-connected signal path and the second parallel-connected signal path includes a main portion and a tail portion,
A display panel wherein the tail portion is implemented with fewer common signal lines than the main portion. According to claim 32,
The display panel, wherein the tail portion is configured as an independent parallel-connected signal path provided at one end of the main portion. According to claim 22,
At least one of the first parallel-connected signal path and the second parallel-connected signal path includes a main portion and a tail portion,
the tail portion includes a first section below one of the plurality of data lines and a second section below another one of the plurality of data lines,
The first section and the second section are connected in series to each other. A plurality of pixels operated by a pixel electrode and a common electrode, wherein the common electrode includes a plurality of separated common electrode blocks, each of the plurality of common electrode blocks being used to operate one or more of the plurality of pixels. the plurality of pixels;
a plurality of thin film transistors coupled to the plurality of pixels and disposed on a lower planarization layer;
touch driver; and
Includes a plurality of common signal lines disposed below the lower planarization layer,
each common electrode block of the first group of common electrode blocks is configured to communicate with the touch driver via a signal path implemented with a first number of sets of common signal lines,
A touch screen device, wherein each common electrode block of the second group of common electrode blocks is configured to communicate with the touch driver via a signal path implemented with a second number of sets of common signal lines. delete delete delete delete delete In an electronic device having a display,
A display area having a plurality of pixels;
a layer of thin film transistor array disposed within the display area;
a plurality of separate transparent electrode blocks disposed on the layer of the thin film transistor array and arranged to overlap the plurality of pixels in the display area;
touch driver; and
disposed beneath a layer of the thin film transistor array, comprising a plurality of common signal lines configured to form a plurality of signal paths;
Each of the plurality of signal paths connects each of the plurality of separate transparent electrode blocks to the touch driver,
wherein at least one signal path of the plurality of signal paths includes a main parallel-connection implemented as a set of a plurality of common signal lines and a tail part implemented as a subset of common signal lines from the set of the plurality of common signal lines. Electronic devices. touch driver;
a plurality of common signal lines on a substrate connected to the touch driver;
a lower planarization layer on the substrate covering the plurality of common signal lines;
A plurality of gate lines and a plurality of data lines disposed on the lower planarization layer, wherein each of the plurality of gate lines and each of the plurality of data lines is connected to one of a plurality of thin film transistors on the lower planarization layer. gate line and the plurality of data lines;
an upper planarization layer disposed on the plurality of thin film transistors;
A plurality of pixel electrodes and a common electrode on the upper planarization layer, wherein the common electrode includes a plurality of common electrode blocks spatially separated from the other plurality of common electrode blocks, and each of the plurality of common electrode blocks is connected to the plurality of common electrode blocks. the plurality of pixel electrodes and the common electrode connected to at least one of the signal lines;
a passivation layer interposed between the common electrode and the plurality of pixel electrodes; and
a shielding electrode at least partially overlapping the space between two immediately adjacent common electrode blocks, wherein the shielding electrode contacts the two immediately adjacent common electrode blocks through the passivation layer and through a shield contact hole. A liquid crystal display device having a touch sensor, comprising: delete delete delete delete delete delete delete a first metal layer including a plurality of common signal lines connected to a touch driver;
a lower planarization layer provided on the first metal layer;
a second metal layer on the lower planarization layer including a plurality of gate lines and a plurality of bypass lines;
a semiconductor layer on the second metal layer;
a third metal layer on the semiconductor layer including a plurality of data lines;
a plurality of thin film transistors, each of which is connected to one of the plurality of gate lines and one of the plurality of data lines;
an upper planarization layer covering the plurality of thin film transistors;
a plurality of common electrode blocks on the upper planarization layer, each of the plurality of common electrode blocks being spatially separated from other common electrode blocks;
a plurality of pixel electrodes on the upper planarization layer, each of the plurality of pixel electrodes being connected to one of the plurality of thin film transistors;
a passivation layer interposed between the plurality of common electrode blocks and the plurality of pixel electrodes; and
Each of the plurality of common electrode blocks is electrically connected to one of a first common electrode block and a second common electrode block immediately adjacent to each other, and is at least partially connected to the space between the first common electrode block and the second common electrode block. Comprising a plurality of overlapping shielding electrodes,
Each of the plurality of common electrode blocks is connected to at least one of the plurality of common signal lines through at least one of the bypass lines. According to claim 50,
One of the plurality of common signal lines and one of the plurality of data lines are configured to extend along a space between the first common electrode block and the second common electrode block,
The display panel, wherein the one of the plurality of common signal lines and the one of the plurality of data lines are arranged to at least partially overlap the shielding electrode extending between the first common electrode block and the second common electrode block. . According to claim 51,
The display panel, wherein the shielding electrode includes a shielding electrode contact portion connected to one of the first common electrode block and the second common electrode block through a shielding contact hole in the passivation layer. According to claim 52,
A display panel, wherein the pixel receiving the shielding electrode contact portion has a comb-shaped pixel electrode. According to claim 53,
The display panel, wherein the comb-shaped pixel electrode includes at least one comb tooth that is longer than other comb teeth of the comb-shaped pixel electrode. According to claim 53,
The display panel, wherein the at least one comb tooth that is longer than the other comb teeth of the comb-shaped pixel electrode is routed next to the shield electrode contact portion of the shield electrode. According to claim 53,
The display panel, wherein the at least one comb tooth that is longer than other comb teeth of the comb-shaped pixel electrode extends onto the plurality of gate lines of pixels in an adjacent row. According to claim 53,
The display panel, wherein the shielding electrode contact portion is arranged to at least partially overlap one of the plurality of gate lines. According to claim 50,
The plurality of common electrode blocks are located on the upper planarization layer,
The passivation layer is disposed on the plurality of common electrode blocks,
The display panel, wherein the plurality of pixel electrodes and the plurality of shielding electrodes are disposed on the passivation layer. According to claim 50,
The plurality of pixel electrodes and the plurality of shielding electrodes are provided on the upper planarization layer,
The passivation layer is provided on the plurality of pixel electrodes and the plurality of shielding electrodes,
The display panel, wherein the plurality of common electrode blocks are located on the passivation layer. According to claim 50,
Each of the plurality of common electrode blocks is configured to communicate with the touch driver through a dedicated signal path including one or more common signal lines, such that the plurality of common electrode blocks serve as self-capacitance touch sensors. Display panel. According to claim 50,
The plurality of common signal lines connected to the plurality of common electrode blocks are connected to be selectively linked together to implement a plurality of touch-driving electrodes and a plurality of touch-sensing electrodes that serve as mutual-capacitance touch sensors. . a plurality of common signal lines on the substrate configured to transmit signals to and from the touch driver;
a lower planarization layer on the plurality of common signal lines;
a buffer layer on the lower planarization layer including at least one of a silicon nitride layer and a silicon oxide layer;
a plurality of thin film transistors on the buffer layer having a coplanar structure;
an upper planarization layer on the plurality of thin film transistors; and
A plurality of transparent electrode blocks on the upper planarization layer, each of the plurality of transparent electrode blocks being connected to one of the plurality of common signal lines through at least one of a plurality of bypass lines interposed between the lower planarization layer and the upper planarization layer. connected to at least one of the plurality of common signal lines, each of the plurality of common signal lines having a plurality of light shielding portions, each of the plurality of light shielding portions being disposed below an active channel region of one of the plurality of thin film transistors. A display panel comprising an electrode block. According to clause 62,
Each of the plurality of light shielding parts protrudes from a routing part of each of the plurality of common signal lines extending along the plurality of data lines,
A display panel, wherein each of the plurality of light shielding units at least partially overlaps one of the plurality of gate lines. According to clause 62,
A display panel, wherein the plurality of thin film transistors include a metal oxide semiconductor layer. According to clause 64,
Each of the plurality of thin film transistors includes a gate electrode protruding from one of the plurality of gate lines, and at least a portion of each of the plurality of light shielding parts protrudes outside an outer edge of the gate electrode of each of the plurality of thin film transistors. A display panel. According to clause 62,
At least some of the plurality of light shielding units contact one of the plurality of bypass lines through a lower contact hole of the lower planarization layer. According to clause 62,
The display panel wherein the lower planarization layer includes an organosiloxane hybrid layer including a Si-O monomer and a polymer. According to clause 62,
Further comprising one or more passivation layers disposed below the lower planarization layer,
A display panel, wherein at least one of the passivation layers is disposed on the plurality of common signal lines. delete According to clause 68,
A display panel, wherein the plurality of common signal lines are formed from a stack of a plurality of metal layers including a copper layer. According to clause 62,
The display panel, wherein the touch driver is configured to measure a change in capacitance on the plurality of transparent electrode blocks. According to claim 71,
The display panel, wherein the plurality of transparent electrode blocks are configured to function as a self-capacitance touch sensor or a mutual-capacitance touch sensor. delete According to claim 71,
Further comprising an organic-light emitting diode (OLED) element,
A display panel, wherein each of the OLED elements is connected to at least one of the plurality of thin film transistors. According to claim 71,
It further includes a color filter substrate and a liquid crystal molecule layer interposed between the substrate and the color filter substrate,
A display panel, wherein each pixel has a pixel electrode configured to generate an electric field with one of the plurality of transparent electrode blocks to control liquid crystal molecules in each pixel of the display panel. In an electronic device having a touch sensor integrated display panel,
a plurality of common signal lines on a substrate, each of the plurality of common signal lines having a routing portion and an optical shielding portion;
a lower planarization layer on the plurality of common signal lines;
a plurality of thin film transistors disposed on the lower planarization layer, each of the plurality of thin film transistors including a gate electrode, a source electrode, and a drain electrode all disposed on a semiconductor layer;
an upper planarization layer on the plurality of thin film transistors;
A layer of separate transparent electrode blocks arranged on the upper planarization layer, each of the transparent electrode blocks being electrically connected to a touch driver through a signal path, the signal path being a plurality of transparent electrode blocks disposed below the lower planarization layer. At least one of the common signal lines, wherein the light shielding portion of each of the plurality of common signal lines includes a layer of transparent electrode blocks positioned to overlap the semiconductor layer of one of the plurality of thin film transistors, Electronic devices. delete delete delete delete delete

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