KR102665086B1 - Input buffer circuit with high operating speed to low voltage level input signal - Google Patents

Abstract

An input buffer circuit capable of high-speed operation for input signals at low voltage levels is published. In the input buffer circuit of the present invention, the transistors of the receiving sensing unit gated by the input signal pair swinging at a low level are implemented as PMOS type, and the transistors of the comparison buffering unit gated by the intermediate signal pair swinging at the high level are AND. It is implemented as a Morse type. Additionally, the current passing unit of the receiving sensing unit is formed between the intrinsic intermediate signal and the complementary intermediate signal output from the receiving sensing unit and is driven to allow current to flow. Accordingly, according to the input buffer circuit of the present invention, it is composed of two stages, minimizes delay time, and enables high-speed operation for input signal pairs at low voltage levels.

Description

Input buffer circuit capable of high-speed operation for low-voltage level input signals {INPUT BUFFER CIRCUIT WITH HIGH OPERATING SPEED TO LOW VOLTAGE LEVEL INPUT SIGNAL}

The present invention relates to an input buffer circuit, and more particularly, to an input buffer circuit capable of high-speed operation for low-voltage level input signals.

The input buffer circuit functions as an interface circuit in a semiconductor memory device, etc., that adjusts input signal pairs received from an external system to match the internal voltage level and provides them as a buffering signal pair. Additionally, it is effective for the input buffer circuit to be composed of two stages for high-speed operation with minimal delay time.

That is, the input buffer circuit is preferably composed of a reception sensing unit that senses the potential difference between the received input signal pair and a comparison buffering unit that buffers and provides the output signal pair of the reception sensing unit.

At this time, the receiving sensing unit needs to respond quickly to the input signal pair, and the comparison buffering unit also needs to be designed to quickly respond to the voltage level of the output signal pair of the receiving sensing unit.

Meanwhile, the input signal provided from an external system may be a high-frequency signal swinging at a low voltage level close to the ground voltage.

In this case, an input buffer circuit capable of high-speed operation for input signal pairs at low voltage levels is required.

The purpose of the present invention is to provide a two-stage input buffer circuit that minimizes delay time and is capable of high-speed operation for low-voltage level input signals.

One aspect of the present invention for achieving the above object is an input buffer circuit that buffers input signal pairs received from an external system and provides them as a buffering signal pair, wherein the input signal pair is complementary to an intrinsic input signal having opposite phases. The input buffer circuit consists of an input signal, and the buffering signal pair consists of an intrinsic buffering signal and a complementary buffering signal. The input buffer circuit according to one aspect of the present invention is a receiving sensing unit that receives the input signal pair and generates an intermediate signal pair, and includes an intrinsic receiving transistor, a complementary receiving transistor, and a current passing unit, and the intermediate signal pair is an intrinsic intermediate signal pair. It is composed of a signal and a complementary intermediate signal, and the intrinsic receiving transistor is a PMOS-type transistor that is gated on the intrinsic input signal to increase the voltage of the intrinsic intermediate signal, and the complementary receiving transistor is gated on the complementary input signal to increase the voltage of the intrinsic intermediate signal. It is a PMOS type transistor that increases the voltage of the complementary intermediate signal, and the current passing unit includes: the receiving sensing unit formed between the intrinsic intermediate signal and the complementary intermediate signal and driven to allow current to flow; and a comparison buffering unit that generates the buffering signal pair by buffering the intermediate signal pair, and includes a first intrinsic buffering transistor, a first complementary buffering transistor, a second intrinsic buffering transistor, and a second complementary buffering transistor, wherein the first The intrinsic buffering transistor is an NMOS type transistor gated on the complementary intermediate signal, the first complementary buffering transistor is an NMOS type transistor gated on the intrinsic intermediate signal, and the second intrinsic buffering transistor is gated on the intrinsic intermediate signal. The second complementary buffering transistor is an NMOS type transistor that is gated on the complementary intermediate signal, and the intrinsic buffering signal is an NMOS type transistor that is gated on the first complementary buffering transistor. It is controlled to a first logic state according to the voltage level being higher than the voltage level of the complementary intermediate signal gating the first intrinsic buffering transistor, and the complementary buffering signal is higher than the voltage level of the complementary intermediate signal gating the second intrinsic buffering transistor. and the comparison buffering unit controlled to a second logic state according to the voltage level being higher than the voltage level of the complementary intermediate signal that gates the second complementary buffering transistor.

In the input buffer circuit of the present invention configured as described above, the transistors of the receiving sensing unit gated by the input signal pair swinging at a low level are implemented as PMOS type, and the transistors gated by the intermediate signal pair swinging at the high level are compared. The transistors of the buffering unit are implemented as NMOS type. Additionally, the current passing unit of the receiving sensing unit is formed between the intrinsic intermediate signal and the complementary intermediate signal output from the receiving sensing unit and is driven to allow current to flow. Accordingly, according to the input buffer circuit of the present invention, it is composed of two stages, minimizes delay time, and enables high-speed operation for input signal pairs at low voltage levels.

A brief description of each drawing used in the present invention is provided.
1 is a diagram showing an input buffer circuit according to an embodiment of the present invention.
FIG. 2A is a diagram showing an example of implementing the reception sensing unit of FIG. 1.
FIG. 2B is a diagram showing another example of implementing the reception and sensing unit of FIG. 1.
FIG. 3 is a diagram showing the comparison buffering unit of FIG. 1.
FIG. 4 is a diagram for explaining the voltage levels of main signal pairs in the input buffer circuit of FIG. 1.

In order to fully understand the present invention, its operational advantages, and the objectives achieved by practicing the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure will be thorough and complete and so that the spirit of the invention can be sufficiently conveyed to those skilled in the art.

Also, when understanding each drawing, it should be noted that like members are shown with the same reference numerals as much as possible. In addition, detailed descriptions of well-known functions and configurations that are judged to unnecessarily obscure the gist of the present invention are omitted.

Meanwhile, in this specification, plural expressions for each component may also be omitted. For example, even if it is composed of a plurality of signal lines, it can be expressed as 'signal lines', or it can be expressed in the singular as 'signal line'. This is also because when a signal line is made up of a bundle of several signal lines with the same properties, for example, data signals, there is no need to distinguish them into singular and plural. In this respect, this description is valid. Therefore, similar expressions should also be interpreted with the same meaning throughout the specification.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings.

1 is a diagram showing an input buffer circuit according to an embodiment of the present invention. Here, the input buffer circuit of the present invention is a circuit that buffers an input signal pair (PXIN) received from an external system and provides it as a buffering signal pair (PXBF), wherein the input signal pair (PXIN) is close to the ground voltage (VSS). It operates very effectively when swinging at low voltage levels.

Here, 'received from an external system' includes the case of receiving directly from a semiconductor memory device in which the input buffer circuit of the present invention is implemented, and the case of receiving through a pad (not shown).

Referring to FIG. 1, the input buffer circuit of the present invention includes a reception sensing unit 100 that receives the input signal pair (PXIN) and generates an intermediate signal pair (PXMD) and buffers the intermediate signal pair (PXMD) to generate the intermediate signal pair (PXMD). It is provided with a comparison buffering unit 200 that generates a buffering signal pair (PXBF).

To describe again, the input buffer circuit of the present invention is composed of two stages to minimize delay time.

At this time, the input signal pair (PXIN) is composed of an intrinsic input signal (XINT) and a complementary input signal (XINB) having opposite phases, and the buffering signal pair (PXBF) is an intrinsic buffering signal (XBFT) and a complementary buffering signal. It consists of a signal (XBFB). And, the intermediate signal pair (PXMD) consists of an intrinsic intermediate signal (XMDT) and a complementary intermediate signal (XMDB).

The reception sensing unit 100 includes an intrinsic reception transistor (TRR), a complementary reception transistor (TRC), and a current passing unit (UIP).

The intrinsic receiving transistor (TRR) is a PMOS-type transistor that is gated on the intrinsic input signal (XINT) to increase the voltage of the intrinsic intermediate signal (XMDT), and the complementary receiving transistor (TRC) receives the complementary input signal ( It is a PMOS-type transistor that is gated on (XINB) to increase the voltage of the complementary intermediate signal (XMDB).

The current passing unit (UIP) is formed between the intrinsic intermediate signal (XMDT) and the complementary intermediate signal (XMDB) and is driven to allow current to flow.

Continuing, examples of the reception and sensing unit 100 are described in detail.

FIG. 2A is a diagram showing an example of implementing the reception and sensing unit 100 of FIG. 1. Referring to FIG. 2A, the reception sensing unit 100 according to an example includes a reception common terminal (NRCM), a reception biasing unit 110, an input reception unit 120, the current passing unit (UIP), and a pull-down shifting unit. (140) is provided.

The receiving biasing unit 110 is formed between the power supply voltage (VDD) and the receiving common terminal (NRCM).

The receiving biasing unit 110 specifically includes a biasing resistor 111 and a biasing transistor 112 formed in series between a power supply voltage (VDD) and the receiving common terminal (NRCM).

At this time, the biasing transistor 112 is a PMOS-type transistor driven so that current flows between the power supply voltage (VDD) and the receiving common terminal (NRCM) in response to the enable signal (XENB).

Accordingly, when the enable signal (XENB) is activated to “L”, the voltage level of the receiving common terminal (NRCM) is pulled up toward the power supply voltage (VDD).

As described above, the input receiving unit 120 includes the intrinsic receiving transistor (TRR) and the complementary receiving transistor (TRC).

At this time, the intrinsic receiving transistor (TRR) is formed between the receiving common terminal (NRCM) and the intrinsic intermediate signal (XMDT) and is a PMOS-type transistor gated by the intrinsic input signal (XINT). Additionally, the complementary receiving transistor (TRC) is formed between the receiving common terminal (NRCM) and the complementary intermediate signal (XMDB) and is a PMOS-type transistor gated by the complementary input signal (XINC).

Accordingly, the intermediate signal pair (PXMD) can quickly respond to a level change of the low level input signal pair (PXIN).

The current passing unit (UIP) includes a current passing resistor (RIP). At this time, one end of the current passing resistor (RIP) is connected to the intrinsic intermediate signal (XMDT), and the other end is connected to the complementary intermediate signal (XMDB).

Accordingly, the voltage difference between the intrinsic intermediate signal (XMDT) and the complementary intermediate signal (XMDB) is limited.

The pull-down shifting unit 140 shifts the pull-down voltage levels of the intrinsic intermediate signal (XMDT) and the complementary intermediate signal (XMDB) upward.

The pull-down shifting unit 140 specifically includes an intrinsic shifting transistor 141, a complementary shifting transistor 142, an intrinsic shifting resistor 143, and a complementary shifting resistor 144.

The intrinsic shifting transistor 141 is an NMOS type transistor whose single junction is connected to the intrinsic intermediate signal (XMDT), and the complementary shifting transistor 142 is an NMOS type whose single junction is connected to the complementary intermediate signal (XMDB). It is a MOS type transistor.

At this time, the intrinsic shifting transistor 141 is gated on the complementary intermediate signal (XMDB), and the complementary shifting transistor 142 is gated on the intrinsic intermediate signal (XMDT).

Accordingly, the change in voltage of the intrinsic intermediate signal (XMDT) and the complementary intermediate signal (XMDB) is accelerated.

In addition, the intrinsic shifting resistor 143 is formed between the other junction of the intrinsic shifting transistor 141 and the ground voltage (VSS), and the complementary shifting resistor 144 is formed between the other junction of the complementary shifting transistor 143. It is formed between the junction and ground voltage (VSS). Accordingly, the voltages of the intrinsic intermediate signal (XMDT) and the complementary intermediate signal (XMDB) are shifted to a high level.

That is, according to the pull-down shifting unit 140, the voltages of the intrinsic intermediate signal (XMDT) and the complementary intermediate signal (XMDB) are shifted to a high level, and also according to the level change of the input signal pair (PXIN). changes quickly.

Continuing, another example of implementing the reception and sensing unit 100 of FIG. 1 is described.

FIG. 2B is a diagram showing another example of implementing the reception and sensing unit 100 of FIG. 1. Referring to FIG. 2B, the reception sensing unit 100 according to another example includes a reception common terminal (NRCM), a reception biasing unit 160, an input reception unit 170, the current passing unit (UIP), and a pull-down shifting unit. It is provided with a unit 190.

The receiving biasing unit 160 is formed between the power supply voltage (VDD) and the receiving common terminal (NRCM).

The receiving biasing unit 160 specifically includes a biasing resistor 161 and a biasing transistor 162 formed in series between the power supply voltage (VDD) and the receiving common terminal (NRCM).

At this time, the biasing transistor 162 is a PMOS-type transistor driven so that current flows between the power supply voltage (VDD) and the receiving common terminal (NRCM) in response to the enable signal (XENB).

Accordingly, when the enable signal (XENB) is activated to “L”, the voltage level of the receiving common terminal (NRCM) is pulled up toward the power supply voltage (VDD).

The input receiving unit 170 includes the intrinsic receiving transistor (TRR) and the complementary receiving transistor (TRC), as described above.

At this time, the intrinsic receiving transistor (TRR) is formed between the receiving common terminal (NRCM) and the intrinsic intermediate signal (XMDT) and is a PMOS-type transistor gated by the intrinsic input signal (XINT). Additionally, the complementary receiving transistor (TRC) is formed between the receiving common terminal (NRCM) and the complementary intermediate signal (XMDC) and is a PMOS-type transistor gated by the complementary input signal (XINC).

Accordingly, the intermediate signal pair (PXMD) can quickly respond to the low level input signal pair (PXIN).

The current passing unit (UIP) includes a passing intermediate terminal (NPS), a first current passing resistor (RIP1), and a first current passing resistor (RIP2). At this time, one end of the first current passing resistor (RIP1) is connected to the intrinsic intermediate signal (XMDT), and the other end is connected to the passing intermediate terminal (NPS). Also, one end of the second current passing resistor RIP2 is connected to the complementary intermediate signal (XMDB), and the other end is connected to the passing intermediate terminal (NPS).

Accordingly, the voltage difference between the intrinsic intermediate signal (XMDT) and the complementary intermediate signal (XMDB) is limited.

The pulldown shifting unit 190 alleviates the pulldown of the intrinsic intermediate signal (XMDT) and the complementary intermediate signal (XMDB).

The pull-down shifting unit 190 specifically includes an intrinsic shifting transistor 191, a complementary shifting transistor 192, an intrinsic shifting resistor 193, and a complementary shifting resistor 194.

The intrinsic shifting transistor 191 is an NMOS type transistor whose single junction is connected to the intrinsic intermediate signal (XMDT), and the complementary shifting transistor 192 is an NMOS type whose single junction is connected to the complementary intermediate signal (XMDB). It is a MOS type transistor.

In addition, the intrinsic shifting transistor 191 and the complementary shifting transistor 192 are gated by the passing intermediate terminal (NPS).

The intrinsic shifting resistor 193 is formed between the other junction of the intrinsic shifting transistor 191 and the ground voltage (VSS), and the complementary shifting resistor 194 is formed between the other junction of the complementary shifting transistor 193. It is formed between the ground voltage (VSS).

That is, according to the pull-down shifting unit 190, the voltages of the intrinsic intermediate signal (XMDT) and the complementary intermediate signal (XMDB) are shifted to a high level.

In the receiving sensing unit 100 as described above, both the intrinsic receiving transistor (TRR) and the complementary receiving transistor (TRC) are implemented as PMOS type transistors, so that the level of the intermediate signal pair (PXMD) is a low voltage level. It changes quickly in response to the input signal pair (PXIN).

And, by the current passing unit (UIP), a current flows between the intrinsic intermediate signal (XMDT) and the complementary intermediate signal (XMDB), so that the intrinsic intermediate signal (XMDT) and the complementary intermediate signal (XMDB) The voltage difference is limited.

That is, by the pull-down shifting unit 190 and the current passing unit (UIP), the intermediate signal pair (PXMD) swings quickly at a high level close to the power supply voltage (VDD).

As a result, the intermediate signal pair (PXMD) provided from the receiving sensing unit 100 changes quickly in response to a high level with respect to the input signal pair (PXIN) swinging at a low level.

Referring again to FIG. 1, the comparison buffering unit 200 includes a first comparison buffering unit 210 and a second comparison buffering unit 230.

The first comparison buffering unit 210 includes a first intrinsic buffering transistor (TMR1) and a first complementary buffering transistor (TMC1), and generates the intrinsic buffering signal (XBFT).

At this time, the first intrinsic buffering transistor (TMR1) is an NMOS type transistor gated on the complementary intermediate signal (XMDB), and the first complementary buffering transistor (TMC1) is an NMOS type transistor gated on the intrinsic intermediate signal (XMDT). It is a MOS type transistor.

In addition, the intrinsic buffering signal (XBFT) is the voltage level of the intrinsic intermediate signal (XMDT) gating the first complementary buffering transistor (TMC1). It is controlled to the first logic state depending on whether it is higher than the voltage level of XMDB).

In this embodiment, the first logic state is “H”.

The second comparison buffering unit 230 includes a second intrinsic buffering transistor (TMR2) and a second complementary buffering transistor (TMC2), and generates the complementary buffering signal (XBFB).

At this time, the second intrinsic buffering transistor (TMR2) is an NMOS type transistor gated on the intrinsic intermediate signal (XMDT), and the second complementary buffering transistor (TMC2) is an NMOS type transistor gated on the complementary intermediate signal (XMDB). It is a MOS type transistor.

And, the complementary buffering signal (XBFB) is the voltage level of the intrinsic intermediate signal (XMDT) gating the second intrinsic buffering transistor (TMR2). The complementary intermediate signal ( It is controlled to the second logic state depending on whether it is higher than the voltage level of XMDB).

In this embodiment, the second logic state is “L”.

Continuing, the comparison buffering unit 200 is described in detail.

FIG. 3 is a diagram showing the comparison buffering unit 200 of FIG. 1, in which the first comparison buffering unit 210 and the second comparison buffering unit 230 are specifically shown.

Referring to FIG. 3, the first comparison buffering unit 210 includes a first buffering common terminal (NBCM1), a first intrinsic spare terminal (NRPR1), a first complementary spare terminal (NCPR1), and a first sourcing transistor 211. , the first intrinsic buffering transistor (TMR1), the first complementary buffering transistor (TMC1), the first intrinsic pull-up transistor 213, the first complementary pull-up transistor 214, and the first inversion driving means 215. .

The first sourcing transistor 211 is an NMOS type transistor formed between the ground voltage VSS and the first buffering common terminal NBCM1 and gated by an enable signal XENB. At this time, the first sourcing transistor 211 is turned on in response to activation of the enable signal (XENB) to “L”, and the first buffering common terminal (NBCM1) falls toward the ground voltage (VSS).

One junction of the first intrinsic buffering transistor TMR1 is connected to the first buffering common terminal NBCM1, and the other junction forms a current path with the first intrinsic spare terminal NRPR1. And, the first intrinsic buffering transistor (TMR1) is an NMOS type transistor that is gated by the complementary intermediate signal (XMDB).

One junction of the first complementary buffering transistor (TMC1) is connected to the first buffering common terminal (NBCM1), and the other junction forms a current path with the first complementary spare terminal (NCPR1). And, the first complementary buffering transistor (TMC1) is an NMOS type transistor that is gated by the intrinsic intermediate signal (XMDT).

The first intrinsic pull-up transistor 213 is formed between the power supply voltage (VDD) and the first intrinsic spare terminal (NRPR1), and is a PMOS type gated by the other junction of the first intrinsic buffering transistor (TMR1). It is implemented with a transistor.

The first complementary pull-up transistor 214 is formed between the power supply voltage (VDD) and the first complementary spare terminal (NCPR1), and is a PMOS type gated by the other junction of the first intrinsic buffering transistor (TMR1). It is implemented with a transistor.

In addition, the first inversion driving means 215 generates the intrinsic buffering signal (XBFT) by inverting the voltage of the first complementary spare terminal (NCPR1) and may be configured as an inverter.

In this way, the first intrinsic buffering transistor (TMR1) and the first complementary buffering transistor (TMC1) are both implemented as NMOS types, so that the intrinsic buffering signal ( The response speed of XBFT is very fast.

Preferably, the first comparison buffering unit 210 further includes a first intrinsic buffering resistor 217 and a first complementary buffering resistor 218.

The first intrinsic buffering resistor 217 is formed between the first intrinsic preliminary terminal NRPR1 and another junction of the first intrinsic buffering transistor TMR1. Additionally, the first complementary buffering resistor 218 is formed between the first complementary preliminary terminal NCPR1 and another junction of the first complementary buffering transistor TMC1.

Due to the first intrinsic buffering resistor 217 and the first complementary buffering resistor 218, the voltage level of the first intrinsic spare terminal NRPR1 and the first complementary spare terminal NCPR1 is equal to the first intrinsic buffering resistor 217 and the first complementary buffering resistor 218. It becomes higher than the level of the other junction of the buffering transistor (TMR1) and the other junction of the first complementary buffering transistor (TMC1).

In this case, the voltage level of the first intrinsic spare terminal (NRPR1) and the first complementary spare terminal (NCPR1) becomes a level that generates a transition of the intrinsic buffering signal (XBFT), that is, a transition level.

Accordingly, the response speed of the intrinsic buffering signal (XBFT) output from the first inversion driving means 215 is improved.

Also preferably, the first comparison buffering unit 210 further comprises first level limiting means 219 . At this time, the first level limiting means 219 limits the change in the voltage level of the first complementary spare terminal NCPR1.

More specifically, the first level limiting means 219 includes a first inverter 219a, a first level limiting resistor 219b, and a first transfer transistor 219c.

The first inverter 219a inverts the level of the first complementary spare terminal NCPR1 and outputs the output. At this time, the switching level of the first inverter 219a is preferably the same as the switching level of the first inverting driving means 215.

One end of the first level limiting resistor 219b is connected to the output of the first inverter 219a.

In addition, the first transfer transistor 219c, in response to activation of the enable signal Send to NCPR1).

In this case, when the enable signal (XENB) is activated, the change in voltage level of the first complementary spare terminal (NCPR1) may be limited to a certain range at the transition level.

Accordingly, the response speed of the intrinsic buffering signal (XBFT) output from the first inversion driving means 215 is improved.

Continuing to refer to FIG. 3, the second comparison buffering unit 230 includes a second buffering common terminal (NBCM2), a second intrinsic spare terminal (NRPR2), a second complementary spare terminal (NCPR2), and a second sourcing transistor (231). ), the second intrinsic buffering transistor (TMR2), the second complementary buffering transistor (TMC2), the second intrinsic pull-up transistor 233, the second complementary pull-up transistor 234, and the second inversion driving means 235. do.

The second sourcing transistor 231 is formed between the ground voltage (VSS) and the second buffering common terminal (NBCM2) and is an NMOS type transistor that is gated by an enable signal (XENB). At this time, the second sourcing transistor 231 is turned on in response to activation of the enable signal (XENB) to “L”, and the second buffering common terminal (NBCM2) falls toward the ground voltage (VSS).

One junction of the second intrinsic buffering transistor TMR2 is connected to the second buffering common terminal NBCM2, and the other junction forms a current path with the second intrinsic spare terminal NRPR2. And, the second intrinsic buffering transistor (TMR2) is an NMOS type transistor that is gated by the intrinsic intermediate signal (XMDT).

One junction of the second complementary buffering transistor (TMC2) is connected to the second buffering common terminal (NBCM2), and the other junction forms a current path with the second complementary preliminary terminal (NCPR2). And, the second complementary buffering transistor (TMC2) is an NMOS type transistor that is gated by the complementary intermediate signal (XMDB).

The second intrinsic pull-up transistor 233 is formed between the power supply voltage (VDD) and the second intrinsic spare terminal (NRPR2), and is a PMOS type gated by the other junction of the second intrinsic buffering transistor (TMR2). It is implemented with a transistor.

The second complementary pull-up transistor 234 is formed between the power supply voltage (VDD) and the second complementary spare terminal (NCPR2), and is a PMOS type gated by the other junction of the second intrinsic buffering transistor (TMR2). It is implemented with a transistor.

In addition, the second inversion driving means 235 inverts the voltage of the second complementary spare terminal NCPR2 to generate the complementary buffering signal XBFB, and may be configured as an inverter.

In this way, both the second intrinsic buffering transistor (TMR2) and the second complementary buffering transistor (TMC2) are implemented as NMOS types, so that the complementary buffering signal ( The response speed of XBFB) is very fast.

Preferably, the second comparison buffering unit 230 further includes a second intrinsic buffering resistor 237 and a second complementary buffering resistor 238.

The second intrinsic buffering resistor 237 is formed between the second intrinsic preliminary terminal NRPR2 and another junction of the second intrinsic buffering transistor TMR2. Additionally, the second complementary buffering resistor 238 is formed between the second complementary preliminary terminal NCPR2 and another junction of the second complementary buffering transistor TMC2.

Due to the second intrinsic buffering resistor 237 and the second complementary buffering resistor 238, the voltage levels of the second intrinsic spare terminal NRPR2 and the second complementary spare terminal NCPR2 are set to the second intrinsic buffering resistor 237 and the second complementary buffering resistor 238. It becomes higher than the level of the other junction of the buffering transistor (TMR2) and the other junction of the second complementary buffering transistor (TMC2).

In this case, the voltage levels of the second intrinsic spare terminal (NRPR2) and the second complementary spare terminal (NCPR2) become a level that generates a transition of the complementary buffering signal (XBFB), that is, a transition level.

Accordingly, the response speed of the complementary buffering signal (XBFB) output from the second inversion driving means 235 is improved.

Also preferably, the second comparison buffering unit 230 further comprises second level limiting means 239. At this time, the second level limiting means 239 limits the change in the voltage level of the second complementary spare terminal NCPR2.

More specifically, the second level limiting means 239 includes a second inverter 239a, a second level limiting resistor 239b, and a second transfer transistor 239c.

The second inverter 239a inverts the level of the second complementary spare terminal NCPR2 and outputs the output. At this time, the switching level of the second inverter 239a is preferably the same as the switching level of the second inverting driving means 235.

One end of the second level limiting resistor 239b is connected to the output of the second inverter 239a.

In addition, the second transfer transistor 239c, in response to activation of the enable signal Send to NCPR2).

In this case, when the enable signal (XENB) is activated, the change in voltage level of the second complementary spare terminal (NCPR2) may be limited to a certain range at the transition level.

Accordingly, the response speed of the complementary buffering signal (XBFB) output from the second inversion driving means 235 is improved.

In the comparison buffering unit 200 configured as described above, the first intrinsic buffering transistor (TMR1), the first complementary buffering transistor (TMC1), the second intrinsic buffering transistor (TMR2), and the second complementary buffering transistor (TMC2) are All are NMOS type transistors. That is, the comparison buffering unit 200 is implemented as an NMOS type differential amplifier.

Accordingly, the first intrinsic buffering transistor (TMR1), the first complementary buffering transistor (TMC1), the second intrinsic buffering transistor (TMR2), and the second complementary buffering transistor (TMC2) are the intermediate signal pair (PXMD) swinging at a high level. ) The response speed is very fast.

To put it again, the comparison buffering unit 200 implemented with an NMOS-type differential amplifier has a faster response speed than when implemented with a PMOS-type differential amplifier.

Continuing, with reference to FIG. 4, the voltage levels of the main signal pairs in the input buffer circuit of the present invention will be examined.

In Figure 4, the level of the power supply voltage (VDD) is set to 1.1V.

At this time, the input signal pair (PXIN) swings at a low voltage level of 0V to 0.3V. Accordingly, the response speed of the intrinsic receiving transistor (TRR) and complementary receiving transistor (TRC) implemented in the PMOS type is very fast.

The intermediate signal pair (PXMD) provided from the receiving sensing unit 100 swings at a high voltage level of 0.5V to 1.1V. Accordingly, the first intrinsic buffering transistor (TMR1), the first complementary buffering transistor (TMC1), the second intrinsic buffering transistor (TMR2), and the second complementary buffering transistor (TMR1) of the comparison buffering unit 200 implemented in the NMOS type ( The response speed of TMC2) is very fast.

At this time, the first complementary spare terminal NCPR1 and the second complementary spare terminal NCPR2 of the comparison buffering unit 200 swing in a level range of 0.2V to 0.9V.

And, the buffering signal pair (PXBF) driven by the voltage of the first complementary spare terminal (NCPR1) and the second complementary spare terminal (NCPR2) swings between the ground voltage (VSS) and the power supply voltage (VDD).

In summary, in the input buffer circuit of the present invention, the transistors (TRR, TRC) of the reception sensing unit 100, which are gated by the input signal pair (PXIN) swinging at a low level, are implemented as PMOS type, and are implemented as PMOS type. The transistors (TMR1, TMC1, TMR2, TMC2) of the comparison buffering unit 200 gated by the intermediate signal pair (PXMD) swinging in are implemented as NMOS type. In addition, the current passing unit (UIP) of the reception sensing unit 100 is formed between the intrinsic intermediate signal (XMDT) and the complementary intermediate signal (XMDB) output from the reception sensing unit 100 and driven so that current flows. Accordingly, according to the input buffer circuit of the present invention, the delay time is minimized as it is composed of two stages, and high-speed operation is possible for the input signal pair (PXIN) at a low voltage level.

As described above, although the embodiments have been described with limited examples and drawings, various modifications and variations can be made by those skilled in the art from the above description. For example, the described techniques are performed in a different order than the described method, and/or components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or other components are used. Alternatively, appropriate results may be achieved even if substituted or substituted by an equivalent.

Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the attached registration claims.

Claims (12)

An input buffer circuit that buffers input signal pairs received from an external system and provides them as a buffering signal pair. The input signal pair consists of an intrinsic input signal and a complementary input signal having opposite phases, and the buffering signal pair is an intrinsic input signal pair. In the input buffer circuit consisting of a buffering signal and a complementary buffering signal,
A receiving sensing unit that receives the input signal pair and generates an intermediate signal pair, including an intrinsic receiving transistor, a complementary receiving transistor, and a current passing unit, wherein the intermediate signal pair consists of an intrinsic intermediate signal and a complementary intermediate signal, The intrinsic receiving transistor is a PMOS type transistor that is gated on the intrinsic input signal to increase the voltage of the intrinsic intermediate signal, and the complementary receiving transistor is a PMOS type transistor that is gated on the complementary input signal to increase the voltage of the complementary intermediate signal. type of transistor, and the current passing unit includes: the receiving sensing unit formed between the intrinsic intermediate signal and the complementary intermediate signal and driven to allow current to flow; and
A comparison buffering unit that generates the buffering signal pair by buffering the intermediate signal pair and includes a first intrinsic buffering transistor, a first complementary buffering transistor, a second intrinsic buffering transistor, and a second complementary buffering transistor, wherein the first intrinsic buffering transistor The buffering transistor is an NMOS type transistor gated on the complementary intermediate signal, the first complementary buffering transistor is an NMOS type transistor gated on the intrinsic intermediate signal, and the second intrinsic buffering transistor is gated on the intrinsic intermediate signal. It is an NMOS type transistor that is gated, and the second complementary buffering transistor is an NMOS type transistor that is gated on the complementary intermediate signal, and the intrinsic buffering signal is the voltage of the intrinsic intermediate signal that gates the first complementary buffering transistor. It is controlled to a first logic state according to the level being higher than the voltage level of the complementary intermediate signal gating the first intrinsic buffering transistor, wherein the complementary buffering signal is the voltage level of the intrinsic intermediate signal gating the second intrinsic buffering transistor. The comparison buffering unit is controlled to a second logic state according to the level being higher than the voltage level of the complementary intermediate signal gating the second complementary buffering transistor,
The receiving sensing unit
Receiving common terminal;
a receiving biasing unit formed between a power supply voltage and the receiving common terminal and driven to pull up the voltage level of the receiving common terminal;
An input receiving unit comprising the intrinsic receiving transistor and the complementary receiving transistor, wherein the intrinsic receiving transistor is formed between the receiving common terminal and the intrinsic intermediate signal, and the complementary receiving transistor is formed between the receiving common terminal and the complementary intermediate signal. The input receiving unit formed between;
the current passing unit; and
A pull-down shifting unit that shifts the pull-down levels of the intrinsic intermediate signal and the complementary intermediate signal,
The pull-down shifting unit is
an NMOS type intrinsic shifting transistor whose one junction is connected to the intrinsic intermediate signal, the intrinsic shifting transistor being gated by the complementary intermediate signal;
an NMOS type complementary shifting transistor whose one junction is connected to the complementary intermediate signal, the complementary shifting transistor being gated by the intrinsic intermediate signal;
an intrinsic shifting resistor formed between the other junction of the intrinsic shifting transistor and a ground voltage; and
An input buffer circuit comprising a complementary shifting resistor formed between the ground voltage and another junction of the complementary shifting transistor.
delete The method of claim 1, wherein the receiving biasing unit
Equipped with a biasing resistor and a biasing transistor formed in series between the power supply voltage and the receiving common terminal,
The biasing transistor is
An input buffer circuit, characterized in that it is a PMOS-type transistor driven so that a current flows between the power supply voltage and the receiving common terminal in response to an enable signal.
The method of claim 1, wherein the current passing unit
An input buffer circuit comprising a current passing resistor having one end connected to the intrinsic intermediate signal and the other end connected to the complementary intermediate signal.
delete The method of claim 1, wherein the current passing unit
Passing middle terminal;
a first current passing resistor having one end connected to the intrinsic intermediate signal and the other end connected to the passing intermediate terminal; and
An input buffer circuit comprising a second current passing resistor having one end connected to the complementary intermediate signal and the other end connected to the passing intermediate terminal.
delete delete An input buffer circuit that buffers input signal pairs received from an external system and provides them as a buffering signal pair. The input signal pair consists of an intrinsic input signal and a complementary input signal having opposite phases, and the buffering signal pair is an intrinsic input signal pair. In the input buffer circuit consisting of a buffering signal and a complementary buffering signal,
A receiving sensing unit that receives the input signal pair and generates an intermediate signal pair, including an intrinsic receiving transistor, a complementary receiving transistor, and a current passing unit, wherein the intermediate signal pair consists of an intrinsic intermediate signal and a complementary intermediate signal, The intrinsic receiving transistor is a PMOS type transistor that is gated on the intrinsic input signal to increase the voltage of the intrinsic intermediate signal, and the complementary receiving transistor is a PMOS type transistor that is gated on the complementary input signal to increase the voltage of the complementary intermediate signal. type of transistor, and the current passing unit includes: the receiving sensing unit formed between the intrinsic intermediate signal and the complementary intermediate signal and driven to allow current to flow; and
A comparison buffering unit that generates the buffering signal pair by buffering the intermediate signal pair and includes a first intrinsic buffering transistor, a first complementary buffering transistor, a second intrinsic buffering transistor, and a second complementary buffering transistor, wherein the first intrinsic buffering transistor The buffering transistor is an NMOS type transistor gated on the complementary intermediate signal, the first complementary buffering transistor is an NMOS type transistor gated on the intrinsic intermediate signal, and the second intrinsic buffering transistor is gated on the intrinsic intermediate signal. It is an NMOS type transistor that is gated, and the second complementary buffering transistor is an NMOS type transistor that is gated on the complementary intermediate signal, and the intrinsic buffering signal is the voltage of the intrinsic intermediate signal that gates the first complementary buffering transistor. It is controlled to a first logic state according to the level being higher than the voltage level of the complementary intermediate signal gating the first intrinsic buffering transistor, wherein the complementary buffering signal is the voltage level of the intrinsic intermediate signal gating the second intrinsic buffering transistor. The comparison buffering unit is controlled to a second logic state according to the level being higher than the voltage level of the complementary intermediate signal gating the second complementary buffering transistor,
The comparison buffering unit
a first comparison buffering unit including the first intrinsic buffering transistor and a first complementary buffering transistor to generate the intrinsic buffering signal; and
A second comparison buffering unit including the second intrinsic buffering transistor and the second complementary buffering transistor to generate the complementary buffering signal,
The first comparison buffering unit is
a first buffering common terminal;
a first true spare terminal;
a first complementary spare terminal;
an NMOS type first sourcing transistor formed between a ground voltage and the first buffering common terminal and gated by an enable signal;
The first intrinsic buffering transistor of an NMOS type, one junction of which is connected to the first buffering common terminal, the other junction of which forms a current path with the first intrinsic spare terminal, and which is gated by the complementary intermediate signal;
The first complementary buffering transistor of an NMOS type, one junction of which is connected to the first buffering common terminal, the other junction of which forms a current path with the first complementary spare terminal, and which is gated by the intrinsic intermediate signal;
a PMOS type first intrinsic pull-up transistor formed between a power supply voltage and the first intrinsic spare terminal and gated by another junction of the first intrinsic buffering transistor;
a PMOS type first complementary pull-up transistor formed between the power supply voltage and the first complementary spare terminal and gated by another junction of the first intrinsic buffering transistor; and
A first inversion driving means is provided to inversely drive the voltage of the first complementary spare terminal to generate the intrinsic buffering signal,
The second comparison buffering unit is
a second buffering common terminal;
a second true spare terminal;
a second complementary spare terminal;
an NMOS-type second sourcing transistor formed between the ground voltage and the second buffering common terminal and gated by the enable signal;
an NMOS type second intrinsic buffering transistor, one junction of which is connected to the second buffering common terminal, the other junction forming a current path with the second intrinsic preliminary terminal, and the second intrinsic buffering transistor being gated by the intrinsic intermediate signal;
The second complementary buffering transistor of the NMOS type, one junction of which is connected to the second buffering common terminal, the other junction of which forms a current path with the second complementary spare terminal, and which is gated by the complementary intermediate signal;
a second intrinsic pull-up transistor of PMOS type formed between the power voltage and the second intrinsic preliminary terminal and gated by another junction of the second intrinsic buffering transistor;
a second complementary pull-up transistor of PMOS type formed between the power supply voltage and the second complementary preliminary terminal and gated by another junction of the second intrinsic buffering transistor; and
An input buffer circuit characterized by comprising a second inversion driving means that inversely drives the voltage of the second complementary spare terminal to generate the complementary buffering signal.
The method of claim 9, wherein the first comparison buffering unit
a first intrinsic buffering resistor formed between the first intrinsic spare terminal and another junction of the first intrinsic buffering transistor; and
Further comprising a first complementary buffering resistor formed between the first complementary spare terminal and another junction of the first complementary buffering transistor,
The second comparison buffering unit is
a second intrinsic buffering resistor formed between the second intrinsic spare terminal and another junction of the second intrinsic buffering transistor; and
An input buffer circuit further comprising a second complementary buffering resistor formed between the second complementary preliminary terminal and another junction of the second complementary buffering transistor.
The method of claim 9, wherein the first comparison buffering unit
Further comprising first level limiting means for alleviating changes in the voltage level of the first complementary spare terminal,
The second comparison buffering unit is
An input buffer circuit further comprising second level limiting means for alleviating changes in the voltage level of the second complementary spare terminal.
12. The method of claim 11, wherein the first level limiting means
a first inverter that inverts the level of the first complementary spare terminal and outputs the output;
a first level limiting resistor, one end of which is connected to the output of the first inverter; and
and a first transfer transistor that transmits the voltage of the other end of the first level limiting resistor to the first complementary spare terminal in response to the enable signal,
The second level limiting means is
a second inverter that inversely drives the signal of the second complementary spare terminal and outputs it;
a second level limiting resistor, one end of which is connected to the output of the second inverter; and
An input buffer circuit comprising a second transfer transistor that transmits the voltage of the other end of the second level limiting resistor to the second complementary spare terminal in response to the enable signal.

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