KR102662095B1 - Surface Trap Level Extraction Method - Google Patents

Abstract

This application provides a surface trap level extraction method that is helpful in evaluating the reliability of HEMT including an epitaxial structure.

Description

Surface Trap Level Extraction Method}

This application relates to a method for extracting surface trap levels.

Recently, high-electron-mobility-transistors (HEMT _S ) have received considerable attention as a next-generation semiconductor technology due to their outstanding material properties and device performance, including power and RF applications up to the subterahertz regime. These advantageous properties and performances are mainly due to the high quality of the epitaxial structure, which consists of an Al _x Ga _1-x N barrier layer and a GaN channel layer, forming a two-dimensional electron gas (2DEG) on Si, Sapphire, and SiC.

In particular, the quality of the interface between the Al _x Ga _1-x N barrier layer and the GaN channel layer is very important for improving carrier transmission in the channel during device operation. In addition to the quality of the epitaxial structure, reliability is an ongoing research topic that requires investigation of various factors.

The purpose of the present invention is to provide a surface trap level extraction method that is helpful in evaluating the reliability of HEMT _S including an epitaxial structure.

The present invention relates to a method for extracting surface trap levels, and provides a method for extracting surface trap levels including interface traps and boundary trap densities between group III-V compounds and group III-V compounds.

Specifically, the present invention relates to an interface trap and boundary trap between an Al _x Ga _1-x N barrier layer and a GaN channel layer in an epitaxial structure including an Al _x Ga _1-x N barrier layer and a GaN channel layer. (border trap) Provides a method to extract the surface trap level including density. The Al _x Ga _1-x N barrier layer may be an Al _0.25 Ga _0.75 N barrier layer.

The epitaxial structure may be applied to high electron mobility transistors (HEMTs). Referring to FIG. 1, the high electron mobility transistor may have a structure in which a SiC substrate, an AlN nucleation layer, a GaN high-resistance layer, a GaN channel layer, an Al _x Ga _1-x N barrier layer, and a gate are sequentially stacked. there is.

The surface trap level extraction method according to the present invention extracts the surface trap level including the interface trap and border trap density between the Al _x Ga _1-x N barrier layer and the GaN channel layer, It is possible to analyze the trap level of _{the x} Ga _1-x N barrier layer, and based on this, it can contribute to improving the electrical characteristics of HEMTs by improving the Al _x Ga _1-x N barrier layer.

The interface trap density (Dit) can be determined using the conductance method. The conductivity method is one of the widely used methods for analyzing interface traps between dielectrics and semiconductors in MOS equipment. _{The Al} . More specifically, FIG. 2A shows an equivalent circuit diagram of a metal-oxide semiconductor filed effect transistor (MOS) in a depleted state containing an interface trap.

Here, C _it is the interfacial trap capacitance, C _s is the semiconductor capacitance and R _s is the series resistance. The interface trap capacitance means C _it = qD _it , where q is the charge of the element and D _it is the interface trap density. When electrons are captured by an interfacial trap, they directly contribute to the formation of the interfacial trap capacitance C _it .

The interfacial trap density (D _it ) can be calculated from the normalized parallel conductance peak (Gp/ω) _max as shown in Equation 1 below.

[Equation 1]

In Equation 1 above, A is the device area, q is the charge, G _p is the equivalent parallel conductance, and ω is the angular frequency. For example, the device area may refer to the area of the section where electrons actually move within HEMTs.

The equivalent parallel conductivity (Gp) can be measured using Equation 2 below.

[Equation 2]

In Equation 2 above, C _ins is the barrier layer capacitance, G _c is the corrected conductivity, and C _c is the corrected capacitance. In the present invention, the term insulator or barrier layer may refer to an Al _x Ga _1-x N barrier layer, and the channel layer may refer to a GaN channel layer.

According to Equations 3 to 5 below, the corrected conductivity and corrected capacitance must each be corrected for series resistance R _s .

For example, the corrected capacitance and the corrected conductivity may be corrected by Equation 3 and Equation 4 below, respectively.

[Equation 3]

[Equation 4]

In Equations 3 and 4 above,

G _m is the measured conductivity, C _m is the measured capacitance, and R _s is the series resistance.

The series resistance can be measured by Equation 5 below.

[Equation 5]

In Equation 5, C _ma and G _ma are the capacitance and conductivity measured in the accumulation state, respectively, and ω is the angular frequency.

As shown in Equation 6 below, the interfacial trap response can be measured by Shockley-Read-Hall statistics of capture and release rates.

[Equation 6]

In Equation 6 above, ΔE is the energy difference between the trap energy level E _T and the conductivity band E _C , K _B is the Boltzmann constant, and T is the temperature. σ is the cross-section of the trap, v _th is the average heat velocity, and D _dos is the effective density of states.

Figure 2b is an equivalent circuit diagram of a distributed bulk oxide trap model representing a metal oxide semiconductor device.

In the present invention, boundary trap extraction (N _bt ) used the distributed circuit model shown in Figure 2b. The distributed circuit model shown in Figure 2b is described in "Yuan, Y. et al. A distributed model for border traps in Al2O3-InGaAs MOS devices. IEEE Electron Device Lett. 32, 485-487 (2011)." This is a modified version based on the literature.

To extract boundary traps, the distributed boundary trap model analyzes the distribution of the frequency of the accumulation region at a specific gate bias voltage. In this model, the barrier layer capacitance is divided into elements with small capacitance. In other words, it can be expressed as ε _ins /△x, where ε _ins is the dielectric permittivity and △x is a small portion of the barrier layer thickness. The boundary trap induced charge and energy loss can be described by a series of admittances for a certain portion of the thickness. The total admittance consists of a series connection of the capacitance C _bt and the conductivity G _bt connected in parallel to the barrier layer capacitance. The semiconductor capacitance C _s is connected in series, and the overall structure can be expressed by a first-order differential equation as shown in Equation 7 below.

[Equation 7]

In equation 7 above,

The boundary conditions are x = 0, Y = jωC _s (Y = total admittance),

j is the imaginary part of the complex number, ω is the angular frequency, q is the electronic charge,

τ is the average time for an empty trap to capture an electron, ε _ins is the dielectric permittivity, and N _bt is the boundary trap density of the insulating layer.

In general, boundary traps within the barrier layer and carriers moving within the channel layer can exchange charges. This charge exchange occurs through tunneling. The average time for an empty trap to capture an electron is expressed as 　τ, which is exponentially proportional to the distance x between the trap and the interface, as shown in Equation 8 below.

[Equation 8]

In Equation 8 above, τ ₀ is the capture/release time constant, and k is the attenuation constant of the barrier layer.

The attenuation constant of the barrier layer is defined by Equation 8-1 below.

[Equation 8-1]

In Equation 8-1, m ^* is the effective mass of the barrier layer, E _b is the height of the energy barrier between the barrier layer and the channel layer, and h is the reduced Planck's constant.

Additionally, t ₀ can be defined as Equation 9 below.

[Equation 9]

In Equation 9 above, n _s is the electron density on the semiconductor surface, v _th is the electron heat velocity, and σ is the trapping cross-sectional area of the boundary trap. When the device is in the accumulation state, the Fermi level is close to the conduction band. In this case, n _s can be relatively equal to the density of states in the conduction band. Assuming ωτ=1, the probe depth (X _p ) of the boundary trap at a fixed frequency (f) can be measured as shown in Equation 10 below.

[Equation 10]

Additionally, Equation 10 above can be simplified as Equations 11 to 13 below for the total capacitance (C _tot ).

[Equation 11]

[Equation 12]

[Equation 13]

The surface trap level extraction method according to the present invention enables accurate measurement of the surface trap level including the interface trap density and boundary trap density between the AlGaN barrier layer and the GaN channel layer, thereby improving the performance of HEMTs containing the AlGaN/GaN epitaxial structure. It can contribute to improvement and reliability evaluation.

Figure 1 is a schematic diagram showing the structure of high electron mobility transistors (HEMTs).
2A is an equivalent circuit diagram of a metal-insulator-semiconductor device in depletion mode.
Figure 2b is an equivalent circuit diagram of a distributed bulk oxide trap model representing a metal oxide semiconductor device.
Figure 3a is a graph showing frequency-based CV measurement results showing the active response area of the trap.
Figure 3b is a comparison graph between measured and simulated CV characteristics.
Figure 3c is a simulated band diagram showing traps in the depletion region.
Figure 3d is a simulated band diagram showing traps in the accumulation region.
Figure 4a is a graph showing the interfacial trap distribution as a function of band energy state.
Figure 4b is a graph showing the equivalent parallel conductance peak (G _p /ω) versus frequency at different gate bias points.
Figure 4c is a graph showing the basic transfer curve (log(I _D ) _-VGS ) showing the subthreshold swing (ss).
Figure 5a is a fitting curve generated using a distributed circuit model at V _GS =-3.5 V.
Figure 5b is a contour mapping graph of the boundary trap distribution of the Al _0.25 Ga _0.7 N barrier layer at the Al _0.25 Ga _0.7 N/GaN interface.
Figure 6a is a graph showing the noise spectral density (S _ID /ID ² ) versus frequency at various gate bias (V _GS ) points.
Figure 6b is a graph showing noise spectral density (S _ID /ID ² ) and (g _m /I _D ) ² as a function of drain current ID.

Since the present invention can make various changes and have various embodiments, specific embodiments will be illustrated in the drawings and described in detail in the detailed description.

However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all changes, equivalents, and substitutes included in the spirit and technical scope of the present invention.

In the present invention, terms such as "comprise" or "have" are intended to designate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but are not intended to indicate the presence of one or more other features. It should be understood that this does not exclude in advance the possibility of the existence or addition of elements, numbers, steps, operations, components, parts, or combinations thereof.

Therefore, the configuration shown in the embodiments described in this specification is only one of the most preferred embodiments of the present invention and does not represent the entire technical idea of the present invention, so various equivalents can be substituted for them at the time of filing the present application. There may be variations.

An epitaxial layer was grown on a SiC substrate using metal organic chemical vapor deposition (MOCVD). As shown in Figure 1, the AlN nucleation layer, 2.6㎛ high-resistance GaN layer, 150nm GaN channel layer, and 28nm Al _0.25 Ga _0.75 N barrier layer were deposited in that order from bottom to top. As a result of Hall measurements, the mobility (μ _{n_Hall} ) and sheet charge density (2DEG) were found to be 2200 cm ² ·V ^-1 ·s ^-1 and 9×10 ¹² cm ^-2 , respectively.

To isolate the devices, mesa isolation was performed by Cl ₂ -based inductively coupled plasma (ICP) etching. Before ohmic metal deposition, the substrate was diluted with a mixture of HCl and deionized water (1:5) for 30 seconds to remove any type of native oxide formed.

To facilitate ohmic contact formation, Si/Ti/Al/Ni/Au ( _1/25/160 /40/100 nm) alloy was deposited on the source and drain regions.

The contact resistance (R _C ) and sheet resistance (R _SH ) were extracted as 1.2 Ω·mm and 320 Ω/□, respectively, by transmission-line-method (TLM) measurements. To achieve strong probe contact, a Ti/Au (20/300 nm) padding layer was deposited using an E-beam evaporator. Lastly, the gate metal Ni/Au (20/400 nm) was also deposited using an e-beam evaporator.

The gate length (L _g ), gate width (W _g ), and source-drain distance (L _sd ) of the fabricated device were 14, 50, and 18 μm, respectively. All devices had the same source-to-gate distance (L _sg ) and a gate-to-source distance (L _gd ) of 2 μm. In the high-resolution TEM image of Figure 1, a well-deposited Al _0.25 GaN _0.75 N/GaN interface could be observed. The thickness of the Al _0.25 GaN _0.75 N barrier layer was about 28 nm (27.8 nm), and it formed a good interface with the GaN channel layer.

Figure 3a is a graph showing frequency-based C-V measurement results showing the active response region of the trap, Figure 3b is a comparison graph between measured and simulated C-V characteristics, and Figure 3c is a simulation showing the trap in the depletion region. This is a simulated band diagram, and Figure 3d is a simulated band diagram showing traps in the accumulation region.

Figure 3a shows the frequency-based CV measurement results of Al _0.25 GaN _0.75 N/GaN HEMT with clear frequency dispersion. Frequency dispersion can occur for several reasons. Some of the major causes of frequency dispersion in CV measurements include parasitic effects, lossy interfacial layers, surface roughness, and quantum mechanical constraints. Among them, the cause that has the greatest impact is the lossy interface layer of Al _x Ga _1-x N/GaN. The trap states in the Al _x Ga _1-x N layer are mostly responsible for the dispersion. The frequency dispersion of the depletion region indicates that this region is a dominant region of interfacial traps, while the dispersion of the accumulation region indicates a dominant region of boundary traps. The Nextnano simulation tool (one-dimensional Poisson-Schrödinger solver) was used to compare measured and simulated capacitances for constant gate overdrive (VGS - VT), as shown in Figure 3b. It can be seen that the measured and simulated CV curves are similar, making it clear that the leakage current effect on the measured data is lower. Therefore, it was confirmed that the Al _x Ga _1-x N layer can be treated as an insulator due to its high dielectric constant, similar to the MIS/MOS structure. Figure 3c, d showed the band diagrams (determined through simulation) in the depletion and accumulation regions, respectively. In the depletion region, the interfacial traps above the Fermi level (E _F ) were mostly activated. This resulted in capture and release of carriers in the channel region. In the accumulation region where E _F penetrates the conduction band E _C , electrons on the surface were captured and released by the border trap through tunneling.

A Keysight B1500A semiconductor device analyzer and Agilent 4384A precision LCR meter were used for all DC measurements. 1/f measurements were performed using a setup consisting of a battery-operated SRS SR570 low-noise current preamplifier, an HP 35670A dynamic signal analyzer, and a 1 Hz filter device. The barrier layer capacitance (C _ins ) was determined by equation 14:

[Equation 14]

In Equation 14 above, ε _o is the permittivity of free space and ε _ins is the dielectric permittivity. "Zhao, JZ et al. Determination of the relative permittivity of the AlGaN barrier layer in strained AlGaN/GaN heterostructures. Chin. Phys. B 18, 3980-3984 (2009)" and "Li, L. et al. On the hole injection for III-nitride based deep ultraviolet light-emitting diodes. Materials (Basel) 10, 1221 (2017). According to the literature, ε=0.5x+9.5 (where x is Al _x Ga _1-x N barrier) represents the Al content of the layer), where the calculated value of ε _ins is approximately 9.375 for x = 25%.

The tensor component of AlN and the {0001} relative permittivity of GaN were linearly interpolated to obtain the relationship. The parallel equivalent conductance (G _p ) was calculated using Equation 1 described above with correction of the measured capacitance and conductance for series resistance.

Figure 4a is a graph showing the interfacial trap distribution as a function of the band energy state, Figure 4b is a graph showing the equivalent parallel conductance peak (Gp/ω) versus frequency at different gate bias points, and Figure 4c is a graph showing the subthreshold voltage swing. This is a graph showing the basic transfer curve (log(I _D ) _-VGS ) showing (subthreshold swing, ss).

In other words, Figure 4b is a graph of parallel conductance peaks (G _p /ω) versus angular frequency (ω).

D _it was extracted from the (Gp/ω) _max peak using Equation 5 described above. "Ma, ", "Liu, WL, Chen, YL, Balandin, AA & Wang, KL Capacitance-voltage spectroscopy of trapping states in GaN/AlGaN hetero-structure field-effect transistors. https://doi.org. /10.1166/jno.2006.212 (2006).” and "Kordos, P., Stoklas, R., Gregusova, D. & Novak, J. Characterization of AlGaN/GaN metal-oxide-semiconductor field-effect transistors by frequency dependent conductance analysis. Appl. Phys. Lett. 94, 1 -4 (2009)." The D _it value extracted using the conductivity method described in the literature ranges from 2.5×10 ¹² cm ^-2 ·eV ^-1 to 7.1×10 ¹² cm ^-2 ·eV ^-1 , which is 10 ¹¹ to 10 ¹⁴ for S-HEMT and MOS-HEMT. ·It was within the range of eV ^-1 . Figure 4a shows D _it versus trap energy (ΔE) calculated using Equation 6. For this calculation, the frequency corresponding to (G _p /ω) _max was considered.

The average thermal rate v _th and effective density of states (D _dos ) of GaN materials at room temperature (300 K) are: “Kordos, P., Stoklas, R., Gregusova, D. & Novak, J. Characterization of AlGaN/GaN metal-oxide -Semiconductor field-effect transistors by frequency dependent conductance analysis. Phys. Lett. 94, 1-4 (2009). It is 2.6x10 ⁷ cm·s-1 and 1.2x10 ¹⁸ cm ^-3, respectively. was considered In addition, from the content described in the literature "Zhang, K. et al. Trap states in InAlN/AlN/GaN-based double-channel high electron mobility transistors. J. Appl. Phys. 113, 10-25 (2013)", the trap cross section The value of σ was assumed to be 3.4×10 ^-15 cm ² . The reliability of the extracted D _it value was determined through theoretical calculation of the subthreshold voltage swing (SS) using Equation 15 below.

[Equation 15]

The SS value calculated from the lowest extracted D _it was found to be approximately 143 mV·dec ^-1 , while the value determined by baseline IV measurements was found to be 142 mV·dec ^-1 (Figure 4c). The similarity between these measured and calculated values confirmed the reliability of the extracted D _it values.

The parameters in Table 1 were used to extract the boundary trap density N _bt .

Sample Al _0.25 Ga _0.75 N/GaN parameter value T _ins [nm] 28 ε _ins 9.375 m ^* [m _o ] 0.19 E _b [eV] 0.8 K[nm ^-1 ] 1.99 C _s [㎌·cm ^-2 ] 0.27 τ ₀ [s] 1Х10 ^-12 D _it [cm ^-2 ·eV ^-1 ] 2.5Х10 ¹² N _bt [cm ^-3 ·eV ^-1 ] 1.5Х10 ¹⁹ N _t [cm ^-3 ·eV ^-1 ] 1.5Х10 ¹⁹

In Table 1 above, for the calculation of the attenuation coefficient, the effective mass of Al _0.25 Ga _0.75 N was considered to be 0.19 m _o (where m _o represents the rest electron mass). Figure 5a is a fitting curve generated using the distributed circuit model at V _GS = -3.5 V, and 5b is a contour mapping graph of the boundary trap distribution of the Al _0.25 Ga _0.7 N barrier layer at the Al _0.25 Ga _0.7 N/GaN interface.

The semiconductor capacitance C _S was estimated through Nextnano simulation at a cumulative gate bias of -3.5V, which is the basic N _bt extraction voltage. According to the above-mentioned equation 4, the optimal capacitance curve was obtained at -3.5V by considering N _bt and τ _o as variable fitting parameters. As shown in Figure 5a, the best-fitting curve was obtained for N _bt = 1.5 × 10 ¹⁹ cm ⁻³ ·eV ⁻¹ and τ _o = 1 × 10 ⁻¹² s. Here, C _M represents the measured capacitance at -3.5 V and various applied frequencies, and Ctot represents the fitted curve. The spatial distribution of N _bt as a function of the applied V _GS and the probe depth (X _P ) from the Al _0.25 Ga _0.75 N/GaN interface into the Al _0.25 Ga _0.75 N barrier layer is shown in Figure 5b. N _bt values were extracted from various applied voltages at specific applied frequencies. The probe depth from the interface into the Al _0.25 Ga _0.75 N layer was calculated using equation 10 described above using different τ values related to the N _bt values. Since boundary traps exhibit more dominant characteristics at low frequencies, a low frequency of 10 kHz was used to extract the probe depth (X _P ).

As V _GS increases, the Fermi level E _F tends to penetrate deeper into the conduction band E _C . As a result, more electrons tended to tunnel into the deep level trap. Since all parameters except τ _o were fixed, τ _o showed an inverse relationship with the probe depth (X _P ).

Figure 6a is a graph showing the noise spectral density (S _ID /ID ² ) versus frequency at various gate bias (VGS) points, and Figure 6b is a graph of the noise spectral density (S _ID /ID 2 ) and (S ID /ID ² ) as a function of drain current ID. This is a graph showing g _m /I _D ) ² .

Frequency measurements were performed by changing the gate voltage V _GS and fixing the drain bias V _DS at 0.5V. Figure 6a shows the normalized S _ID /ID ² (drain current noise spectral density) for frequencies up to 10 ⁴ Hz for various V _GS in the linear region. The noise level (S _ID /ID ² ) was found to decrease as V ^GS increases and the device switches from weak to strong inversion. A clearer result can be obtained by plotting the normalized S _ID /ID ² as a function of ID (drain current). Figure 6b shows a plot of normalized S _ID /ID ² (blue spheres) as a function of ID at a frequency of 10 Hz.

"Lyu, J.-S. A new method for extracting interface trap density in short-channel MOSFETs from substrate-bias-dependent subthresh-old slopes. ETRI J. 15, 10-25 (1993)." According to the literature, the phenomenon of channel carrier trapping in the gate dielectric is described below using the carrier number variation (CNF) model in Equations 16 and 17.

[Equation 16]

[Equation 17]

In Equations 16 and 17 above, S _Vfb is the flatband voltage power spectral density, kT is the heat energy, WL is the channel area, Cd is the dielectric capacitance, f is the frequency, N _t is the bulk/boundary trap density. Additionally, λ is the tunneling attenuation distance of the dielectric, expressed as λ = [4π(2m*Ф _B ) ^1/2 /h] ^-1 , where Ф _B is the dielectric barrier height.

According to the CNF model, S _ID /I _D ² and (g _m /I _D ) ² vary in a range similar to the drain current or gate voltage. Referring to Figure 6b, S _ID /I _D ² (blue sphere) and (g _m /I _D ) ² (red line) were confirmed to change similarly at various _IDs . From Equation 16, the S _Vfb value was calculated as 10 ^-10 V ² ·Hz ^-1 , and from Equation 17, the boundary trap density N _t was calculated as 1.3 × 10 ¹⁹ cm ^-3 ·eV ^-1 .

These values were similar to the values of the boundary trap density N _bt extracted from the distributed circuit model, and were reported in “Im, K.-S., Lee, J.-H., Choi, YJ & An, SJ Effects of GaN buffer resistance on The device performances of AlGaN/GaN HEMTs 10, 1-7 (2020).", "Vodapally, S. et al. Comparison for 1/f noise characteristics of AlGaN/GaN FinFET and planar MISHFET. Electron Devices 64, 3634-3638 (2017)" and "Effects of series resistance and interface properties on the operation of AlGaN/GaN high electron mobility microelectrons. 2018)." It was at a similar level to the values of 10 ¹⁸ to 10 ²² cm ^-3 ·eV ^-1 found in the literature.

Review

Unlike existing MOS trap extraction methods that mainly focus on the insulator/AlGaN interface, the present invention performed trap analysis focusing on the AlGaN/GaN interface. The interfacial trap density D _it and boundary trap density N _bt of the Al _0.25 Ga _0.75 N/GaN interface were extracted using a modified version of the existing MOS trap extraction method. The Al _0.25 Ga _0.75 N barrier layer was similar to the insulator of the MOS structure because it had a relatively high dielectric constant. The D _it value extracted using the conductivity method ranged from 2.5Х10 ¹² cm ^-2 ·eV ^-1 to 7.1Х10 ¹² cm ^-2 ·eV ^-1 , and the N ^bt value extracted using the distributed circuit model was 1.5Х10 ¹⁹ cm ^-3 · It was eV ^-1 , o was 1 Х 10 ^-12 s. The boundary trap density N _t extracted using the CNF model through 1/f frequency measurements was 1.3 Х 10 ¹⁹ cm ^-3 ·eV ^-1 (same level as the N _bt value extracted above), demonstrating the validity and reliability of the trap extraction method. was confirmed.

Claims (8)

In an epitaxial structure including an Al _x Ga _{1 -x} N barrier layer and a GaN channel layer _, the interface trap density (D _it ) and boundary trap ( It is characterized by extracting the surface trap level including the border trap density (N _bt ),
The Al _x Ga _1-x N barrier layer is an insulating layer,
The interfacial trap density (D _it ) is measured using Equation 1 below according to the conductance method,
The border trap density (N _bt ) is measured using Equation 7 below according to the distributed border trap model, and the method of extracting the surface trap level is:
[Equation 1]

[Equation 7]

In equation 1 above,
A is the device area, q is the charge, G _p is the equivalent parallel conductance, ω is the angular frequency,
In equation 7 above,
The boundary conditions are x = 0, Y = jωC _s (Y = total admittance),
j is the imaginary part of the complex number, ω is the angular frequency, q is the electronic charge,
τ is the average time for an empty trap to capture an electron, ε _ins is the dielectric permittivity, and N _bt is the boundary trap density of the insulating layer. delete According to claim 1,
The equivalent parallel conductivity is measured by the following equation 2. Extraction method of surface trap level:
[Equation 2]

In Equation 2 above, C _ins is the capacitance of the barrier layer, G _c is the corrected conductivity, and C _c is the corrected capacitance. According to claim 3,
Method for extracting surface trap level wherein the corrected capacitance and corrected conductivity are corrected by the following equations 3 and 4, respectively:
[Equation 3]

[Equation 4]

In Equations 3 and 4 above,
G _m is the measured conductivity, C _m is the measured capacitance, and R _s is the series resistance. According to claim 4,
The series resistance is measured by the following equation 5. Extraction method of surface trap level:
[Equation 5]

In Equation 5 above,
C _ma and G _ma are the capacitance and conductivity measured in the accumulated state, respectively. delete According to claim 1,
The average time for an empty trap to capture the electron is defined by the following equation 8. Extraction method of surface trap level:
[Equation 8]

In Equation 8 above,
τ ₀ is the capture/release time constant, k is the attenuation constant of the barrier layer,
The attenuation constant of the barrier layer is defined by the following equation 8-1,
[Equation 8-1]

In Equation 8-1 above,
m ^* is the effective mass of the barrier layer, E _b is the height of the energy barrier between the barrier layer and the channel layer, and h is the reduced Planck's constant.

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