KR102660254B1 - Compositions for cleaning semiconductor substrate and cleaning method - Google Patents

Abstract

The present invention relates to a composition for cleaning a III-V compound semiconductor substrate and a cleaning method using the same. According to the present invention, the substrate is deformed and damaged without causing material loss or increased surface roughness for the III-V compound. can be minimized, which can be very advantageous in manufacturing devices that implement improved hole mobility and conductivity.

Description

Composition and cleaning method for cleaning semiconductor substrates {COMPOSITIONS FOR CLEANING SEMICONDUCTOR SUBSTRATE AND CLEANING METHOD}

The present invention relates to a composition and cleaning method for cleaning semiconductor substrates, and more specifically, to a composition for cleaning group III-V compound semiconductor substrates and a cleaning method using the same.

Current semiconductor manufacturing technology is approaching the physical shrinkage limit of materials due to continuous miniaturization, which is causing problems such as short channel effects and increased leakage current. In addition, semiconductors, which have entered the era of the 4th Industrial Revolution, are not only used in high-performance smart devices, artificial intelligence, and the Internet of Things, but also in wearable devices such as smart watches and earphones, leading to continued demand for miniaturization and miniaturization of semiconductors. As the number increases, the above problems are becoming more prominent.

To solve these problems, various materials have been introduced for use in the developed CMOS (complementary metal-oxide-semiconductor) process. One of these materials is the use of group III-V compounds, which can achieve higher hole mobility compared to silicon. It is attracting attention as a channel material for next-generation semiconductor devices as it enables the production of high-speed and low-power devices. When using Group III-V compounds as substrates for high-performance devices, the Group III-V compounds must comply with strict metal contamination guidelines or requirements of semiconductor manufacturing facilities. Meeting these guidelines or requirements is highly dependent on the cleaning and etching composition used, especially since the surface roughness of the cleaned substrate must not be affected.

The prior art regarding cleaning of III-V compound semiconductor substrates deals with bulk etching (micro scale), but little is known about how to effectively clean III-V compound semiconductor substrates that are only nanometers thick. As prior art, Non-Patent Document 1 discloses a hydrochloric acid (HCl)-based solution process. However, the process using this is not suitable because it can deform and damage the channel surface of the semiconductor device by causing material loss and an increase in surface roughness for group III-V compounds, which are easily oxidized compared to silicon.

Accordingly, there is still a need for the development of new compositions and processes that can solve the problems in the hydrochloric acid-based solution process described above without containing hydrochloric acid.

ECS Journal of Solid State Science and Technology, 3 (6) P179-P184 (2014)

The purpose of the present invention is to provide a composition for cleaning group III-V compound semiconductor substrates that exhibits excellent cleaning effect and a cleaning method using the same.

In detail, a composition for cleaning group III-V compound semiconductor substrates that does not cause material loss or increase in surface roughness of the cleaning object and a cleaning method using the same are provided.

In detail, it provides a simple and commercially very advantageous cleaning method.

In order to solve the above-described problem, the present invention includes an oxygen compound selected from nitric acid and phosphoric acid, hydrogen peroxide, and water, where the oxygen compound and the hydrogen peroxide are 1:1 to 10:1, and the oxygen compound and the water are 1:1. A composition for cleaning a group III-V compound semiconductor substrate is provided, comprising a volume ratio of 50 to 1:200.

The composition for cleaning group III-V compound semiconductor substrates according to an embodiment of the present invention may not contain halogen anions.

The composition for cleaning group III-V compound semiconductor substrates according to an embodiment of the present invention may have a pH value in the range of 0 to 4.

In the composition for cleaning a group III-V compound semiconductor substrate according to an embodiment of the present invention, the group III-V compound semiconductor substrate may contain arsenic (As).

In the composition for cleaning a III-V compound semiconductor substrate according to an embodiment of the present invention, the III-V compound semiconductor substrate may be selected from InAs, GaAs, InGaAs, InGaAsP, AlAs, AlGaAs, InAlAs, and InAlGaAs. there is.

In the composition for cleaning a group III-V compound semiconductor substrate according to an embodiment of the present invention, the roughness value after cleaning compared to the roughness value before cleaning of the group III-V compound semiconductor substrate may satisfy the following equation 1.

[Equation 1]

RMS ₁ - RMS ₀ ≤ 1.5 nm

[In Equation 1 above, RMS ₀ is the roughness value before cleaning, and RMS ₁ is the roughness value after cleaning.]

In the composition for cleaning group III-V compound semiconductor substrates according to an embodiment of the present invention, the RMS ₁ may be 5 nm or less.

In addition, the present invention provides a method for cleaning a III-V compound semiconductor substrate, including the step of contacting one surface of the III-V compound semiconductor substrate with the cleaning composition described above.

In the cleaning method according to an embodiment of the present invention, the step may be performed at 60°C or lower.

In addition, the present invention includes forming a channel region including an epitaxial layer including a group III-V compound on a semiconductor wafer; and cleaning the semiconductor wafer by contacting it with the cleaning composition described above.

In the method of manufacturing a semiconductor device according to an embodiment of the present invention, the group III-V compound may be selected from InAs, GaAs, InGaAs, InGaAsP, AlAs, AlGaAs, InAlAs, and InAlGaAs.

In the method of manufacturing a semiconductor device according to an embodiment of the present invention, the InGaAs may be In _x Ga _1-x As (0<x<1).

The composition for cleaning group III-V compound semiconductor substrates according to the present invention may be a composition that does not cause material loss and increase in surface roughness for group III-V compounds, which are problems in conventional hydrochloric acid-based solution processes. Through a stable cleaning process using this, it is possible to easily control the surface roughness of the III-V compound semiconductor substrate and minimize deformation and damage to the substrate. Moreover, residues that may exist on the surface of the substrate, such as trace amounts of metal particles and organic substances, can be effectively cleaned.

According to the present invention, it can serve as a very advantageous advantage in manufacturing devices that implement more improved hole mobility and conductivity. In addition, the cleaning process using this can be performed under mild conditions such as normal pressure and room temperature, which has the effect of greatly simplifying the process.

1 is an image showing the roughness (root mean square) measured by an atomic force microscope (AFM) of a group III-V compound semiconductor substrate according to the cleaning method of Examples and Comparative Examples of the present invention. .

Hereinafter, the present invention will be described in more detail. Unless otherwise defined, the technical and scientific terms used herein have meanings commonly understood by those skilled in the art to which this invention pertains, and the following description may not unnecessarily obscure the gist of the present invention. Descriptions of the known functions and configuration are omitted.

Additionally, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly dictates otherwise.

In addition, units used in this specification without special mention are based on volume, and for example, units of % or ratio mean volume % or volume ratio.

In addition, the numerical range used in this specification includes the lower limit and the upper limit and all values within the range, the increments logically derived from the shape and width of the defined range, all double-defined values, and the upper limit and the upper limit of the numerical range defined in different forms. Includes all possible combinations of lower bounds. As an example, if the numerical value is 100 to 10,000, and specifically limited to 500 to 5,000, the numerical range of 500 to 10,000 or 100 to 5,000 should also be interpreted as described in the specification of the present invention. Unless otherwise specified in the specification of the present invention, values outside the numerical range that may occur due to experimental error or rounding of values are also included in the defined numerical range.

It is an open description that has the same meaning as the terms in this specification, such as "comprises," "comprises," "contains," "has," or "featured," and is not additionally listed. or does not exclude the process.

The term "substantially not including" in this specification means that other elements, materials or processes not listed together with the specified element, material or process are impermissible for at least one basic and novel technical idea of the invention. This means that it can be present in an amount that does not have a significant effect. Additionally, this means that the impact is minimal.

As used herein, the term “cleaning” may refer to a process of effectively cleaning and removing substances that may be present on the surface of the cleaning target. As a non-limiting example of the cleaning target, the wafer surface is uniformly etched to reduce material loss. This may mean a process that can minimize surface roughness and reduce surface roughness.

Group III-V compound semiconductor substrates, such as InGaAs, are attracting attention as channel materials for next-generation semiconductor devices because they enable the production of high-speed and low-power devices. In order to use a group III-V compound semiconductor substrate in a device channel, a cleaning process is required to remove contaminants (e.g., metal particles, organic substances, etc.) generated during the semiconductor manufacturing process or generated on the substrate from various contaminants. need. Additionally, to improve the yield, performance, and reliability of semiconductor chips, cleaning the substrate before subsequent processes is essential.

The cleaning method typically used in conventional semiconductor manufacturing processes is the RCA cleaning method developed by RCA in the United States around 1970. This is SC1 (Standard Cleaning-1, NH ₄ OH:H ₂ O ₂ :H ₂ O=1:1:5 at SC2 (Standard Cleaning-2, HCl:H ₂ O ₂ :H ₂ O=1:1:5 at 75~ using 75~90℃, oxidation reaction by hydrogen peroxide on the semiconductor surface, and complex formation reaction between metal contaminants and hydrochloric acid. This conventional cleaning method consists of a sequential process at 90°C and is also used to clean group III-V compound semiconductor substrates. However, the existing hydrochloric acid-based cleaning method, such as SC2, is used to clean group III-V compounds, which are more easily oxidized than silicon. It is not suitable as a cleaning method for semiconductor channels because it can cause material loss and increase surface roughness, causing deformation and damage to the semiconductor channel surface. Therefore, III-V method can minimize deformation and damage to the semiconductor surface without containing hydrochloric acid. Surface cleaning technology for compound semiconductors is expected to have a significant impact on next-generation semiconductor device manufacturing technology.

Under this recognition, the present inventors have intensified their research on a new cleaning technology that can effectively control material loss and surface roughness of III-V compound semiconductor substrates without using hydrochloric acid. As a result, it was discovered that synergy can be provided to the above-described effects by implementing stable etching behavior for the InGaAs substrate in a specific acidic solution containing hydrogen peroxide, and the present invention is proposed.

Hereinafter, the present invention will be described in detail.

The cleaning composition according to an embodiment of the present invention may be intended for cleaning group III-V compound semiconductor substrates. In addition, the surface of the group III-V compound semiconductor substrate cleaned according to the present invention can be cleaned without substantial change in stoichiometry, and the surface roughness can be controlled by uniform etching.

Specifically, the cleaning composition according to an embodiment of the present invention includes an oxygen compound selected from nitric acid and phosphoric acid, hydrogen peroxide, and water, and the oxygen compound and the hydrogen peroxide are 1:1 to 10:1, and the oxygen compound and the hydrogen peroxide are The water may be included in a volume ratio of 1:50 to 1:200. More specifically, the oxygen compound and the hydrogen peroxide may be included in a volume ratio of 1:1 to 5:1, more specifically, 1:1 to 2:1. Additionally, the acid compound and water may be included in a volume ratio of 1:70 to 1:150 or 1:90 to 1:120. A cleaning composition that satisfies this composition can provide improved cleaning performance with stable etching behavior.

More specifically, the cleaning composition satisfies the above-mentioned volume ratio and may include 0.5 to 3% by weight of the oxygen compound, 0.05 to 2% by weight of hydrogen peroxide, and a remaining amount of water, or 0.5 to 2% by weight of the oxygen compound. %, it may contain 0.05 to 1.5% by weight of hydrogen peroxide and the remaining amount of water, or it may contain 0.5 to 1.5% by weight of the above-mentioned acid compound, 0.05 to 1.5% by weight of hydrogen peroxide and the remaining amount of water.

Moreover, the cleaning composition according to an embodiment of the present invention is a composition containing hydrochloric acid, that is, when it contains chloride anions, the substrate is deteriorated due to material loss and surface roughness of the III-V compound semiconductor and the use of concentrated hydrochloric acid. It is possible to minimize surface particle contamination of semiconductor substrates, and to rule out environmental safety and health problems such as corrosion of metals, alloys and equipment exposed to chloride anions, or respiratory and burn symptoms when exposed to humans. has an advantage in Accordingly, the composition for cleaning group III-V compound semiconductor substrates according to an embodiment of the present invention may not contain halogen anions such as chloride anions (Cl ^- ). For example, the halogen anion does not substantially contain at least one anion selected from fluoride anion (F ^- ), chloride anion (Cl ^- ), bromine anion (Br ^- ), iodine anion (I ^- ), etc. You can.

For example, when the cleaning composition contains halogen anions, some metal components of the group III-V compound semiconductor substrate may be dissolved. As a result, the surface roughness of the substrate may be deteriorated.

Additionally, the composition for cleaning group III-V compound semiconductor substrates according to an embodiment of the present invention may have a pH value in the range of 0 to 4. Additionally, the pH of the cleaning composition may satisfy the range of 0 to 3.5, or 0 to 3, or 0 to 2.5.

As an example, the cleaning composition may contain phosphoric acid.

In the composition for cleaning a group III-V compound semiconductor substrate according to an embodiment of the present invention, the group III-V compound semiconductor substrate may contain arsenic (As). A non-limiting example thereof may be one selected from InAs, GaAs, InGaAs, InGaAsP, AlAs, AlGaAs, InAlAs, and InAlGaAs. In terms of realizing an electron mobility that is more than 8 times higher than that of Si, it may specifically be In _x Ga _1-x As (0<x<1). In this case, more specifically, it may be 0.4<x<0.8 or 0.5<x<0.7. More specifically, it may be 0.52<x<0.61. Most specifically, x may be 0.53, but is not limited thereto. Here, the cleaning composition may be used to uniformly etch the surface of the substrate so that the roughness value after cleaning satisfies the range of 5 nm or less. If the roughness value after cleaning is satisfied, the decrease in electron or hole mobility of the semiconductor wafer due to surface cleaning can be suppressed, and the speed of the CMOS device manufactured thereafter can be improved. Accordingly, there is less attack on the substrate, and further improved removal of residues that may exist on the surface of the substrate, such as trace amounts of metal particles and organic substances, can be provided.

In the composition for cleaning a group III-V compound semiconductor substrate according to an embodiment of the present invention, the roughness value after cleaning compared to the roughness value before cleaning of the group III-V compound semiconductor substrate may satisfy the following equation 1.

[Equation 1]

RMS ₁ - RMS ₀ ≤ 1.5 nm

[In Equation 1 above, RMS ₀ is the roughness value before cleaning, and RMS ₁ is the roughness value after cleaning.]

For example, when a cleaning process is performed using the cleaning composition, Equation 1 may satisfy 1.5 nm or less, 1 nm or less, or 0.2 nm or less.

As an example, when performing a cleaning process using the cleaning composition, Equation 1 satisfies the range of 1.5 nm or less, and the roughness value after cleaning (RMS ₁ ) satisfies 5 nm or 4.5 nm or less. It could be.

As shown in FIG. 1, according to the present invention, the surface roughness value is significantly suppressed, and a III-V compound semiconductor substrate with low surface roughness can be provided. However, if the volume ratio condition of the above-described oxygen compound and hydrogen peroxide is not satisfied, the roughness value after cleaning increases rapidly, and the condition of Equation 1 described above as well as the roughness value after cleaning (RMS ₁ ) cannot be satisfied, which is not desirable.

Additionally, the present invention provides a cleaning use of the above-described group III-V compound semiconductor substrate cleaning composition.

The cleaning application according to one aspect of the present invention may be a cleaning process including the step of contacting one surface of a group III-V compound semiconductor substrate with the cleaning composition of the present invention described above. In the above cleaning process, the cleaning temperature, cleaning conditions, etc. are not particularly limited, and of course, they can be appropriately adjusted depending on the type and thickness of the cleaning object to be cleaned, the desired roughness value after cleaning, etc.

In addition, a cleaning application according to an aspect of the present invention includes forming a channel region including an epitaxial layer including a group III-V compound on a semiconductor wafer; and cleaning the semiconductor wafer by contacting it with the cleaning composition of the present invention described above.

As an example, the semiconductor device includes a first metal oxide and a second metal oxide by atomic layer deposition (ALD) using a first metal precursor, a second metal precursor, and an oxidizing agent on a channel layer based on a group III-V compound. It may include forming a gate oxide film. Here, during the atomic layer deposition, the first metal oxide and the second metal oxide may include a gate structure that is alternately deposited. Here, the formation of the gate oxide film is described later by atomic layer deposition, but is not limited to this deposition method.

In the atomic layer deposition, when the cycle number of the first metal oxide is x, the cycle number of the second metal oxide is y, and the total number of cycles is n, x:y is 1:9 to 7:3, and n is 20. It can be performed as follows, but is not limited to this. For example, x:y may be 1:5 to 6:4, 1:4 to 6:4, or 1:3 to 6:4, and n may be 15 or less, 12 or less, 11 or less, and 9 or less. Or it may be 8 or less. At this time, the first metal precursor may be trimethylaluminum, etc., and the second metal precursor may be tetrakis (ethylmethylamido) hafnium). The oxidizing agent is not limited as long as it is a common oxidizing agent. Additionally, the atomic layer deposition may be performed at 200 to 300°C, for example, 220 to 280°C or 240 to 260°C.

As an example, the thickness of the group III-V compound-based panel layer and gate oxide film is not limited, but may be formed in the range of 1 to 30 nm, 3 to 20 nm, or 4 to 10 nm.

The group III-V compound in the channel layer may be selected from InAs, GaAs, InGaAs, InGaAsP, AlAs, AlGaAs, InAlAs, and InAlGaAs. Group III-V compounds as described above have a lower effective mass than conventionally used Si, enabling high electron mobility and injection speed. By increasing the average carrier velocity due to the above-described high electron mobility, high operative drive current and high switching speed can be achieved, and these physical properties are further improved through the cleaning process according to the present invention. It can be improved. For example, the group III-V compound in the channel layer may be InGaAs, and specifically, In _x Ga _1-x As (0<x<1). In particular, In _0.53 Ga _0.47 As, where x is 0.53, is preferable in that it can achieve mobility 8 times higher than Si, but is not limited thereto.

Specifically, in the cleaning application according to an embodiment of the present invention, the contact may be performed at 60°C or lower, or 50°C or lower, or in the range of 0 to 40°C. Accordingly, according to the present invention, stable cleaning performance can be realized even under milder cleaning temperature conditions, and improved electrical characteristics can be provided by controlling the surface characteristics (surface roughness value) of the group III-V compound semiconductor substrate.

Additionally, according to the present invention, it is possible to provide advantages in the rate of change of the surface hole mobility and conductivity. For example, the surface hole mobility may implement a change rate of 5% or less, specifically, a change rate of 4% or less compared to the initial (surface hole mobility before cleaning) value. Here, the rate of change may be the rate of change of the surface hole mobility value measured based on 30 minutes of cleaning time compared to the initial value, and the (-) value means a decrease in the surface hole mobility value. The cleaning composition according to the present invention solves the above-described problems caused by halogen anions such as conventional chloride anions (Cl ^- ), uniformly etch the substrate surface, and remove electrons or holes (electrons) of the semiconductor wafer according to surface cleaning. It can have an excellent effect in suppressing the decrease in mobility of holes.

The present invention will be described in more detail below based on examples and comparative examples. However, the following Examples and Comparative Examples are only one example to explain the present invention in more detail, and the present invention is not limited by the following Examples and Comparative Examples. In the invention, unless otherwise stated, all temperatures refer to ℃ units, and unless otherwise specified, the amount of composition used refers to the volume ratio.

(Examples 1 to 4 and Comparative Examples 1 to 6)

The compositions and ratios shown in Table 1 below were mixed and stirred at 500 rpm for 5 minutes at 25°C to prepare a cleaning composition.

(Table 1)

(Assessment Methods)

To evaluate the performance of the cleaning composition prepared in the above examples and comparative examples, a Si-doped n-type In _0.53 Ga _0.47 As epitaxial layer deposited by metal-organic chemical vapor deposition on a 2-inch Fe-doped InP wafer was used. A substrate was prepared. The prepared substrate was cut into 0.5 cm × 0.5 cm or 1 cm × 1 cm, washed with deionized water, dried using nitrogen gas, and then used.

Evaluation①

Before and after the cleaning process, the thickness of the substrate was measured using a scanning electron microscope (FE-SEM, Field Emission Scanning Electron Microscopes, model name: JEOL-7610-Plus, manufacturer: JEOL Ltd.). The material loss rate was calculated by dividing the change in thickness before and after the cleaning process by the cleaning process time. The cleaning process was performed by immersion at 25°C for 5 minutes.

Evaluation②

Before and after the cleaning process, the roughness (RMS: root mean square) value of the substrate was measured using an atomic force microscope (AFM). The cleaning process was performed by immersion at 25°C for 5 minutes.

Evaluation③

The surface hole mobility and conductivity of the substrate were measured using Hall measurement. The InGaAs wafer before and after the cleaning process was mounted on a Hall measurement equipment, and the hole mobility and conductivity of a 0.5 cm × 0.5 cm square area on the InGaAs wafer were measured using a 0.565 T magnet. Here, cleaning was performed through immersion at 25°C for 5 minutes. Afterwards, the boards were cleaned again for 25 minutes for a total of 30 minutes, and then hole mobility and conductivity were measured.

(Evaluation results)

Result①

As a result of checking the material loss rate, it was confirmed that Examples 2 and 4 according to the present invention showed material loss rates of 0.54 nm/min and 0.70 nm/min, as shown in Table 2 below. On the other hand, in the case of Comparative Example 2, the material loss rate was significantly higher than that of the example of the present invention, and it was confirmed that the material loss rate was rapid as the amount of hydrogen peroxide used increased.

(Table 2)

Result②

As a result of checking the surface roughness value of the substrate, the change in roughness value before and after cleaning was 1.5 nm or less in all cases of examples according to the present invention, as shown in Table 3 and Figure 1 below. In addition, at the same time, it was confirmed that the surface roughness value after cleaning was 5 nm or less in all cases of the examples. On the other hand, in the case of Comparative Example 1, a sharp increase in roughness value was confirmed compared to the Example.

(Table 3)

Result③

As a result of measuring the surface hole mobility and conductivity of the substrate, as shown in Table 4 below, in the case of Examples 2 and 4 according to the present invention, the hole mobility and conductivity decreased slightly as the cleaning process time increased. . However, Comparative Example 2 showed a greater decrease in changes in hole mobility and conductivity compared to the example according to the present invention.

(Table 4)

It was confirmed that when using the cleaning composition according to the present invention, damage and deformation of the substrate, such as material loss rate, surface roughness, and change in surface electrical characteristics, can be minimized compared to the prior art. Accordingly, according to the present invention, it is possible to provide a semiconductor device that can realize a stable cleaning effect and at the same time realize improved electrical characteristics without causing damage or deformation of the substrate. In addition, according to the present invention, the process is greatly simplified, so that a group III-V compound semiconductor substrate can be cleaned in a more economical manner and can be commercially advantageous.

The present invention is not limited to the above-described embodiments, and it is understood by those skilled in the art that various substitutions, modifications and changes can be made without departing from the technical spirit of the present invention. It will be clear to

Claims (12)

In a group III-V compound semiconductor substrate containing arsenic (As),
An oxygen compound selected from nitric acid and phosphoric acid and hydrogen peroxide are contained in a volume ratio of 1:0.1 to 1:1, and the mixture of the acid compound and hydrogen peroxide and water is contained in a volume ratio of 1.1:100 to 2:100,
A composition for cleaning a group III-V compound semiconductor substrate, wherein the roughness value after cleaning compared to the roughness value before cleaning of the group III-V compound semiconductor substrate satisfies the following equation 1:
[Equation 1]
RMS ₁ - RMS ₀ ≤ 1.5 nm
In Equation 1, RMS ₀ is the roughness value before cleaning, and RMS ₁ is the roughness value after cleaning. According to clause 1,
A composition for cleaning a group III-V compound semiconductor substrate that does not contain halogen anions. According to clause 1,
A composition for cleaning a group III-V compound semiconductor substrate having a pH value in the range of 0 to 4. delete According to clause 1,
The III-V compound semiconductor substrate is,
A composition for cleaning a group III-V compound semiconductor substrate selected from InAs, GaAs, InGaAs, InGaAsP, AlAs, AlGaAs, InAlAs and InAlGaAs. delete According to clause 1,
A composition for cleaning a group III-V compound semiconductor substrate, wherein the RMS ₁ is 5 nm or less. Cleaning of a III-V compound semiconductor substrate comprising the step of contacting one surface of the III-V compound semiconductor substrate with the cleaning composition of any one of claims 1 to 3, 5, and 7. method. According to clause 8,
The step is performed at 60°C or lower. A method for cleaning a group III-V compound semiconductor substrate. Forming a channel region including an epitaxial layer including a group III-V compound on a semiconductor wafer; and
A method of manufacturing a semiconductor device comprising: cleaning the semiconductor wafer by contacting it with the cleaning composition of any one of claims 1 to 3, 5, and 7. According to clause 10,
The III-V group compounds are,
A method of manufacturing a semiconductor device selected from InAs, GaAs, InGaAs, InGaAsP, AlAs, AlGaAs, InAlAs and InAlGaAs. According to claim 11,
The InGaAs is,
Method for manufacturing a semiconductor device where In _x Ga _1-x As (0<x<1).