KR102640502B1 - Semiconductor circuit and semiconductor circuit layout system - Google Patents

Abstract

A semiconductor circuit and a layout system for the semiconductor circuit are provided. The semiconductor circuit includes a latch, a feedback inverter that receives the output signal of the latch through a first node and feeds back the output signal to the latch, and inputs the output signal of the latch through the first node. It includes an output driver that receives the output signal and outputs the output signal to the outside. The output driver includes an even number of inverters, and the latch, feedback inverter, and output driver have a single active region formed integrally. It is laid out to share.

Description

Semiconductor circuit and semiconductor circuit layout system {SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR CIRCUIT LAYOUT SYSTEM}

The present invention relates to semiconductor circuits and semiconductor circuit layout systems.

Reducing the area of ICs (Integrated Circuits) such as System-on-Chip (SoC) commonly used in mobile devices is important in terms of productivity of mobile devices. Meanwhile, improving IC performance as user demands increase is another important aspect.

In order to improve the cell performance of the IC while also minimizing the area, design the layout of the semiconductor circuit (e.g., standard cell) to maintain a low area while implementing all the semiconductor elements necessary for performance improvement. is required.

The technical problem to be solved by the present invention is a semiconductor circuit that improves the performance of the output driver of a latch or flip-flop while eliminating or minimizing an increase in the layout area of the latch or flip-flop, and It provides a layout system for semiconductor circuits.

The technical problem of the present invention is not limited to the technical problem mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

A semiconductor circuit according to an embodiment of the present invention for achieving the above technical problem includes a latch, a feedback inverter that receives the output signal of the latch through a first node and feeds the output signal to the latch, and an output driver that receives the output signal of the latch through the first node and outputs the output signal to the outside. The output driver includes an even number of inverters, and the latch, the feedback inverter, and the output driver are sequentially connected. They are laid out to share a single active region that is formed integrally.

A semiconductor circuit according to another embodiment of the present invention for achieving the above technical problem includes a first PMOS transistor formed on a first gate line to which a signal from a first node is applied and providing a power supply voltage to a second node; A feedback inverter including a first NMOS transistor (MN1) formed on the first gate line to provide a ground voltage to the second node, and a signal to the first node is applied adjacent to the first gate line. A second PMOS transistor formed on the second gate line to provide a power voltage to the third node, a second NMOS transistor formed on the second gate line to provide a ground voltage to the third node, and a signal of the first node is applied, a third PMOS transistor formed on a third gate line formed adjacent to the second gate line to provide a power voltage to the third node, and a third PMOS transistor formed on the third gate line to provide a ground voltage to the third node. An output driver including a third NMOS transistor (MN3), wherein the output driver is a first node disposed between the output driver and a latch that receives the signal of the first node as a feedback input through the second node. The power supply voltage and ground voltage applied through the VDD power contact and the first VSS power contact, respectively, are shared with the latch, and are applied through the second VDD power contact and the second VSS power contact respectively disposed between the feedback inverter and the output driver. The power supply voltage and ground voltage are shared with the feedback inverter.

A semiconductor circuit according to another embodiment of the present invention for achieving the above technical problem includes a latch that receives a signal from a first node as a feedback input through a second node, and a latch to which the signal from the first node is applied adjacent to one side of the latch. Feedback including a first PMOS transistor formed on the first gate line to provide a power voltage to the second node, and a first NMOS transistor formed on the first gate line to provide a ground voltage to the second node. An inverter (feedback inverter), and a second PMOS transistor formed on a second gate line formed adjacent to the other side of the latch to which the signal of the first node is applied and providing a power voltage to the third node, on the second gate line a second NMOS transistor formed on a third gate line formed adjacent to the second gate line to which a signal from the first node is applied and provided to provide a power voltage to the third node; An output driver including 3 PMOS transistors and a third NMOS transistor formed on a third gate line to provide a ground voltage to the third node, wherein the feedback inverter is disposed between the latch and the feedback inverter. The power supply voltage and ground voltage applied through the first VDD power contact and the first VSS power contact, respectively, are shared with the latch, and the output driver has a second VDD power contact and a second VSS power contact disposed between the latch and the output driver. The power supply voltage and ground voltage applied respectively are shared with the latch.

A semiconductor circuit layout system according to an embodiment of the present invention for achieving the above technical problem uses one or more processors, storage storing one or more standard cell designs, and one or more processors to meet defined requirements. It includes a layout module that layouts one or more standard cell designs according to requirements, where the layout module receives the output signal of the latch through a latch and a first node and sends the output signal to the latch. A feedback inverter that inputs feedback, and an output driver that receives the output signal of the latch through the first node and outputs the output signal to the outside, and includes an even number of inverters, are continuously formed ( formed integrally Lay out to share a single active region.

Specific details of other embodiments are included in the detailed description and drawings.

1 is a block diagram for explaining a semiconductor circuit layout system according to an embodiment of the present invention.
2A to 2C are circuit diagrams for explaining a semiconductor circuit according to an embodiment of the present invention.
3 to 5 are layout diagrams for explaining semiconductor circuits according to various embodiments of the present invention.
6A to 6E are circuit diagrams for explaining a semiconductor circuit according to an embodiment of the present invention.
7 to 11 are layout diagrams for explaining semiconductor circuits according to various embodiments of the present invention.

Hereinafter, various embodiments of the present invention will be described with reference to the attached drawings.

1 is a block diagram for explaining a semiconductor circuit layout system according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor circuit layout system 100 according to an embodiment of the present invention can perform layout for a semiconductor circuit.

The layout system 100 includes a processor 110, memory 120, storage 130, layout module 140, input device 150, and output device 160. And the processor 110, memory 120, storage 130, layout module 140, input device 150, and output device 160 are electrically connected through the bus 170 to exchange data. there is. However, the scope of the present invention is not limited thereto, and depending on the specific purpose of implementation, the layout system 100 includes a processor 110, a memory 120, a storage 130, a layout module 140, and an input device 150. ) and some of the output device 160 may be omitted, or may be implemented to further include a device not shown in FIG. 1 (eg, a display device).

First, the layout module 140 can perform layout for the semiconductor circuit described in this specification. The layout module 140 may be implemented as software, hardware, or a combination of software and hardware. When implemented in software, the layout module 140 may include one or more instructions for performing layout for the semiconductor circuit described in this specification. Meanwhile, when implemented as hardware, the layout module 140 may include one or more programmable electronic circuits, for example, to perform layout for the semiconductor circuit described in this specification. Meanwhile, part of the layout module 140 may be implemented as software and another part may be implemented as hardware.

The layout module 140 may use the processor 110 to lay out one or more standard cell designs according to defined requirements, for example, design rules. These standard cell designs can be stored in storage 130. The layout of the semiconductor circuit performed by the layout module 140 will be described later with reference to FIGS. 3 to 5 and 7 to 11.

The processor 110 controls the overall operation of the layout system 100. In particular, the processor 110 may control or execute the layout module 140 to perform layout for the semiconductor circuit described in this specification. In some embodiments of the present invention, the processor 110 may be implemented as a CPU (Central Processing Unit), GPU (Graphic Processing Unit), etc., but the scope of the present invention is not limited thereto.

The memory 120 provides a space where the layout module 140 can store instructions, program codes, data, etc. required to perform layout for the semiconductor circuit described in this specification. In some embodiments of the present invention, the memory 120 may be implemented as a volatile memory such as Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM), but the scope of the present invention is not limited thereto and is not limited to flash memory. It may also be implemented as non-volatile memory, such as memory.

If all or part of the layout module 140 is implemented as software, the storage 130 stores the corresponding instructions or program code, or the layout module 140 performs layout for the semiconductor circuit described in this specification. Necessary data can be stored, or, for example, layout-related data such as constraints such as design rules, data on various elements used in the layout of a semiconductor circuit, and standard cell data. In some embodiments of the present invention, the storage 130 may be implemented as a solid state drive (SSD), a hard disk drive (HDD), etc., but the scope of the present invention is not limited thereto and can be read by any computer. It can be implemented as a non-transitory computer readable medium.

The layout system 100 can receive layout-related data from a user or another device implemented inside/outside the layout system 100 using the input device 150, and can receive layout-related data from the user or layout using the output device 60. Layout-related data, storage data, result data, etc. can be transmitted to other devices implemented inside/outside the system 100.

2A to 2C are circuit diagrams for explaining a semiconductor circuit according to an embodiment of the present invention.

Referring to FIG. 2A, the semiconductor circuit 1 according to an embodiment of the present invention includes an input selecting circuit (5, 10), a latch (20, 40), a feedback inverter (30, 50), and an output It may include a driver 60 and a clock inverter 70.

Note that FIG. 2A shows a scan flip-flop ( Although a scan flip-flop) is shown, the scope of the present invention is not limited thereto. In particular, the semiconductor circuit of the present invention is a simple flip-flop in which the input selection circuits 5 and 10 are omitted in FIG. 2A or a simple flip-flop in which the input selection circuits 5 and 10, a latch 20 and a feedback inverter 30 are used in FIG. 2A. It may contain a simple latch that is omitted.

The input selection circuits 5 and 10 receive data (D) or a scan input signal (SI) for a scan operation on a semiconductor circuit, and select one of them as a node (N). provided to. Specifically, the input selection circuits 5 and 10 include a scan enable inverter 5 and a multiplexer 10.

The scan enable inverter 5 receives a scan enable signal (SE), outputs an inverted scan enable signal (SEN) that inverts the scan enable signal (SE), and then outputs an inverted scan enable signal (SEN). An enable signal (SEN) is provided to the multiplexer 10.

The multiplexer 10 selects one of the data (D) and the scan input signal (SI) according to the value of the inverted scan enable signal (SEN) provided from the scan enable inverter (5) and sends it to the node (N). to provide. For this purpose, the multiplexer 10 may include tri-state inverters 11 and 13. Here, the tri-state inverter 11 inverts the scan input signal SI when the scan enable signal SE is logic high and the inverted scan enable signal SEN is logic low. and outputs it to the node (N). Meanwhile, when the scan enable signal SE is logic low and the inverted scan enable signal SEN is logic high, the tri-state inverter 13 inverts the data D and outputs it to the node N.

Meanwhile, the clock inverter 70 receives the clock signal CK and outputs an inverted clock signal CKN by inverting the clock signal CK. The clock signal CK and the inverted clock signal CKN are provided to the latches 20 and 40.

The latch 20 latches the signal of the node N based on the clock signal CK and the inverted clock signal CKN and transmits it to the node SA. For this purpose, the latch 20 may include tri-state inverters 21 and 23. Here, when the clock signal CK is logic low and the inverted clock signal CKN is logic high, the tri-state inverter 21 inverts the signal of the node N and outputs it to the node SA. In contrast, the tri-state inverter 21 may block the node SA from the node N when the clock signal CK is logic high and the inverted clock signal CKN is logic low.

Meanwhile, the feedback inverter 30 receives the output signal of the latch 20 through the node SA and inputs the output signal as feedback to the latch 20. Specifically, the feedback inverter 30 feeds back the signal output to the node SD to the latch 20 by inverting the output signal of the tri-state inverter 21 applied to the node SA. And the tri-state inverter 23 operates when the clock signal CK is logic high and the inverted clock signal CKN is logic low, that is, when the node SA is blocked from the node N, the feedback inverter 30 The signal provided from is inverted and output to the node (SA). Accordingly, the signal latched by the tri-state inverter 21 from the node N is maintained at the same value in the section where the clock signal CK is logic high.

Next, the latch 40 latches the signal of the node SA based on the clock signal CK and the inverted clock signal CKN and transmits it to the node SC. To this end, the latch 40 may include tri-state inverters 41 and 43. Here, when the clock signal CK is logic high and the inverted clock signal CKN is logic low, the tri-state inverter 41 inverts the signal at the node SA and outputs it to the node SC. In contrast, the tri-state inverter 41 may block the node SC from the node SA when the clock signal CK is logic low and the inverted clock signal CKN is logic high.

Meanwhile, the feedback inverter 50 receives the output signal of the latch 40 through the node SC and inputs the output signal as feedback to the latch 40. Specifically, the feedback inverter 50 feeds back the signal output to the node SB to the latch 40 by inverting the output signal of the tri-state inverter 41 provided to the node SC. And the tri-state inverter 43 operates when the clock signal CK is logic low and the inverted clock signal CKN is logic high, that is, when the node SC is blocked from the node SA, the feedback inverter 50 The signal provided from is inverted and output to the node (SC). Accordingly, the signal latched by the tri-state inverter 41 from the node SA is maintained at the same value in the section where the clock signal CK is logic low.

In other words, the latch 20 functions as a master latch that latches the signal of the node N at the rising edge of the clock signal CK and transmits it to the node SA, and the latch 40 serves as a master latch for the node (SA). It can act as a slave latch that latches the signal transmitted to SA) and transmits it to the node (SC).

The output driver 60 receives the output signal of the latch 40 through the node SC and outputs the output signal to the outside as data Q. What is particularly noteworthy in this embodiment is that the output driver 60 includes an even number of inverters. That is, the output driver 60 may include, for example, two inverters 61 and 63. In this way, the performance of the output driver 60 can be improved by implementing the output driver 60 to include two or more even number of inverters.

Figure 2b is a circuit diagram showing an implementation example of the feedback inverter 50. In this figure, the feedback inverter 50 is gated on the voltage level of the node SC and provides the power supply voltage VDD to the node SB, and the PMOS transistor MP1 is gated on the voltage level of the node SC. It can be implemented by connecting the NMOS transistor (MN1) that provides the ground voltage (VSS) to the node (SB).

Next, FIG. 2C is a circuit diagram showing an example of an implementation of the output driver 60 including two inverters. In this figure, the output driver 60 is gated at the voltage level of the node (SC) and the PMOS transistors (MP2, MP3) that provide the power supply voltage (VDD) to the node (Q), and the output driver 60 is gated at the voltage level of the node (SC). It can be implemented by connecting NMOS transistors (MN2, MN3) that are gated and provide a ground voltage (VSS) to the node (Q).

Below, based on the implementation examples of FIGS. 2B and 2C, a layout method that minimizes the increase in the area of the flip-flop or latch of the semiconductor circuit 1 while seeking to improve the performance of the output driver 60 is described in FIGS. 3 to 3. This will be explained with reference to FIG. 5 .

3 to 5 are layout diagrams for explaining semiconductor circuits according to various embodiments of the present invention.

Referring to FIG. 3, the layout LO1 according to an embodiment of the present invention may include a latch 40, a feedback inverter 50, and an output driver 60 of the semiconductor circuit 1. In this embodiment, the latch 40, the feedback inverter 50, and the output driver 60 may form a simple latch, and include a master latch 20 that delivers data D to the input of the latch 40, and Together they can form a simple flip-flop.

In the layout LO1 according to this embodiment, the latch 40 may be arranged adjacent to one side of the output driver 60, and the feedback inverter 50 may be arranged adjacent to the other side of the output driver 60. In FIG. 3, the latch 40 is shown to be placed adjacent to the left side of the output driver 60, and the feedback inverter 50 is shown to be placed adjacent to the right side of the output driver 60. However, unlike this, the latch 40 is shown to be adjacent to the left side of the output driver 60. It is possible to arrange it adjacent to the right side of the output driver 60, and it is also possible for the feedback inverter 50 to be arranged adjacent to the left side of the output driver 60.

Specifically, the latch 40 may be laid out in any form to latch a signal from the node SA and transmit it to the node SC. Therefore, in this drawing, the specific layout configuration of the latch 40 is omitted, and only the output terminal is provided to the node SC.

The feedback inverter 50 includes a PMOS transistor (MP1) and an NMOS transistor (MN1). The PMOS transistor MP1 is formed on the gate line GL3 to which the signal from the node SC is applied and provides the power supply voltage VDD to the node SB. And the NMOS transistor MN1 is formed on the gate line GL3 to provide the ground voltage VSS to the node SB.

Here, the metal 510 connects the node SC and the gate line GL3, and the metal 512 connects the output of the PMOS transistor MP1 and the output of the NMOS transistor MN1.

The output driver 60 includes PMOS transistors (MP2, MP3) and NMOS transistors (MN2, MN3). The PMOS transistor MP2 is formed on the gate line GL2 formed adjacent to the gate line GL3 to which the signal from the node SC is applied, and provides the power supply voltage VDD to the node Q. And the NMOS transistor MN2 is formed on the gate line GL2 to provide the ground voltage VSS to the third node Q. Meanwhile, the PMOS transistor MP3 is formed on the gate line GL1 formed adjacent to the gate line GL2 to which the signal from the node SC is applied, and provides the power supply voltage VDD to the node Q. And the NMOS transistor MN3 is formed on the gate line GL1 to provide the ground voltage VSS to the node Q.

Here, the metal 610 connects the node (SC) and the gate line (GL2) and gate line (GL1), and the metal 612 connects the outputs of the PMOS transistors (MP2 and MP3) and the outputs of the NMOS transistors (MN2 and MN3). Connect.

Of note in this embodiment is that the latch 40, feedback inverter 50, and output driver 60 are laid out to share a single formed integrally active region (ACT1, ACT2). am. That is, there is no isolation such as a dummy gate line or diffusion break between the latch 40, the feedback inverter 50, and the output driver 60, so the latch 40 ), the active areas (ACT1, ACT2) of the feedback inverter 50 and the output driver 60 are connected without electrical disconnection.

Another thing to note is that the latch 40, feedback inverter 50, and output driver 60 share a power contact.

Specifically, the layout LO1 according to this embodiment includes a VDD power contact (P1) and a VSS power contact (P2) disposed between the latch 40 and the output driver 60. And the latch 40 and the output driver 60 share the power supply voltage (VDD) and ground voltage (VSS) applied through the VDD power contact (P1) and the VSS power contact (P2), respectively.

Additionally, the layout LO1 according to this embodiment includes a VDD power contact (P3) and a VSS power contact (P4) disposed between the output driver 60 and the feedback inverter 50. And the output driver 60 and the feedback inverter 50 share the power supply voltage (VDD) and ground voltage (VSS) applied through the VDD power contact (P3) and the VSS power contact (P4), respectively.

Generally, when the number of inverters of the output driver 60 is increased from 1 to 2, the area increases by 1 pitch, but in the case of the layout LO1 according to this embodiment, the latch 40 and the feedback inverter 50 ) and the output driver 60, so that an isolation area is not created, and in the case of a process using a double diffusion break (DDB) generated across the gate line GL4, the effect of reducing the pitch by 2 occurs. That is, even though the area of the output driver 60 increases by 1 pitch, the overall area of the latch 40, feedback inverter 50, and output driver 60 can be reduced by 1 pitch.

Referring to Figure 4, this embodiment is different from the embodiment of Figure 3. It indicates the layout (LO2) used in the process of creating a single diffusion break (SDB) in the gate line (GL4).

Accordingly, in the case of the layout LO2 according to this embodiment, an isolation area is not created between the latch 40, the feedback inverter 50, and the output driver 60, so that the SDB generated across the gate line GL4 In the case of a process using a single diffusion break, the pitch is reduced by 1. That is, even though the area of the output driver 60 increases by 1 pitch, the overall area of the latch 40, the feedback inverter 50, and the output driver 60 is maintained without increase or decrease.

Referring to FIG. 5, the layout LO3 according to an embodiment of the present invention represents a 1-bit flip-flop.

In the layout LO3 according to this embodiment, the scan enable inverter 5, multiplexer 10, latch 20, feedback inverter 30, and clock inverter 70 may be sequentially arranged. Subsequently, the latch 40, output driver 60, and feedback inverter 50 may be sequentially arranged.

That is, the latch 40 may be placed adjacent to one side of the output driver 60, and the feedback inverter 50 may be placed adjacent to the other side of the output driver 60. In Figure 5, the latch 40 is shown to be placed adjacent to the left side of the output driver 60, and the feedback inverter 50 is shown to be placed adjacent to the right side of the output driver 60. However, unlike this, the latch 40 is shown to be adjacent to the left side of the output driver 60. It is possible to arrange it adjacent to the right side of the output driver 60, and it is also possible for the feedback inverter 50 to be arranged adjacent to the left side of the output driver 60.

According to this arrangement, as described above, it is possible to improve the performance of the output driver 60 while preventing or minimizing an increase in the layout area of the flip-flop.

6A to 6E are circuit diagrams for explaining a semiconductor circuit according to an embodiment of the present invention.

Referring to FIG. 6A, the semiconductor circuit 2 according to an embodiment of the present invention includes an input selection circuit (5, 10a, 10b), a latch (20a, 20b, 40a, 40b), and a feedback inverter (30a, 30b, 50a). , 50b), output drivers 60a, 60b, and clock inverter 70.

Note that Figure 6a shows input select circuits (5, 10a, 10b), latches (20a, 20b, 40a, 40b), feedback inverters (30a, 30b, 50a, 50b), output drivers (60a, 60b), and clock Although a multibit scan flip-flop including all the inverters 70 is shown, the scope of the present invention is not limited thereto. In particular, the semiconductor circuit of the present invention is a simple multi-bit flip-flop with the input selection circuits 5, 10a, and 10b omitted in FIG. 6A, or a simple multi-bit flip-flop with the input selection circuits 5, 10a, and 10b and latches 20a and 20b in FIG. 6A. ) and a simple multi-bit latch in which the feedback inverters 30a and 30b are omitted.

The input selection circuits 5, 10a, and 10b receive data (D0, D1) or scan input signals (SI0, SI1) for a scan operation for a semiconductor circuit, and select one of them to the node (N0, N1). to provide. Specifically, the input selection circuits 5, 10a, 10b include a scan enable inverter 5 and multiplexers 10a, 10b.

The scan enable inverter (5) receives the scan enable signal (SE), outputs an inverted scan enable signal (SEN) by inverting the scan enable signal (SE), and then outputs an inverted scan enable signal (SEN). is provided to the multiplexers 10a and 10b.

The multiplexer 10a selects one of the first bit data D0 and the first scan input signal SI0 according to the value of the inverted scan enable signal SEN provided from the scan enable inverter 5. Provided to node (N0). And the multiplexer 10b selects one of the second bit data D1 and the second scan input signal SI1 according to the value of the inverted scan enable signal SEN provided from the scan enable inverter 5. and provides it to the node (N1). Here, the tri-state inverters 11a, 11b, 13a, and 13b operate in a similar manner to the tri-state inverters 11 and 13 described in FIG. 2A, so redundant description will be omitted.

Meanwhile, the clock inverter 70 receives the clock signal CK and outputs an inverted clock signal CKN by inverting the clock signal CK. The clock signal CK and the inverted clock signal CKN are provided to the latches 20a, 20b, 40a, and 40b.

The latch 20a latches the signal of the node N0 based on the clock signal CK and the inverted clock signal CKN and transmits it to the node SA0. Meanwhile, the feedback inverter 30a receives the output signal of the latch 20a through the node SA0 and inputs the output signal as feedback to the latch 20a. And the latch 20b latches the signal of the node N1 based on the clock signal CK and the inverted clock signal CKN and transmits it to the node SA1. Meanwhile, the feedback inverter 30b receives the output signal of the latch 20b through the node SA1 and inputs the output signal as feedback to the latch 20b. Here, the tri-state inverters 21a, 21b, 23a, and 23b operate in a similar manner to the tri-state inverters 21 and 23 described in FIG. 2A, so redundant description will be omitted.

Next, the latch 40a latches the signal of the node SA0 based on the clock signal CK and the inverted clock signal CKN and transmits it to the node SC0. Meanwhile, the feedback inverter 50a receives the output signal of the latch 40a through the node SC0 and feedback inputs the output signal to the latch 40a. And the latch 40b latches the signal of the node SA1 based on the clock signal CK and the inverted clock signal CKN and transmits it to the node SC1. Meanwhile, the feedback inverter 50b receives the output signal of the latch 40b through the node SC1 and inputs the output signal as feedback to the latch 40b. Here, the tri-state inverters 41a, 41b, 43a, and 43b operate in a similar manner to the tri-state inverters 41 and 43 described in FIG. 2A, so redundant description will be omitted.

That is, the latches 20a and 20b serve as master latches that latch the signals of the nodes N0 and N1 at the rising edge of the clock signal CK and transmit them to the nodes SA0 and SA1, respectively, and the latch 40a , 40b) may function as a slave latch that latches the signals transmitted to the nodes SA0 and SA1 and transmits them to the nodes SC0 and SC1, respectively.

The output driver 60a receives the output signal of the latch 40a through the node SC0 and outputs the output signal to the outside as data Q0. What is particularly noteworthy in this embodiment is that the output driver 60a includes an even number of inverters. That is, the output driver 60a may include, for example, two inverters 61a and 63a. In this way, the performance of the output driver 60a can be improved by implementing the output driver 60a to include two or more even number of inverters.

And the output driver 60b receives the output signal of the latch 40b through the node SC1 and outputs the output signal to the outside as data Q1. What is particularly noteworthy in this embodiment is that the output driver 60b includes an even number of inverters. That is, the output driver 60b may include, for example, two inverters 61b and 63b. In this way, the performance of the output driver 60b can be improved by implementing the output driver 60b to include two or more even number of inverters.

Figure 6b is a circuit diagram showing an example of implementation of the feedback inverter 50a. In this figure, the feedback inverter 50a is gated on the voltage level of the node SC0 and the PMOS transistor MP1 that provides the power supply voltage VDD to the node SB0, and the feedback inverter 50a is gated on the voltage level of the node SC0. It can be implemented by connecting the NMOS transistor (MN1) that provides the ground voltage (VSS) to the node (SB0).

Next, FIG. 6C is a circuit diagram showing an example of an implementation of the output driver 60a including two inverters. In this figure, the output driver 60a is gated at the voltage level of the node SC0, and the PMOS transistors MP2 and MP3 provide the power supply voltage VDD to the node Q0, and the output driver 60a is gated at the voltage level of the node SC0. It can be implemented by connecting NMOS transistors (MN2, MN3) that are gated and provide a ground voltage (VSS) to the node (Q0).

Next, FIG. 6D is a circuit diagram showing an example of implementation of the feedback inverter 50b. In this figure, the feedback inverter 50b is gated on the voltage level of the node SC1 and the PMOS transistor MP4 provides the power supply voltage VDD to the node SB1, and the feedback inverter 50b is gated on the voltage level of the node SC1. It can be implemented by connecting the NMOS transistor (MN4) that provides the ground voltage (VSS) to the node (SB1).

Next, FIG. 6C is a circuit diagram showing an example of an implementation of the output driver 60b including two inverters. In this figure, the output driver 60b is gated at the voltage level of the node SC1, and the PMOS transistors MP5 and MP6 provide the power supply voltage VDD to the node Q1, and the output driver 60b is gated at the voltage level of the node SC1. It can be implemented by connecting NMOS transistors (MN5, MN6) that are gated and provide a ground voltage (VSS) to the node (Q1).

Hereinafter, based on the implementation examples of FIGS. 6B to 6E, a layout method that minimizes the increase in the area of the flip-flop or latch of the semiconductor circuit 2 while seeking to improve the performance of the output drivers 60a and 60b will be described. This will be explained with reference to Figures 7 to 11.

7 to 11 are layout diagrams for explaining semiconductor circuits according to various embodiments of the present invention.

Referring to FIG. 7, the layout LO4 according to an embodiment of the present invention may include latches 40a and 40b, feedback inverters 50a and 50b, and output drivers 60a and 60b of the semiconductor circuit 2. You can. In this embodiment, the latches 40a and 40b, the feedback inverters 50a and 50b, and the output drivers 60a and 60b may form a simple multi-bit latch, and data D0 is input to the inputs of the latches 40a and 40b. , D1) can also form a simple multi-bit flip-flop with the master latches 20a and 20b.

In the layout LO4 according to this embodiment, the latches 40a and 40b are disposed adjacent to one side of the output drivers 60a and 60b, and the feedback inverters 50a and 50b are located on the other side of the output drivers 60a and 60b. It can be placed adjacent to . In FIG. 7, the latches 40a and 40b are shown to be adjacent to the left sides of the output drivers 60a and 60b, and the feedback inverters 50a and 50b are shown to be adjacent to the right sides of the output drivers 60a and 60b. , Alternatively, it is possible for the latches 40a and 40b to be arranged adjacent to the right sides of the output drivers 60a and 60b, and the feedback inverters 50a and 50b to be arranged adjacent to the left sides of the output drivers 60a and 60b. .

Specifically, the latches 40a and 40b may be laid out in any form to latch signals from the nodes SA0 and SA1 and transmit them to the nodes SC0 and SC1. Therefore, in this drawing, the specific layout configuration of the latches 40a and 40b is omitted, and only the output terminals are provided to the nodes SC0 and SC1.

The feedback inverter 50a includes a PMOS transistor (MP1) and an NMOS transistor (MN1). The PMOS transistor MP1 is formed on the gate line GL3 to which the signal from the node SC0 is applied and provides the power supply voltage VDD1 to the node SB0. And the NMOS transistor MN1 is formed on the gate line GL3 to provide the ground voltage VSS to the node SB0.

Here, the metal 510 connects the node SC0 and the gate line GL3, and the metal 512 connects the output of the PMOS transistor MP1 and the output of the NMOS transistor MN1.

And the feedback inverter 50b includes an NMOS transistor (MN4) and a PMOS transistor (MP4). The NMOS transistor MN4 is formed on the gate line GL7 to which the signal from the node SC1 is applied and provides the ground voltage VSS to the node SB1. And the PMOS transistor MP4 is formed on the gate line GL7 to provide the power supply voltage VDD2 to the node SB1.

Here, the metal 514 connects the node SC1 and the gate line GL7, and the metal 516 connects the output of the NMOS transistor MN1 and the output of the PMOS transistor MP1.

The output driver 60a includes PMOS transistors (MP2, MP3) and NMOS transistors (MN2, MN3). The PMOS transistor MP2 is formed on the gate line GL2 formed adjacent to the gate line GL3 to which the signal from the node SC0 is applied, and provides the power supply voltage VDD1 to the node Q0. And the NMOS transistor MN2 is formed on the gate line GL2 to provide the ground voltage VSS to the node Q. Meanwhile, the PMOS transistor MP3 is formed on the gate line GL1 formed adjacent to the gate line GL2 to which the signal from the node SC0 is applied, and provides the power supply voltage VDD1 to the node Q0. And the NMOS transistor MN3 is formed on the gate line GL1 to provide the ground voltage VSS to the node Q0.

Here, the metal 610 connects the node (SC0), the gate line (GL2), and the gate line (GL1), and the metal 612 connects the outputs of the PMOS transistors (MP2, MP3) and the outputs of the NMOS transistors (MN2, MN3). Connect.

And the output driver 60b includes NMOS transistors (MN5, MN6) and PMOS transistors (MP5, MP6). The NMOS transistor MN5 receives the signal from the node SC1 and is formed on the gate line GL6 formed adjacent to the gate line GL7 to provide the ground voltage VSS to the node Q1. And the PMOS transistor MP5 is formed on the gate line GL6 to provide the power supply voltage VDD2 to the node Q1. Meanwhile, the NMOS transistor MN6 receives the signal from the node SC1 and is formed on the gate line GL5 formed adjacent to the gate line GL6 to provide the ground voltage VSS to the node Q1. And the PMOS transistor MP6 is formed on the gate line GL5 to provide the power supply voltage VDD2 to the node Q1.

Here, the metal 614 connects the node (SC1), the gate line (GL6), and the gate line (GL5), and the metal 616 connects the outputs of the NMOS transistors (MN5, MN6) and the outputs of the PMOS transistors (MP5, MP6). Connect.

What is noteworthy in this embodiment is that the latch 40a, the feedback inverter 50a, and the output driver 60a share a single continuously formed active area (ACT11, ACT12), and the latch 40b, the feedback inverter 50b and that the output driver 60b is laid out to share a single continuously formed active area (ACT21, ACT22).

Another thing to note is that the latch 40a, feedback inverter 50a, and output driver 60a share a power contact. That is, the layout LO4 according to this embodiment includes the VDD power contact P1 and the VSS power contact P2 disposed between the latch 40a and the output driver 60a. And the latch 40a and the output driver 60a share the power supply voltage (VDD1) and ground voltage (VSS) applied through the VDD power contact (P1) and the VSS power contact (P2), respectively. Additionally, the layout LO4 according to this embodiment includes a VDD power contact (P3) and a VSS power contact (P4) disposed between the output driver 60a and the feedback inverter 50a. And the output driver 60a and the feedback inverter 50a share the power supply voltage (VDD1) and ground voltage (VSS) applied through the VDD power contact (P3) and the VSS power contact (P4), respectively.

And the latch 40b, feedback inverter 50b, and output driver 60b also share the power contact. That is, the layout LO4 according to this embodiment includes the VSS power contact (P2) and the VDD power contact (P5) disposed between the latch 40b and the output driver 60b. And the latch 40b and the output driver 60b share the ground voltage (VSS) and power voltage (VDD2) applied through the VSS power contact (P2) and the VDD power contact (P5), respectively. Additionally, the layout LO4 according to this embodiment includes a VSS power contact (P4) and a VDD power contact (P6) disposed between the output driver 60b and the feedback inverter 50b. And the output driver 60b and the feedback inverter 50b share the ground voltage (VSS) and power voltage (VDD2) applied through the VSS power contact (P4) and the VDD power contact (P6), respectively.

In the case of the layout (LO4) according to this embodiment, an isolation area is not created between the latches (40a, 40b), the feedback inverters (50a, 50b), and the output drivers (60a, 60b), so that the gate lines (GL4, GL8) In the case of a process using DDB generated over 2, the effect of reducing the pitch occurs. In other words, even though the area of the output drivers (60a, 60b) increases by 1 pitch, the area of the latches (40a, 40b), feedback inverters (50a, 50b), and output drivers (60a, 60b) as a whole decreases by 1 pitch. You can.

Referring to FIG. 8, this embodiment is different from the embodiment of FIG. 7. It indicates the layout (LO5) used in the process of generating SDB1 and SDB2 on the gate lines (GL4 and GL8), respectively.

Accordingly, in the case of the layout LO5 according to this embodiment, an isolation area is not created between the latches 40a and 40b, the feedback inverters 50a and 50b, and the output drivers 60a and 60b, so that the gate line GL4 , In the case of a process using SDB1 and SDB2 generated over GL8), the effect of reducing the pitch by 1 occurs. In other words, even though the area of the output drivers (60a, 60b) increases by 1 pitch, the overall area of the latches (40a, 40b), feedback inverters (50a, 50b), and output drivers (60a, 60b) remains the same without increasing or decreasing. You can get it.

Referring to FIG. 9, the layout LO6 according to an embodiment of the present invention is different from the layout LO4 of FIG. 7 in that the feedback inverters 50a and 50b are adjacent to one side of the latches 40a and 40b. The point is that the output drivers 60a and 60b can be arranged adjacent to the other side of the latches 40a and 40b. In FIG. 9, the feedback inverters 50a and 50b are shown to be adjacent to the left sides of the latches 40a and 40b, and the output drivers 60a and 60b are shown to be adjacent to the right sides of the latches 40a and 40b. Alternatively, the feedback inverters 50a and 50b may be arranged adjacent to the right sides of the latches 40a and 40b, and the output drivers 60a and 60b may be arranged adjacent to the left sides of the latches 40a and 40b.

The feedback inverter 50a includes a PMOS transistor (MP1) and an NMOS transistor (MN1). The PMOS transistor MP1 is formed on the gate line GL1 formed adjacent to one side of the latch 40 to which the signal from the node SC0 is applied, and provides the power supply voltage VDD1 to the node SB0. And the NMOS transistor MN1 is formed on the gate line GL1 to provide the ground voltage VSS to the node SB0.

Here, the metal 510 connects the node SC0 and the gate line GL1, and the metal 512 connects the output of the PMOS transistor MP1 and the output of the NMOS transistor MN1.

And the feedback inverter 50b includes an NMOS transistor (MN4) and a PMOS transistor (MP4). The NMOS transistor MN4 receives the signal from the node SC1 and is formed on the gate line GL5 formed adjacent to one side of the latch 40b to provide the ground voltage VSS to the node SB1. And the PMOS transistor MP4 is formed on the gate line GL5 to provide the power supply voltage VDD2 to the node SB1.

Here, the metal 514 connects the node SC1 and the gate line GL5, and the metal 516 connects the output of the NMOS transistor MN4 and the output of the PMOS transistor MP4.

The output driver 60a includes PMOS transistors (MP2, MP3) and NMOS transistors (MN2, MN3). The PMOS transistor MP2 is formed on the gate line GL2 formed adjacent to the other side of the latch 40 to which the signal from the node SC0 is applied, and provides the power supply voltage VDD1 to the node Q0. Additionally, the NMOS transistor MN2 is formed on the gate line GL2 to provide a ground voltage VSS to the node Q0. Meanwhile, the PMOS transistor MP3 is formed on the gate line GL3 formed adjacent to the gate line GL2 to which the signal from the node SC0 is applied, and provides the power supply voltage VDD1 to the node Q0. And the NMOS transistor MN3 is formed on the gate line GL3 to provide the ground voltage VSS to the node Q0.

Here, the metal 610 connects the node (SC0) and the gate line (GL2) and gate line (GL3), and the metal 612 connects the outputs of the PMOS transistors (MP2 and MP3) and the outputs of the NMOS transistors (MN2 and MN3). Connect.

And the output driver 60b includes NMOS transistors (MN5, MN6) and PMOS transistors (MP5, MP6). The NMOS transistor MN5 receives the signal from the node SC1 and is formed on the gate line GL6 formed adjacent to the latch 40b to provide the ground voltage VSS to the node Q1. And the PMOS transistor MP5 is formed on the gate line GL6 to provide the power supply voltage VDD2 to the node Q1. Meanwhile, the NMOS transistor MN6 receives the signal from the node SC1 and is formed on the gate line GL7 formed adjacent to the gate line GL6 to provide the ground voltage VSS to the node Q1. And the PMOS transistor MP6 is formed on the gate line GL7 to provide the power supply voltage VDD2 to the node Q1.

Here, the metal 614 connects the node (SC1), the gate line (GL6), and the gate line (GL7), and the metal 616 connects the outputs of the NMOS transistors (MN5, MN6) and the outputs of the PMOS transistors (MP5, MP6). Connect.

What is noteworthy in this embodiment is that the latch 40a, the feedback inverter 50a, and the output driver 60a share a single continuously formed active area (ACT11, ACT12), and the latch 40b, the feedback inverter 50b and that the output driver 60b is laid out to share a single continuously formed active area (ACT21, ACT22).

Another thing to note is that the latch 40a, feedback inverter 50a, and output driver 60a share a power contact. That is, the layout LO6 according to this embodiment includes the VDD power contact P1 and the VSS power contact P2 disposed between the feedback inverter 50a and the latch 40a. And the feedback inverter 50a and the latch 40a share the power supply voltage (VDD1) and the ground voltage (VSS) applied through the VDD power contact (P1) and the VSS power contact (P2), respectively. Additionally, the layout LO6 according to this embodiment includes a VDD power contact (P3) and a VSS power contact (P4) disposed between the latch 40a and the output driver 60a. And the latch 40a and the output driver 60a share the power supply voltage (VDD1) and ground voltage (VSS) applied through the VDD power contact (P3) and the VSS power contact (P4), respectively.

And the latch 40b, feedback inverter 50b, and output driver 60b also share the power contact. That is, the layout LO6 according to this embodiment includes the VSS power contact (P2) and the VDD power contact (P5) disposed between the feedback inverter 50b and the latch 40b. And the feedback inverter 50b and the latch 40b share the ground voltage (VSS) and power voltage (VDD2) applied through the VSS power contact (P2) and the VDD power contact (P5), respectively. Additionally, the layout LO6 according to this embodiment includes a VSS power contact (P4) and a VDD power contact (P6) disposed between the latch 40b and the output driver 60b. And the latch 40b and the output driver 60b share the ground voltage (VSS) and power voltage (VDD2) applied through the VSS power contact (P4) and the VDD power contact (P6), respectively.

In the case of the layout (LO6) according to this embodiment, an isolation area is not created between the latches (40a, 40b), the feedback inverters (50a, 50b), and the output drivers (60a, 60b), so that the gate lines (GL4, GL8) In the case of a process using DDB generated over 2, the effect of reducing the pitch occurs. In other words, even though the area of the output drivers (60a, 60b) increases by 1 pitch, the area of the latches (40a, 40b), feedback inverters (50a, 50b), and output drivers (60a, 60b) as a whole decreases by 1 pitch. You can.

Referring to FIG. 10, this embodiment is different from the embodiment of FIG. 8. It indicates the layout (LO7) used in the process of generating SDB1 and SDB2 on the gate lines (GL4 and GL8), respectively.

Accordingly, in the case of the layout LO7 according to this embodiment, an isolation area is not created between the latches 40a and 40b, the feedback inverters 50a and 50b, and the output drivers 60a and 60b, so that the gate line GL4 , In the case of a process using SDB1 and SDB2 generated over GL8), the effect of reducing the pitch by 1 occurs. In other words, even though the area of the output drivers (60a, 60b) increases by 1 pitch, the overall area of the latches (40a, 40b), feedback inverters (50a, 50b), and output drivers (60a, 60b) remains the same without increasing or decreasing. You can get it.

Referring to FIG. 11, the layout LO8 according to an embodiment of the present invention represents a 2-bit flip-flop.

In the layout LO8 according to this embodiment, the first row includes a scan enable inverter 5, a multiplexer 10a, a latch 20a, a feedback inverter 30a, a latch 40a, an output driver 60a, and Feedback inverters 50a may be arranged sequentially. Subsequently, in the second row, the clock inverter 70, multiplexer 10b, latch 20b, feedback inverter 30b, latch 40b, output driver 60b, and feedback inverter 50b may be sequentially arranged. .

That is, the latches 40a and 40b may be arranged adjacent to one side of the output drivers 60a and 60b, and the feedback inverters 50a and 50b may be arranged adjacent to the other side of the output drivers 60a and 60b. In FIG. 11, the latches 40a and 40b are shown to be adjacent to the left sides of the output drivers 60a and 60b, and the feedback inverters 50a and 50b are shown to be adjacent to the right sides of the output drivers 60a and 60b. , Alternatively, it is possible for the latches 40a and 40b to be arranged adjacent to the right sides of the output drivers 60a and 60b, and the feedback inverters 50a and 50b to be arranged adjacent to the left sides of the output drivers 60a and 60b. .

Furthermore, the feedback inverters 50a and 50b may be arranged adjacent to one side of the latches 40a and 40b, and the output drivers 60a and 60b may be arranged adjacent to the other side of the latches 40a and 40b.

According to this arrangement, as described above, it is possible to improve the performance of the output driver 60 while preventing or minimizing an increase in the layout area of the flip-flop.

Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and can be manufactured in various different forms by those skilled in the art. It will be understood by those who understand that the present invention can be implemented in other specific forms without changing its technical spirit or essential features. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

1, 2: Semiconductor circuit 5: Scan enable inverter
10, 10a, 10b: multiplexer 20, 20a, 20b, 40, 40a, 40b: latch
30, 30a, 30b, 50, 50a, 50b: Feedback inverter
60, 60a, 60b: Output driver 70: Clock inverter
100: layout system 110: processor
120: memory 130: storage
140: Layout module 150: Input device
160: output device

Claims (20)

latch;
a feedback inverter that receives the output signal of the latch through a first node and inputs the output signal as feedback to the latch; and
An output driver that receives the output signal of the latch through the first node and outputs the output signal to the outside,
The output driver includes an even number of inverters,
A semiconductor circuit wherein the latch, the feedback inverter, and the output driver are laid out so that they share a single integrally formed active region. According to paragraph 1,
In the layout of the semiconductor circuit, the latch is disposed adjacent to one side of the output driver, and the feedback inverter is disposed adjacent to the other side of the output driver. According to paragraph 2,
The layout of the semiconductor circuit further includes a first VDD power contact and a first VSS power contact disposed between the latch and the output driver,
The latch and the output driver share a power voltage and a ground voltage respectively applied through the first VDD power contact and the first VSS power contact. According to paragraph 2,
The layout of the semiconductor circuit further includes a second VDD power contact and a second VSS power contact disposed between the output driver and the feedback inverter,
The output driver and the feedback inverter share a power voltage and a ground voltage respectively applied through the second VDD power contact and the second VSS power contact. According to paragraph 1,
In the layout of the semiconductor circuit, the feedback inverter is disposed adjacent to one side of the latch, and the output driver is disposed adjacent to the other side of the latch. According to clause 5,
The layout of the semiconductor circuit further includes a first VDD power contact and a first VSS power contact disposed between the feedback inverter and the latch,
The feedback inverter and the latch share a power voltage and a ground voltage respectively applied through the first VDD power contact and the first VSS power contact. According to clause 5,
The layout of the semiconductor circuit further includes a second VDD power contact and a second VSS power contact disposed between the latch and the output driver,
The latch and the output driver share a power voltage and a ground voltage respectively applied through the second VDD power contact and the second VSS power contact. According to paragraph 1,
The latch includes a first latch operating on first bit data and a second latch operating on second bit data,
The feedback inverter includes a first feedback inverter operating on the first bit data and a second feedback inverter operating on the second bit data,
The output driver includes a first output driver operating on the first bit data and a second output driver operating on the second bit data,
The single active area includes a first single active area shared by the first latch, the first feedback inverter, and the first output driver, and a first single active area shared by the second latch, the second feedback inverter, and the second output driver. comprising a second single active region,
The first latch, the first feedback inverter, the first output driver, the second latch, the second feedback inverter, and the second output driver form a multibit latch. According to clause 8,
Further comprising a first master latch transmitting the first bit data to the input of the first latch and a second master latch transmitting the second bit data to the input of the second latch,
The first master latch, the first latch, the first feedback inverter, the first output driver, the second master latch, the second latch, the second feedback inverter, and the second output driver are multi-bit flip-flops. A semiconductor circuit that forms a (multibit flip-flop). a first PMOS transistor formed on a first gate line to which a signal from the first node is applied and providing a power supply voltage to the second node;
a feedback inverter including a first NMOS transistor (MN1) formed on the first gate line and providing a ground voltage to the second node; and
A second PMOS transistor to which a signal from the first node is applied and formed on a second gate line formed adjacent to the first gate line to provide a power voltage to a third node,
A second NMOS transistor formed on the second gate line to provide a ground voltage to the third node,
A third PMOS transistor to which the signal from the first node is applied and formed on a third gate line formed adjacent to the second gate line to provide a power supply voltage to the third node; and
An output driver including a third NMOS transistor (MN3) formed on the third gate line to provide a ground voltage to the third node,
The output driver is,
The power voltage and the ground voltage respectively applied through the first VDD power contact and the first VSS power contact disposed between the latch that receives the signal of the first node as a feedback input through the second node and the output driver. Share with Latch,
A semiconductor circuit that shares with the feedback inverter a power voltage and a ground voltage respectively applied through a second VDD power contact and a second VSS power contact disposed between the feedback inverter and the output driver. According to clause 10,
A semiconductor circuit wherein the latch, the feedback inverter, and the output driver are laid out so that they share a single integrally formed active region. According to clause 11,
Further comprising a master latch that transmits data to the input of the latch,
A semiconductor circuit in which the master latch, the latch, the feedback inverter, and the output driver form a flip-flop. According to clause 11,
The latch includes a first latch operating on first bit data and a second latch operating on second bit data,
The feedback inverter includes a first feedback inverter operating on the first bit data and a second feedback inverter operating on the second bit data,
The output driver includes a first output driver operating on the first bit data and a second output driver operating on the second bit data,
The second latch receives the signal of the fourth node as a feedback input through the fifth node,
The first feedback inverter includes the first PMOS transistor and the first NMOS transistor,
The second feedback inverter,
a fourth NMOS transistor formed on a fourth gate line to which the signal of the fourth node is applied and providing a ground voltage to the fifth node;
A fourth PMOS transistor formed on the fourth gate line to provide a power supply voltage to the fifth node,
The first output driver includes the second PMOS transistor, the second NMOS transistor, the third PMOS transistor, and the third NMOS transistor,
The second output driver is,
A fifth NMOS transistor to which a signal from the fourth node is applied and formed on a fifth gate line formed adjacent to the fourth gate line to provide a ground voltage to the sixth node,
A fifth PMOS transistor formed on the fifth gate line to provide a power supply voltage to the sixth node,
A sixth NMOS transistor to which a signal from the fourth node is applied and formed on a sixth gate line formed adjacent to the fifth gate line to provide a ground voltage to the sixth node; and
It includes a sixth PMOS transistor formed on the sixth gate line to provide a power supply voltage to the sixth node,
The first latch, the first feedback inverter, the first output driver, the second latch, the second feedback inverter, and the second output driver form a multibit latch. According to clause 13,
Further comprising a first master latch transmitting the first bit data to the input of the first latch and a second master latch transmitting the second bit data to the input of the second latch,
The first master latch, the first latch, the first feedback inverter, the first output driver, the second master latch, the second latch, the second feedback inverter, and the second output driver are multi-bit flip-flops. A semiconductor circuit that forms a (multibit flip-flop). a latch that receives a signal from a first node as a feedback input through a second node;
A first PMOS transistor to which a signal from the first node is applied and formed on a first gate line formed adjacent to one side of the latch to provide a power supply voltage to the second node;
a feedback inverter including a first NMOS transistor formed on the first gate line and providing a ground voltage to the second node; and
A second PMOS transistor to which the signal from the first node is applied and formed on a second gate line formed adjacent to the other side of the latch to provide a power supply voltage to a third node,
A second NMOS transistor formed on the second gate line to provide a ground voltage to the third node,
A third PMOS transistor to which the signal from the first node is applied and formed on a third gate line formed adjacent to the second gate line to provide a power supply voltage to the third node; and
An output driver including a third NMOS transistor formed on the third gate line to provide a ground voltage to the third node,
The feedback inverter shares with the latch a power voltage and a ground voltage respectively applied through a first VDD power contact and a first VSS power contact disposed between the latch and the feedback inverter,
The output driver is a semiconductor circuit that shares with the latch a power voltage and a ground voltage respectively applied through a second VDD power contact and a second VSS power contact disposed between the latch and the output driver. According to clause 15,
A semiconductor circuit wherein the latch, the feedback inverter, and the output driver are laid out so that they share a single integrally formed active region. According to clause 16,
Further comprising a master latch that transmits data to the input of the latch,
A semiconductor circuit in which the master latch, the latch, the feedback inverter, and the output driver form a flip-flop. According to clause 16,
The latch includes a first latch operating on first bit data and a second latch operating on second bit data,
The feedback inverter includes a first feedback inverter operating on the first bit data and a second feedback inverter operating on the second bit data,
The output driver includes a first output driver operating on the first bit data and a second output driver operating on the second bit data,
The first feedback inverter includes the first PMOS transistor and the first NMOS transistor,
The second feedback inverter,
A fourth NMOS transistor to which a signal from a fourth node is applied and formed on a fourth gate line formed adjacent to one side of the second latch to provide a ground voltage to the fifth node;
A fourth PMOS transistor formed on the fourth gate line to provide a power supply voltage to the fifth node,
The first output driver includes the second PMOS transistor, the second NMOS transistor, the third PMOS transistor, and the third NMOS transistor,
The second output driver is,
A fifth NMOS transistor to which a signal from the fourth node is applied and formed on a fifth gate line formed adjacent to the second latch to provide a ground voltage to the sixth node,
A fifth PMOS transistor formed on the fifth gate line to provide a power supply voltage to the sixth node,
A sixth NMOS transistor to which a signal from the fourth node is applied and formed on a sixth gate line formed adjacent to the fifth gate line to provide a ground voltage to the sixth node; and
It includes a sixth PMOS transistor formed on the sixth gate line to provide a power supply voltage to the sixth node,
The first latch, the first feedback inverter, the first output driver, the second latch, the second feedback inverter, and the second output driver form a multibit latch. According to clause 18,
Further comprising a first master latch transmitting the first bit data to the input of the first latch and a second master latch transmitting the second bit data to the input of the second latch,
The first master latch, the first latch, the first feedback inverter, the first output driver, the second master latch, the second latch, the second feedback inverter, and the second output driver are multi-bit flip-flops. A semiconductor circuit that forms a (multibit flip-flop). One or more processors;
Storage storing one or more standard cell designs; and
A layout module that uses the one or more processors to layout the one or more standard cell designs according to defined requirements,
The layout module is,
latch,
a feedback inverter that receives the output signal of the latch through a first node and inputs the output signal as feedback to the latch;
The output signal of the latch is input through the first node and the output signal is output to the outside, and an output driver including an even number of inverters is formed integrally into a single active region. A layout system for semiconductor circuits that layouts to share.

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