KR102639877B1 - Semiconductor memory device - Google Patents

Abstract

The present invention relates to semiconductor memory devices. The semiconductor memory device of the present invention includes a memory cell array including memory cells, a row decoder connected to the memory cell array through first conductive lines, write drivers and sense amplifiers connected to the memory cell array through second conductive lines. , a voltage generator configured to supply a first voltage to the row decoder and a second voltage to the write drivers and sense amplifiers, and coupled to the write drivers and sense amplifiers, the write drivers and sense amplifiers It includes a data buffer configured to exchange data with an external device. At least one of the row decoder, write drivers and sense amplifiers, voltage generator, and data buffer includes a first ferroelectric capacitor configured to amplify the voltage.

Description

Semiconductor memory device {SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to semiconductor devices, and more specifically, to semiconductor memory devices that use amplified voltage through passive elements.

Computing devices such as computers, smartphones, smart pads, etc. use semiconductor memory devices. Computing devices may use semiconductor memory devices as main or auxiliary memory. Main memory is used by computing devices to run various software such as operating systems, applications, etc. Auxiliary storage devices are used by computing devices to preserve original data such as operating systems and applications, or user data generated by them.

Semiconductor memory devices are one of the main factors that determine the power consumption of computing devices. As the amount of power consumed by a semiconductor memory device decreases, the amount of power consumed by a computing device decreases. In particular, in mobile devices that use batteries with a limited amount of power, such as smartphones and smart pads, the amount of power consumed by a semiconductor memory device can determine the operating time of the mobile devices.

In order to reduce power consumption of a semiconductor memory device, the semiconductor memory device may be designed to consume low power. To reduce power consumption, the operating voltage of semiconductor memory devices must be lowered. When the operating voltage of the semiconductor memory device is lowered, the swing width of the operating voltage of the semiconductor memory device decreases, which may limit the operating speed of the semiconductor memory device.

The purpose of the present invention is to provide a semiconductor memory device that overcomes limitations in operating speed by increasing the swing width of the operating voltage while maintaining the operating voltage.

A semiconductor memory device according to an embodiment of the present invention includes a memory cell array including memory cells, a row decoder connected to the memory cell array through first conductive lines, and write drivers connected to the memory cell array through second conductive lines. and sense amplifiers, a voltage generator configured to supply a first voltage to the row decoder and a second voltage to the write drivers and sense amplifiers, and coupled to the write drivers and sense amplifiers, the write drivers and It includes a data buffer configured to exchange data between the sense amplifiers and an external device. At least one of the row decoder, write drivers and sense amplifiers, voltage generator, and data buffer includes a first ferroelectric capacitor configured to amplify the voltage.

A semiconductor memory device according to an embodiment of the present invention includes a memory cell array including memory cells, a row decoder connected to the memory cell array through first conductive lines, and write drivers connected to the memory cell array through second conductive lines. and sense amplifiers, a voltage generator configured to supply a first voltage to the row decoder and a second voltage to the write drivers and sense amplifiers, and coupled to the write drivers and sense amplifiers, the write drivers and It includes a data buffer configured to exchange data between the sense amplifiers and an external device. Each of the first conductive lines or second conductive lines includes a ferroelectric capacitor.

A semiconductor memory device according to an embodiment of the present invention includes a memory cell array including memory cells, a row decoder connected to the memory cell array through first conductive lines, and write drivers connected to the memory cell array through second conductive lines. and sense amplifiers, a voltage generator configured to supply a first voltage to the row decoder and a second voltage to the write drivers and sense amplifiers, and coupled to the write drivers and sense amplifiers, the write drivers and It includes a data buffer configured to exchange data between the sense amplifiers and an external device. Each of the memory cells is a storage element that stores at least one bit, and a second conductive line of one of the second conductive lines and a second conductive line of the other one of the second conductive lines depending on the voltage of the first conductive line of one of the first conductive lines. It includes at least one transistor that electrically connects the storage element between the conductive lines. The gate insulating film of at least one transistor includes a ferroelectric material.

According to the present invention, the voltage delivered to the gate of the transistor is amplified through a ferroelectric material. Accordingly, a semiconductor memory device is provided that achieves improved operating speed or stability within a specific operating speed by increasing the swing width of the voltage delivered to the gate of the transistor while maintaining the operating voltage.

1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention.
Figure 2 shows a memory cell array according to an embodiment of the present invention.
Figure 3 shows a memory cell according to the first embodiment of the present invention.
Figure 4 shows a transistor according to an embodiment of the present invention.
Figure 5 shows a memory cell according to a second embodiment of the present invention.
Figure 6 shows a memory cell according to a third embodiment of the present invention.
Figure 7 is a block diagram showing a semiconductor memory device according to another embodiment of the present invention.
Figure 8 is a block diagram showing a semiconductor memory device according to another embodiment of the present invention.
Figure 9 shows an example of components associated with voltage amplification elements implemented in a row decoder or write drivers and sense amplifiers.
Figure 10 is a block diagram showing a semiconductor memory device according to another embodiment of the present invention.
Figure 11 shows an example of voltage amplification elements and associated components implemented in a voltage generator.
Figure 12 is a block diagram showing a semiconductor memory device according to another embodiment of the present invention.
Figure 13 shows an example of components associated with voltage amplification elements implemented in a data buffer.
Figure 14 is a block diagram showing a semiconductor memory device according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described clearly and in detail so that a person skilled in the art can easily practice the present invention.

Figure 1 is a block diagram showing a semiconductor memory device 100 according to an embodiment of the present invention. Referring to FIG. 1, the semiconductor memory device 100 includes a memory cell array 110, a row decoder 120, write drivers and sense amplifiers 130, a data buffer 140, an address buffer 150, and a command It includes a buffer 160, a voltage generator 170, and a control logic block 180.

Memory cell array 110 includes memory cells. Memory cells may be arranged in rows and columns. Rows of memory cells may be connected to first conductive lines CL1. Rows of memory cells may be connected to second conductive lines CL2. Each of the memory cells can store one or more bits.

The row decoder 120 is connected to the memory cell array 110 through the first conductive lines CL1. The row decoder 120 may receive the row address RA from the address buffer 150 and receive first voltages V1 (or first currents) from the voltage generator 170. The row decoder 120 may select one of the first conductive lines CL1 connected to a row of memory cells that are to be read or written in response to the row address.

The row decoder 120 applies a selection voltage or a selection current of the first voltages V1 (or first currents) to the selected first conductive line, and applies the first voltage V1 to the unselected first conductive lines. ) (or first currents), a non-selected voltage or a non-selected current may be applied. The first conductive lines CL1 may be called word lines.

The write drivers and sense amplifiers 130 are connected to the memory cell array 110 through the second conductive lines CL2. Write drivers and sense amplifiers 130 may receive a column address (CA) from the address buffer 150 and receive second voltages (V2) (or second currents) from the voltage generator 170. there is.

The write drivers and sense amplifiers 130 apply the second voltages V2 (or second currents) to the second conductive lines CL2 to select memory cells in the row selected by the row decoder 120. You can write data to or read data from memory cells in the selected row.

The write drivers and sense amplifiers 130 may perform writing or reading to memory cells selected by the column address (CA) among memory cells in the selected row. Write drivers and sense amplifiers 130 may receive data to be written in selected memory cells from the data buffer 140. The write drivers and sense amplifiers 130 may transmit data read from selected memory cells to the data buffer 140.

The data buffer 140 may transfer data (DATA) received from an external device, for example, an external memory controller, to the write drivers and sense amplifiers 130. Additionally, the data buffer 140 may transfer data (DATA) transmitted from the write drivers and sense amplifiers 130 to an external device.

The address buffer 150 may receive an address (ADDR) from an external device, for example, an external memory controller. The address buffer 150 may transmit the row address (RA) among the received addresses (ADDR) to the row decoder 120. The address buffer 150 may transfer the column address (CA) among the received addresses (ADDR) to the write drivers and sense amplifiers 130.

The command buffer 160 may receive a command (CMD) from an external device, for example, an external memory controller. The command buffer 160 may transfer the received command (CMD) to the control logic block 180.

The voltage generator 170 can generate various voltages required by the semiconductor memory device 100. For example, the voltage generator 170 may generate first voltages V1 and transmit them to the row decoder 120. The voltage generator 170 may generate second voltages V2 and transmit them to the write drivers and sense amplifiers 130.

The control logic block 180 may receive control signals CTRL from an external device, for example, an external memory controller. The control logic block 180 may receive a command (CMD) from the command buffer 160. The control logic block 180 may control operations of components of the semiconductor memory device 100 in response to control signals CTRL and commands CMD.

For example, the control logic block 180 may control the row decoder 120 to select one first conductive line corresponding to the row address RA among the first conductive lines CL1 at an appropriate timing. . The control logic block 180 may control the write drivers and sense amplifiers 130 at appropriate timing to read or write memory cells corresponding to the column address (CA) among the memory cells in the selected row.

The memory cell array 110 according to an embodiment of the present invention may include voltage amplification elements 11. The voltage amplification elements 11 may be configured to amplify and output a received voltage. Each of the voltage amplification elements 11 may be composed of one passive electrical element. Accordingly, the voltage used inside the memory cell array 110 can be increased without significantly increasing complexity and without increasing the operating voltage of the semiconductor memory device 100.

Figure 2 shows a memory cell array 110 according to an embodiment of the present invention. Referring to FIGS. 1 and 2 , the memory cell array 110 may include memory cells MC arranged in rows and columns. The rows of memory cells MC may be connected to the first conductive lines CL1, more specifically, m (m is a positive integer) first conductive lines CL1_1 to CL1_m.

The rows of memory cells MC include second conductive lines CL2, more specifically, n (n is a positive integer) 2a conductive lines (CL2a_1 to CL2a_n) and n 2b conductive lines ( It can be connected to CL2b_1~CL2b_n). Each of the memory cells MC includes a first conductive line of one of the first conductive lines CL1_1 to CL1_n, a 2a conductive line of one of the 2a conductive lines CL2a_1 to CL2a_n, and a 2b conductive line. It can be connected to one of the 2b conductive lines (CL2b_1 to CL2b_n).

For example, the first conductive lines CL1_1 to CL1_m may be called word lines. The 2a conductive lines (CL2a_1 to CL2a_n) may be called bit lines. The 2b conductive lines (CL2b_1 to CL2b_n) may be called inverted bit lines or source lines.

Figure 3 shows a memory cell (MC) according to the first embodiment of the present invention. Referring to FIGS. 2 and 3 , memory cells MC connected to the first first conductive line CL1_1, the first 2a conductive line CL2a_1, and the first 2b conductive line CL2b_1 are shown.

The memory cell MC may include first to sixth transistors T1 to T6. The first transistor T1 and the second transistor T2 may be connected in series between a power node to which the power supply voltage VDD is supplied and a ground node to which the ground voltage VSS is supplied. The first transistor T1 may be a PMOS transistor, and the second transistor T2 may be an NMOS transistor.

The third transistor T3 and the fourth transistor T4 may be connected in series between a power node to which the power supply voltage VDD is supplied and a ground node to which the ground voltage VSS is supplied. The third transistor T3 may be a PMOS transistor, and the fourth transistor T4 may be an NMOS transistor.

The fifth transistor T5 may be connected between the gates of the third transistor T3 and the fourth transistor T4 and the 2a conductive line CL2a_1. The gate of the fifth transistor T5 may be connected to the first conductive line CL1_1. The fifth transistor T5 may be an NMOS transistor.

The sixth transistor T6 may be connected between the gates of the first transistor T1 and the second transistor T2 and the 2b conductive line CL2b_1. The gate of the sixth transistor T6 may be connected to the first conductive line CL1_1. The sixth transistor T6 may be an NMOS transistor.

The first to fourth transistors T1 to T4 may function as cross coupled inverters. The first to fourth transistors T1 to T4 may function as storage elements that store data in the memory cell MC. The fifth and sixth transistors T5 and T6 may function as selection elements that electrically connect the storage element between the 2a conductive line CL2a_1 and the 2b conductive line CL2b_1.

The memory cell (MC) may be a static random access memory (SRAM) cell. An exemplary 6T SRAM cell is shown in Figure 3. However, the memory cell (MC) according to an embodiment of the present invention is not limited to 6T SRAM cells. A memory cell (MC) can be implemented as various types of SRAM cells.

Each of the first to sixth transistors T1 to T6 may include voltage amplification elements 11 . For example, each of the first to sixth transistors T1 to T6 may amplify the voltage applied to the gate and transmit it to the body. The first to sixth transistors T1 to T6 may perform voltage amplification using passive elements. When the voltage transmitted to the body is amplified, the response speed of the first to sixth transistors T1 to T6 is improved, so the memory cell MC can be accessed more quickly.

Figure 4 shows a transistor according to an embodiment of the present invention. Exemplarily, the transistor T may be one of the first to sixth transistors T1 to T6 of FIG. 3 . 3 and 4, the transistor T has a gate electrode G, a body BD, a first junction J1 and a second junction J2 formed on the body BD, and a body BD. ) and a voltage amplification element 11 disposed between the gate electrode (G).

The gate electrode (G) can function as the gate of the transistor (T). The first junction (J1) and the second junction (J2) may function as the drain and source of the transistor (T). When the transistor T is NMOS, the body BD may be doped to the P type, and the first junction (J1) and the second junction (J2) may be doped to the N type. When the transistor T is a PMOS, the body BD may be doped to the N-type, and the first junction (J1) and the second junction (J2) may be doped to the P-type.

The voltage amplification element 11 may function as an insulating film between the gate electrode (G) and the body (BD). Additionally, the voltage amplification element 11 may amplify the voltage transmitted to the gate electrode G and transmit it to the surface of the body BD. The voltage amplification element 11 may include a ferroelectric material.

Ferroelectric materials have the property of amplifying the voltage transmitted to one end and transmitting it to the other end, regardless of their state (for example, electrical polarization state, etc.). This characteristic may be called a negative capacitor. For example, when an external voltage is applied to a ferroelectric film, a negative capacitance effect may occur due to a phase change from the initial polarity state to another state due to the movement of dipoles inside the ferroelectric film. there is.

As explained with reference to FIG. 4, when the gate insulating films of the first to sixth transistors T1 to T6 of FIG. 3 are implemented with a ferroelectric material, the angle of the first to sixth transistors T1 to T6 is The gate voltage is amplified and transmitted to the body (BD). Accordingly, the response speed of the selection element and the storage element of the memory cell MC can be increased, and the access speed of the memory cell MC can be improved.

Exemplarily, the voltage amplification element 11 may include HfO doped with at least one of Zr, Si, Al, and La. By doping HfO with at least one of Zr, Si, Al, and La at a predetermined ratio, the voltage amplification element 11 may have an orthorhombic crystal structure. Negative capacitance effects may occur when the ferroelectric film has an orthorhombic crystal structure.

When the voltage amplification element 11 includes ZrHfO, the ratio of Zr atoms among total Zr and Hf atoms (Zr/(Hf+Zr)) may be 45 at% to 55 at%. When the voltage amplification element 11 includes SiHfO, the ratio of Si atoms among total Si and Hf atoms (Si/(Hf+Si)) may be 4 at% to 7 at%. When the voltage amplification element 11 includes AlHfO, the ratio of Al atoms (Al/(Hf+Al)) among the total Al and Hf atoms may be 4 at% to 7 at%. When the voltage amplification element 11 includes LaHfO, the ratio of La atoms (La/(La+Al)) among the total La and Hf atoms may be 5 at% to 10 at%.

Figure 5 shows a memory cell (MC) according to a second embodiment of the present invention. Referring to FIGS. 2 and 5 , memory cells MC connected to the first first conductive line CL1_1, the first 2a conductive line CL2a_1, and the first 2b conductive line CL2b_1 are shown.

The memory cell (MC) may include a selection element (SE) and a variable resistance element (RE) that functions as a storage element. The selection element SE is connected between the variable resistance element RE and the seconda conductive line CL2a_1 and may include a transistor controlled by the voltage of the first conductive line CL1_1.

The variable resistance element RE may be connected between the selection element SE and the 2b conductive line CL2b_1. The variable resistance element RE may have a resistance value that changes depending on the voltage applied to the variable resistance element RE or the current flowing through the variable resistance element RE. By adjusting the resistance value of the variable resistance element (RE), data can be stored in the variable resistance element (RE). By detecting the resistance value of the variable resistance element RE, data written to the variable resistance element RE can be read.

For example, the variable resistance element RE may include at least one of a phase change material, a ferroelectric material, a resistive material, and a magnetic material. Phase change materials may have different crystal structures depending on temperature and may have different resistance values depending on the crystal structure.

A ferroelectric material may have different electric polarization states depending on the magnetic or electric field, and may have different resistance values depending on the polarization states. Resistive materials create or disappear electrical passages depending on voltage, and may have different resistance values depending on the presence or absence of electrical passages. Magnetic materials have magnetization directions that vary depending on the magnetic field or the flow of current, and may have different resistance values depending on the magnetization directions.

The transistor of the selection element SE may be implemented in the same manner as described with reference to FIG. 4 . For example, the gate insulating film of the transistor of the selection element SE may include a ferroelectric material. The transistor of the selection element SE may be implemented to include a voltage amplification element 11 that amplifies the gate voltage and transfers it to the body BD (see FIG. 4).

Figure 6 shows a memory cell (MC) according to a third embodiment of the present invention. Referring to FIGS. 2 and 6 , memory cells MC connected to the first first conductive line CL1_1, the first 2a conductive line CL2a_1, and the first 2b conductive line CL2b_1 are shown.

The memory cell (MC) may include a selection element (SE) and a capacitor (C) that functions as a storage element. The selection element SE is connected between the variable resistance element RE and the seconda conductive line CL2a_1 and may include a transistor controlled by the voltage of the first conductive line CL1_1. Capacitor (C) can store data by charging or discharging voltage. The memory cell (MC) may be a dynamic random access memory (DRAM) cell.

The transistor of the selection element SE may be implemented in the same manner as described with reference to FIG. 4 . For example, the gate insulating film of the transistor of the selection element SE may include a ferroelectric material. The transistor of the selection element SE may be implemented to include a voltage amplification element 11 that amplifies the gate voltage and transfers it to the body BD (see FIG. 4).

Figure 7 is a block diagram showing a semiconductor memory device 200 according to another embodiment of the present invention. Referring to FIG. 7, the semiconductor memory device 200 includes a memory cell array 210, a row decoder 220, write drivers and sense amplifiers 230, a data buffer 240, an address buffer 250, and a command It includes a buffer 260, a voltage generator 270, and a control logic block 280.

Memory cell array 210 may be implemented as described with reference to FIGS. 2, 3, 5, and 6. Each of the memory cells MC of the memory cell array 210 may be implemented to include a voltage amplification element 11 as described with reference to FIG. 4 . As another example, each of the memory cells MC of the memory cell array 210 may be implemented not to have the voltage amplification element 11 . The gate insulating film of each transistor of the memory cells MC may be implemented as a conventional insulating film or a paradielectric.

Row decoder 220, write drivers and sense amplifiers 230, data buffer 240, address buffer 250, command buffer 260, voltage generator 270, and control logic block 280 are shown in FIG. Row decoder 120, write drivers and sense amplifiers 130, data buffer 140, address buffer 150, command buffer 160, voltage generator 170, and control logic described with reference to 1. It may be implemented the same as block 180.

The row decoder 220 may be connected to the memory cell array 210 through the first conductive lines CL1_1 to CL1_m. Each of the first conductive lines CL1_1 to CL1_m may include voltage amplification elements 12. The voltage amplification elements 12 may be implemented in the form of a capacitor (eg, a ferroelectric capacitor) filled with a ferroelectric material.

When the first conductive lines (CL1_1 to CL1_m) include the voltage amplification elements 12, the voltages applied by the row decoder 220 to the first conductive lines (CL1_1 to CL1_m) are amplified to form the memory cell array 210. ) can be passed on. In particular, memory cells MC are formed on a substrate and are limited in size.

On the other hand, the first conductive lines CL1_1 to CL1_m are formed in various layers including metal layers, and are less limited in size than the memory cells MC. Accordingly, the voltage amplification elements 12 formed in the first conductive lines CL1_1 to CL1_m can be manufactured to be larger than the voltage amplification elements 11 formed in the memory cells MC. Accordingly, the amplification factor of the voltage amplification elements 12 of the first conductive lines CL1_1 to CL1_m may be higher than the amplification factor of the voltage amplification elements 11 of the memory cells MC.

The write drivers and sense amplifiers 230 may be connected to the memory cell array 210 through second conductive lines CL2_1 to CL2_n. Each of the second conductive lines CL2_1 to CL2_n may be implemented as a pair of a 2a conductive line and a 2b conductive line. Each of the second conductive lines CL2_1 to CL2_n may include voltage amplification elements 13. The voltage amplification elements 13 may be implemented in the form of a capacitor (eg, a ferroelectric capacitor) filled with a ferroelectric material.

Like the voltage amplification elements 12 of the first conductive lines CL1_1 to CL1_m, the voltage amplification factors of the voltage amplification elements 13 of the second conductive lines CL2_1 to CL2_n are determined by the voltage of the memory cells MC. It may be higher than the voltage amplification factor of the amplification elements 11.

Exemplarily, the semiconductor memory device such that the voltage amplification elements 12 are provided only to the first conductive lines (CL1_1 to CL1_m) or the voltage amplification elements 13 are provided only to the second conductive lines (CL2_1 to CL2_n). (200) can be implemented.

Figure 8 is a block diagram showing a semiconductor memory device 300 according to another embodiment of the present invention. Referring to FIG. 8, the semiconductor memory device 300 includes a memory cell array 310, a row decoder 320, write drivers and sense amplifiers 330, a data buffer 340, an address buffer 350, and a command It includes a buffer 360, a voltage generator 370, and a control logic block 380.

Memory cell array 310 may be implemented as described with reference to FIGS. 2, 3, 5, and 6. Each of the memory cells MC of the memory cell array 310 may be implemented to include a voltage amplification element 11 as described with reference to FIG. 4 . As another example, each of the memory cells MC of the memory cell array 310 may be implemented not to have the voltage amplification element 11 . The gate insulating film of each transistor of the memory cells MC may be implemented as a conventional insulating film or a paradielectric.

The first conductive lines CL1 may be implemented to include voltage amplification elements 12 as described with reference to FIG. 7 . The second conductive lines CL2 may be implemented to include voltage amplification elements 13 as described with reference to FIG. 7 .

Row decoder 320, write drivers and sense amplifiers 330, data buffer 340, address buffer 350, command buffer 360, voltage generator 370, and control logic block 380 are shown in FIG. Row decoder 120, write drivers and sense amplifiers 130, data buffer 140, address buffer 150, command buffer 160, voltage generator 170, and control logic described with reference to 1. It may be implemented the same as block 180.

The row decoder 320 may include voltage amplification elements 14 in addition to the row decoder 120 described with reference to FIG. 1 . The write drivers and sense amplifiers 330 may include voltage amplification elements 15 in addition to the write drivers and sense amplifiers 130 described with reference to FIG. 1 .

Figure 9 shows an example of components associated with the voltage amplification elements 14 or 15 implemented in the row decoder 320 or the write drivers and sense amplifiers 330. 8 and 9, the row decoder 320 or write drivers and sense amplifiers 330 include the seventh transistor T7, the eighth transistor T8, the first inverter INV1, and the voltage amplification. It includes elements 14 or 15.

The seventh transistor T7 connects the internal line IL of the row decoder 320 or the write drivers and sense amplifiers 330 to the conductive line CL (e.g., in response to the first activation signal EN1). It can be electrically connected to the first conductive line or the second conductive line). The eighth transistor T8 responds to the signal in which the first activation signal EN1 is inverted by the first inverter INV1, and connects the internal line IL to the conductive line CL through the voltage amplification element 14 or 15. ) can be connected to.

When the seventh transistor T7 is turned on, the voltage of the internal line IL may be transmitted to the conductive line CL without passing through the voltage amplification element 14 or 15. When the eighth transistor T8 is turned on, the voltage of the internal line IL may be amplified by the voltage amplification element 14 or 15 and transmitted to the conductive line CL.

In FIG. 9, the row decoder 320 or the write drivers and sense amplifiers 330 use voltage amplification elements 14 or 15 to selectively amplify the voltage applied to the conductive line CL. explained. However, the use of the voltage amplification elements 14 or 15 is not limited.

For example, gate insulating films of transistors constituting operators such as the first inverter INV1 may be implemented to include a ferroelectric material as described with reference to FIG. 4 . Alternatively, ferroelectric capacitors may be placed at regular intervals in the wiring through which voltage is transmitted. Alternatively, ferroelectric capacitors may be placed on wires through which signals are transmitted between specific combinational logics.

Figure 10 is a block diagram showing a semiconductor memory device 400 according to another embodiment of the present invention. Referring to FIG. 10, the semiconductor memory device 400 includes a memory cell array 410, a row decoder 420, write drivers and sense amplifiers 430, a data buffer 440, an address buffer 450, and a command It includes a buffer 460, a voltage generator 470, and a control logic block 480.

Memory cell array 410 may be implemented as described with reference to FIGS. 2, 3, 5, and 6. Each of the memory cells MC of the memory cell array 410 may be implemented to include a voltage amplification element 11 as described with reference to FIG. 4 . As another example, each of the memory cells MC of the memory cell array 410 may be implemented not to have the voltage amplification element 11 . The gate insulating film of each transistor of the memory cells MC may be implemented as a conventional insulating film or a paradielectric.

The first conductive lines CL1 may be implemented to include voltage amplification elements 12 as described with reference to FIG. 7 . The second conductive lines CL2 may be implemented to include voltage amplification elements 13 as described with reference to FIG. 7 .

Row decoder 420, write drivers and sense amplifiers 430, data buffer 440, address buffer 450, command buffer 460, voltage generator 470, and control logic block 480 are shown in FIG. Row decoder 120, write drivers and sense amplifiers 130, data buffer 140, address buffer 150, command buffer 160, voltage generator 170, and control logic described with reference to 1. It may be implemented identically to block 180.

Row decoder 420 or write drivers and sense amplifiers 430 may be implemented to include voltage amplification elements 14 or 15 as described with reference to FIGS. 8 and 9 . The voltage generator 470 may further include voltage amplification elements 16 in addition to the voltage generator 170 of FIG. 1 .

Figure 11 shows an example of the components associated with the voltage amplification elements 16 implemented in the voltage generator 470. 10 and 11, the voltage generator 470 includes a ninth transistor (T9), a tenth transistor (T10), a second inverter (INV2), and a voltage amplification element (16).

The ninth transistor T9 outputs the output voltage VO of the voltage generator 470 to the generation node NG through which the generated voltage VG of the voltage generator 470 is output in response to the second activation signal EN2. It can be electrically connected to the output node (NO). The tenth transistor T10 responds to the second activation signal EN2 being inverted by the second inverter INV2, and connects the generation node NG to the output node NO through the voltage amplification element 16. You can connect.

When the ninth transistor T9 is turned on, the generated voltage VG of the generation node NG can be output through the output node NO as the output voltage VO without passing through the voltage amplification element 16. there is. When the tenth transistor T10 is turned on, the generated voltage VG of the generating node NG is amplified by the voltage amplifying element 16 and output as the output voltage VO through the output node NO. You can.

The output voltage VO may be output as one of the first voltages V1 or the second voltages V2. By way of example, the configurations shown in FIG. 11 may be provided for each of the first voltages V1 and the second voltages V2.

In Figure 11, the voltage generator 470 is illustrated as using voltage amplification elements 16 to selectively amplify the output voltage VO. However, the uses of the voltage amplification elements 16 are not limited. For example, gate insulating films of transistors constituting operators such as the second inverter INV2 may be implemented to include a ferroelectric material as described with reference to FIG. 4 . Alternatively, ferroelectric capacitors may be placed at regular intervals in the wiring through which voltage is transmitted. Alternatively, ferroelectric capacitors may be placed on wires through which signals are transmitted between specific combinational logics.

Figure 12 is a block diagram showing a semiconductor memory device 500 according to another embodiment of the present invention. Referring to FIG. 12, the semiconductor memory device 500 includes a memory cell array 510, a row decoder 520, write drivers and sense amplifiers 530, a data buffer 540, an address buffer 550, and a command It includes a buffer 560, a voltage generator 570, and a control logic block 580.

Memory cell array 510 may be implemented as described with reference to FIGS. 2, 3, 5, and 6. Each of the memory cells MC of the memory cell array 510 may be implemented to include a voltage amplification element 11 as described with reference to FIG. 4 . As another example, each of the memory cells MC of the memory cell array 510 may be implemented not to have the voltage amplification element 11 . The gate insulating film of each transistor of the memory cells MC may be implemented as a conventional insulating film or a paradielectric.

The first conductive lines CL1 may be implemented to include voltage amplification elements 12 as described with reference to FIG. 7 . The second conductive lines CL2 may be implemented to include voltage amplification elements 13 as described with reference to FIG. 7 .

Row decoder 520, write drivers and sense amplifiers 530, data buffer 540, address buffer 550, command buffer 560, voltage generator 570, and control logic block 580 are shown in FIG. Row decoder 120, write drivers and sense amplifiers 130, data buffer 140, address buffer 150, command buffer 160, voltage generator 170, and control logic described with reference to 1. It may be implemented the same as block 180.

Row decoder 520 or write drivers and sense amplifiers 530 may be implemented to include voltage amplification elements 14 or 15 as described with reference to FIGS. 8 and 9 . Voltage generator 570 may be implemented to include voltage amplification elements 16 as described with reference to FIGS. 10 and 11 . The data buffer 540 may be implemented to include voltage amplification elements 17 in addition to the data buffer 140 of FIG. 1 .

FIG. 13 shows an example of components associated with the voltage amplification elements 17 implemented in the data buffer 540. 12 and 13, the data buffer 540 includes a serializer 541, a deserializer 542, voltage amplification elements 17, first to third pads (P1 to P3), and a first to third pad (P1 to P3). It includes first and second transmitters (TX1, TX2), first to third receivers (RX1 to RX3), first and second flip-flops (FF1, FF2), and a signal generator 543.

The serializer 541 may serialize signals (eg, bits) transmitted from the write drivers and sense amplifiers 530 and transmit them to the first flip-flop FF1. The deserializer 542 may deserialize (or parallelize) signals (eg, bits) transmitted from the second flip-flop FF2 and transmit them to the write drivers and sense amplifiers 530 .

The first flip-flop FF1 may be synchronized with the output signal of the signal generator 543 and transmit the output signals of the serializer 541 to the first transmitter TX1. The first transmitter TX1 may output the output signal of the first flip-flop FF1 to the first pad P1 through the voltage amplification element 17. The first pad P1 may be connected to an external device, for example, an external memory controller.

The first receiver RX1 may transmit the signal transmitted from the first pad P1 through the voltage amplification element 17 to the second flip-flop FF2. The second flip-flop FF2 may be synchronized with the output signal of the second receiver RX2 and transmit the output signal of the first receiver RX1 to the deserializer 542.

The second receiver RX2 may receive a signal from the second pad P2 through the voltage amplification element 17. The output signal of the second receiver (RX2) may be transmitted to the clock input of the second flip-flop (FF2). The second transmitter TX2 may output the output signal of the signal generator 543 to the second pad P2 through the voltage amplification element 17. The second pad P2 may be connected to an external device, for example, an external memory controller.

The third receiver RX3 may receive a signal from the third pad P3 through the voltage amplification element 17. The output signal of the third receiver (RX3) is transmitted to the signal generator 543. The third pad P3 may be connected to an external device, for example, an external memory controller.

The signal generator 543 may transition between a low level and a high level from the output signal of the third receiver (RX3) and generate a timing signal (e.g., a toggle signal, a strobe signal, or a toggle signal) indicating operation timings. . The output signal of the signal generator 543 may be transmitted to the clock input of the first flip-flop (FF1) and the second transmitter (TX2).

For example, the third pad P3 may be configured to allow the data buffer 540 to receive a timing signal from an external device. The signal received through the third pad P3 may be called a data strobe signal or a clock signal. The signal of the third pad P3 may be used by the signal generator 543 to generate another timing signal, for example, another data strobe signal.

The second pad P2 may be configured to allow the data buffer 540 to communicate a timing signal, for example, a data strobe signal, in a data input cycle or a data output cycle.

In a data input cycle, a data strobe signal may be received from the second pad P2 through the voltage amplification element 17 and the second receiver RX2. The second flip-flop FF2 is synchronized with the data strobe signal and can identify the data signal transmitted from the first pad P1 through the voltage amplification element 17 and the first receiver RX1.

In the data output cycle, the data strobe signal generated by the signal generator 543 may be output to the second pad P2 through the second transmitter TX2 and the voltage amplification element 17. The first flip-flop FF1 may be synchronized with the data strobe signal and output a data signal to the first pad P1 through the first transmitter TX1 and the voltage amplifier 17.

As shown in FIG. 13, signals received from the data buffer 540 are transmitted through the voltage amplification elements 17. Additionally, signals output from the data buffer 540 are output through the voltage amplification elements 17. Accordingly, the strength of the signal through which the data buffer 540 communicates with an external device, for example, an external memory controller, can be strengthened without additional resources, and signal integrity can be improved.

In FIG. 13, the data buffer 540 is explained as using voltage amplification elements 17 to amplify signals for communication with an external device. However, the use of the voltage amplification elements 17 is not limited. For example, gate insulating films of transistors constituting operators such as inverters and logic gates may be implemented to include a ferroelectric material, as described with reference to FIG. 4 . Alternatively, ferroelectric capacitors may be placed at regular intervals in the wiring through which voltage is transmitted. Alternatively, ferroelectric capacitors may be placed on wires through which signals are transmitted between specific combinational logics.

Figure 14 is a block diagram showing a semiconductor memory device 600 according to another embodiment of the present invention. Referring to FIG. 14, the semiconductor memory device 600 includes a memory cell array 610, a row decoder 620, write drivers and sense amplifiers 630, a data buffer 640, an address buffer 650, and a command It includes a buffer 660, a voltage generator 670, and a control logic block 680.

Memory cell array 610 may be implemented as described with reference to FIGS. 2, 3, 5, and 6. Each of the memory cells MC of the memory cell array 610 may be implemented to include a voltage amplification element 11 as described with reference to FIG. 4 .

The first conductive lines CL1_1 to CL1_m may be implemented to include voltage amplification elements 12 as described with reference to FIG. 7 . The second conductive lines CL2_1 to CL2_n may be implemented to include voltage amplification elements 13 as described with reference to FIG. 7 .

Row decoder 620, write drivers and sense amplifiers 630, data buffer 640, address buffer 650, command buffer 660, voltage generator 670, and control logic block 680 are shown in FIG. Row decoder 120, write drivers and sense amplifiers 130, data buffer 140, address buffer 150, command buffer 160, voltage generator 170, and control logic described with reference to 1. It may be implemented the same as block 180.

The row decoder 620 and the write drivers and sense amplifiers 530 may be implemented to include voltage amplification elements 14 and 15 as described with reference to FIGS. 8 and 9 . Voltage generator 670 may be implemented to include voltage amplification elements 16 as described with reference to FIGS. 10 and 11 . The data buffer 640 may be implemented to include voltage amplification elements 17 as described with reference to FIGS. 12 and 13 .

As described above, components of the semiconductor memory devices 100, 200, 300, 400, 500, and 600 have been described using terms such as first, second, third, etc. However, terms such as first, second, third, etc. are used to distinguish components from each other and do not limit the present invention. For example, terms such as first, second, third, etc. do not imply order or any form of numerical meaning.

In the above-described embodiments, components according to embodiments of the present invention have been referenced using blocks. Blocks include various hardware devices such as IC (Integrated Circuit), ASIC (Application Specific IC), FPGA (Field Programmable Gate Array), and CPLD (Complex Programmable Logic Device), software such as firmware and applications running on the hardware devices, Alternatively, it may be implemented as a combination of a hardware device and software. Additionally, blocks may include circuits composed of semiconductor elements within an IC or IP (Intellectual Property).

The above-described details are specific embodiments for carrying out the present invention. The present invention will include not only the above-described embodiments, but also embodiments that can be simply changed or easily changed in design. In addition, the present invention will also include technologies that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims and equivalents of the present invention as well as the claims described later.

100, 200, 300, 400, 500, 600: Semiconductor memory device
110, 210, 310, 410, 510, 610: memory cell array
120, 220, 320, 420, 520, 620: row decoders
130, 230, 330, 430, 530, 630: Write drivers and sense amplifiers
140, 240, 340, 440, 540, 640: Data buffer
150, 250, 350, 450, 550, 650: Address buffer
160, 260, 360, 460, 560, 660: Command buffer
170, 270, 370, 470, 570, 670: Voltage generator
180, 280, 380, 480, 580, 680: Control logic blocks
11, 12, 13, 14, 15, 16, 17: voltage amplification elements

Claims (20)

a memory cell array including memory cells;
a row decoder connected to the memory cell array through first conductive lines;
Write drivers and sense amplifiers connected to the memory cell array through second conductive lines;
a voltage generator configured to supply a first voltage to the row decoder and a second voltage to the write drivers and sense amplifiers; and
a data buffer coupled to the write drivers and sense amplifiers and configured to exchange data between the write drivers and sense amplifiers and an external device;
At least one of the row decoder, the write drivers, the sense amplifiers, and the data buffer includes a first ferroelectric capacitor configured to amplify a voltage. According to paragraph 1,
Each of the memory cells:
A first transistor and a second transistor connected in series between a power node to which a power voltage is supplied and a ground node to which a ground voltage is supplied;
A third transistor and a fourth transistor connected in series between the power node and the ground node,
A first node commonly connected to the gate of the third transistor and the gate of the fourth transistor, a second node connected to one of the second conductive lines, and one of the first conductive lines. a fifth transistor having a gate connected to one first conductive line; and
A third node commonly connected to the gate of the first transistor and the gate of the second transistor, a fourth node connected to the second conductive line of another one of the second conductive lines, and the one first conductive line. A sixth transistor having a gate connected to the line,
A semiconductor memory device wherein a gate insulating layer of at least one of the first to sixth transistors includes a ferroelectric material. According to paragraph 1,
Each of the memory cells:
a variable resistance element connected to one of the second conductive lines; and
A first node connected to another second conductive line of the second conductive lines, a second node connected to the variable resistance element, and a gate connected to the first conductive line of one of the first conductive lines. It includes a transistor having,
A semiconductor memory device wherein the gate insulating film of the transistor includes a ferroelectric material. According to paragraph 3,
The variable resistance element is a semiconductor memory device including at least one of a phase change material, a ferroelectric material, a resistive material, and a magnetic material. According to paragraph 1,
Each of the memory cells:
a capacitor connected to one of the second conductive lines;
having a first node connected to a second conductive line of another one of the second conductive lines, a second node connected to the capacitor, and a gate connected to the first conductive line of one of the first conductive lines. Contains a transistor,
A semiconductor memory device wherein the gate insulating film of the transistor includes a ferroelectric material. According to paragraph 1,
Each of the first conductive lines or the second conductive lines includes a second ferroelectric capacitor. According to clause 1:
The row decoder is:
a first transistor connected between one of the first conductive lines and an internal line corresponding to the one first conductive line; and
Comprising a second transistor and the first ferroelectric capacitor connected in series between the one first conductive line and the internal line,
The second transistor and the first ferroelectric capacitor are connected in parallel with the first transistor,
A semiconductor memory device in which the first transistor and the second transistor are controlled by complementary signals. According to clause 1:
The write drivers and sense amplifiers:
a first transistor connected between one of the second conductive lines and an internal line corresponding to the one second conductive line; and
A second transistor and a first ferroelectric capacitor connected in series between the one second conductive line and the internal line,
The second transistor and the first ferroelectric capacitor are connected in parallel with the first transistor,
A semiconductor memory device in which the first transistor and the second transistor are controlled by complementary signals. According to paragraph 1,
The voltage generator is:
a first transistor connected between the voltage generation node and the voltage output node; and
Comprising a second transistor and a first ferroelectric capacitor connected in series between the voltage generation node and the voltage output node,
The second transistor and the first ferroelectric capacitor are connected in parallel with the first transistor,
The first transistor and the second transistor are controlled by complementary signals,
A semiconductor memory device wherein the voltage of the voltage output node is transmitted as the first voltage or the second voltage to the row decoder or the write drivers and sense amplifiers. According to paragraph 1,
The data buffer is:
a first pad configured to be connected to the external device;
a first receiver configured to generate a second signal by amplifying the first signal received from the first pad; and
A semiconductor memory device comprising the first ferroelectric capacitor connected between the first pad and the first receiver. According to clause 10,
The data buffer is:
a first transmitter configured to amplify an internal signal to generate a third signal and transmit the third signal to the first pad; and
A semiconductor memory device further comprising a second ferroelectric capacitor connected between the first pad and the first transmitter. According to clause 11,
The data buffer is:
a second pad configured to be connected to the external device;
a second receiver configured to generate a fifth signal by amplifying the fourth signal received from the second pad;
a third ferroelectric capacitor connected between the second receiver and the second pad;
A semiconductor memory device comprising a flip-flop configured to convert the second signal of the first receiver into a digital value in synchronization with the fifth signal of the second receiver. According to clause 12,
The data buffer further includes a deserializer configured to deserialize the outputs of the flip-flop and transmit them to the write drivers and sense amplifiers. According to clause 11,
The data buffer is:
a second pad configured to be connected to the external device;
a second receiver configured to generate a fifth signal by amplifying the fourth signal received from the second pad;
a third ferroelectric capacitor connected between the second pad and the second receiver;
a signal generator configured to generate a sixth signal from the fifth signal of the second receiver;
A semiconductor memory device further comprising a flip-flop configured to transmit the internal signal to the first transmitter in synchronization with the sixth signal. According to clause 14,
The data buffer further includes a serializer configured to serialize signals transmitted from the sense amplifiers and the write drivers and transmit them to the flip-flop. According to clause 14,
The data buffer is:
a third pad configured to be connected to the external device;
a second transmitter configured to amplify the sixth signal of the signal generator to generate a seventh signal, and transmit the seventh signal to the third pad; and
A semiconductor memory device further comprising a fourth ferroelectric capacitor connected between the third pad and the second transmitter. a memory cell array including memory cells;
a row decoder connected to the memory cell array through first conductive lines;
Write drivers and sense amplifiers connected to the memory cell array through second conductive lines;
a voltage generator configured to supply a first voltage to the row decoder and a second voltage to the write drivers and sense amplifiers; and
a data buffer coupled to the write drivers and sense amplifiers and configured to exchange data between the write drivers and sense amplifiers and an external device;
At least one of the row decoder, the write drivers and sense amplifiers, the voltage generator, and the data buffer includes a first ferroelectric capacitor configured to amplify a voltage,
The voltage generator is:
a first transistor connected between the voltage generation node and the voltage output node; and
Comprising a second transistor and a first ferroelectric capacitor connected in series between the voltage generation node and the voltage output node,
The second transistor and the first ferroelectric capacitor are connected in parallel with the first transistor,
The first transistor and the second transistor are controlled by complementary signals,
A semiconductor memory device wherein the voltage of the voltage output node is transmitted as the first voltage or the second voltage to the row decoder or the write drivers and sense amplifiers. a memory cell array including memory cells;
a row decoder connected to the memory cell array through first conductive lines;
Write drivers and sense amplifiers connected to the memory cell array through second conductive lines;
a voltage generator configured to supply a first voltage to the row decoder and a second voltage to the write drivers and sense amplifiers; and
a data buffer coupled to the write drivers and sense amplifiers and configured to exchange data between the write drivers and sense amplifiers and an external device;
At least one of the row decoder, the write drivers and sense amplifiers, the voltage generator, and the data buffer includes a first ferroelectric capacitor configured to amplify a voltage,
Each of the first conductive lines or the second conductive lines includes a second ferroelectric capacitor. delete delete

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