KR102639325B1 - Derivative receiver and method for receiving a signal - Google Patents

Abstract

The differential receiver according to this technology includes a differentiator that differentiates the input signal; a hysteresis comparator that compares the differential signal provided from the differentiator with a threshold voltage and outputs a comparison signal; and a pattern detection equalizer that provides a data signal by sampling the equalization signal whose level of the comparison signal has been adjusted according to the clock signal, wherein the level of the comparison signal is adjusted with reference to the past value of the data signal.

Description

Differential receiver and signal reception method {DERIVATIVE RECEIVER AND METHOD FOR RECEIVING A SIGNAL}

The present invention relates to a differential receiver that differentiates and receives an input signal and a signal reception method.

FIG. 1(A) is a block diagram briefly showing a semiconductor chip 1 including internal channels 11 and 21.

The semiconductor chip 1 includes a plurality of dies 10 and 20. In Figure 1, a DRAM die is used as an example.

The plurality of dies 10 and 20 are connected to a terminal N0 provided on the semiconductor chip through wire bonding.

The terminal N0 is connected to the external channel 2 to transmit and receive signals.

Each die (10, 20) provides signals input through wire bonding to the receivers (12, 22) through internal channels (11, 21).

FIG. 1(B) is a diagram showing a situation in which a signal (Vi) input through an external channel (CH) is provided to the receiver 12 of one die 10.

The signal input to the receiver 12 is the first signal (V ₁ ) and the external channel (2, CH) transmitted through external channel (2, CH) -> N0 -> internal channel (11, ICH) -> N1. -> N0 -> Internal channel (21, ICH) -> N2 (reflection) -> Internal channel (21) -> N0 -> Internal channel (11) -> Includes the reflected signal (V _R ) transmitted through N1 do.

Figure 2 is a graph showing the voltage of node N1 over time.

The first signal (V ₁ ) appears after the external channel transit time (T _CH ) and the internal channel transit time (T _ICH ) have elapsed.

At this time, the first signal (V ₁ ) becomes the input voltage (V _i ) multiplied by the first passing coefficient (T ₁ ).

The first passing coefficient (T ₁ ) represents the rate at which a signal input through an external channel (CH) is transmitted through the node (N0) and node (N1) and input to the receiver 12.

Since the reflected signal (V _R ) appears after passing through the internal channels (11, 21), it appears after twice the internal channel transit time (T _ICH ).

The reflected signal (V _R ) is a signal that is transmitted after the signal arriving at N2 is reflected at the input terminal of the receiver 22.

When the receiver 12 is operating, the receiver 22 is in a floating state, so the size of the signal reflected from the input terminal of the receiver 22 is the same as the size of the first signal (V ₁ ).

The reflected signal (V _R ) is the value obtained by multiplying the reflected signal by the second pass coefficient (T ₂ ) as above.

The second passing coefficient (T ₂ ) represents the rate at which signals transmitted through the node N2, node N0, and node N1 are input to the receiver 12.

In this way, when one of the plurality of dies, each of which has an internal channel, is connected to an external channel and receives a signal, the received signal is distorted due to the signal reflected from the other die, resulting in an error in receiving data at high speed. may occur.

KR 10-0706732 B1 US 9425905 B2

This technology provides a differential receiver that differentiates and processes an input signal and a signal reception method.

A differential receiver according to an embodiment of the present invention includes a differentiator that differentiates an input signal; a hysteresis comparator that compares the differential signal provided from the differentiator with a threshold voltage and outputs a comparison signal; and a pattern detection equalizer that provides a data signal by sampling the equalization signal whose level of the comparison signal has been adjusted according to the clock signal, wherein the level of the comparison signal is adjusted with reference to the past value of the data signal.

A signal reception method according to an embodiment of the present invention includes the steps of differentiating an input signal to generate a differential signal; Comparing the differential signal with a threshold voltage to generate a comparison signal; generating an equalization signal by adjusting the level of the comparison signal according to the past value of the data signal; and generating a data signal by sampling the equalization signal.

The differential receiver and signal reception method according to an embodiment of the present invention can remove errors due to reflected signals by differentiating the signal, performing hysteresis comparison, and then performing sampling.

The differential receiver and signal reception method according to an embodiment of the present invention can eliminate inter-symbol interference by adjusting the hysteresis comparison result using past values of output data.

1 is a block diagram showing a semiconductor device including an internal channel.
Figure 2 is a graph showing a signal transmitted to a receiver through an internal channel.
Figure 3 is a block diagram of a differential receiver according to an embodiment of the present invention.
Figure 4 is a waveform diagram showing the operation of a differentiator and a hysteresis comparator according to an embodiment of the present invention.
Figure 5 is a block diagram of a pattern detection equalizer according to an embodiment of the present invention.
Figure 6 is an explanatory diagram illustrating the operation of a transition detector according to an embodiment of the present invention.
Figure 7 is a waveform diagram showing the operation of a voltage adjustment circuit according to an embodiment of the present invention.
Figure 8 is a block diagram of a pattern detection equalizer according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be disclosed with reference to the attached drawings.

Figure 3 is a block diagram showing a differential receiver 1000 according to an embodiment of the present invention.

The differentiation receiver 1000 according to an embodiment of the present invention includes a differentiator 100 that differentiates an input signal and outputs it, a hysteresis comparator 200 that compares the output of the differentiator 100 and has hysteresis characteristics, and a hysteresis comparator 200. It includes a pattern detection equalizer 300 that performs an equalization operation on the output of.

The differentiator 100 may include a capacitor (C) connected between the input terminal and the output terminal and a resistor (R) connected between the output terminal and the common voltage terminal (VCOM), and a differential signal (IN') obtained by differentiating the input signal (IN). outputs.

The differential receiver 1000 may further include an equalizer 400 that performs an equalization operation on a signal input from a channel. At this time, the equalizer 400 is a continuous time linear equalizer (CTLE).

The differential receiver 1000 may further include an amplifier 500 that amplifies the differential signal IN' output from the differentiator 100, outputs an amplified differential signal IN' _A , and provides the amplified differential signal IN' A to the hysteresis comparator 200. You can.

Hereinafter, the signal provided to the input terminal of the hysteresis comparator 200 is referred to as the differential signal IN' without distinguishing whether it is output from the differentiator 100 or the amplifier 500.

The hysteresis comparator 200 compares the differential signal IN' with the threshold voltage and outputs a comparison signal VH.

Figure 4 is a waveform diagram showing the operation of the differentiator 100 and the hysteresis comparator 200 according to an embodiment of the present invention.

In this embodiment, the input signal IN input to the differentiator 100 is a signal in which reflected waves are mixed for the same reason as described in FIGS. 1 and 2.

*In other words, after the data transitions from a high level to a low level or from a low level to a high level, a step waveform that transitions once more due to a reflected wave occurs after a certain period of time (2T _ICH ).

As described above, the differential signal IN' is an output signal of the differentiator 100 or an output signal of the amplifier 500 and is input to the hysteresis comparator 200.

When the input signal (IN) is differentiated, two peaks occur in the differential signal (IN') every time there is a transition due to the reflected wave.

For example, when the input signal (IN) transitions from high level to low level, two downward peaks occur in the differential signal (IN'), and when the input signal (IN) transitions from low level to high level, the differential signal Two upward peaks occur at (IN').

The hysteresis comparator 200 outputs a low-level comparison signal (VH) when the differential signal (IN') becomes lower than the downward threshold voltage (VTHDN), and when the differential signal (IN') becomes higher than the upward threshold voltage (VTHUP), the hysteresis comparator 200 outputs a low-level comparison signal (VH). Outputs a high-level comparison signal (VH). When the differential signal IN' exists between the upward threshold voltage VTHUP and the downward threshold voltage VTHDN, the hysteresis comparator 200 maintains the current output as is.

Accordingly, even if two peaks occur in the differential signal (IN') due to the reflection signal included in the input signal (IN), the output of the comparison signal (VH) transitions only at T0, T1, T2, T3, and T4, and T01, There is no transition at T11, T21, T31, T41, etc.

The transition time of the input signal (IN) may vary due to Inter Symbol Interference (ISI).

In FIG. 4, when there was no signal transition immediately before, there is no change in the signal transition speed.

In Figure 4, as in the case of (a) and (c), the falling speed of the signal decreases due to the rising transition of the signal that occurred immediately before, and as in the case of (b), the signal rises due to the falling transition of the signal that occurred immediately before. Speed decreases.

Accordingly, the peak value of the differential signal (IN') in the corresponding section decreases compared to other cases, and the comparison signal (VH) corresponding to the sections (a), (b), and (c) transitions somewhat late due to the ISI effect. do.

In the comparison signal (VH) waveform of FIG. 4, the part indicated by a dotted line corresponds to a case where the signal is not affected by ISI, and the part indicated by a solid line indicates that the transition time is delayed due to the influence of ISI.

The pattern detection equalizer 300 adjusts the transition time of the signal by removing ISI effects.

Figure 5 is a block diagram of a pattern detection equalizer 300 according to an embodiment of the present invention.

In this embodiment, the pattern detection equalizer 300 includes a voltage adjustment circuit 310, a sampler 320, a latch 330, a transition detector 340, and a plurality of flip-flops 351 and 352.

The voltage adjustment circuit 310 adjusts the voltage level of the comparison signal (VH) according to the equalization control signal (H) and outputs the equalization signal (VHE).

The sampler 320 samples the equalization signal (VHE) according to the clock signal (CLK).

In this embodiment, the sampler 320 samples the equalization signal (VHE) at the rising edge of the clock signal (CLK).

The latch 330 latches the output of the sampler 320 and outputs a data signal (D[0]).

The data signal D[0] output from the latch 330 may be referred to as the current value of data.

In this embodiment, the plurality of flip-flops 351 and 352 include a first flip-flop 351 that outputs a data signal (D[-1]) and a second flip-flop that outputs a data signal (D[-2]). Includes (352).

The data signal (D[-1]) can be referred to as the first past value, and the data signal (D[-2]) can be referred to as the second past value.

In this embodiment, the transition detector 340 outputs an equalization control signal (H) with reference to the past value of the data signal.

Figure 6 is a waveform diagram and table showing the operation of the transition detector 340.

The sampler 320 samples the equalization signal (VHE) at the rising edge of the clock signal (CLK).

The transition detector 350 outputs an equalization control signal (H) from the second past value sampled at t-2 and the first past value sampled at t-1.

As shown in the table, when the first past value and the second past value are both 0 or 1, the transition detector 350 considers that there was no transition in the past and outputs 0 as the equalization control signal (H).

The transition detector 350 outputs a negative equalization control signal (H) when the second past value is 0 and the first past value is 1. This indicates that an upward transition exists in the input signal (IN') before t.

The transition detector 350 outputs a positive equalization control signal (H) when the second past value is 1 and the first past value is 0. This indicates that a downward transition exists in the input signal (IN') before t.

Figure 7 is a waveform diagram showing comparison between the comparison signal (VH) and the equalization signal (VHE).

As described with reference to FIG. 4, the comparison signal VH transitions to a low level at T2 and T4, and transitions to a high level at T3.

In this embodiment, when the equalization control signal (H) is 0, the voltage adjustment circuit 310 outputs the comparison signal (VH) as is, and when the equalization control signal (H) is positive as in T3, the voltage adjustment circuit 310 outputs the comparison signal (VH) as is. The level of the comparison signal (VH) is raised to output the equalization signal (VHE), and when the equalization control signal (H) is negative as in T2 and T4, the voltage adjustment circuit 310 reduces the level of the comparison signal (VH). outputs an equalization signal (VHE).

Accordingly, the point at which the equalization signal (VHE) passes through the intermediate voltage (V _MP ) of the sampler 320 is advanced from T3' to T3, and the equalization signal (VHE) passes through the intermediate voltage (V _MP ) of the sampler 320. The passing point is advanced from T2' and T4' to T2 and T4.

Through this, an equalization signal (VHE) in which the influence of ISI shown in FIG. 4 is removed is generated, and errors in the data signal (D[0]) passing through the sampler can be removed.

Figure 8 is a block diagram showing a pattern detection equalizer 300-1 according to another embodiment of the present invention.

The embodiment of FIG. 8 is a pattern detection equalizer 300-1 that uses four-phase clock signals (CLK0, CLK90, CLK180, and CLK270) to sample four times during one cycle of the clock signal (CLK).

That is, the embodiment of FIG. 8 can sample at a frequency four times that of the embodiment of FIG. 5.

Except that the embodiment of Figure 8 includes voltage adjustment circuits 311 to 314, samplers 321 to 324, latches 331 to 334, and transition detectors 341 to 344 corresponding to each phase of the clock signal. Since it is substantially the same as the embodiment of FIG. 5, detailed description will be omitted.

In the embodiment of FIG. 8, a circuit that outputs a data signal in response to each phase of a multi-phase clock signal may be referred to as a unit pattern detection equalizer.

For example, a circuit that provides the data signal D0, including the voltage adjustment circuit 311, sampler 321, latch 331, and transition detector 341, may be referred to as a unit pattern detection equalizer.

The embodiment of FIG. 8 does not include a separate flip-flop for storing past data values.

Because, for example, based on the transition detector 344 corresponding to the 4th phase, the first past value of the data corresponds to D180 and the second past value corresponds to D90, so a separate flip-flop is not required. .

Transition detectors corresponding to the remaining phases also do not require separate flip-flops because they can use past values of data in a similar way.

The scope of rights of the present invention is not limited to the above disclosure. The scope of rights of the present invention should be interpreted based on the scope literally stated in the claims and the scope of equivalents thereof.

1: Semiconductor chip 2: External channel
10, 20: DRAM die 11, 21: internal channel
12, 22: Receiver
1000: Differentiation receiver 100: Differentiator
200: Hysteresis comparator 300: Pattern detection equalizer
400: Equalizer 500: Amplifier
310 ~ 314: Voltage adjustment circuit 320 ~ 324: Sampler
330 to 334: Latch 340 to 344: Transition Detector
351: first flip-flop 352: second flip-flop

Claims (16)

A differentiator that differentiates the input signal;
a hysteresis comparator that compares the differential signal provided from the differentiator with a threshold voltage and outputs a comparison signal; and
A pattern detection equalizer that provides a data signal by sampling the equalization signal whose level of the comparison signal is adjusted according to a clock signal.
A differential receiver wherein the level of the comparison signal is adjusted by referring to the past value of the data signal. The differential receiver according to claim 1, further comprising an equalizer for equalizing a signal provided from a channel and providing the signal as the input signal. The differential receiver according to claim 1, further comprising an amplifier that amplifies the output of the differentiator to provide the differential signal. The method of claim 1, wherein the pattern detection equalizer
a voltage adjustment circuit that provides the equalization signal by adjusting the level of the comparison signal according to an equalization control signal;
a sampler for sampling the equalization signal according to the clock signal; and
A transition detector that outputs the equalization control signal from the past value of the data signal provided from the sampler.
Differential receiver containing . The differential receiver of claim 4, further comprising a latch for latching the output of the sampler to provide the data signal. The differential receiver of claim 4, further comprising at least one flip-flop that latches the data signal according to the clock signal and provides a past value of the data signal. The method of claim 4, wherein the transition detector detects whether a transition exists before sampling by the sampler from a past value of the data signal, and when a transition exists, the equalization control signal controls the level of the comparison signal to increase or decrease. A differential receiver that outputs . The method of claim 7, wherein the transition detector outputs the equalization control signal to control the level of the comparison signal to be reduced when detecting that a transition from a low level to a high level previously exists, and to control the level of the comparison signal to decrease from a previously high level to a low level. A differential receiver that outputs the equalization control signal to control the level of the comparison signal to increase when detecting that a level transition exists. The method of claim 1, wherein the clock signal is a multiphase clock signal.
The pattern detection equalizer is a differential receiver including a plurality of unit pattern detection equalizers corresponding to the multi-phase clock signal. The method of claim 9, wherein the unit pattern detection equalizer
a voltage adjustment circuit that provides the equalization signal by adjusting the level of the comparison signal according to an equalization control signal;
a sampler for sampling the equalization signal according to any one of the multi-phase clock signals; and
A transition detector that outputs the equalization control signal from the past value of the data signal provided from the sampler.
Differential receiver containing . The differential receiver of claim 10, further comprising a latch for latching the output of the sampler to provide the data signal. The differential receiver of claim 10, wherein the past value of the data signal is provided from a unit pattern detection equalizer corresponding to a different phase of the multi-phase clock signal.
Differentiating an input signal to generate a differential signal;
Comparing the differential signal with a threshold voltage to generate a comparison signal;
generating an equalization signal by adjusting the level of the comparison signal according to the past value of the data signal; and
Generating the data signal by sampling the equalization signal
A signal reception method comprising: In claim 13,
A signal receiving method further comprising generating the input signal by equalizing a signal provided through a channel. In claim 13,
generating an equalization control signal according to the past value of the data signal;
generating the equalization signal by adjusting the level of the comparison signal according to the equalization control signal; and
A signal reception method further comprising generating the data signal by sampling the equalization signal according to a clock signal. The method of claim 15, wherein generating the equalization signal includes adding the comparison signal and the equalization control signal.