KR102638562B1 - Apparatus and method of continuous wavelet transform - Google Patents

Abstract

A continuous wavelet transform device according to an embodiment of the present invention includes an R2SDF FFT module for FFT processing an input signal (biological signal); 4 SRAMs for reordering the FFT processing results of the R2SDF FFT module by distributing and sorting them into 4 channels; Four wavelet SRAMs in which daughter wavelets values in the frequency domain are initialized; 4 multipliers for the 4-channel multiplication; and an MRMDC IFFT module with a 4-channel parallel input structure that IFFT processes the calculated values of the four multipliers.

Description

Continuous wavelet transform apparatus and method {Apparatus and method of continuous wavelet transform}

The present invention can be applied to fields requiring high-speed biosignal monitoring or high-resolution signal-frequency analysis, so that the length and characteristics of the signal can be adjusted according to the biosignal to be observed, 8/16/32/64/128/256 /512/1024-point Pertains to a continuous wavelet transform apparatus and method in which variable length and variable wavelet are supported.

Invasive biosignal measurement seriously limits a person's independence and mobility, can cause pain due to patches and sensor electrodes, and has the disadvantage of being difficult to attach if the patient has suffered severe burns or injuries.

Due to this problem, invasive bio-signal measurement has significant limitations in its use from the perspective of long-term sleep monitoring and health management, where continuous bio-signal monitoring is important.

To overcome this, non-invasive bio-signal monitoring is attracting attention, and depth cameras, infrared thermal sensors, radar, etc. are used.

Among them, the radar sensor is not affected by day or night, and observation is possible even if an obstacle such as a wall exists between the radar and the object of observation.

In addition, it can be implemented with low power and a small area, making it more advantageous for continuous monitoring than other non-invasive sensors.

Radar-based biological signal processing requires time-frequency analysis to detect irregular non-stationary signals.

In the case of STFT (Short-time-Fourier-transform), a widely known time-frequency analysis method, there is a problem that the observation time must be large in order to obtain high reliability of the analysis signal, which can cause a delay in response in emergency situations.

Due to the above problems, CWT (Continuous-wavelet-transform)-based radar biosignal processing technology, which can achieve high accuracy even with a shorter observation time compared to STFT, is attracting attention.

However, due to the many convolution operations of the CWT (Continuous-wavelet-transform) algorithm alone and the characteristic that the computational complexity increases exponentially depending on the signal length, it has the disadvantage of being difficult to analyze biological signals in real time, so it has not been widely used. .

For this reason, in order to process real-time continuous monitoring of biological signals at the edge device level, it is essential to implement an accelerator in hardware form to minimize the time required for CWT calculation.

The convolution operation in the time domain of CWT can reduce computational complexity by transferring target signals to the frequency domain and then performing the multiplication of the two signals.

FFT processors for transition between time and frequency domains can be implemented in butterfly structure, pipeline structure, and parallel structure, of which the pipeline structure best satisfies the trade-off between calculation speed and area.

The pipeline structure is further divided into the SDF (single-path delay feedback) method and the MDC (multi-path delay commutator) method depending on the data ordering method.

The radix-2-based SDF method has a simple structure because it can minimize non-simple multiplication in the case of a single-channel FFT, but has the disadvantage that hardware complexity increases linearly in the case of multi-channel FFT.

The MDC method has a larger area than SDF when using a single channel, but when using multi-channel FFT, it has the advantage of being able to implement a smaller area than SDF.

In the conventional case, low-area implementation is possible by implementing CWT hardware (HW) based on a single butterfly structure, but high-speed processing of biological signals with many analysis frequency components is difficult, and the signal to be analyzed is targeted to the Electroencephalogram (EEG) signal. (targeting), CWT operations of various lengths are not supported.

Accordingly, the present invention adopts the R2SDF (radix-2 SDF) method for FFT, which is a single channel input, and proposes a continuous wavelet transform device that is a pipeline FFT-based mixed-radix CWT processor that minimizes FFT complexity.

The proposed continuous wavelet transform device uses multi-parallel channel input IFFT based on radix-4, and MRMDC (mixed-radix MDC) structure using the radix-4/2 FFT algorithm that minimizes non-simple multipliers (minimizing area increase). By doing so, it is designed to have high speed and low complexity) and adopts the DMM1 in a removed form. In addition, the observation time and sampling frequency of biological signals vary depending on the target signal to be observed, such as EEG, respiration, and heart rate. Available in various lengths, 8/16/32/64/… /Designed to support operations of various lengths of 1024-point.

Optimized FPGA based continuous wavelet transform Yahya T. Qassim, et. al.Computers & Electrical Engineering 49 (2016) 84-94.

The purpose of the present invention is to provide a continuous wavelet transform device and method that can solve conventional problems.

A continuous wavelet transform device according to an embodiment of the present invention to solve the above problem includes an R2SDF FFT module for FFT processing an input signal; 4 SRAMs for reordering the FFT processing results of the R2SDF FFT module into 4 channels; Four wavelet SRAMs with initialized daughter wavelet values in the frequency domain; 4 multipliers for the 4-channel multiplication; and an MRMDC IFFT module with a 4-channel parallel input structure that IFFT processes the calculated values of the four multipliers.

A continuous wavelet transform method according to an embodiment of the present invention to solve the above problem includes FFT processing an input signal in an R2SDF FFT module; Reordering the FFT processing results of the R2SDF FFT module into 4 channels using 4 SRAMs; Performing element-by-element multiplication in four multipliers with the FFT processing results stored in four SRAMs and the daughter wavelets values in the frequency domain of the input signal stored in four wavelet SRAMs; It includes the step of IFFT processing the calculated values of the four multipliers in the MRMDC IFFT module with a 4-channel parallel input structure.

Therefore, the continuous wavelet transform device and method according to an embodiment of the present invention is 8/16/32/64/128/256/512/1024- 8/16/32/64/128/256/512/1024- point This is about the hardware structure of a high-speed scalable CWT processor that supports variable length and variable wavelets. The computational complexity was reduced by using the FFT-based CWT algorithm, and multi-channel multiplication and IFFT operations were used to enable multiple wavelets. It provides the advantage of reducing the overall operation speed by reducing the number of multiplication operations with (wavelet) and IFFT operations.

In addition, the exchange relationship between area and speed can be adjusted by using different FFT and IFFT modules depending on the number of input channels. The FFT module, which is a single channel input, can be implemented with low complexity and has a pipeline structure to exchange between area and speed. The R2SDF structure that satisfies the relationship is used, and the IFFT module, which is a 4-channel input, has fewer non-simplex multipliers and uses the MRMDC structure with better area efficiency than the SDF structure in 4 channels. As described above, the FFT result value is By aligning through four SRAMs, it provides the advantage of reducing the overall processor area and computation time by eliminating the first DMM, which has the largest area in the MDC structure and causes a lot of latency.

Figure 1 is a graph showing the shape of the wavelet functions Morlet, Mexican hat, and Paul wavelets in the time and frequency domains when the scale is 1.
Figure 2 is a hardware structure diagram of a conventional FFT-based CWT calculation device.
Figure 3a is a hardware structure diagram of a continuous wavelet transform device according to an embodiment of the present invention.
Figure 3b is a flowchart explaining a continuous wavelet transform method according to an embodiment of the present invention.
FIG. 4A is a hardware architecture of the R2SDF FFT module shown in FIG. 3A, and FIG. 4B is a timing diagram for the above operation using a stage for 32-point FFT as an example.
FIG. 5 is a timing diagram of the SRAM write pattern shown in FIG. 3.
Figure 6a is the hardware architecture of the MRMDC IFFT module shown in Figure 3, and Figure 6b shows the structure of the DMM for data mapping of the 16-point FFT, which is the second stage in the FFT operation process of a signal with a total signal length of 64-points. , is a data flow.
Figure 6c is an example diagram showing the structure of a DMM for mapping the input of the Radix-4 butterfly operator and the input data of the last stage.
Figure 6d is a block diagram of a circuit for implementing multiplication of W ₈ ¹ , W ₈ ² , and W ₈ ³ .
FIG. 7 is an operation (multiplication) timing diagram of the MRMDC IFFT module shown in FIG. 3A.

Hereinafter, embodiments of the present specification are described with reference to the attached drawings. However, this does not limit the technology described herein to specific embodiments, and should be understood to include various modifications, equivalents, and/or alternatives to the embodiments herein. . In connection with the description of the drawings, similar reference numbers may be used for similar components. In this specification, expressions such as “have,” “may have,” “includes,” or “may include” refer to the presence of the corresponding feature (e.g., component such as numerical value, function, operation, or part). , and does not rule out the existence of additional features.

As used herein, expressions such as “A or B,” “at least one of A or/and B,” or “one or more of A or/and B” may include all possible combinations of the items listed together. . For example, “A or B,” “at least one of A and B,” or “at least one of A or B” includes (1) at least one A, (2) at least one B, or (3) it may refer to all cases including both at least one A and at least one B.

As used herein, expressions such as “first,” “second,” “first,” or “second,” can modify various components regardless of order and/or importance, and refer to one component. It is only used to distinguish from other components and does not limit the components. For example, a first user device and a second user device may represent different user devices regardless of order or importance. For example, a first component may be renamed a second component without departing from the scope of rights described in this specification, and similarly, the second component may also be renamed to the first component.

A component (e.g., a first component) is “(operatively or communicatively) coupled with/to” another component (e.g., a second component). When referred to as being “connected to,” it should be understood that any component may be directly connected to the other component or may be connected through another component (e.g., a third component). On the other hand, when a component (e.g., a first component) is said to be “directly connected” or “directly connected” to another component (e.g., a second component), the component and the It may be understood that no other component (e.g., a third component) exists between other components.

As used herein, the expression “configured to” may mean, for example, “suitable for,” “having the capacity to,” or “having the capacity to.” ," can be used interchangeably with "designed to," "adapted to," "made to," or "capable of." The term “configured (or set to)” may not necessarily mean “specifically designed to” in hardware. Instead, in some contexts, the expression “a device configured to” may mean that the device is “capable of” working with other devices or components.

For example, the phrase "processor configured (or set) to perform A, B, and C" refers to a processor dedicated to performing the operations (e.g., an embedded processor), or by executing one or more software programs stored on a memory device. , may refer to a general-purpose processor (e.g., CPU or application processor) capable of performing the corresponding operations.

Terms used in this specification are merely used to describe specific embodiments and may not be intended to limit the scope of other embodiments. Singular expressions may include plural expressions, unless the context clearly indicates otherwise. Terms used herein, including technical or scientific terms, may have the same meaning as generally understood by a person of ordinary skill in the technical field described herein. Among the terms used in this specification, terms defined in general dictionaries may be interpreted to have the same or similar meaning as the meaning they have in the context of related technology, and unless clearly defined in this specification, have an ideal or excessively formal meaning. It is not interpreted as In some cases, even terms defined in this specification cannot be interpreted to exclude embodiments of this specification.

Hereinafter, a continuous wavelet transform apparatus and method according to an embodiment of the present invention will be described in more detail based on the attached drawings.

Before explaining the present invention, the CWT algorithm and FFT-based CWT hardware architecture will be briefly described.

CWT is a time-frequency analysis method like STFT for continuous signals. When entered, it is expressed as [Equation 1]. is the CWT result, means the wavelet function, * means the complex conjugate number, and s is the scale that determines the time axis area of the wavelet function.

[Equation 1]

By repeatedly performing the above convolution equation at various scales, time-frequency analysis is possible.

Here, wavelets refer to signals whose size converges to 0 on both sides of the time axis and oscillates with an average of 0.

When the scale of the representative wavelet functions, Morlet, Mexican hat, and Paul wavelet, is 1, the shape is expressed in the time and frequency domains as shown in Figure 1.

CWT can select an appropriate wavelet according to the shape of the signal to be analyzed, making it highly applicable to monitoring biological signals where the shape of the signal is important.

The basic wavelet selected in this way and used in CWT calculation is called the mother wavelet, and the wavelet created by changing the scale of the mother wavelet is called the daughter wavelet.

The scale of the wavelet is used for various frequency analysis. The smaller the scale, the stronger the time axis compression of the wavelet, making it effective in detecting high frequency components. Conversely, the larger the scale, the more advantageous it is in detecting low frequency components.

The absolute value of the 2D correlation set obtained through the calculation of [Equation 1] of wavelets and signals with various scales is called a scalogram, and time-frequency analysis can be performed using this. Unlike STFT, which is the same time-frequency analysis method, the frequency resolution of CWT depends on how tightly the scale value is taken, so there is no need to have a longer observation time compared to the STFT method to obtain high frequency resolution.

However, in the time domain, CWT operation requires the calculation amount to be the square of the signal length due to the nature of convolution ( ), which makes it difficult to apply it to real-time monitoring due to the high computational complexity that is proportional to ). This complexity problem can be solved using the relationship in [Equation 2] below. X(w) refers to the signal in the time domain, and Y(w) refers to the signal in the frequency domain.

[Equation 2]

A convolution in the time domain is converted to a simple product in the frequency domain, and vice versa.

In other words, CWT can significantly reduce the computational complexity caused by convolution by transferring signals and wavelets from the time domain to the frequency domain and then performing a multiplication operation, enabling real-time use even at the edge-device level.

Next, the FFT-based CWT operation to minimize the complexity of the convolution operation is largely carried out in three processes.

This is the process of FFT of the input signal, multiplication of the FFT result of the input signal and the frequency domain wavelet, and IFFT of the multiplied signal.

In CWT, the precision of observation and frequency observation range are determined depending on the number of scales used, so repetitive multiplication and IFFT operations occur.

Figure 2 shows the data flow of a basic FFT-based CWT operation. The CWT operation is performed using one data path, and multiplication and IFFT are repeated as many times as the number of scales used.

Methods for implementing the FFT and IFFT modules in Figure 2 include a single butterfly structure with one butterfly operator, and a butterfly operator at each stage to perform operations in the form of a stream. There is a pipeline structure and a parallel structure that performs calculations simultaneously using multiple channels.

Here, the parallel structure has the greatest advantage in terms of yield, but has the disadvantage of increasing hardware complexity, making it difficult to use at the edge device level.

When the FFT/IFFT module is implemented with a single butterfly structure based on the Radix-2 algorithm, the FFT operation of a signal with an N-point length is cycle is consumed.

Since the CWT operation includes FFT operation, IFFT operation, and multiplication, when implemented with a single butterfly structure, when the number of scales is M, A cycle is needed.

The single butterfly structure based on the conventional radix-4 algorithm has the advantage of being able to implement a lower area than other FFT structures and having a higher yield compared to the radix-2 algorithm.

However, due to the limitations of the single butterfly structure, when using many scales, latency may increase excessively, which may cause problems such as delayed response in emergency situations when used to observe important biological signals such as breathing and heart rate.

If FFT and IFFT operations are performed with R2SDF among the pipelined FFT structures, the CWT operation cycle has a very short cycle compared to the single butterfly structure, at about 2N+M(N) when the scale is M, but each repeated element has a very short cycle. Due to multiplication and IFFT operations, it is difficult to expect acceleration effects with 1-channel operations alone.

For good acceleration effects, it is desirable to suppress the number of repetitions by using an MDC structure specialized for multi-channel operations.

Accordingly, the present invention proposes a CWT that can accelerate the CWT operation by reducing the number of repetitions by performing repeated multiplication and IFFT operations in parallel for each element.

FIG. 3A is a device block diagram of a continuous wavelet transform device according to an embodiment of the present invention, and FIG. 3B is a flowchart explaining a continuous wavelet transform method according to an embodiment of the present invention.

As shown in Figure 3a, the continuous wavelet transform device 100 according to an embodiment of the present invention includes an R2SDF FFT module 110 for FFT processing an input signal (biological signal), and an FFT processing result of the R2SDF FFT module. Four SRAMs 120 for reordering into 4 channels, 4 wavelet SRAMs 130 with initialized daughter wavelet values in the frequency domain, 4 multipliers 140 for the 4-channel multiplication, and the 4 multipliers It includes an MRMDC IFFT module 150 with a 4-channel parallel input structure that IFFT processes the calculated value.

As shown in Figure 3b, the continuous wavelet transform method according to an embodiment of the present invention includes a process of FFT processing an input signal (biological signal) in the R2SDF FFT module (S710), and FFT of the R2SDF FFT module in four SRAMs. The process of reordering the processing results to 4 channels (S720), the process of performing element-by-element multiplication with the FFT processing results stored in 4 SRAMs in 4 multipliers and the daughter wavelets values in the frequency domain stored in 4 wavelet SRAMs ( S730) and IFFT processing the calculated values of the four multipliers in the MRMDC IFFT module with a 4-channel parallel input structure (S740).

The continuous wavelet transform device 100 of the present invention is a mixed-radix CWT processor proposed for high-speed biological signal processing, and performs multi-channel multiplication and IFFT to reduce repetition due to wavelet scales.

Here, the number of channels was selected as 4-channel to minimize the increase in area of the MRMDC IFFT module 150.

Meanwhile, the input value is a biological signal and is the target signal for time-frequency analysis.

The input value is subject to element-by-element multiplication with a number of daughter wavelets by storing the result in SRAM (120) after completing the first FFT operation.

The R2SDF FFT module 110 is based on the radix-2 algorithm with low implementation complexity, and has an SDF pipeline structure known to best satisfy the trade-off between speed and area for 1-channel input.

Figure 4a shows the hardware structure of the Radix-2 Single-Path Delay Feedback (R2SDF) FFT module shown in Figure 3a.

Referring to FIG. 4, the R2SDF FFT module 110 selects the input signal to be used for calculation in each stage to achieve 8/16/32/64/... /1024-point variable points can be supported.

The FFT operation value of the R2SDF FFT module 110 undergoes 4-channel multiplication and IFFT operation.

Here, performing the FFT operation again at each repetition to perform repeated element-wise multiplication and IFFT is inefficient in terms of speed and amount of calculation.

Therefore, in order to avoid repetitive FFT operations, SRAM to store FFT results must exist.

That is, the four SRAMs 120 of the present invention may be configured to store FFT results for use in 4-channel multiplication.

In addition, the four Wavelet SRAMs 130 of the present invention are configured to initialize and use the frequency domain signal of the daughter wavelets to be used according to the signal to be analyzed.

For example, through the four Wavelet SRAMs 130, up to 24 wavelet signals in the frequency domain with a maximum length of 1024 points can be initialized, and the initialized wavelet signals can range from at least 4 to multiples of 4 using external input signals. The number of uses is controlled per unit.

Next, the multiplier 140 performs 4-channel multiplication when all FFT results are written to four SRAMs. That is, the FFT result data of the input signal stored in the SRAM and the value initialized in the Wavelet SRAM (130) are input one by one, a multiplication operation is performed, and the multiplication result is output in the form of a stream. The output result of multiplication is transmitted to the input of the IFFT module 140.

For reference, referring to FIG. 4b, the R2SDF FFT module has a simple structure and is widely used in 1-channel pipeline FFT calculation. The R2SDF structure performs data mapping through a delay element that has a 1-channel input in each stage. The delay elements in each stage have half the number of FFT points that must be performed in the stage. In the case of N-point FFT, when 1-channel input data comes in, the 0th to (N/2-1)th point is delayed using a delay element, and the radix- 2 It becomes possible to match input pairs of the butterfly operator. Among the 2-channel data output after the Radix-2 butterfly operation, one channel on which the '+' operation was performed in the butterfly operator goes directly into the input of the next stage. The other channel on which the '-' operation has been performed in the butterfly operator does not immediately go to the next stage, but is input to the delay element in the stage, and output is delayed until all '+' operation values in the butterfly operator are output. , After the multiplication operation of the twiddle factor is performed, it is followed by the 1-channel input of the next stage. In Figure 4b, a timing diagram for the above operation is attached as an example of a stage for 32-point FFT.

Next, the MRMDC IFFT module 150 has a 4-channel input pipeline IFFT structure to efficiently process 4-channel input in the form of a stream in a few cycles. .

For example, among the pipeline IFFT methods, the SDF structure processor is commonly used due to its low complexity during single-channel operation, but in the case of multi-channel operation, the disadvantage is that an IFFT processor must be implemented for each channel, which is the same as the proposed processor for 4-channel operation. not suitable for

In addition, the MDC-type IFFT processor has a larger area than the SDF method when performing single-channel operations, but in the case of 4-channel IFFT operations, one MDC-type processor can implement a smaller area than a processor using four SDF methods. .

For the above reasons, the 4-channel MRMDC IFFT module 150 of the present invention was designed using the MRMDC structure.

However, if the existing MDC structure is applied as is, the problem of additional increase in overall operation latency and processor area occurs due to the large number of delay elements in the first data mapping module (DMM) that sorts the data at the input stage.

In order to avoid the above problem, the continuous wavelet transform device 100 of the present invention imitates the data sorting process of the first DMM of the MDC structure by dividing the SRAM into four when storing the FFT result value in the SRAM.

In order to eliminate the first DMM, the present invention performs the access order of SRAM and the address access inside SRAM in bit-reverse order to store the FFT results output in bit-reverse order in four SRAMs.

For reference, referring to Figure 6a, the R2SDF pipeline FFT module is a pipeline MDC structure based on the radix-4/2 algorithm. It is based on the R4MDC structure, which is known to be more efficient than the R2SDF module in 4-channel operations, can reduce the number of non-simple multipliers, and can support various point FFTs. The MDC-structured FFT module performs data mapping using a DMM (Data mapping module) consisting of multiple delay elements and a commutator. At this time, due to the nature of the MRMDC structure, two butterfly operators, radix-2 and radix-4, are used, so the DMM also has two types of structures.

Except for the last stage, the delay elements of the DMM for input to the radix-2 butterfly operator have sizes of N/4, 2N/4, and 3N/4 of the FFT-point that must be performed in the corresponding stage.

Figure 6b shows the structure and data flow of a DMM for data mapping of 16-point FFT, the second stage in the FFT calculation process of a signal with a total signal length of 64 points. Through DMM, data can be mapped so that iDATA1 and iDATA3 have an N/2-point difference, and iDATA2 and iDATA4 have an N/2-point difference, and can be entered as input to the following radix-2 butterfly operator.

Figure 6c is an example diagram showing the structure of a DMM for mapping the input data of the Radix-4 butterfly operator and the input data of the last stage, which is the 8-point FFT, which is the third stage in the FFT calculation process of a signal with a total signal length of 64 points. It shows the structure and data flow of DMM for data mapping. By mapping the data through the DMM so that the data of each channel differs by N/4-point, it can be input as input to the following radix-4 butterfly operator.

The Radix-4/2 algorithm can fix the twiddle factor multiplied after the radix-4 butterfly operation to W ₈ ¹ , W ₈ ² , and W ₈ ³ . Each value is expressed as the formula below.

At this time, the value of the twiddle factor is fixed, and the value of 1/sqrt(2) can be implemented with only a simple multiplier with a simple bit shift, as shown below, without consuming DSP when using the fixed-point number system.

Compared to the R4MDC structure, which requires the conventional twiddle factor multiplication to be implemented with a non-simple multiplier, the MRMDC structure can be implemented in a smaller area using a simple multiplier. Figure 6d is a block diagram of a circuit for implementing multiplication of W ₈ ¹ , W ₈ ² , and W ₈ ³ , where R means round in the fixed point number system and C means clip in the fixed point number system. These two operations are used to adjust the number of bits in the Q-format. Lastly, 2'S means conversion to 2's complement, that is, changing the sign of the number.

Figure 5 is a timing diagram for storing 64-point FFT results in SRAM and a memory map of SRAM formed as a result.

At this time, the four wavelet SRAMs 130 that store wavelet data also store wavelet data in the same alignment pattern as the SRAM 120.

Referring to FIG. 5, the function of the first DMM can be replaced by reordering the output of the FFT module 110 using four SRAMs.

For this reason, the DMM, which can be removed in the present invention, has a total of 3072 delay elements and a memory size of about 12.29 KB based on 32-bit complex data, so through data ordering using 4 SRAMs 120, resources equivalent to the corresponding size are available. (resource) usage can be reduced.

The MDC-type 4-channel IFFT module with the first DMM removed is an MRMDC structure based on the radix-4/2 algorithm. Compared to the R4MDC structure, some non-simple multipliers can be replaced with simple multipliers, resulting in a smaller area. have In addition, it has a higher yield compared to the radix-2 algorithm structure, and unlike the radix-4 algorithm, which supports variable points limited to an exponent of 4, it controls various variable points like the radix-2 algorithm by adjusting the input stage and data path. Points can be supported.

The MRMDC IFFT module 150 of the present invention has the DMM at the input stage removed through the data sorting process using the four SRAMs 120 described above, so it receives the 4-channel multiplication result and immediately starts the calculation of the first stage. Because it can, it has a short latency.

Also, by selecting the input signal at each stage like the R2SDF FFT module in the same processor, 8/16/32/64/… /Designed to support variable points of 1024-point.

Figure 7 is a timing diagram for 4-channel multiplication and IFFT operation after N-point FFT in the continuous wavelet transform device of the present invention.

Wav_SRAM shown in Figure 7 shows the output of Wavelet SRAM.

Previously, for data sorting, data of length N was divided into N/4 lengths and stored in 4 SRAMs, so it operates with the highest yield in CWT calculation with 4 daughter wavelets with N-points.

At this time, the cycle required for CWT operation of the continuous wavelet transform device 100 of the present invention takes 2N+M/4(N) when using M scales.

In case of single butterfly structure based on Radix-2 algorithm When the cycle is an R2SDF(FFT)-R2SDF(IFFT) structure, it takes 2N+M(N) cycles, so due to the nature of CWT operation that requires repeated operations with many daughter wavelets, the proposed processor was compared with other proposed structures. It can be confirmed that high-speed CWT operations can be supported.

Hereinafter, the execution results of the continuous wavelet transform device of the present invention will be briefly described.

The continuous wavelet transform device 100 of the present invention was designed by RTL using Verilog, a hardware description language (HDL), and then implemented and verified based on Xilinx's UltraScale+ ZCU104 FPGA. As a result of synthesis, it was confirmed that it can operate at a maximum of 302 MHz.

[Table 1] is a table that summarizes the calculation process (cycle) and calculation time required for CWT calculation using 4 scales and 24 scales for signals with 512-point and 1024-point lengths, respectively. .

At the maximum operating frequency of 302MHz, the CWT operation of a 512-point signal using 4 scales takes 7μs, and the CWT operation of a 1024-point signal using 24 scales takes 31μs.

[Table 1]

[Table 2] summarizes the resource usage of the present invention.

The continuous wavelet transform device of the present invention was synthesized using a total of 89,941 LUTs and 108,598 FFs, and uses 92 DSPs. This figure corresponds to 39.04% of LUT and 23.57% of FF of the total based on the UltraScale+ ZCU104 FPGA board, and in the case of DSP, 5.32% of the total.

[Table 2]

In order to confirm whether the present invention has high speed, a comparison is made with the CWT processor of the existing literature.

When investigating implementation cases of CWT processors for acceleration, except for implementation cases in the form of general purpose processor (GPP) or DSP or implementation of 2-D CWT for image processing, comparison with the present invention can be made. The only example of FPGA implementation of 1-D CWT for biological signal monitoring is the research literature by Qassim et al .

In the conventional case, the FFT-based CWT processor for ERP feature extraction has an FFT-based CWT structure implemented using Xilinx V.5 FFT core and Radix-4 Burst I/O.

In order to make the comparison as fair as possible, the calculation time was normalized using T _norm expressed in [Equation 3].

‘Tech’ in the formula represents the nanometer technology of the FPGA’s CMOS process, and as the number increases, problems such as slower speeds and longer execution times occur. The signal point in Equation 3 uses the commonly supported 1024-point for comparison of the two processors.

Lastly, to reduce the influence of the number of scales used, normalization was performed on the number of scales.

[Equation 3]

[Table 3]

The present invention can reduce the operation speed by 73.04% compared to the conventional CWT processor.

At this time, the present invention cannot fix the wavelet to be used for measuring biological signals, but the purpose of the conventional processor is fixed to ERP feature extraction, so the wavelet that can be used for observation is fixed.

As a result, many cycles could be reduced through the zero exclusion process in the conventional element-by-element multiplication process, and the maximum operating frequency could be increased.

If the wavelet to be used for observation cannot be fixed, the difference between the T _norm between the conventional and the present invention will widen further.

Therefore, the present invention has a faster CWT calculation time compared to the prior art, and has a structure more suitable for real-time vital signal measurement (general vital signal measurement).

The present invention discloses a continuous wavelet transform device, which is an FFT-based mixed radix CWT processor for real-time biosignal monitoring.

The present invention is designed to have high speed to prevent delays in response in emergency situations while monitoring biosignals.

The present invention has low latency for high speed and uses a pipeline FFT/IFFT structure to achieve high yield.

The FFT module for 1-channel input signals uses the R2SDF structure to have low complexity, and the IFFT module for 4-channel input signals uses an MDC structure that occupies a smaller area than the SDF structure in multiple channels. applied.

At this time, the IFFT module can minimize the number of non-simplex multipliers based on the radix-4/2 algorithm, and applies the MRMDC structure that can support input signals of various lengths like the radix-2 algorithm.

Therefore, the present invention is 8/16/32/64/… /1024-point variable input is supported and up to 24 daughter wavelets of up to 1024-point length can be initialized using SRAM.

The number of initialized daughter wavelets can be adjusted in multiples of 4 using an external input signal. Compared to the existing processor designed with the same FFT-based CWT algorithm, the CWT calculation time of the present invention for a 1024-point length signal was reduced by 94.56% in absolute terms.

For a fair comparison, it was confirmed that the calculation time could be reduced by 73.27% by normalizing the technology of the FPGA board used and the number of scales used for calculation. Through this, the present invention proved to be efficient for real-time biosignal analysis that requires high speed.

The term '~unit' used in the above embodiments refers to software or hardware components such as FPGA (field programmable gate array) or ASIC, and the '~unit' performs certain roles. However, '~part' is not limited to software or hardware. The '~ part' may be configured to reside in an addressable storage medium and may be configured to reproduce on one or more processors. Therefore, as an example, '~ part' refers to components such as software components, object-oriented software components, class components, and task components, processes, functions, properties, and procedures. , subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables.

The functions provided within components and parts can be combined into smaller numbers of components and parts or separated from additional components and parts. In addition, the components and 'parts' may be implemented to regenerate one or more CPUs within the device or secure multimedia card.

The method according to the embodiment described through the drawings may also be implemented in the form of a computer-readable medium that stores instructions and data executable by a computer. At this time, instructions and data can be stored in the form of program code, and when executed by a processor, they can generate a certain program module and perform a certain operation. Additionally, computer-readable media can be any available media that can be accessed by a computer and includes both volatile and non-volatile media, removable and non-removable media. Additionally, computer-readable media may be computer recording media, which are volatile media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules, or other data. and non-volatile, removable and non-removable media. For example, computer recording media may be magnetic storage media such as HDDs and SSDs, optical recording media such as CDs, DVDs, and Blu-ray discs, or memory included in servers accessible through a network.

Additionally, the method according to an embodiment of the present invention may be implemented as a computer program (or computer program product) including instructions executable by a computer. A computer program includes programmable machine instructions processed by a processor and can be implemented in a high-level programming language, object-oriented programming language, assembly language, or machine language. there is. Additionally, the computer program may be recorded on a tangible computer-readable recording medium (e.g., memory, hard disk, magnetic/optical medium, or solid-state drive (SSD), etc.)

Accordingly, the method according to the embodiment described in the present invention can be implemented by executing the above-described computer program by a computing device. The computing device may include at least some of a processor, memory, a storage device, a high-speed interface connected to the memory and a high-speed expansion port, and a low-speed interface connected to a low-speed bus and a storage device. Each of these components is connected to each other using various buses and may be mounted on a common motherboard or in some other suitable manner.

Here, the processor can process instructions within the computing device, such as displaying graphical information to provide a graphic user interface (GUI) on an external input or output device, such as a display connected to a high-speed interface. These may include instructions stored in memory or a storage device. In other embodiments, multiple processors and/or multiple buses may be utilized along with multiple memories and memory types as appropriate. Additionally, the processor may be implemented as a chipset consisting of chips including multiple independent analog and/or digital processors.

Memory also stores information within a computing device. In one example, memory may be comprised of volatile memory units or sets thereof. As another example, memory may consist of non-volatile memory units or sets thereof. The memory may also be another type of computer-readable medium, such as a magnetic or optical disk.

And the storage device can provide a large amount of storage space to the computing device. A storage device may be a computer-readable medium or a component containing such a medium, for example, devices within a storage area network (SAN) or other components, such as a floppy disk device, a hard disk device, or an optical disk device. , or it may be a tape device, flash memory, or other similar semiconductor memory device or device array.

The above-described embodiments are for illustrative purposes, and those of ordinary skill in the technical field to which the above-described embodiments belong can easily transform them into other specific forms without changing the technical idea or essential features of the above-described embodiments. You will be able to understand it. Therefore, the above-described embodiments should be understood in all respects as illustrative and not restrictive. For example, each component described as unitary may be implemented in a distributed manner, and similarly, components described as distributed may also be implemented in a combined form.

The scope sought to be protected through this specification is indicated by the patent claims described later rather than the detailed description above, and should be interpreted to include the meaning and scope of the claims and all changes or modified forms derived from the equivalent concept. .

a-Rial, F.; Hernndez, C.; Montesano, D.; Godino-Llorente, J.I.; Grajal, J. Cardiopulmonary Activity Monitoring Using Millimeter Wave Radars. Remote Sens. 2020, 12, 2265.
[4] Y. S. Lee, P. N. Pathirana, C. L. Steinfort and T. Caelli, "Monitoring and Analysis of Respiratory Patterns Using Microwave Doppler Radar," in IEEE Journal of Translational Engineering in Health and Medicine, vol. 2, pp. 1-12, 2014.
[5] I.V. Mikhelson, S. Bakhtiari, T.W. Elmer II, and A.V. Sahakian, "Remote ensing f atterns f ardiac ctivity n n mbulatory ubject sing illimeter-wave nterferometry nd tatistical ethods,”Med. iol. ng. omput., ol. 1, pp. 135-142, October 2012.
[6] Valenzuela, A.; Sibuet, N.; Hornero, G.; Casas, O. Non-Contact Video-Based Assessment of the Respiratory Function Using a RGB-D Camera. Sensors 2021, 21, 5605.
[7] K. Abbas, K. Heiman, T. Orlikowsky, S. Leonhardt. “t respiratory monitoring based on real-time IR-thermography,”in FMBE roc. f C2009, 5/IV, 009, p.1306-1309.
[8] A. Tariq and H. Ghafouri-Shiraz, "Vital signs detection using Doppler radar and continuous wavelet Transform," Proceedings of the 5th European Conference on Antennas and Propagation (EUCAP), 2011, pp. 285-288.
[9] Zhang, X.; Yang, X.; Ding, Y.; Wang, Y.; Zhou, J.; Zhang, L. Contactless Simultaneous Breathing and Heart Rate Detections in Physical Activity Using IR-UWB Radars. Sensors 2021, 21, 5503.
[10] Y. S. Lee, P. N. Pathirana, C. L. Steinfort and T. Caelli, "Monitoring and Analysis of Respiratory Patterns Using Microwave Doppler Radar," in IEEE Journal of Translational Engineering in Health and Medicine, vol. 2, pp. 1-12, 2014, Art no. 1800912.
[11] D. Rissacher and D. Galy, "Cardiac radar for biometric identification using nearest neighbour of continuous wavelet transform peaks," IEEE International Conference on Identity, Security and Behavior Analysis (ISBA 2015), 2015, pp. 1-6.
[12] S. Tomii and T. Ohtsuki, "Heartbeat detection by using Doppler radar with wavelet transform based on scale factor learning," 2015 IEEE International Conference on Communications (ICC), 2015, pp. 483-488.
[13] Hu, X.; Jin, T. Short-Range Vital Signs Sensing Based on EEMD and CWT Using IR-UWB Radar. Sensors 2016, 16, 2025.
[14] T. Zhangi, G. Valerio, J. Sarrazin and D. Istrate, "Wavelet-based analysis of 60 GHz Doppler radar for non-stationary vital sign monitoring," 2017 11th European Conference on Antennas and Propagation (EUCAP), 2017, pp. 1876-1877.
[15] M. Li and J. Lin, "Wavelet-Transform-Based Data-Length-Variation Technique for Fast Heart Rate Detection Using 5.8-GHz CW Doppler Radar," in IEEE Transactions on Microwave Theory and Techniques, vol. 66, no. 1, pp. 568-576, Jan. 2018.
[16] N. T. P. Van, L. Tang, A. Singh, N. D. Minh, S. C. Mukhopadhyay and S. F. Hasan, "Self-Identification Respiratory Disorder Based on Continuous Wave Radar Sensor System," in IEEE Access, vol. 7, pp. 40019-40026, 2019.
[17] F. Wang, T. Horng, K. Peng, H. Jau, J. Li, and C. Chen, “of oncealed ndividuals ased n heir ital igns y sing ee-throughwall maging ystem ith elf-injection-locked adar,"IEEE rans. icrow. heory Techn., vol. 61, no. 1, pp. 696-704, 2013.
[18] Z. Peng et al., "A Portable FMCW Interferometry Radar With Programmable Low-IF Architecture for Localization, ISAR Imaging, and Vital Sign Tracking," in IEEE Transactions on Microwave Theory and Techniques, vol. 65, no. 4, pp. 1334-1344, April 2017
[19] R. R. Fletcher and S. Kulkarni, "Wearable Doppler radar with integrated antenna for patient vital sign monitoring," 2010 IEEE Radio and Wireless Symposium (RWS), 2010, pp. 276-279.
[20] R. Kukkapalli, N. Banerjee, R. Robucci and Y. Kostov, "Micro-radar wearable respiration monitor," 2016 IEEE SENSORS, 2016, pp. 1-3
[21] D. Zito et al., "Wearable System-on-a-Chip UWB Radar for Health Care and its Application to the Safety Improvement of Emergency Operators," 2007 29th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2007, pp. 2651-2654.
[22] J. E. Johnson, O. Shay, C. Kim and C. Liao, "Wearable Millimeter-Wave Device for Contactless Measurement of Arterial Pulses," in IEEE Transactions on Biomedical Circuits and Systems, vol. 13, no. 6, pp. 1525-1534, Dec. 2019.
[23] I. S. Barak, “Microwave contactless heart rate sensor," Sensifree Ltd. (Kfar ava, IL), U.S. patent Grant 9,713,434 B2, Jul. 25, 2017.
[24] M. C. Tang, C. M. Liao, F. K. Wang, and T. S. Horng, “Noncontact pulse transit time measurement using a single-frequency continuous-wave radar,”in Proc. IEEE MTT-S Int. Microw. Symp. Dig., 2018, vol. 2018, pp. 1409-1412.
[25] P. RamaRaju, N. Aurora and V. Rao, “Relevance of wavelet transform for taxonomy of EEG signals”electronics computer technology (ICECT), 3rd international conference on, 2011, pp. 466-470.
[26] A. Diery, D. Rowlands, T.R.H. Cutmore and D. James, “ECG diagnostic P-wave analysis using wavelets,”computer methods and programs in biomedicine, vol 101, pp.33-43, 2011.
[27] T. Rondik and J. Ciniburk, “Comparison of various approaches for P3 component detection using basic methods for signal processing,”in Biomedical Engineering and Informatics (BMEI), 2011 4th international. Conference, 2011, pp. 698-702.
[28] Y. T. Qassim, T. Cutmore, D. James and D. Rowlands, "FPGA implementation of Morlet continuous wavelet transform for EEG analysis," 2012 International Conference on Computer and Communication Engineering (ICCCE), 2012, pp. 59-64.
[29] Yahya T. Qassim, Tim RH Cutmore, David D. Rowlands, Optimized FPGA based continuous wavelet transform, Computers & Electrical Engineering 49 (2016) 84-94.
[30] Jeon, H.; Jung, Y.; Lee, S.; Jung, Y. Area-Efficient Short-Time Fourier Transform Processor for Time-Frequency Analysis of Non-Stationary Signals. Appl. Sci. 2020, 10, 7208.
[31] Y. Jung, H. Yoon, J. Kim, “efficient FFT algorithm and pipeline implementation results for OFDM/DMT applications,”IEEE Trans. Consumer Electron, vol. 49, pp. 14-20, Feb. 2003.
[32] Shousheng He and M. Torkelson, "A new approach to pipeline FFT processor," Proceedings of International Conference on Parallel Processing, 1996, pp. 766-770
[33] N. Srinivas, P. K. Kumar and G. Pradhan, "Low latency architecture design and implementation for short-time fourier transform algorithm on FPGA," 2017 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS), pp. 1-5, Nov 2017.
[34] S. Lee, Y. Jung, and J. Kim, “complexity ipeline FFT processor for MIMO-OFDM systems,”IEICE lectron. xpress, ol. , o. 3, p. 50-754, ec. 007
[35] S. Tomii and T. Ohtsuki, "Heartbeat detection by using Doppler radar with wavelet transform based on scale factor learning," 2015 IEEE International Conference on Communications (ICC), 2015, pp. 483-488
[36] Sansaloni, T.; Perez-Pascual, A.; Torres, V.; Valls, J. Efficient pipeline FFT processors for WLAN MIMO-OFDM systems. IET Electorn. Lett. 2005, 41, 1043-1044
[37] Lee, T. Y.; Huang, C. H.; Chen, W. C.; Liu, M. J. A low-area dynamic reconfigurable MDC FFT processor design. Microprocess. Microsyst. 2016, 42, 227-234.
[38] S. Jang, et al.: “FFT rocessor or IMO-OFDM ased DR ystems,"EICE lectron. Express 10 (2013) 20130490.
[39] G. Yang and Y. Jung, "Scalable FFT processor for MIMO-OFDM based SDR systems," IEEE 5th International Symposium on Wireless Pervasive Computing 2010, 2010, pp. 517-521
[40] Bostanov V. BCI competition 2003-data sets Ib and IIb: feature extraction from event-related brain potentials with the continuous wavelet transform and the t-value scalogram. Biomed Eng, IEEE Trans 2004;51:1057-61.
[41] Patil S, Abel E. Real time continuous wavelet transform implementation on a DSP processor. J Med Eng Technol 2009;33:223-31.
[42] Kang S, Xuezeng P, Lingdi P. A reconfigurable computing engine for wavelet transforms. In: Parallel and distributed processing symposium, 2007. IPDPS 2007. IEEE International; 2007. p. 1-5.
[43] Mao, L., Ma, J., Chen, H., Ma, Y., Chen, S., & Xu, C. (2019). 2D-CWT IP core design and implementation for fringe pattern analysis. IOP Conference Series: Materials Science and Engineering, 569, 032071.100: continuous wavelet transform device
200: R2SDF FFT module
300: SRAM
400: Multiplier
500: MRMDC IFFT module
[references]
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[2] Khanam, F.-T.-Z.; Perera, A.G.; Al-Naji, A.; Gibson, K.; Chahl, J. Non-Contact Automatic Vital Signs Monitoring of Infants in a Neonatal Intensive Care Unit Based on Neural Networks. J. Imaging 2021, 7, 122.
[3] Antolinos, E.; Garc

a-Rial, F.; Hern ndez, C.; Montesano, D.; Godino-Llorente, JI; Grajal, J. Cardiopulmonary Activity Monitoring Using Millimeter Wave Radars. Remote Sens. 2020, 12, 2265.
[4] YS Lee, PN Pathirana, CL Steinfort and T. Caelli, “Monitoring and Analysis of Respiratory Patterns Using Microwave Doppler Radar,” in IEEE Journal of Translational Engineering in Health and Medicine, vol. 2, pp. 1-12, 2014.
[5] IV Mikhelson, S. Bakhtiari, TW Elmer II, and AV Sahakian, “Remote ensing f atterns f ardiac ctivity nn mbulatory ubject sing illimeter-wave nterferometry nd tatistic ethods,” Med. iol. ng. omput., ol. 1, pp. 135-142, October 2012.
[6] Valenzuela, A.; Sibuet, N.; Hornero, G.; Casas, O. Non-Contact Video-Based Assessment of the Respiratory Function Using a RGB-D Camera. Sensors 2021, 21, 5605.
[7] K. Abbas, K. Heiman, T. Orlikowsky, and S. Leonhardt. “t respiratory monitoring based on real-time IR-thermography,” in FMBE roc. f C2009, 5/IV, 009, p.1306-1309.
[8] A. Tariq and H. Ghafouri-Shiraz, “Vital signs detection using Doppler radar and continuous wavelet Transform,” Proceedings of the 5th European Conference on Antennas and Propagation (EUCAP), 2011, pp. 285-288.
[9] Zhang, X.; Yang, X.; Ding, Y.; Wang, Y.; Zhou, J.; Zhang, L. Contactless Simultaneous Breathing and Heart Rate Detections in Physical Activity Using IR-UWB Radars. Sensors 2021, 21, 5503.
[10] YS Lee, PN Pathirana, CL Steinfort and T. Caelli, “Monitoring and Analysis of Respiratory Patterns Using Microwave Doppler Radar,” in IEEE Journal of Translational Engineering in Health and Medicine, vol. 2, pp. 1-12, 2014, Art no. 1800912.
[11] D. Rissacher and D. Galy, “Cardiac radar for biometric identification using nearest neighbor of continuous wavelet transform peaks,” IEEE International Conference on Identity, Security and Behavior Analysis (ISBA 2015), 2015, pp. 1-6.
[12] S. Tomii and T. Ohtsuki, "Heartbeat detection by using Doppler radar with wavelet transform based on scale factor learning," 2015 IEEE International Conference on Communications (ICC), 2015, pp. 483-488.
[13] Hu, X.; Jin, T. Short-Range Vital Signs Sensing Based on EEMD and CWT Using IR-UWB Radar. Sensors 2016, 16, 2025.
[14] T. Zhangi, G. Valerio, J. Sarrazin and D. Istrate, “Wavelet-based analysis of 60 GHz Doppler radar for non-stationary vital sign monitoring,” 2017 11th European Conference on Antennas and Propagation (EUCAP), 2017, pp. 1876-1877.
[15] M. Li and J. Lin, “Wavelet-Transform-Based Data-Length-Variation Technique for Fast Heart Rate Detection Using 5.8-GHz CW Doppler Radar,” in IEEE Transactions on Microwave Theory and Techniques, vol. 66, no. 1, pp. 568-576, Jan. 2018.
[16] NTP Van, L. Tang, A. Singh, ND Minh, SC Mukhopadhyay and SF Hasan, “Self-Identification Respiratory Disorder Based on Continuous Wave Radar Sensor System,” in IEEE Access, vol. 7, pp. 40019-40026, 2019.
[17] F. Wang, T. Horng, K. Peng, H. Jau, J. Li, and C. Chen, “of oncealed individuals ased n heir ital igns y sing ee-throughwall maging ystem ith elf-injection-locked adar, "IEEE rans. icrow. heory Techn., vol. 61, no. 1, pp. 696-704, 2013.
[18] Z. Peng et al., “A Portable FMCW Interferometry Radar With Programmable Low-IF Architecture for Localization, ISAR Imaging, and Vital Sign Tracking,” in IEEE Transactions on Microwave Theory and Techniques, vol. 65, no. 4, pp. 1334-1344, April 2017
[19] R. R. Fletcher and S. Kulkarni, "Wearable Doppler radar with integrated antenna for patient vital sign monitoring," 2010 IEEE Radio and Wireless Symposium (RWS), 2010, pp. 276-279.
[20] R. Kukkapalli, N. Banerjee, R. Robucci and Y. Kostov, “Micro-radar wearable respiration monitor,” 2016 IEEE SENSORS, 2016, pp. 1-3
[21] D. Zito et al., "Wearable System-on-a-Chip UWB Radar for Health Care and its Application to the Safety Improvement of Emergency Operators," 2007 29th Annual International Conference of the IEEE Engineering in Medicine and Biology Society , 2007, pp. 2651-2654.
[22] J.E. Johnson, O. Shay, C. Kim and C. Liao, “Wearable Millimeter-Wave Device for Contactless Measurement of Arterial Pulses,” in IEEE Transactions on Biomedical Circuits and Systems, vol. 13, no. 6, pp. 1525-1534, Dec. 2019.
[23] IS Barak, “Microwave contactless heart rate sensor,” Sensifree Ltd. (Kfar ava, IL), US patent Grant 9,713,434 B2, Jul. 25, 2017.
[24] MC Tang, CM Liao, FK Wang, and TS Horng, “Noncontact pulse transit time measurement using a single-frequency continuous-wave radar,” in Proc. IEEE MTT-S Int. Microw. Symp. Dig., 2018, vol. 2018, pp. 1409-1412.
[25] P. RamaRaju, N. Aurora and V. Rao, “Relevance of wavelet transform for taxonomy of EEG signals”electronics computer technology (ICECT), 3rd international conference on, 2011, pp. 466-470.
[26] A. Diery, D. Rowlands, TRH Cutmore and D. James, “ECG diagnostic P-wave analysis using wavelets,” computer methods and programs in biomedicine, vol 101, pp.33-43, 2011.
[27] T. Rondik and J. Ciniburk, “Comparison of various approaches for P3 component detection using basic methods for signal processing,” in Biomedical Engineering and Informatics (BMEI), 2011 4th international. Conference, 2011, pp. 698-702.
[28] YT Qassim, T. Cutmore, D. James and D. Rowlands, "FPGA implementation of Morlet continuous wavelet transform for EEG analysis," 2012 International Conference on Computer and Communication Engineering (ICCCE), 2012, pp. 59-64.
[29] Yahya T. Qassim, Tim RH Cutmore, David D. Rowlands, Optimized FPGA based continuous wavelet transform, Computers & Electrical Engineering 49 (2016) 84-94.
[30] Jeon, H.; Jung, Y.; Lee, S.; Jung, Y. Area-Efficient Short-Time Fourier Transform Processor for Time-Frequency Analysis of Non-Stationary Signals. Appl. Sci. 2020, 10, 7208.
[31] Y. Jung, H. Yoon, J. Kim, “efficient FFT algorithm and pipeline implementation results for OFDM/DMT applications,” IEEE Trans. Consumer Electronics, vol. 49, pp. 14-20, Feb. 2003.
[32] Shousheng He and M. Torkelson, “A new approach to pipeline FFT processor,” Proceedings of International Conference on Parallel Processing, 1996, pp. 766-770
[33] N. Srinivas, PK Kumar and G. Pradhan, "Low latency architecture design and implementation for short-time fourier transform algorithm on FPGA," 2017 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS), pp . 1-5, Nov 2017.
[34] S. Lee, Y. Jung, and J. Kim, “complexity ipeline FFT processor for MIMO-OFDM systems,” IEICE lectron. xpress, ol. ,o. 3, p. 50-754, ec. 007
[35] S. Tomii and T. Ohtsuki, “Heartbeat detection by using Doppler radar with wavelet transform based on scale factor learning,” 2015 IEEE International Conference on Communications (ICC), 2015, pp. 483-488
[36] Sansaloni, T.; Perez-Pascual, A.; Torres, V.; Valls, J. Efficient pipeline FFT processors for WLAN MIMO-OFDM systems. IET Elector. Lett. 2005, 41, 1043-1044
[37] Lee, T.Y.; Huang, C.H.; Chen, W.C.; Liu, MJ A low-area dynamic reconfigurable MDC FFT processor design. Microprocess. Microsystem. 2016, 42, 227-234.
[38] S. Jang, et al.: “FFT processor or IMO-OFDM ased DR systems,” EICE lectron. Express 10 (2013) 20130490.
[39] G. Yang and Y. Jung, “Scalable FFT processor for MIMO-OFDM based SDR systems,” IEEE 5th International Symposium on Wireless Pervasive Computing 2010, 2010, pp. 517-521
[40] Bostanov V. BCI competition 2003-data sets Ib and IIb: feature extraction from event-related brain potentials with the continuous wavelet transform and the t-value scalogram. Biomed Eng, IEEE Trans 2004;51:1057-61.
[41] Patil S, Abel E. Real time continuous wavelet transform implementation on a DSP processor. J Med Eng Technol 2009;33:223-31.
[42] Kang S, Xuezeng P, Lingdi P. A reconfigurable computing engine for wavelet transforms. In: Parallel and distributed processing symposium, 2007. IPDPS 2007. IEEE International; 2007.p. 1-5.
[43] Mao, L., Ma, J., Chen, H., Ma, Y., Chen, S., & Xu, C. (2019). 2D-CWT IP core design and implementation for fringe pattern analysis. IOP Conference Series: Materials Science and Engineering, 569, 032071.

Claims (18)

R2SDF FFT module that performs FFT processing on input signals;
4 SRAMs for reordering the FFT processing results of the R2SDF FFT module into 4 channels;
Four wavelet SRAMs with initialized daughter wavelet values in the frequency domain;
4 multipliers for the 4-channel multiplication; and
A continuous wavelet transform device including an MRMDC IFFT module with a 4-channel parallel input structure that IFFT processes the calculated values of the four multipliers.
According to paragraph 1,
The R2SDF FFT module is
A continuous wavelet transform device based on the radix-2 algorithm and characterized by an SDF pipeline structure with an exchange relationship between speed and area for 1-channel input.
According to paragraph 1,
The R2SDF FFT module is
A continuous wavelet transform device that supports 8/16/32/64/128/256/1024-point variable points by selecting the input signal to be used for calculation at each stage.
According to paragraph 1,
The four wavelet SRAMs are
Initializes up to 24 wavelet signals in the frequency domain with a maximum length of 1024 points,
A continuous wavelet transform device characterized in that the number of initialized wavelet signals is controlled from a minimum of 4 to multiples of 4 using an external input signal.
According to paragraph 1,
Each of the four multipliers is
A continuous wavelet transform device that multiplies the FFT result data of the input signal stored in the SRAM and the value initialized in the Wavelet SRAM and then outputs the data to the input terminal of the IFFT module in the form of a stream.
According to clause 5,
The MRMDC IFFT module is a continuous wavelet transform device with a 4-channel input pipeline FFT structure.
According to paragraph 1,
The R2SDF FFT module is
A continuous wavelet transform device characterized by transmitting the FFT results to four SRAMs in bit-reverse order.
According to paragraph 1,
The MRMDC IFFT module is
A continuous wavelet transform device that supports 8/16/32/64/128/256/1024-point variable points to select the input signal to be used for calculation at each stage.
According to paragraph 1,
A continuous wavelet transform device characterized in that when using M scales for a signal with a length of N-point, the total operation cycle is 2N+M/4(N).
FFT processing the input signal in the R2SDF FFT module;
Reordering the FFT processing results of the R2SDF FFT module in 4 SRAMs to 4 channels;
Performing element-by-element multiplication in four multipliers with the FFT processing results stored in four SRAMs and the daughter wavelets values in the frequency domain of the input signal stored in four wavelet SRAMs;
A continuous wavelet transform method comprising IFFT processing the operation values of the four multipliers in an MRMDC IFFT module with a 4-channel parallel input structure.
According to clause 10,
The R2SDF FFT module is
A continuous wavelet transform method based on the radix-2 algorithm and characterized by an SDF pipeline structure with an exchange relationship between speed and area for 1-channel input.
According to clause 11,
The FFT processing step is
A continuous wavelet transform method comprising the step of supporting 8/16/32/64/128/256/1024-point variable points to select an input signal to be used for calculation at each stage of the R2SDF FFT module.
According to clause 11,
The four wavelet SRAMs are
Initializes up to 24 wavelet signals in the frequency domain with a maximum length of 1024 points,
A continuous wavelet transform method characterized in that the number of initialized wavelet signals used is controlled from a minimum of 4 to multiples of 4 using an external input signal.
According to clause 11,
The step of performing element-by-element multiplication with the daughter wavelets value in the frequency domain of the input signal is
A continuous wavelet transform method comprising multiplying the FFT result data of the input signal stored in the SRAM and the value initialized in the Wavelet SRAM in a multiplier and then outputting the data to the input terminal of the IFFT module in the form of a stream. .
According to clause 11,
The MRMDC IFFT module is a continuous wavelet transform method with a 4-channel input pipeline FFT structure.
According to clause 11,
The FFT processing step is
A continuous wavelet transform method comprising the step of the R2SDF FFT module transmitting the FFT results to four SRAMs in bit-reverse order.
According to clause 11,
The IFFT processing step is
A continuous wavelet transform method comprising supporting 8/16/32/64/128/256/1024-point variable points in the MRMDC IFFT module to select an input signal to be used for calculation at each stage.
According to clause 11,
A continuous wavelet transform method, characterized in that when the total calculation cycle uses M scales, the total number of calculation cycles is 2N+M/4(N).