KR102635470B1 - Signal stabilizing method and signal stabilizing apparatus - Google Patents

Abstract

The signal stabilization apparatus of this embodiment includes a consistency determination unit that determines whether one or more matching bits included in a serial signal including a channel field and a data field conform to a consistency rule; a selection signal generator for generating a selection signal corresponding to the position of the data field from a clock signal synchronized with the serial signal, and initializing the selection signal generator if the one or more matching bits do not meet a consistency rule. It includes an initialization signal generator that generates an initialization signal.

Description

Signal stabilization method and signal stabilization device {SIGNAL STABILIZING METHOD AND SIGNAL STABILIZING APPARATUS}

The present technology relates to signal stabilization methods and signal stabilization devices.

The superconducting quantum interference device, called SQUID (Superconducting Quantum Interference Device) sensor, is a device that sensitively and precisely measures small magnetic fields and is based on a superconducting loop containing a Josephson junction. This superconducting quantum interference device can be applied to a multi-channel MCG (Magnetocardiograph) system such as 64 or 96 channels and a 128 channel MEG (Magnetoencepharograph) system.

The device operates electrically and magnetically sensitively. Therefore, when transmitting a signal to a multi-channel device, it is necessary to minimize the intervention of noise. To this end, the signal formed in the user terminal is transmitted to the receiving side through an optical cable to control the device.

The optical signal transmitted through the optical cable is converted into an electrical signal at the receiving end. The electrical signal may include channel selection-related information for selecting a channel in a multi-channel device and information corresponding to voltage, current, etc. provided to the channel.

Noise may be introduced during the process of forming an electrical signal corresponding to an optical signal on the receiving side, and in this case, the desired electrical signal may not be formed, and from this, information related to channel selection or voltage or current may be obtained. It cannot be distinguished from the corresponding information. Accordingly, errors may occur in channel selection and/or errors in electrical information.

Digital noise occurs on the user side and is converted into an optical signal and transmitted through an optical cable, or occurs in the user's system and mainly occurs when the user's terminal first operates. Additionally, when specific software operates on the user's terminal, unintended digital signals may be generated, converted to optical signals, and transmitted through optical cables.

To prevent this, you can first start the computer to stabilize it so that the digital noise signal does not pass through the optical cable, and then drive the receiving side to prevent the digital noise from reacting on the receiving side. Meanwhile, while the receiving side is operating normally, digital noise may be formed when certain software operates on the user side. When digital noise is converted into an optical signal and transmitted through an optical cable, and the serial signal restorer malfunctions, the receiving system is turned off and forced to restart to remove the incoming digital noise signal and then receive a retransmission of the signal from the user.

By transmitting a reset signal without restarting the power, the receiving side can be reset when a specific digital signal is detected by the receiver, but a part of the digital signal without noise may be identical to the specific digital signal. In this case, the receiving side may be reset unnecessarily by a signal without noise, and if this occurs, the device must be forced to restart.

As another method, if a certain number of digital signals 1 or 0 are continuously transmitted, the receiver detects this and activates a timer to forcibly erase all input and output signals of the signal restoration device for a certain period of time, thereby initializing the receiving side. In this case, the erasing time is not constant, so a sufficient elapsed time is required after initialization starts, so there is a disadvantage in that the control signal is transmitted again after a certain period of time has elapsed, and an external hardware timer is required.

One of the technical challenges to be solved with this technology is to solve the difficulties of the prior art described above. In other words, providing a technology for stabilizing signals generated from optical signals without restarting the receiving side is one of the technical challenges to be solved with this technology.

The signal stabilization method of this embodiment includes the steps of receiving an optical signal including a channel field and a data field, forming a serial signal that is an electrical signal including a channel field and a data field from the optical signal, and the serial signal It includes determining the consistency of and forming a selection signal corresponding to the position of the data field in the serial signal.

According to one aspect of this embodiment, in the step of forming the channel field and the data field, a clock signal synchronized with the channel field and the data field is further formed.

According to one aspect of this embodiment, the step of determining the consistency of the serial signal is performed by determining whether two or more bits at predetermined positions in the channel field correspond to a consistency rule.

According to one aspect of this embodiment, the signal stabilization method includes the step of determining consistency of the data field after forming the selection signal.

According to one aspect of this embodiment, the step of determining the consistency of the data field is performed by determining whether two or more bits at predetermined positions in the data field correspond to a predetermined rule.

According to one aspect of this embodiment, the signal stabilization method is performed in a multi-channel magnetocardiograph (MCG) system and a multi-channel magnetoencephalograph (MEG) system.

The signal stabilization apparatus of this embodiment includes a consistency determination unit that determines whether one or more matching bits included in a serial signal including a channel field and a data field conform to a consistency rule; a selection signal generator for generating a selection signal corresponding to the position of the data field from a clock signal synchronized with the serial signal, and initializing the selection signal generator if the one or more matching bits do not meet a consistency rule. It includes an initialization signal generator that generates an initialization signal.

According to one aspect of this embodiment, the consistency determination unit outputs a serial register in which the one or more flip-flops provided with the one or more consistency bits are cascaded, and the one or more consistency bits maintained in the serial register in parallel. a parallel register containing the one or more flip-flops; and a logic operation unit that calculates the output of the parallel register using the consistency rule.

According to one aspect of this embodiment, the signal stabilization device further includes a pulse generator that outputs a pulse upon receiving the clock signal corresponding to the number of the consistency bits, wherein the consistency determination unit receives the pulse, It further includes a sampling clock generator that generates and outputs a sampling clock of the parallel register.

According to one aspect of this embodiment, the serial signal further includes a preparation field, and the consistency bit is included in the channel field or the preparation field.

According to one aspect of this embodiment, the ready field has a bit sequence that does not conform to the consistency rule.

According to one aspect of this embodiment, the selection signal generator includes a binary counter that receives the inverted clock signal and counts it; Selection signal generation logic for forming a selection signal corresponding to the position of the data field in the serial signal from the output of the binary counter, and logic for generating the binary counter and the selection signal upon input of a clock corresponding to the number of bits of the data field. It includes a clear signal generation logic that generates a clear signal to clear.

According to one aspect of this embodiment, the selection signal generation logic forms and outputs a leading edge of the selection signal from the value output by the binary counter counting the number of clocks corresponding to the start of the data field, and outputs the binary counter. The counter is initialized according to the initialization signal and outputs the trailing edge of the selection signal.

According to one aspect of this embodiment, the output of the binary counter is cleared to a predetermined logic level by the clear signal, and the binary counter is initialized by the initialization signal.

According to one aspect of this embodiment, the signal stabilization device is included in a multi-channel magnetocardiograph (MCG) system and a multi-channel magnetoencephalograph (MEG) system.

According to this embodiment, the advantage of stabilizing the signal is provided by minimizing the influence of noise involved in the signal.

Figure 1 is a block diagram showing the outline of a system including the signal stabilization device 10 according to this embodiment.
FIG. 2 is a diagram showing an outline of signals formed at the receiving side without noise intervening. FIG. 2(a) is a diagram showing a serial signal without noise intervening, and FIG. 2(b) is a diagram illustrating a serial signal without noise intervening. ) is a diagram showing a clock signal without noise, and FIG. 2(c) is a diagram showing a selection signal without noise.
Figure 3 is a diagram showing the outline of the stabilizer 10 according to this embodiment.
4 shows serial signals and values stored in parallel registers. This is an example timing diagram showing the output and electrical signals of the counter.
5 shows a serial signal and a value stored in a parallel register in an embodiment of transmitting a preparation field prior to transmitting a channel field in serial data (SD). This is an example timing diagram showing the number of bits in the output and ready fields of the counter.
FIG. 6 is an exemplary timing diagram illustrating a case in which noise in a logic high state intervenes in an embodiment of transmitting a preparation field prior to transmitting a channel field in serial data.
FIG. 7 is an exemplary timing diagram illustrating a case in which noise in a logic low state intervenes in an embodiment of transmitting a preparation field prior to transmitting a channel field in serial data.
FIG. 8 is an exemplary timing diagram illustrating a case in which multiple bits of noise intervene in an embodiment of transmitting a preparation field prior to transmitting a channel field in serial data.

Hereinafter, this embodiment will be described with reference to the attached drawings. In describing embodiments, logic high and logic low represent two contrasting states of a signal and are not necessarily connected to a specific voltage level such as a driving voltage (VDD) or ground voltage. Additionally, in describing the embodiments, an active high signaling scheme and rising edge sampling will be used. However, if it operates using an active low signaling scheme and a falling edge sampling scheme, this should be clearly explained.

The above-described operating methods are not intended to limit the invention, but are intended to easily explain the invention. Furthermore, based on the described embodiments, a person skilled in the art can easily modify and implement them in other ways.

Figure 1 is a block diagram showing the outline of a system including the signal stabilization device 10 according to this embodiment. Figure 2 is a diagram showing an outline of signals formed on the receiver side without noise, and Figure 2(a) shows a serial signal (SD) without noise. 2(b) is a diagram showing the clock signal (CLK) without noise, and FIG. 2(c) is a diagram showing the selection signal (CS) without noise. It is a drawing.

Referring to Figures 1 and 2, the system includes a user side and a receiver side that receives a signal from the user side through an optical cable (OC).

The user side is a terminal through which the user can input parameters, commands, etc. to form a control signal to control a device (not shown) connected to the receiver side. It includes a digital output unit that outputs a signal formed by a terminal as a digital signal, and an optical converter that converts the digital signal output from the digital output unit into an optical signal. can do.

The signal converted and output by the optical converter is provided to the receiver side through an optical cable (OC). The receiver side receives the optical signal and outputs the signal by removing the influence of noise. The receiver side has a signal conv. and a signal conv. that stabilize the serial signal (SD) and convert it into a serial signal (SD), which is the corresponding electrical signal. It includes a clock generator (CLK gen.) that forms a clock signal (CLK) synchronized from one signal and a stabilizer (100) that forms a selection signal (CS).

The clock generator (CLK gen.) receives the serial signal (SD), forms a clock signal (CLK) synchronized with the electrical signal, and outputs it. In one embodiment, the clock generator (CLK gen.) may include a clock data recovery (CDR) circuit that restores data and clock signals from the serial signal (SD). In another embodiment, the clock generator (CLK gen.) may include a phase locked loop (PLL) or a delay locked loop (DLL) that restores a clock signal from the serial signal (SD).

The serial signal (SD) output from the signal converter may be a serial signal in which a channel field (CH.) and a data field (DATA) are continuous. In the example shown, the channel field (CH.) includes 8 bits, and the data field (DATA) includes 16 bits. However, this is only an example, and the number of bits forming the channel field (CH.) and data field (DATA) may change.

As illustrated in FIG. 2(a), the serial signal (SD) may include a channel field (CH.) and a data field (DATA). The channel field (CH.) is a field in which information for selecting a channel of a device (not shown) connected to the receiver side is transmitted. The data field (DATA) may be information provided to the selected channel, and for example, may be information about the voltage of the selected channel.

In the illustrated embodiment, the serial signal (SD) may be a serial signal in which a channel field (CH.) and a data field (DATA) are sequentially sequential, and the channel field (CH.) is 8 bits of binary information, and the data field ( DATA) may be 16 bits of binary information. However, this is only an example, and the order of fields forming the serial signal SD and the number of bits of binary information forming the fields may be implemented differently.

In one embodiment, the channel field (CH.) may have a value of decimal numbers 0 to 63 or 192 to 255 (binary numbers 0000 0000 to 0011 1111 or 1100 0000 - 1111 1111). In one embodiment, the first two bits of the channel field (CH.) may be matching bits, and the matching bit (M) is formed to comply with the matching rule. For example, the consistency rule is to ensure that a logical row is formed as a result of an XOR operation. Therefore, when the consistency bit (M) is two bits and the binary number 00 or 11 is used, the consistency rule is satisfied. However, the number of consistency bits (M) and consistency rules may vary depending on the embodiment.

In addition, the consistency bit (M) is shown as the first two bits of the channel field (CH.) included in the serial signal (SD), but in an embodiment not shown, the serial signal (SD) has a continuous data field and a channel field. In this case, the consistency bit (M) may be the first bits of the data field.

The data field (DATA) is 16 bits following the channel field (CH.) in the serial signal (SD). In one embodiment, the data field (DATA) is a code corresponding to the voltage output by a device (not shown) and activates a digital to analog converter (DAC) included in the device (not shown). The data field (DATA) includes an activation code for operating the DAC of the channel selected in the channel field (CH.). The DAC included in the device is activated by an activation code.

In one embodiment, the activation code of the DAC includes control bits and random bits. For example, the control bits are 4 bits and may be the binary number 1011, and the random bits are 12 bits and may be a random bit sequence.

After the activation code is provided and the DAC is activated, the lower channel is selected by outputting the ADC's sub-selection code as a control bit. In addition, data corresponding to the voltage is output using 12 data bits, so that the lower channel outputs the corresponding analog voltage. In one embodiment, the activation code may be transmitted once for the first time when driving to activate the DAC.

In one embodiment, the serial signal SD may further include a ready field (P, see FIG. 5). The preparation field may be transmitted prior to the channel field (CH.) and data field (DATA). In addition, the preparation field is formed so as not to comply with the consistency rule requested in the consistency bit (M), and from this, the preparation field minimizes the effect of noise even when noise intervenes in the serial signal (SD) to maintain the selection signal (CS). Form and stabilize the serial signal (SD).

Figure 3 is a diagram showing an outline of the stabilizer 10 according to this embodiment, and Figure 4 shows a serial signal (SD) and a value stored in a parallel register. This is an example timing diagram showing the output and electrical signals of the counter. 3 and 4, the stabilizer 10 configures one or more matching bits included in a serial signal (SD) including a channel field (CH.) and a data field (DATA) according to a matching rule. A consistency determination unit 110 that determines whether it matches, and a selection signal generator 120 that generates a selection signal (CS) corresponding to the position of the data field (DATA) from a clock signal (CLK) synchronized with the serial signal (SD). ) and an initialization signal generator 130 that generates an initialization signal to initialize the selection signal generator 120 when one or more matching bits do not meet the matching rule. In one embodiment, the stabilizer 10 further includes a pulse generator 140 that outputs a pulse when receiving a clock signal CLK corresponding to the number of consistency bits M in the serial signal SD.

The serial signal SD and the clock signal CLK are input to the serial register 112 of the consistency determination unit 110. As the serial signal SD is sequentially input to the stabilizer 10, the consistency bit M, which is the first two bits of the serial signal SD, is latched up in the serial register 112 by the clock signal CLK.

The binary counter 122 of the selection signal generator 120 receives a clock signal CLK that is inverted and delayed by a half cycle, and outputs a result of counting the pulses of the clock signal CLK. When the binary counter 122 latches up the consistency bit (M), which is the first two bits of the serial signal (SD), to the flip-flop of the serial register 112, the binary counter 122 outputs Q1 as a result of counting the input clock pulse. Convert to logic high state.

The Q1 output of the logic high binary counter is provided as a clock input to the flip-flop of the pulse generator 140 through the AND gate of the pulse generator 140, and the flip-flop of the pulse generator 140 outputs a logic high signal. . The output of the pulse generator 140 is inverted by the inverter and provided as the input of the AND gate, so the input of the AND gate is masked as logic low, and the pulse generator 140 provides a clear signal to the inverted clear (BCLR) input. It is deactivated until

The logic high output signal of the pulse generator 140 is provided as a clock input to the flip-flop of the clock generation logic 116 of the consistency determination portion 110. A clock generation logic 116 flip-flop provided with a clock input provides a logic high sampling clock to parallel register 114 flip-flops. The logic high output of the clock generation logic 116 is inverted to a logic low by the inverter and is input to the inverted clear input of the flip-flop of the clock generation logic 116. Accordingly, the clock generation logic 116 flip-flop is initialized after providing a clock signal to the parallel register 114.

The parallel register 114, which receives the sampling clock signal from the clock generation logic 116, receives the consistency bit (M) provided by the serial register 112 and latches up. The data (d1, d2) latched up by the parallel register 114 is provided to the logic operation unit 118, which performs a logical operation on the input data according to the consistency rules, and is logically operated according to the consistency rules.

In the illustrated embodiment, the consistency rule is an XOR operation, and the logic operation unit 118 is an XOR gate that performs an XOR operation on input data. In another embodiment not shown, the logic operation unit may be implemented as combinational logic, sequential logic, or a combination thereof that performs a predetermined logical operation on input data. As illustrated in FIG. 4, if the data (d1, d2) latched up by the parallel register meets the consistency rule, the output of the logical operation unit 118 maintains a logic low state.

As the 9th clock signal synchronized with the first bit of the data field (DATA) of the serial data (SD) is input to the binary counter 122, the binary counter 122 outputs a logic high state signal through output Q3.

The output Q3 of the binary counter 122 converted to a logic high state is provided as a clock input to the flip-flop of the selection signal generation logic 124 through the AND gate, and the flip-flop of the selection signal generation logic 124 generates the selection signal (CS). The rising edge of is formed and output. Additionally, the output Q3 of the binary counter 122 in the logic high state is inverted by the inverter and provided to the input of the AND gate of the selection signal logic 124 to be masked.

As the 24th clock signal (CLK) synchronized with the last bit of the data field (DATA) is input to the binary counter 122, the binary counter 122 outputs a logic high state signal through outputs Q3 and Q4. The AND gate of the clear signal generation logic 126 generates a clear signal by ANDing the Q3 and Q4 signals in the logic high state.

The clear signal inverted by the inverter is provided as the inverted clear (BCLR) input of the binary counter 122 and the inverted clear (BCLR) input of the selection signal generation logic 124, and is provided to the binary counter 122 and the selection signal generation logic 124. is cleared. As the selection signal generation logic 124 is cleared, a falling edge is formed and output in the selection signal CS.

The clear signal output by the AND gate of the clear signal generation logic 126 is provided to one input of the OR gate of the initialization signal generator 130, and is inverted to generate the flip-flop of the initialization signal generator 130 and the pulse generator 140. It is provided as an inversion clear (BCLR) input of the flip-flop. Therefore, the flip-flop of the initialization signal generator 130 and the flip-flop of the pulse generator 140 are initialized.

5 shows a serial signal (SD), a value stored in a parallel register, in an embodiment of transmitting a preparation field (P) prior to transmission of a channel field (CH.) in serial data (SD). This is an example timing diagram showing the number of bits in the output and ready fields of the counter. Referring to Figures 3 and 5, as the first two bits p1 and p2 of the ready field are input, the ready field is latched up in the serial register 112, and the pulse generator 140 generates a pulse to generate clock generation logic ( 116). The clock generation logic 116 provides a sampling clock to the parallel register 114, and the p1 and p2 bits of the preparation field are latched up in the parallel register 114 and provided to the logic operation unit 118.

As described above, the bit sequence forming the ready field does not comply with the consistency rules of the logical operation unit 118. In the illustrated embodiment, the ready field P alternates between logic low and logic high states. Accordingly, the logic operation unit 118 provides a signal in a logic high state as a clock input to the flip-flop of the initialization signal generation unit 130. The initialization signal generator 130 delays the logic high state signal output from the flip-flop and outputs the inverted initialization signal to the inverted set (BSET) input of the binary counter 122. As an initialization signal is provided to the inverting set (BSET) input, the binary counter 122 is set by switching the Q1 output to a logic high state.

The Q1 output of the binary counter 122 switched to the logic high state is provided to the pulse generator 140, and the clock generation logic 116 is supplied to the parallel register 114 by the pulse output by the pulse generator 14. By outputting the sampling clock, the p1 and p2 bits of the preparation field are provided to the logic operation unit 118 for logical operation. As described above, the bit sequence forming the ready field does not conform to the consistency rule of the logic operation unit 118, so when all bits of the ready field P are input, the separation signal CS does not transition to the logic high state.

However, after completion of transmission of the preparation field (P), when transmission of the channel field (CH.) begins, a bit sequence is provided to the stabilizer 10, as illustrated in FIG. 4, and the stabilizer 10 allows the user to The desired data can be transmitted to the desired channel.

FIG. 6 is an exemplary timing diagram illustrating a case where noise (N) in a logic high state intervenes in an embodiment of transmitting a preparation field (P) prior to transmission of a channel field (CH.) in serial data (SD). Referring to Figures 3 and 6, when noise (N) intervenes before transmission of the preparation field (P), the noise (N) and the preparation field p1 bit are latched up in the serial register 112, and the pulse generator ( 140) generates a pulse and is provided to the clock generation logic 116. Clock generation logic 116 provides a sampling clock to parallel register 114. The noise (N) and the p1 bit of the ready field are latched up in the parallel register 114 and provided to the logic operation unit 118.

When the noise (N) is logic high and the p1 bit of the preparation field (P) is in the logic low state, the logic operation unit 118 initializes a signal in the logic high state as a result of the logic operation. The signal generator 130 flip-flop Provided as a clock input. The initialization signal generator 130 delays the logic high state signal output from the flip-flop and outputs the inverted initialization signal to the inverted set (BSET) input of the binary counter 122. As an initialization signal is provided to the inverting set (BSET) input, the binary counter 122 is set by switching the Q1 output to a logic high state.

Since bits p2 to p24 of the subsequent preparation field (P) do not comply with the consistency rules of the logic operation unit 118 as described above, the separation signal (CS) is not converted to the logic high state. In addition, as the transmission of the preparation field (P) is completed and the channel field (CH.) is transmitted, a bit sequence is provided to the stabilizer 10 as illustrated in FIG. 4, and the stabilizer 10 The desired data can be transmitted to the channel. Therefore, even if noise intervenes in the serial data (SD), the advantage is provided that the signal can be stabilized by excluding the influence of the noise.

FIG. 7 is an exemplary timing diagram illustrating a case where noise (N) in a logic low state intervenes in an embodiment of transmitting a preparation field (P) prior to transmission of a channel field (CH.) in serial data (SD). Referring to Figures 3 and 7, when noise (N) intervenes before transmission of the preparation field (P), the noise (N) and the preparation field p1 bit are latched up in the serial register 112, and the pulse generator ( 140) generates a pulse and is provided to the clock generation logic 116. Clock generation logic 116 provides a sampling clock to parallel register 114. The noise (N) and the p1 bit of the ready field are latched up in the parallel register 114 and provided to the logic operation unit 118.

In one embodiment, since the noise (N) is logic low and the p1 bit of the ready field (P) is logic low, the consistency determination unit 110 outputs a logic low signal and the binary counter 122 is not set. The selection signal generator 120 forms a rising edge of the selection signal CS in synchronization with the p8 bit of the preparation field and outputs it. Next, the selection signal generator 120 forms a rising edge of the selection signal CS and outputs it at the same time as the transmission of the p23 bit of the preparation field P ends.

However, in the illustrated embodiment, data corresponding to the decimal number 43 (binary 0010 1010) is transmitted in the channel field (CH.) to select channel 43, and values corresponding to bits p8 to p23 are provided as data. do. However, the data field (DATA) includes a predetermined activation code as described above, and bits p8 to p23 do not correspond to the activation code, so a device (not shown) provided with the data field (DATA) trashes the data field. ) is treated as a value and ignored.

In the ready field (P) p24 bit, the binary counter 122 is cleared and Q0 is set to logic high, and as the first bit d1 of the channel field (CH.) of the serial data (SD) is input, the output of the binary counter is Q1. Although it switches to logic high, the p24 bit of the preparation field (P) and the first bit d1 of the channel field (CH.) are logic high and logic low, respectively, by the consistency determination unit 110, so it does not comply with the consistency rule of the consistency bit (M). Therefore, the output of the binary counter 122 is initialized as Q0fh.

As d2, the subsequent bit of the channel field (CH.), is input, the counter increases to Q1, and in the identity check, d1 and d2 meet the consistency rule, so as illustrated in Figure 4, a selection signal (CS) is formed to select the channel Fields and data fields can be separated.

Accordingly, even if noise having any value of logic high or logic low intervenes in the serial data (SD), an advantage is provided in that the signal can be stabilized by excluding the influence of the noise.

FIG. 8 is an exemplary timing diagram illustrating a case in which multiple bits of noise (N) intervene in an embodiment of transmitting a preparation field (P) prior to transmission of a channel field (CH.) in serial data (SD). Referring to Figures 3 and 8, when multiple bits of noise (N) intervene before transmission of the preparation field (P), if the first two bits N1 and N2 in the noise (N) have two different logic values, consistency is That influence can be excluded by the determination unit 110.

However, as illustrated in FIG. 8, the first two bits N1 and N2 of the noise (N) may have the same logical value, and in this case, the channel field (CH.) is a channel with values corresponding to bits N1 to N2. is selected, and values corresponding to N9, N10, and p1 to p14 are selected as the data field (DATA). However, since the values selected for the data field (DATA) do not correspond to the predetermined activation code, a device (not shown) providing the data field (DATA) treats the data field as a garbage value and ignores it.

The embodiment described above is used to adjust a SQUID sensor that converts a serial signal into an optical signal and transmits it through an optical cable to measure a precise magnetic field, and is used in a 64- or 96-channel MCG (Magnetocardiograph) system and a 128-channel magnetoencephalogram. It can be applied to precision magnetic field measurement devices such as (MEG, Magnetoencepharograph) systems. According to this embodiment, when starting the system, even if digital noise generated from the computer during operation is transmitted to the control device, the advantage is provided that the SQUID signal detection system can be adjusted by stabilizing the system with software without restarting the system.

Although the present invention has been described with reference to the embodiments shown in the drawings to aid understanding, these are embodiments for implementation and are merely illustrative, and those skilled in the art will be able to make various modifications and equivalents therefrom. It will be appreciated that other embodiments are possible. Therefore, the true technical protection scope of the present invention should be determined by the attached patent claims.

10: Stabilizer
110: consistency determination unit 112: serial register
114: parallel register 116: clock generation logic
118: logic operation unit 120: selection signal generation unit
122: binary counter 124: selection signal generation logic
126: Clear signal generation logic 130: Initialization signal generation unit
140: Pulse generator

Claims (15)

receiving an optical signal including a channel field and a data field;
forming a serial signal, which is an electrical signal including a channel field and a data field, from the optical signal;
determining consistency of the serial signal;
forming a selection signal corresponding to the position of the data field in the serial signal,
The step of determining the consistency is,
One or more consistency bits are provided by a serial register connected in series,
Parallelizing and outputting the one or more consistency bits provided by the serial register to a parallel register,
A signal stabilization method in which a logic operation unit operates the output of the parallel register according to consistency rules. According to paragraph 1,
In forming the channel field and the data field,
A signal stabilization method further forming a clock signal synchronized with the channel field and the data field. According to paragraph 1,
The step of determining the consistency of the serial signal is,
A signal stabilization method performed by determining whether two or more bits at predetermined positions in the channel field correspond to a consistency rule. According to paragraph 1,
The signal stabilization method is,
After forming the selection signal,
A signal stabilization method comprising determining consistency of the data field. According to paragraph 4,
The step of determining the consistency of the data field is,
A signal stabilization method performed by determining whether two or more bits at predetermined positions in the data field correspond to a predetermined rule. According to paragraph 1,
The signal stabilization method is,
A signal stabilization method performed in a multi-channel magnetocardiograph (MCG) system and a multi-channel magnetoencephalograph (MEG) system. a consistency determination unit that determines whether one or more matching bits included in a serial signal including a channel field and a data field conform to a consistency rule;
a selection signal generator that generates a selection signal corresponding to the position of the data field from a clock signal synchronized with the serial signal; and
An initialization signal generator that generates an initialization signal to initialize the selection signal generator if the one or more matching bits do not meet a consistency rule,
The consistency determination unit,
a serial register in which the one or more flip-flops are cascaded and provided with the one or more consistency bits;
a parallel register including the one or more flip-flops that parallelize and output the one or more consistency bits held in the serial register; and
A signal stabilization device including a logic operation unit that calculates the output of the parallel register using the consistency rule. delete In clause 7,
The signal stabilization device,
Further comprising a pulse generator that outputs a pulse upon receiving the clock signal corresponding to the number of consistency bits,
The consistency determination unit,
A signal stabilization device further comprising a sampling clock generator that receives the pulse, forms a sampling clock of the parallel register, and outputs the sample clock. In clause 7,
The serial signal further includes a ready field,
A signal stabilization device wherein the consistency bit is included in the channel field or the preparation field. According to clause 10,
A signal stabilization device wherein the preparation field has a bit sequence that does not conform to the consistency rule. In clause 7,
The selection signal generator,
a binary counter that receives the inverted clock signal and counts it;
selection signal generation logic to form a selection signal corresponding to the position of the data field in the serial signal from the output of the binary counter;
A signal stabilization device comprising a clear signal generation logic that generates a clear signal that clears the binary counter and the selection signal generation logic when a clock corresponding to the number of bits of the data field is input. According to clause 12,
The selection signal generation logic is,
The binary counter counts the number of clocks corresponding to the start of the data field, forms a leading edge of the selection signal from the output value, and outputs it,
A signal stabilization device wherein the binary counter is initialized according to the initialization signal to form and output a trailing edge of the selection signal. According to clause 12,
The output of the binary counter is cleared to a predetermined logic level by the clear signal,
A signal stabilization device wherein the binary counter is initialized by the initialization signal. In clause 7,
The signal stabilization device is
A signal stabilization device included in a multi-channel magnetocardiograph (MCG) system and a multi-channel magnetoencephalograph (MEG) system.