KR102629152B1 - Liquid crystal display device and method of driving the same - Google Patents

Abstract

In the present invention, when driving a VRR type liquid crystal display device, the pulse width of the gate voltage is increased and/or the potential is raised during low frequency driving.
Therefore, by alleviating the negative bias state of the gate-source voltage of the switching transistor during low-frequency driving, the negative shift phenomenon of the threshold voltage can be effectively improved, thereby improving image quality.

Description

Liquid crystal display device and method of driving the same}

The present invention relates to a liquid crystal display device, and more specifically, to a liquid crystal display device and a driving method thereof that can improve the negative shift phenomenon of the threshold voltage of a switching transistor due to low-frequency driving.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), organic Various flat display devices such as organic light emitting diode (OLED) displays are being used.

Among these flat panel displays, liquid crystal displays are widely used because they have the advantages of miniaturization, weight reduction, thinness, and low-power operation.

Generally, the liquid crystal display device receives a clock with a driving frequency of 60Hz input from an external system, and operates according to this driving frequency.

In such a case, the display device operates at substantially the same driving frequency not only for images with large changes in images, such as moving images, but also for images with small changes in images, such as still images, so power consumption increases.

To improve this, the so-called Variable Refresh Rate is used to reduce power consumption by driving the display device at a normal frequency of 60Hz when displaying moving images and at a low frequency lower than the normal frequency when displaying still images. rate: VRR) driving method was proposed.

However, when the display device is operated in low-frequency mode for a long time, the gate-source voltage (Vgs) of the switching transistor is in a negative bias state for most of the time, and accordingly, the threshold voltage (Vth) of the switching transistor becomes negative. Shifting causes image quality deterioration such as cross-talk. Moreover, switching transistors using oxide semiconductors are more vulnerable to negative bias of the gate-source voltage (Vgs).

Refer to FIGS. 1 and 2 for this conventional threshold voltage negative shift and the resulting image quality deterioration phenomenon. FIG. 1 is a diagram showing a negative shift phenomenon of the threshold voltage in a conventional VRR type liquid crystal display device, and FIG. 2 is a diagram showing crosstalk generated by a conventional threshold voltage negative shift.

Referring to FIG. 1, as the gate-source voltage (Vgs) of the switching transistor is in a negative bias state for a long time due to low-frequency driving, the threshold voltage (Vth) is shifted negatively compared to the initial state, and the drain-source current (Ids) becomes You can see that things are changing. Accordingly, crosstalk as shown in FIG. 2 is caused.

The object of the present invention is to provide a method for improving the negative shift phenomenon of the threshold voltage of a switching transistor caused by low-frequency driving.

In order to achieve the above-described problem, the present invention provides a liquid crystal display device driven at a normal frequency or a lower frequency, including a pixel having a switching transistor; a data line that transmits a data voltage to the pixel; and a gate wire that transmits a first gate voltage to the pixel when driving at the normal frequency and a second gate voltage when driving at the low frequency, wherein the second gate voltage has a pulse width greater/larger than the first gate voltage. Alternatively, a liquid crystal display device with high potential is provided.

Here, the second gate voltage may have higher high and low voltages than the first gate voltage.

The switching transistor may include an oxide semiconductor.

The second gate voltage may have a pulse width twice or more than that of the first gate voltage.

In another aspect, the present invention relates to a method of driving a liquid crystal display device driven at a normal frequency or a lower frequency, wherein a first gate voltage is transmitted to a pixel equipped with a switching transistor when driven at the normal frequency, and a first gate voltage is transmitted when driven at the low frequency. transmitting two gate voltages; A method of driving a liquid crystal display device includes transmitting a data voltage to the pixel, wherein the second gate voltage has a pulse width and/or a higher potential than the first gate voltage.

The second gate voltage may have higher high and low voltages than the first gate voltage.

The switching transistor may include an oxide semiconductor.

The second gate voltage may have a pulse width twice or more than that of the first gate voltage.

In the present invention, when driving a VRR type liquid crystal display device, the pulse width of the gate voltage is increased and/or the potential is increased during low frequency driving.

Therefore, by alleviating the negative bias state of the gate-source voltage of the switching transistor during low-frequency driving, the negative shift phenomenon of the threshold voltage can be effectively improved, thereby improving image quality.

Figure 1 is a diagram showing the negative shift phenomenon of the threshold voltage in a conventional VRR type liquid crystal display device.
Figure 2 is a diagram showing crosstalk generated by a conventional threshold voltage negative shift.
Figure 3 is a block diagram schematically showing a liquid crystal display device according to an embodiment of the present invention.
Figure 4 is an equivalent circuit diagram showing pixels of a liquid crystal display device according to an embodiment of the present invention.
Figure 5 is a diagram schematically showing the gate voltage and pixel voltage during normal frequency mode and low frequency mode driving in the liquid crystal display device according to an embodiment of the present invention.
Figure 6 is a diagram comparing gate voltages when driving in low-frequency mode in the prior art and this embodiment.
Figure 7 is a diagram showing the results of an experiment measuring the threshold voltage shift level of a liquid crystal display device according to the related art and an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Figure 3 is a block diagram schematically showing a liquid crystal display device according to an embodiment of the present invention, and Figure 4 is an equivalent circuit diagram showing pixels of the liquid crystal display device according to an embodiment of the present invention.

Referring to FIG. 3, the liquid crystal display device 100 according to this embodiment may include a display panel 110 in which a plurality of pixels P are arranged in a matrix form and a driving circuit that drives the display panel 110. You can. Additionally, the driving circuit that drives the display panel 110 may include a data driving circuit 120, a gate driving circuit 130, and a timing control circuit 140.

The liquid crystal display device 100 of this embodiment is a so-called VRR type liquid crystal display device 100 in which the frequency changes depending on the displayed image.

In this regard, when displaying an image with large changes in the image, such as a video, the liquid crystal display device 100 is driven in a normal frequency mode according to a normal frequency of, for example, 60 Hz as the driving frequency input from an external system.

In addition, when displaying an image with little change in the image, such as a still image, the liquid crystal display device 100 is driven in a low-frequency mode according to a low frequency lower than the normal frequency. In the low-frequency mode, the number of frames is reduced compared to the normal frequency mode, thereby reducing the number of data writes, or refreshes, and thus the power consumption of the liquid crystal display device 100 can be reduced.

Looking at the display panel 110, various wires that transmit driving signals for driving the pixels P are formed in the display panel 110.

In this regard, for example, a plurality of data lines DL that transmit data voltages may extend along the direction of each column line and be connected to the pixels P of the corresponding column line.

Additionally, a plurality of gate wires (GL) transmitting the gate voltage may extend along the direction of each row line and be connected to the pixel (P) of the corresponding row line.

The timing control circuit 140 controls the driving timing of the data driving circuit 120 and the gate driving circuit 130.

In this regard, the timing control circuit 140 may rearrange digital data (RGB) input from an external system to match the resolution of the display panel 110 and supply it to the data driving circuit 120. In addition, the timing control circuit 140 operates the data driving circuit 120 based on timing signals such as the vertical synchronization signal (Vsync), the horizontal synchronization signal (Hsync), the clock signal (CLK), and the data enable signal (DE). A data control signal (DCS) for controlling the operation timing of and a gate control signal (GCS) for controlling the operation timing of the gate driving circuit 130 can be generated.

The data driving circuit 120 drives the data line DL. In this regard, the data driving circuit 120 may convert input digital data (RGB) into an analog data voltage based on the data control signal (DCS) and supply it to the corresponding data line (DL).

The gate driving circuit 130 drives the gate wiring (GL). In this regard, the gate driving circuit 130 may generate a gate voltage based on the gate control signal (GCS) and supply it to the gate wiring (GL) in a line sequential manner.

Hereinafter, the structure of the pixel P formed in the display panel 110 will be described with reference to FIG. 4 .

Referring to FIG. 4, the pixel (P) of this embodiment includes a switching transistor (T) that functions as a switching element, a liquid crystal capacitor (Clc) and a storage capacitor (Cst) that function as a driving element that drives the pixel (P). It can be configured to include.

The switching transistor (T) is connected to the corresponding gate wiring and data wiring (GL, DL) to receive gate voltage and data voltage. The gate of this switching transistor (T) is connected to the gate line (GL), the drain is connected to the data line (DL), and the source is connected to the liquid crystal capacitor (Clc). Here, the switching transistor (T) may be constructed using an oxide semiconductor with excellent mobility or off-current characteristics, but is not limited to this.

The liquid crystal capacitor (Clc) may be composed of a pixel electrode and a common electrode that face each other, and a liquid crystal layer filled between these electrodes. The pixel electrode is connected to the source of the switching transistor (T) and receives the data voltage, and the common electrode receives the common voltage through the common wiring. An electric field is generated between the pixel electrode and the common electrode due to the voltage difference between the data voltage and the common voltage, thereby changing the arrangement of the liquid crystal molecules, allowing images to be displayed.

The storage capacitor (Cst) is connected in parallel to the liquid crystal capacitor (Clc) and stores the data voltage, or pixel voltage, applied to the pixel electrode until the next frame.

In the liquid crystal display device 100 configured as above, in this embodiment, the negative shift phenomenon of the threshold voltage (Vth) of the switching transistor (T) is improved by modulating the gate voltage during low-frequency mode driving, which is shown in Figure 5. and 6 together for a more detailed description.

Figure 5 is a diagram schematically showing the gate voltage and pixel voltage when driving in the normal frequency mode and the low frequency mode in the liquid crystal display device according to an embodiment of the present invention, and Figure 6 is a diagram showing the gate voltage when driving in the low frequency mode in the conventional and this embodiment. This is a drawing comparing .

The liquid crystal display device 100 of this embodiment is selectively driven in a normal frequency mode or a low frequency mode depending on the type of image being displayed, and at this time, the gate voltage is modulated according to the frequency mode.

First, in the normal frequency mode, it is driven according to the normal frequency (f1), that is, the first frequency (f1), so f1 first frames (F1), which are the first frequency, are set per second, and the first frame (F1) is 1 /f1 time (i.e., cycle), and a data writing operation is performed on the pixel (P) every first frame (F1).

In this normal frequency mode, a gate voltage (Vg1) consisting of a high voltage (Vgh1), which is a turn-on voltage, and a low voltage (Vgl1), which is a turn-off voltage, is applied to each gate wire (GL) in each first frame (F1). At this time, for convenience of explanation, the gate voltage (Vg1) in the normal frequency mode is called the first gate voltage (Vg1), and its high voltage (Vgh1) and low voltage (Vgl1) are the first high voltage (Vgh1) and the low voltage (Vgl1), respectively. It is called the first low voltage (Vgl1).

The first pulse (VP1), which is a pulse of the first gate voltage (Vg1) in the first high voltage (Vgh1) state, is its first pulse width (w1), and the first write period ( During tw1), it is applied to the gate wiring (GL) of the corresponding row line. In response, the switching transistor (T) is turned on, and in this turned-on state, the data voltage provided through the data line (DL) is transmitted into the pixel (P) and is written and stored as the pixel voltage (Vp).

After the first writing period (tw1) has elapsed, the first gate voltage (Vg1) in the first low voltage (Vgl1) state is applied to the gate wiring (GL) during the first holding period (th1), which is the remaining section of the first frame (F1). approved.

In this normal frequency mode, the first pulse VP1 of the first pulse width w1 is applied during the first writing period tw1 of the first frame F1, and the first pulse VP1 applied during this period tw1 The gate voltage (Vg1) is the first high voltage (Vgh1), which is greater than the data voltage written to the pixel (P), that is, the pixel voltage (Vp). Accordingly, the gate-source voltage (Vgs_w1) of the switching transistor (T) is in a positive bias state during the first write period (tw1).

In addition, the first low voltage Vgl1 is applied during the first holding period (th1) of the first frame (F1), and the first low voltage (Vgl1) is stored in the pixel (P) during the first holding period (th1). It is smaller than the pixel voltage (Vp). Accordingly, during the first holding period (th1), the gate-source voltage (Vgs_h1) of the switching transistor (T) is in a negative bias (positive bias) state.

As such, in the normal frequency mode, the gate-source voltage of the switching transistor (T) alternates between the positive bias state and the negative bias state based on the first frame (F1), which is a short period, so the negative bias state is short-term. It is maintained during the first holding period (th1).

Therefore, when driven in normal frequency mode, the negative bias state of the switching transistor (T1) is maintained for a short time and then resolved, and the negative shift phenomenon of the threshold voltage (Vth) of the switching transistor (T) due to the negative bias state is It doesn't actually happen.

Next, in the low-frequency mode, it is driven according to the corresponding low frequency (f2), that is, the second frequency (f2), so f2 second frames (F2), which are the second frequency, are set per second, and the second frame (F2) is 1/ There is time f2 (i.e., cycle), and a data writing operation is performed on the pixel P every second frame F2. As such, in the low-frequency mode, it operates at a low frequency (f2) that is smaller than the normal frequency (f1), so the number of frames is smaller and the period is increased compared to the normal frequency mode.

In this low-frequency mode, a gate voltage (Vg2) consisting of a high voltage (Vgh2) and a low voltage (Vgl2) is applied to each gate line (GL) every second frame (F2). At this time, for convenience of explanation, the gate voltage (Vg2) in the low-frequency mode is called the second gate voltage (Vg2), and its high voltage (Vgh2) and low voltage (Vgl2) are the second high voltage (Vgh2) and the second gate voltage (Vg2), respectively. It is called 2 low voltage (Vgl2).

The second gate voltage (Vg2) in the second high voltage (Vgh2) state, that is, the second pulse (VP2), is its second pulse width (w2) and is the second writing period (tw2), which is the horizontal period of the pixel (P). During this time, it is applied to the gate wiring (GL) of the corresponding row line. In response, the switching transistor (T) is turned on, and in this turned-on state, the data voltage provided through the data line (DL) is transmitted into the pixel (P) and is written and stored as the pixel voltage (Vp).

After the second writing period (tw2) has elapsed, the second gate voltage (Vg2) in the second low voltage (Vgl2) state is applied to the gate wiring (GL) during the second holding period (th2), which is the remaining section of the second frame (F2). approved.

In this low-frequency mode, the second pulse VP2 having the second pulse width w2 is applied during the second writing period tw2 of the second frame F2, and the second pulse VP2 applied during this period tw2 The gate voltage (Vg2) is the second high voltage (Vgh2), which is greater than the data voltage written to the pixel (P), that is, the pixel voltage (Vp). Accordingly, the gate-source voltage (Vgs_w2) of the switching transistor (T) is in a positive bias state during the second write period (tw2).

Also, the second low voltage Vgl2 is applied during the second holding period (th2) of the second frame (F2), and the second low voltage (Vgl2) is stored in the pixel (P) during the second holding period (th2). It is smaller than the pixel voltage (Vp). Accordingly, during the second holding period (th2), the gate-source voltage (Vgs_h2) of the switching transistor (T) is in a negative bias (positive bias) state.

As such, in the low-frequency mode, the gate-low voltage of the switching transistor (T) alternates between the positive bias state and the negative bias state based on the second frame (F2), which is a very long period, so the negative bias state is maintained for a long period of time. It is maintained during the second holding period (th2). That is, the second frame (F2) has a longer period than the first frame (F1), and furthermore, the second holding section (th2) substantially occupies most of the time of the second frame (F2).

As such, in the low-frequency mode, the time occupied by the negative bias state of the switching transistor T rapidly increases compared to the normal frequency mode.

Therefore, when driving in the low-frequency mode, if a gate voltage with the same characteristics as the gate voltage in the normal frequency mode is applied to the low-frequency mode as in the past, a strong negative shift phenomenon in the threshold voltage (Vth) due to the negative bias state occurs. .

To improve this, according to this embodiment, when driving in the low-frequency mode, unlike the prior art, by applying a gate voltage (Vg2) with characteristics different from the gate voltage in the normal frequency mode, the threshold voltage (Vth) due to the conventional negative bias state is reduced. The negative shift phenomenon can be improved.

Regarding this, referring to FIG. 6, conventionally, the gate voltage (Vgp) when driving in the low-frequency mode, indicated by a dotted line, has substantially the same pulse width and potential as when driving in the normal frequency mode. In this case, in the present embodiment shown in FIG. It is said that the gate voltage (Vg1) of the normal frequency mode in the example is the same as the gate voltage of the conventional normal frequency mode.

That is, the width (VPp) of the pulse (VP) of the gate voltage (Vgp) in the conventional low-frequency mode and the high and low voltages (Vghp, Vglp) are the pulse width (VP1) of the gate voltage (Vg1) in the normal frequency mode. It is the same as the high voltage and low voltage (Vgh1, Vgl1), and the holding section (thp) in the conventional low-frequency mode corresponds to the section excluding the corresponding writing period (twp) in the second frame (F2).

On the other hand, the pulse width of the second gate voltage (Vg2) in the low frequency mode of this embodiment increases (i.e., w2 > w1) and/or the potential (i.e., level) of the low voltage and high voltage increases compared to the normal frequency mode. (i.e., Vgh2 > Vgh1 and Vgl2 > Vgl1). In other words, the pulse width of the second gate voltage (Vg2) in the low-frequency mode of this embodiment increases (i.e., w2 > wp) and/or the potentials of the low and high voltages increase (i.e., Vgh2) compared to the conventional low-frequency mode. > Vghp and Vgl2 > Vglp).

In this way, when the pulse width of the second gate voltage (Vg2) is increased, the second holding period (th2) is reduced compared to the holding period (thp) of the conventional low-frequency mode (that is, th2 < thp). Because of this, the time during which the switching transistor (T) is in a negative bias state in the holding period can be reduced, and as a result, the negative shift phenomenon of the threshold voltage (Vth) of the switching transistor (T) can be alleviated.

At this time, it is preferable that the pulse width (w2) of the second gate voltage (Vg2) is set to more than twice the pulse width (w1) of the first gate voltage (Vg1), but is not limited to this.

In addition, when the low voltage is shifted by raising the potential of the second gate voltage (Vg2) to a high level, the gate-source voltage in the holding section decreases compared to the prior art (i.e., Vgs_h2 < Vgs_hp), thereby reducing the accumulated negative bias. , As a result, the negative shift phenomenon of the threshold voltage (Vth) of the switching transistor (T) can be alleviated.

In addition, when the high voltage is shifted by raising the potential of the second gate voltage (Vg2) to a high level, the gate-source voltage in the writing period increases compared to the conventional case (i.e., Vgs_w2 > Vgs_wp), thereby increasing the amount of positive bias. I do it. In this way, when the amount of positive bias in the writing section increases, it acts to alleviate the negative bias in the previous holding section, and as a result, the negative shift phenomenon of the threshold voltage (Vth) of the switching transistor (T) can be alleviated. do.

Therefore, as in this embodiment, the negative bias state can be alleviated by modulating the pulse width and/or potential of the gate voltage during low-frequency mode driving. Accordingly, it is possible to improve image quality by effectively improving the negative shift phenomenon of the threshold voltage (Vth) of the switching transistor (T).

In particular, in the case of a switching transistor (T) using an oxide semiconductor, the effect of improving the negative shift phenomenon is excellent.

FIG. 7 may be referred to in relation to the improvement of the threshold voltage shift of the present invention. Figure 7 is a diagram showing the results of an experiment measuring the threshold voltage shift level of the liquid crystal display device of the prior art and an embodiment of the present invention.

Referring to FIG. 7, it can be seen that in the conventional case, the threshold voltage variation (ΔVth) continuously shifts negatively over time.

On the other hand, in the case of Experimental Examples 1-3 of the present invention, it can be confirmed that the threshold voltage variation (ΔVth) saturates to a very low level over time.

Considering these experimental results, if the gate voltage is modulated and applied during low-frequency mode driving according to an embodiment of the present invention, the negative shift of the threshold voltage can be effectively improved by alleviating the negative bias state of the switching transistor.

As described above, according to an embodiment of the present invention, when driving a VRR type liquid crystal display device, the pulse width of the gate voltage is increased and/or the potential is increased during low frequency driving.

Therefore, by alleviating the negative bias state of the gate-source voltage of the switching transistor during low-frequency driving, the negative shift phenomenon of the threshold voltage can be effectively improved, thereby improving image quality.

The above-described embodiment of the present invention is an example of the present invention, and free modification is possible within the scope included in the spirit of the present invention. Accordingly, the present invention includes modifications of the present invention within the scope of the appended claims and their equivalents.

100: liquid crystal display device 110: display panel
120: data driving circuit 130: gate driving circuit
140: Timing control circuit
P: Pixel
T: switching transistor
Clc: liquid crystal capacitor
Cst: storage capacitor
GL, DL: Gate wiring, data wiring
Vp: pixel voltage
Vg1, Vg2: 1st and 2nd gate voltages
Vgh1, Vgh2: 1st and 2nd high voltage
Vgl1, Vgl2: 1st, 2nd low voltage
VP1,VP2: 1st, 2nd pulse
w1,w2: 1st, 2nd pulse width
Vgs_w1, Vsg_w2: Gate-source voltage in the first and second writing periods
Vgs_h1, Vsg_h2: Gate-source voltage in the first and second holding periods
F1, F2: 1st, 2nd frame
tw1,tw2: 1st and 2nd entry period
th1,th2: 1st, 2nd holding period

Claims (10)

In a liquid crystal display device driven at a normal frequency or a lower frequency,
a pixel including a switching transistor;
a data line that transmits a data voltage to the pixel;
A gate wiring that transmits a first gate voltage to the pixel when driven at the normal frequency and a second gate voltage when driven at the low frequency,
The second gate voltage has a pulse width and/or a higher potential than the first gate voltage.
Liquid crystal display device.
According to claim 1,
The second gate voltage has higher high and low voltages than the first gate voltage.
Liquid crystal display device.
According to claim 1,
The switching transistor includes an oxide semiconductor.
Liquid crystal display device.
According to claim 1,
The second gate voltage has a pulse width twice or more than the first gate voltage.
Liquid crystal display device.
In a method of driving a liquid crystal display device driven at a normal frequency or a lower frequency,
transmitting a first gate voltage when driven at the normal frequency and transmitting a second gate voltage when driven at the low frequency to a pixel equipped with a switching transistor;
Including transmitting a data voltage to the pixel,
The second gate voltage has a pulse width and/or a higher potential than the first gate voltage.
How to drive a liquid crystal display.
According to claim 5,
The second gate voltage has higher high and low voltages than the first gate voltage.
How to drive a liquid crystal display.
According to claim 5,
The switching transistor includes an oxide semiconductor.
How to drive a liquid crystal display.
According to claim 5,
The second gate voltage has a pulse width twice or more than the first gate voltage.
How to drive a liquid crystal display. According to claim 1,
A plurality of the gate wires extend along each of the plurality of row lines,
Each of the plurality of gate wires transmits the first gate voltage when driven at the normal frequency and transmits the second gate voltage when driven at the low frequency.
Liquid crystal display device.
According to claim 5,
A plurality of gate wires extend along each of the plurality of row lines,
Each of the plurality of gate wires transmits the first gate voltage when driven at the normal frequency and transmits the second gate voltage when driven at the low frequency.
How to drive a liquid crystal display.

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