KR102628658B1 - Neural processor and control method of neural processor - Google Patents

Abstract

A neural processor and a method for controlling the neural processor are disclosed. The neural process discloses an image sensor and a method of operating the image sensor. The neural processor includes a plurality of processing element groups, each of the processing element groups is a plurality of processing elements that perform a vector operation, is shared by a plurality of processing elements, and overflow or underflow occurs among the plurality of processing elements. It includes an overflow accumulator that is occupied by the processing element that occurs, and a register that stores information indicating the occupied processing element that occupies the overflow accumulator.

Description

Neural processor and control method of neural processor {NEURAL PROCESSOR AND CONTROL METHOD OF NEURAL PROCESSOR}

The following embodiments relate to a neural processor and a method of controlling the neural processor.

For applications in the field of artificial intelligence, a hardware accelerator consisting of a neural processing unit (NPU) can basically implement a dot product operation between two vectors. A neural network processing unit (NPU) can perform inner product operations and use accumulators and adders with a large number of bits to store the operation results. Additionally, multipliers, accumulators, and adders can be used to implement the dot product operation. For example, when a neural network processing unit performs an operation of 8 bits or more, the cost of the multiplier is generally large, whereas when the precision of the operation is lowered to less than 8 bits, the cost of the accumulator and adder becomes relatively large compared to the multiplier. You can. Therefore, a method of reducing the cost of accumulators and adders is required for efficient implementation of neural network processing devices that perform low-precision calculations.

According to one embodiment, a neural processor includes a plurality of processing element groups, each of the processing element groups comprising a plurality of processing elements that perform a vector operation; an overflow accumulator shared by the plurality of processing elements and occupied by a processing element in which an overflow or underflow occurs among the plurality of processing elements; and a register that stores information indicating an occupied processing element that occupies the overflow accumulator.

The overflow accumulator accumulates the operation result of the accumulator of the occupied processing element based on information indicating whether overflow or underflow has occurred received from the accumulators included in each of the processing elements ( accumulation) can occur.

The information may indicate at least one of overflow, underflow, and none.

The overflow accumulator may be connected to each of the plurality of processing elements through a pipelined interconnect.

The neural processor determines whether an overflow accumulator shared by a plurality of processing elements performing the vector operation is occupied by at least one of the plurality of processing elements, based on information indicating the occupied processing element. You can check it.

When the overflow accumulator is occupied, the neural processor controls the overflow accumulator to add 1 according to the overflow signal output from the occupied processing element, and controls the overflow accumulator to add 1 according to the underflow signal output from the occupied processing element. The overflow accumulator can be controlled to subtract 1.

When the overflow accumulator is not occupied, the neural processor may set the processing element that outputs the overflow signal or the underflow signal among the processing elements as the occupied processing element.

As the vector operation is terminated, the occupied processing element may output information indicating the occupied processing element together with the operation result of the overflow accumulator and the operation result of the occupied processing element.

Among the processing elements, non-occupied processing elements excluding the occupied processing element may output operation results of an accumulator of the non-occupied processing elements as the vector operation is terminated.

When the neural processor simultaneously receives the overflow signal or the underflow signal from two or more processing elements among the plurality of processing elements, the neural processor randomly selects one of the two or more processing elements. It can be set as an occupied processing element.

The register may further store information indicating whether overflow or underflow occurred in the occupied processing element.

Each of the processing elements may include a plurality of multipliers, a plurality of adders, and an accumulator.

Each of the processing elements may include a multiplier-adder tree (MAT), an adder, and an accumulator.

The overflow accumulator may include an accumulator and an adder.

According to one embodiment, a method for controlling a neural processor includes checking whether an overflow accumulator shared by a plurality of processing elements that perform a vector operation is occupied by at least one of the plurality of processing elements; When the overflow accumulator is not occupied, setting a processing element that outputs an overflow signal or an underflow signal among the processing elements as an occupied processing element; When the overflow accumulator is occupied, controlling the overflow accumulator to add or subtract according to a signal output from the occupied processing element occupying the overflow accumulator; and outputting information indicating the occupied processing element along with an operation result of the overflow accumulator and an operation result of the occupied processing element as the vector operation is terminated.

The checking may include checking whether the overflow accumulator is occupied by at least one of the plurality of processing elements, based on information indicating the occupied processing element.

The controlling step includes, when the overflow accumulator is occupied, adding 1 to the overflow accumulator according to an overflow signal output from the processing element occupying the overflow accumulator; and subtracting 1 from the overflow accumulator according to an underflow signal output from the processing element occupying the overflow accumulator.

The outputting step may include outputting a result of adding the data of the overflow accumulator and the operation result of the occupied processing element through a pipeline interconnection connected vertically between the occupied processing element and the overflow accumulator. You can.

The control method of the neural processor is to randomly select any one of the two or more processing elements when the overflow signal or the underflow signal is simultaneously received from two or more processing elements among the plurality of processing elements. ) may further include setting the occupied processing element.

1 to 2 are diagrams showing the configuration of a neural processor according to embodiments.
3 and 4 are flowcharts showing a control method of a neural processor according to embodiments.

Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be changed and implemented in various forms. Accordingly, the actual implementation form is not limited to the specific disclosed embodiments, and the scope of the present specification includes changes, equivalents, or substitutes included in the technical idea described in the embodiments.

Terms such as first or second may be used to describe various components, but these terms should be interpreted only for the purpose of distinguishing one component from another component. For example, a first component may be named a second component, and similarly, the second component may also be named a first component.

When a component is referred to as being “connected” to another component, it should be understood that it may be directly connected or connected to the other component, but that other components may exist in between.

Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as “comprise” or “have” are intended to designate the presence of the described features, numbers, steps, operations, components, parts, or combinations thereof, and are intended to indicate the presence of one or more other features or numbers, It should be understood that this does not exclude in advance the possibility of the presence or addition of steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art. Terms as defined in commonly used dictionaries should be interpreted as having meanings consistent with the meanings they have in the context of the related technology, and unless clearly defined in this specification, should not be interpreted in an idealized or overly formal sense. No.

Hereinafter, embodiments will be described in detail with reference to the attached drawings. In the description with reference to the accompanying drawings, identical components will be assigned the same reference numerals regardless of the reference numerals, and overlapping descriptions thereof will be omitted.

1 is a diagram illustrating the configuration of a neural processor according to one embodiment. Referring to FIG. 1, the structure of a neural processor 10 is shown including a plurality of processing element groups (PEGs) in a systolic array structure.

Each of the processing element groups (PEG _{i -1,} PEG _{i ,} PEG _{i +1} ) has a systolic array structure designed so that cells with the same function can form a network and perform one operation in accordance with the overall synchronization signal. Therefore, the function and operation may be the same. Below, the configuration and operation will be described focusing on the processing element group (PEG _i ) 100 of any one of the processing element groups (PEG _{i -1,} PEG _{i ,} PEG _{i +1} ). The configuration and operation of the processing element group (PEG _i ) 100 can be equally applied to other processing element groups (PEG _i-1, PEG _i+1 ).

The processing element group (PEG _i ) 100 includes a plurality of processing elements (PEs) (110, 120, 130, 140), an overflow accumulator (OA) 150, and a register ( 160) may be included. In one embodiment, a plurality of processing elements (PEs) 110, 120, 130, and 140 that share one overflow accumulator (OA) 150 may be referred to as a 'processing element group (PEG)'.

A plurality of processing elements (PEs) 110, 120, 130, and 140 may perform vector operations. Vector operations may include, for example, a dot product operation between two vectors, but are not necessarily limited thereto. In Figure 1, for convenience of explanation, an embodiment in which the processing element group (PEG _i ) 100 includes four processing elements (PEs) 110, 120, 130, and 140 is described as an example, but it is necessarily limited to this. It doesn't work. The number of processing elements included in one processing element group (PEG _i ) 100 may be variously configured, for example, 2, 8, or 16.

The processing element (PE) may also be called a 'dot product engine (DPE)' or an 'accelerator' in that it implements vector operations, more specifically, inner product operations between vectors, in hardware.

Each of the processing elements (PEs) 110, 120, 130, and 140 may include an accumulator (ACC) 115, 125, 135, and 145. Although not shown in the drawing, each of the processing elements (PEs) 110, 120, 130, and 140 includes a plurality of multipliers and a plurality of adders in addition to the accumulators (ACCs) 115, 125, 135, and 145. Additional (adders) may be included. Processing elements (PEs) 110, 120, 130, 140 each produce an operation result (e.g., final result of dot product or partial sum, etc.) of accumulators (ACC) 115, 125, 135, 145. can be transmitted externally through vertical pipeline interconnections. At this time, the processing elements (PEs) 110, 120, 130, and 140, each accumulator (ACC) 115, 125, 135, and 145, and a plurality of adders may be implemented with a small number of bits.

Depending on the embodiment, each of the processing elements 110, 120, 130, and 140 may include a multiplier-adder tree (MAT), an adder, and an accumulator. An embodiment in which processing elements include a MAT, an adder, and an accumulator will be described in more detail with reference to FIG. 2 below.

The overflow accumulator (OA) 150 is shared by processing elements (PEs) 110, 120, 130, and 140, and is used in the vector operation process among the processing elements (PEs) 110, 120, 130, and 140. It may be occupied by a processing element that overflows or underflows.

For example, the overflow accumulator (OA) 150 collects 2 bits from the N bit accumulators 115, 125, 135, and 145 included in each of the processing elements (PEs) 110, 120, 130, and 140. Information (e.g., information indicating overflow, underflow, or none) may be received. The overflow accumulator (OA) 150 can accumulate the operation result of any one of the accumulators 115, 125, 135, and 145 according to the received 2 bits of information.

The overflow accumulator (OA) 150 may be connected to each of the processing elements (PEs) 110, 120, 130, and 140 through a pipelined interconnect indicated by a dotted line. A pipeline interconnect may be connected to interconnect line 170.

When processing elements (PEs) (110, 120, 130, 140) each send N bit data, which is the contents of N bit accumulators (115, 125, 135, 145), to the outside through the pipeline interconnection, over The flow accumulator (OA) 150 calculates its M bit (overflow accumulator (OA) 150) according to the clock cycle in which the N bit operation results of the N bit accumulators 115, 125, 135, and 145 are output. By outputting the calculation result, M+N bit data can be transmitted to the outside through the interconnect line 170.

For example, if the processing elements (PEs) 110, 120, 130, and 140 each have a size of 10 bits, and the overflow accumulator (OA) 150 has a size of 10 bits, the interconnect line 170 In addition to a total of 50 bits, data of a total size of 54 bits can be transmitted by adding information (2 bits) indicating the occupied processing element and information (2 bits) indicating whether overflow or underflow has occurred. there is. Here, 'occupied processing element' refers to one processing element that occupies the overflow accumulator (OA) 150 among the processing elements (PEs) 110, 120, 130, and 140 constituting one processing element group. It can be understood as doing so. At this time, the remaining processing elements that do not occupy the overflow accumulator (OA) 150 among the processing elements (PEs) 110, 120, 130, and 140 may be called 'unoccupied processing element(s)'.

Although not shown in the drawing, the overflow accumulator 150 may include an accumulator and an adder.

A register (Reg) 160 may store information indicating the occupied processing element that occupies the overflow accumulator (OA) 150. Information indicating the occupied processing element may consist of 2 bits such as "00", "01", "10", and "11", and may be selected among the processing elements 110, 120, 130, and 140. Can indicate any one processing element. For example, “00” may indicate that processing elements 110 are occupied processing elements. “01” may indicate that the processing elements 120 are occupied processing elements. “10” may indicate that the processing elements 130 are occupied processing elements. “11” may indicate that the processing elements 140 are occupied processing elements.

Additionally, the register (Reg) 160 may further store 2 bits of information indicating whether overflow or underflow occurred in the occupied processing element. For example, "01" indicates that an overflow occurred, "10" indicates that an underflow occurred, and "00" is none, that is, no overflow or underflow occurred. You can indicate sound.

The neural processor 10 assumes that the processing element that first generates the overflow signal or underflow signal occupies the overflow accumulator, so that the overflow accumulator (OA) 150 is connected to the processing element every clock cycle. You can check whether it is occupied. The neural processor 10 includes an overflow accumulator (OA) ( It may be checked whether 150) is occupied by at least one of a plurality of processing elements (PEs) 110, 120, 130, and 140.

When the overflow accumulator (OA) 150 is not occupied, the neural processor 10 selects the processing element that first outputs the overflow signal or underflow signal among the processing elements (PEs) 110, 120, 130, and 140. can be set as an occupied processing element.

When the overflow accumulator (OA) 150 is occupied, the neural processor 10 can control the overflow accumulator (OA) 150 to add 1 according to the overflow signal output from the occupied processing element. The neural processor 10 may control the overflow accumulator (OA) 150 to subtract 1 according to the underflow signal output from the occupied processing element. At this time, a signal that controls the overflow accumulator (OA) 150 to add or subtract 1 may be transmitted through the control logic (not shown) of the neural processor 10.

The control logic may generate an output control signal when the vector operation is terminated. The occupied processing element that receives the output control signal transmits its operation result through the interconnect line 170 in accordance with the clock cycle, and the operation result of the overflow accumulator (OA) 150 is transmitted in accordance with the same clock cycle through the interconnect line ( 170).

As the vector operation is terminated, the occupied processing element may output information indicating the occupied processing element along with the operation result of the overflow accumulator (OA) 150 and the operation result of the occupied processing element.

Among the processing elements, the non-occupied processing elements excluding the occupied processing elements may output the operation results of the accumulators of the non-occupied processing elements through the interconnect line 170 as the vector operation is completed.

When an overflow signal or an underflow signal is simultaneously received from two or more of the plurality of processing elements (PEs) 110, 120, 130, and 140, the neural processor 10 receives the two or more processing elements. Any one of them can be randomly set as the occupied processing element.

In one embodiment, considering that a large number of bits is rarely used to store the result of the dot product operation, the cost of the accumulator and the adder (that is, using an accumulator and an adder with a small number of bits to reduce the gate of the accumulator and the adder) (gate number) can be reduced. For example, if four processing elements (PEs) 110, 120, 130, 140 each have an accumulator and an adder with a size of (M+N) bits, their cost is 4(M+N). ) can be a bit. In contrast, four processing elements (PEs) 110, 120, 130, 140 share one M bits overflow accumulator (OA) 150, and four processing elements (PEs) 110, 120 , 130, 140) If each has an N bit accumulator, the total cost of each accumulator and adder included in one processing element group can be expressed as 4N+M bits. Compared to the case where each of the four processing elements (PEs) (110, 120, 130, and 140) has an accumulator and an adder with a size of (M+N) bits, the cost can be reduced by 3M bits. At this time, the interconnect line 170 can also reduce the cost (eg, the number of pipefine interconnected wires) at the same rate.

In addition, in one embodiment, a plurality of processing elements (PEs) (110, 120, 130, 140) are configured by an accumulator and an adder using a small number of bits, and a plurality of processing elements (PEs) (110, 120) are formed. , 130, 140), the cost of the accumulator and adder is reduced while the cost of the accumulator and adder is improved by allowing the occupied processing element where overflow or underflow occurs to occupy and use the overflow accumulator (OA) 150. You can do it.

Figure 2 is a diagram showing the configuration of a neural processor according to other embodiments. Referring to Figure 2, a neural processor 200 is shown in which two processing elements 210 and 230 share one overflow accumulator 270.

For example, let's say that the two processing elements 210 and 230 each have N bits of accumulators (ACCs) 217 and 237, and the overflow accumulator 270 has M bits. At this time, the two processing elements (210, 230) include a multiplier-adder tree (MAT) (213, 233), an N bit adder (215, 235), and an N bit accumulator (ACC) (217, 237). It can be included.

The overflow accumulator 270 may include an M bit adder 260 and an M bit accumulator.

For example, of the two processing elements 210 and 230, processing element 210 is the occupying processing element that occupies the overflow accumulator 270, and processing element 230 does not occupy the overflow accumulator 270. Assume that it is an unoccupied processing element.

The occupied processing element 210 may output an operation result of M+N bits by combining the N bits of the accumulator 217 and the M bits of the overflow accumulator 270. The occupied processing element 210 can output calculation results with high precision. At this time, the M bit operation result provided to the overflow accumulator 270 may correspond to the operation result of the occupied processing element 210 selected by the 2-to-1 MUX 250 according to the information indicating the occupied processing element. there is.

The occupied processing element 210 may output an operation result of M+N bits through the pipeline interconnection 280.

In contrast, the non-occupied processing element 230 may output the operation result of N bits of the accumulator 237. The non-occupied processing element 230 can output the operation result of N bits of the accumulator 237 as a valid result among M+N bits output. The unoccupied processing element 230 may output low-precision calculation results. At this time, in the M bit corresponding to the most significant bit, numbers can be added, for example, through a sign extension operation that increases the number of bits of a binary number while maintaining the sign (positive or negative) and value of the number. The non-occupied processing element 230 can output an operation result of N bits through the pipeline interconnection 290.

Figure 3 is a flowchart showing a control method of a neural processor according to an embodiment. Referring to FIG. 3, a process in which a neural processor outputs calculation results through steps 310 to 340 is shown.

In step 310, the neural processor checks whether an overflow accumulator shared by a plurality of processing elements performing a vector operation is occupied by at least one of the plurality of processing elements. For example, the neural processor may check whether the overflow accumulator is occupied by at least one of the plurality of processing elements, based on information indicating the occupied processing element.

As a result of the check in step 310, if the overflow accumulator is not occupied, in step 320, the neural processor sets the processing element that outputs the overflow signal or the underflow signal among the processing elements as the occupied processing element.

When an overflow signal or an underflow signal is simultaneously received from two or more processing elements among a plurality of processing elements, the neural processor may randomly set any one of the two or more processing elements as the occupied processing element. there is.

As a result of the check in step 310, if the overflow accumulator is occupied, in step 330, the neural processor controls the overflow accumulator to add or subtract according to a signal output from the occupied processing element that occupies the overflow accumulator. At this time, the signal output from the occupied processing element may be an overflow signal or an underflow signal. For example, if the overflow accumulator is occupied, the neural processor adds 1 to the overflow accumulator according to the overflow signal output from the processing element occupying the overflow accumulator, or Depending on the output underflow signal, 1 can be subtracted from the overflow accumulator.

In step 340, as the vector operation is completed, the neural processor outputs information indicating the occupied processing element along with the operation result of the overflow accumulator and the operation result of the occupied processing element. The neural processor can output the result of adding the data of the overflow accumulator and the operation results of the occupied processing element to the outside through a pipeline interconnection connected vertically between the occupied processing element and the overflow accumulator.

Figure 4 is a flowchart showing a control method of a neural processor according to another embodiment. Referring to FIG. 4, operations performed by the overflow accumulator of the neural processor in each cycle through steps 410 to 460 are shown.

In step 410, the neural processor may check whether an overflow accumulator shared by a plurality of processing elements that perform a vector operation is occupied by at least one of the plurality of processing elements.

If it is checked in step 410 that the overflow accumulator is occupied by at least one processing element, in step 440 the neural processor responds to the overflow signal or underflow signal output from the occupying processing element occupying the overflow accumulator. Accordingly, 1 can be added to the overflow accumulator (more specifically, the accumulator (OACC) included in the overflow accumulator) or 1 can be subtracted. The neural processor may add 1 to the overflow accumulator when an overflow signal is output from the occupied processing element, and may subtract 1 from the underflow accumulator when an underflow signal is output.

If it is checked in step 410 that the overflow accumulator is not occupied by at least one processing element, in step 420 the neural processor may determine whether an underflow signal or an overflow signal is received.

If it is determined in step 420 that the underflow signal or overflow signal has not been received, the neural processor may wait until the underflow signal or overflow signal is received. Depending on the embodiment, if it is determined in step 420 that the underflow signal or overflow signal has not been received, the neural processor returns to step 410 to determine whether the overflow accumulator is occupied by at least one of the plurality of processing elements. You can also check .

If it is determined in step 420 that an underflow signal or overflow signal has been received, in step 430 the neural processor may set the processing element that output the underflow signal or overflow signal as the occupied processing element (owner PE). .

If it is determined in step 420 that two or more underflow signals or overflow signals are received at the same time, the neural processor may randomly set an occupied processing element among the processing elements that output the underflow signal or overflow signal.

The neural processor may add 1 to or subtract 1 from the overflow accumulator in step 440 according to the overflow signal or underflow signal output from the occupied processing element set in step 430.

In step 450, the neural processor may determine whether an output control signal has been generated from the control logic as the vector operation is completed. If it is determined in step 450 that the output control signal has not been generated, the neural processor may end the operation.

If it is determined that the output control signal has occurred in step 450, in step 460, the neural processor outputs the operation result of the overflow accumulator through the pipeline interconnection in accordance with the clock cycle, while processing the occupied processing element in the same clock cycle. Calculation results can also be output through pipeline interconnection. At this time, the neural processor may output information indicating the occupied processing element together with the operation result of the overflow accumulator and the operation result of the occupied processing element.

The embodiments described above may be implemented with hardware components, software components, and/or a combination of hardware components and software components. For example, the devices, methods, and components described in the embodiments may include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, and a field programmable gate (FPGA). It may be implemented using a general-purpose computer or a special-purpose computer, such as an array, programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and software applications running on the operating system. Additionally, a processing device may access, store, manipulate, process, and generate data in response to the execution of software. For ease of understanding, a single processing device may be described as being used; however, those skilled in the art will understand that a processing device includes multiple processing elements and/or multiple types of processing elements. It can be seen that it may include. For example, a processing device may include multiple processors or one processor and one controller. Additionally, other processing configurations, such as parallel processors, are possible.

Software may include a computer program, code, instructions, or a combination of one or more of these, which may configure a processing unit to operate as desired, or may be processed independently or collectively. You can command the device. Software and/or data may be used on any type of machine, component, physical device, virtual equipment, computer storage medium or device to be interpreted by or to provide instructions or data to a processing device. , or may be permanently or temporarily embodied in a transmitted signal wave. Software may be distributed over networked computer systems and stored or executed in a distributed manner. Software and data may be stored on a computer-readable recording medium.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. A computer-readable medium may store program instructions, data files, data structures, etc., singly or in combination, and the program instructions recorded on the medium may be specially designed and constructed for the embodiment or may be known and available to those skilled in the art of computer software. there is. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic media such as floptical disks. -Includes optical media (magneto-optical media) and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, etc. Examples of program instructions include machine language code, such as that produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc.

The hardware devices described above may be configured to operate as one or multiple software modules to perform the operations of the embodiments, and vice versa.

Although the embodiments have been described with limited drawings as described above, those skilled in the art can apply various technical modifications and variations based on this. For example, the described techniques are performed in a different order than the described method, and/or components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or other components are used. Alternatively, appropriate results may be achieved even if substituted or substituted by an equivalent.

Therefore, other implementations, other embodiments, and equivalents of the claims also fall within the scope of the claims described below.

Claims (20)

Contains a plurality of processing element groups,
Each of the processing element groups is
A plurality of processing elements that perform vector operations;
an overflow accumulator shared by the plurality of processing elements and occupied by a processing element in which an overflow or underflow occurs among the plurality of processing elements; and
A register that stores information indicating the occupied processing element that occupies the overflow accumulator.
Neural processor, including. According to paragraph 1,
The overflow accumulator is
Neural, which accumulates the operation result of the accumulator of the occupied processing element based on information indicating whether overflow or underflow has occurred received from the accumulators included in each of the processing elements. processor. According to paragraph 2,
The above information is
A neural processor that indicates at least one of overflow, underflow, and none. According to paragraph 1,
The overflow accumulator is
A neural processor connected to each of the plurality of processing elements through a pipelined interconnect. According to paragraph 1,
The neural processor is
A neural method that checks whether an overflow accumulator shared by a plurality of processing elements performing the vector operation is occupied by at least one of the plurality of processing elements, based on information indicating the occupied processing element. Processor. According to clause 5,
If the overflow accumulator is occupied, the neural processor
Control to add 1 to the overflow accumulator according to the overflow signal output from the occupied processing element,
A neural processor that controls the overflow accumulator to subtract 1 according to an underflow signal output from the occupied processing element. According to clause 5,
If the overflow accumulator is not occupied, the neural processor
A neural processor that sets a processing element that outputs an overflow signal or an underflow signal among the processing elements as the occupied processing element. According to paragraph 1,
The occupied processing element is
A neural processor that outputs information indicating the occupied processing element along with an operation result of the overflow accumulator and an operation result of the occupied processing element as the vector operation is terminated. According to paragraph 1,
Among the processing elements, unoccupied processing elements excluding the occupied processing element are
A neural processor that outputs an operation result of an accumulator of the unoccupied processing elements as the vector operation is terminated. According to paragraph 1,
The neural processor is
When an overflow signal or an underflow signal is simultaneously received from two or more of the plurality of processing elements, one of the two or more processing elements is randomly set as the occupied processing element. , neural processor. According to paragraph 1,
The register is
A neural processor further storing information indicating whether overflow or underflow occurred in the occupied processing element. According to paragraph 1,
Each of the processing elements is
A neural processor, comprising a plurality of multipliers, a plurality of adders, and an accumulator. According to paragraph 1,
Each of the processing elements is
A neural processor, including a multiplier-adder tree (MAT), an adder, and an accumulator. According to paragraph 1,
The overflow accumulator is
Neural processor, including an accumulator and an adder. checking whether an overflow accumulator shared by a plurality of processing elements performing a vector operation is occupied by at least one of the plurality of processing elements;
When the overflow accumulator is not occupied, setting a processing element that outputs an overflow signal or an underflow signal among the processing elements as an occupied processing element;
When the overflow accumulator is occupied, controlling the overflow accumulator to add or subtract according to a signal output from an occupied processing element that occupies the overflow accumulator; and
As the vector operation is terminated, outputting information indicating the occupied processing element together with the operation result of the overflow accumulator and the operation result of the occupied processing element.
A control method of a neural processor, including. According to clause 15,
The above checking steps are
Checking whether the overflow accumulator is occupied by at least one of the plurality of processing elements, based on information indicating the occupied processing element.
A control method of a neural processor, including. According to clause 15,
The controlling step is
If the overflow accumulator is occupied,
adding 1 to the overflow accumulator according to an overflow signal output from a processing element occupying the overflow accumulator; and
Subtracting 1 from the overflow accumulator according to an underflow signal output from the processing element occupying the overflow accumulator.
A control method of a neural processor, including. According to clause 15,
The output step is
A step of outputting a result of adding the data of the overflow accumulator and the operation result of the occupied processing element through a pipeline interconnection connected vertically between the occupied processing element and the overflow accumulator.
A control method of a neural processor, including. According to clause 15,
When the overflow signal or the underflow signal is simultaneously received from two or more processing elements among the plurality of processing elements, one of the two or more processing elements is randomly assigned to the occupied processing element. Steps to set up
A control method of a neural processor, further comprising: A computer program stored in a computer-readable recording medium in combination with hardware to execute the method of any one of claims 15 to 19.

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