KR102628535B1 - Semiconductor device - Google Patents

Abstract

The semiconductor device latches the internal chip selection signal and internal control signal in synchronization with the divided clock to generate a latch chip selection signal and a latch control signal, and generates an effective command for performing a preset function from the latch control signal. generating circuit; a reset pulse generation circuit that generates a reset pulse in response to an internal chip selection signal; and a training control circuit that generates a training result signal from a latch control signal in response to the flag and initializes the training result signal in response to the reset pulse.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device that performs training.

For mobile devices such as portable computers, PDAs, and mobile phones, it is important to reduce weight to increase portability. An important component that determines the weight of a mobile device is the battery that supplies operating power. As the power consumption of the semiconductor device used in the mobile device is reduced, the capacity of the battery decreases, so by reducing the power consumption of the semiconductor device, the mobile device The weight of the device can be reduced. In the case of mobile devices, as they gradually develop into multimedia devices that provide a variety of services, fast operating speeds are required, and accordingly, it serves as an important factor in determining the data transfer speed of the mobile memory chip or the operating speed of the mobile device.

Recently, semiconductor devices receive commands and addresses simultaneously through multiple pins instead of receiving commands and addresses through separate pins (PINs). At this time, the signal input through a plurality of pins includes both command and address information, and the command decoder and address decoder decode the signal input through a plurality of pins to extract the command and address.

In the case of synchronous semiconductor devices, commands and addresses are input in synchronization with the clock. DDR (Double Data Rate) type semiconductor devices receive inputs by synchronizing commands and addresses with the rising edge and falling edge of the clock, and SDR (Single Data Rate) type semiconductor devices receive commands and addresses. is input in synchronization with the rising edge of the clock.

The present invention provides a semiconductor device that performs training on control signals.

For this purpose, the present invention latches the internal chip selection signal and internal control signal in synchronization with the divided clock to generate a latch chip selection signal and a latch control signal, and generates an effective command for performing a preset function from the latch control signal. Effective command generation circuit; a reset pulse generation circuit that generates a reset pulse in response to an internal chip selection signal; and a training control circuit that generates a training result signal from a latch control signal in response to a flag and initializes the training result signal in response to the reset pulse.

In addition, the present invention includes an effective command generation circuit that latches an internal control signal in synchronization with a divided clock to generate a latch control signal, and generates an effective command for performing a preset function from the latch control signal; a reset pulse generation circuit that generates a reset pulse in response to an internal chip selection signal; and a training control circuit that generates a training result signal from the latch control signal in response to a flag and initializes the training result signal in response to the reset pulse.

According to the present invention, by resetting the training result signal according to a reset pulse generated in synchronization with the chip selection signal, there is an effect of performing a training operation for the control signal at a high speed.

In addition, according to the present invention, by performing training on a continuously variable control signal using only the pulse generation circuit, there is an effect of reducing the increase in layout area due to the use of additional circuits.

1 is a block diagram showing the configuration of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a block diagram showing the configuration of an effective command generation circuit included in the semiconductor device shown in FIG. 1 according to an embodiment.
FIG. 3 is a block diagram showing the configuration of a comparison output circuit included in the effective command generation circuit shown in FIG. 2 according to an embodiment.
FIG. 4 is a block diagram showing the configuration of a training control circuit included in the semiconductor device shown in FIG. 1 according to an embodiment.
Figure 5 is a table defining the functions of effective commands performed according to the logic level combination of bits included in the control signal published in the JEDEC standard.
FIG. 6 is a timing diagram for explaining the operation of the semiconductor device shown in FIG. 1.
FIG. 7 is a timing diagram for explaining a training operation performed in the semiconductor device shown in FIG. 1.
FIG. 8 is a diagram illustrating the configuration of an electronic system to which the semiconductor device shown in FIG. 1 is applied according to an embodiment.

Hereinafter, the present invention will be described in more detail through examples. These examples are only for illustrating the present invention, and the scope of rights protection of the present invention is not limited by these examples.

As shown in FIG. 1, the semiconductor device according to an embodiment of the present invention includes an input buffer circuit (1), a divided clock generator (2), an effective command generation circuit (3), a flag generation circuit (4), and a reset pulse. It may include a generation circuit (5), a training control circuit (6), an output pad (7), and an operation control circuit (8).

The input buffer circuit (1) responds to the clock (CLK), control signal (CA<1:L>), and chip select signal (CS) by generating the internal clock (ICLK), internal control signal (ICA<1:L>), and An internal chip select signal (ICS) can be generated. The clock (CLK) may be applied from a controller (not shown) or a host (not shown) external to the semiconductor device. The control signal (CA<1:L>) may be input through a line (not shown) through which a command or address is applied. The control signal (CA<1:L>) may be applied from a controller (not shown) or a host (not shown) external to the semiconductor device. The chip select signal CS may be enabled to select a semiconductor device and perform a specific function. The chip select signal CS may be applied from a controller (not shown) or a host (not shown) external to the semiconductor device. The input buffer circuit 1 may include a buffer (not shown) that can generate an internal clock (ICLK) by buffering the clock (CLK). The input buffer circuit 1 may include a buffer (not shown) that can generate an internal control signal (ICA<1:L>) by buffering the control signal (CA<1:L>). The input buffer circuit 1 may include a buffer (not shown) that can generate an internal chip select signal (ICS) by buffering the chip select signal (CS).

The divided clock generator 2 may generate a first divided clock (CLKR1), a second divided clock (CLKF1), a third divided clock (CLKR2), and a fourth divided clock (CLKF2) from the internal clock (ICLK). The first divided clock (CLKR1), the second divided clock (CLKF1), the third divided clock (CLKR2), and the fourth divided clock (CLKF2) may be generated as a signal divided by 2 of the internal clock (ICLK). The period of each of the first divided clock (CLKR1), second divided clock (CLKF1), third divided clock (CLKR2), and fourth divided clock (CLKF2) may be formed to be twice larger than the period of the internal clock (ICLK). . Depending on the embodiment, the first divided clock (CLKR1), the second divided clock (CLKF1), the third divided clock (CLKR2), and the fourth divided clock (CLKF2) may be generated as an N divided signal of the internal clock (ICLK). . Here, N may be set to a natural number greater than 3. The first divided clock (CLKR1) and the third divided clock (CLKR2) can be generated in synchronization with the rising edge of the internal clock (ICLK), and the second divided clock (CLKF1) and the fourth divided clock (CLKF2) ) can be generated in synchronization with the falling edge of the internal clock (ICLK). The phase of the second divided clock CLKF1 may be set to be 90° later than the phase of the first divided clock CLKR1. The phase of the third divided clock CLKR2 may be set to be 90° later than the phase of the second divided clock CLKF1. The phase of the fourth divided clock CLKF2 may be set to be 90° later than the phase of the third divided clock CLKR2. In this embodiment, the phase difference between the first divided clock (CLKR1), the second divided clock (CLKF1), the third divided clock (CLKR2), and the fourth divided clock (CLKF2) is set to 90°, but may vary depending on the embodiment. can be set.

The effective command generation circuit 3 is synchronized with the first divided clock (CLKR1), second divided clock (CLKF1), third divided clock (CLKR2), and fourth divided clock (CLKF2) to generate an internal control signal (ICA < 1: L>) and the internal chip selection signal (ICS), the first latch control signal (LCA1<1:L>), the second latch control signal (LCA2<1:L>), the first latch chip selection signal (LCS1), A second latch chip selection signal (LCS2), a first effective command (VCMD1), and a second effective command (VCMD2) can be generated. The effective command generation circuit 3 may latch the internal chip select signal ICS in synchronization with the first divided clock CLKR1 to generate the first latch chip select signal LCS1. The effective command generation circuit 3 may latch the internal chip select signal ICS in synchronization with the third divided clock CLKR2 to generate the second latch chip select signal LCS2. The effective command generation circuit 3 latches the internal control signal (ICA<1:L>) in synchronization with the first divided clock (CLKR1) and the first latch chip selection signal (LCS1) to generate the first latch control signal (LCA1< 1:L>) can be generated. The effective command generation circuit 3 latches the internal control signal (ICA<1:L>) in synchronization with the third divided clock (CLKR2) and the second latch chip selection signal (LCS2) to generate the second latch control signal (LCA2<1:L>). 1:L>) can be generated. The effective command generation circuit 3 generates a second divided clock (CLKF1) when the first latch control signal (LCA1<1:L>) and the second latch control signal (LCA2<1:L>) have the same logic level combination. ) can be generated in synchronization with the first effective command (VCMD1). The effective command generation circuit 3 generates a fourth divided clock CLKF2 when the first latch control signal LCA1<1:L> and the second latch control signal LCA2<1:L> have the same logic level combination. ) can be generated in synchronization with the second valid command (VCMD2). The effective command generation circuit (3) generates a preset signal when the internal control signal (ICA<1:L>) is input in synchronization with the internal chip select signal (ICS) without changing the logic level during the two-cycle period of the internal clock (ICLK). A first effective command (VCMD1) or a second effective command (VCMD2) for performing a function may be generated. In this embodiment, the first effective signal is enabled when the internal control signal (ICA<1:L>) is input in synchronization with the internal chip select signal (ICS) without changing the logic level during the two-cycle period of the internal clock (ICLK). A command (VCMD1) and a second effective command (VCMD2) are generated. According to the embodiment, the first valid command (VCMD1) and the second valid command (VCMD2) are internal control signals (ICA<1:L>) during the two-cycle period of the internal clock (ICLK) regardless of the internal chip select signal (ICS). ) can be enabled even when input without a change in logic level. The logic level at which the first valid command (VCMD1) and the second valid command (VCMD2) are enabled may be set in various ways depending on the embodiment.

The flag generation circuit 4 may generate a flag (TFLAG) in response to the first valid command (VCMD1) and the second valid command (VCMD2). The flag generation circuit 4 may generate an enabled flag (TFLAG) when the first valid command (VCMD1) or the second valid command (VCMD2) is enabled to perform a preset function. For example, the flag generation circuit 4 generates a flag ( TFLAG) can be created. The logic level at which the flag (TFLAG) is enabled may be set in various ways depending on the embodiment.

The reset pulse generation circuit 5 may generate a reset pulse (R_PUL) in response to the internal chip select signal (ICS). The reset pulse generation circuit 5 may generate a reset pulse (R_PUL) that is enabled when the internal chip select signal (ICS) changes level. For example, the reset pulse generation circuit 5 may generate a reset pulse (R_PUL) that is enabled when the internal chip select signal (ICS) transitions from a logic high level to a logic low level. Enabled reset pulse (R_PUL) means that it is generated as a pulse, and depending on the embodiment, it may correspond to a signal with a specific logic level.

The training control circuit 6 responds to the flag (TFLAG) and the reset pulse (R_PUL) by sending a first latch control signal (LCA1<1:L>), a second latch control signal (LCA2<1:L>), and a first latch control signal (LCA2<1:L>). A training result signal (TRS) can be generated from the latch chip selection signal (LCS1) and the second latch chip selection signal (LCS2). When the control signal training entry (CA training entry) function is performed and the flag (TFLAG) is enabled, the training control circuit 6 outputs the first latch control signal (LCA1<1:L>) or the second latch control signal (LCA2). <1:L>), a training result signal (TRS) can be generated. The control signal training entry (CA training entry) function is a first latch control signal (LCA1<1:L>) that is output as a training result signal (TRS) in synchronization with the time when the chip selection signal (CS) for which training is completed is enabled. Alternatively, it can be performed by detecting the logic level combination of the second latch control signal (LCA2<1:L>) and adjusting the input timing of the control signal (CA<1:L>). The training control circuit 6 can initialize the training result signal (TRS) when the reset pulse (R_PUL) is enabled. The logic level of the training result signal (TRS) initialized by the reset pulse (R_PUL) may be set in various ways depending on the embodiment. The training control circuit 6 can output the generated training result signal (TRS) through the output pad 7. Depending on the embodiment, the output pad 7 may be implemented as a pad through which data is output.

The operation control circuit 8 may receive the first effective command (VCMD1) and the second effective command (VCMD2) and perform preset functions. The functions performed by the first effective command (VCMD1) and the second effective command (VCMD2) include control signal reference voltage setting, control signal termination resistance setting, chip selection signal training entry (CS training entry), and chip selection. It may include signal training exit (CS training exit), control signal training entry (CA training entry), and control signal training exit (CA training exit). The control signal reference voltage setting function sets the reference voltage used to buffer the control signal (CA<1:L>) in the input buffer (not shown) where the control signal (CA<1:L>) is input during training. This can be performed through the operation of setting the level. The control signal termination resistance setting function can be performed through an operation of setting the resistance value of a termination resistor connected to a pad (not shown) through which a control signal is input while training is performed. The chip selection signal training entry (CS training entry) function may be performed to enter chip selection signal training, and the chip selection signal training exit (CS training exit) function may be performed to end chip selection signal training. The control signal training entry (CA training entry) function may be performed to enter control signal training, and the control signal training exit (CA training exit) function may be performed to end control signal training. In this embodiment, the first effective command (VCMD1) and the second effective command (VCMD2) are expressed as singular numbers, but depending on the embodiment, they may be implemented as a plurality of signals provided for each function.

Referring to FIG. 2, the effective command generation circuit 3 may include a first input latch circuit 31, a second input latch circuit 32, a command decoder 33, and a comparison output circuit 34.

The first input latch circuit 31 selects the first latch chip selection signal (LCS1) or the second latch chip from the internal chip selection signal (ICS) in response to the first divided clock (CLKR1) and the third divided clock (CLKR2). A signal (LCS2) can be generated. The first input latch circuit 31 may latch the internal chip select signal ICS in synchronization with the first divided clock CLKR1 to generate the first latch chip select signal LCS1. The first input latch circuit 31 may latch the internal chip select signal ICS in synchronization with the third divided clock CLKR2 to generate the second latch chip select signal LCS2.

The second input latch circuit 32 generates an internal control signal in response to the first divided clock (CLKR1), the third divided clock (CLKR2), the first latch chip selection signal (LCS1), and the second latch chip selection signal (LCS2). The first latch control signal (LCA1<1:L>) or the second latch control signal (LCA2<1:L>) can be generated from (ICA<1:L>). The second input latch circuit 32 latches the internal control signal (ICA<1:L>) in synchronization with the first divided clock (CLKR1) while the first latch chip selection signal (LCS1) is enabled. A latch control signal (LCA1<1:L>) can be generated. The second input latch circuit 32 latches the internal control signal (ICA<1:L>) in synchronization with the third divided clock (CLKR2) while the second latch chip selection signal (LCS2) is enabled. A latch control signal (LCA2<1:L>) can be generated.

The command decoder 33 generates the first internal command (ICMD1) or the second internal command (ICMD2) in response to the first latch control signal (LCA1<1:L>) and the second latch control signal (LCA2<1:L>). ) can be created. The command decoder 33 may generate a first internal command (ICMD1) by decoding the first latch control signal (LCA1<1:L>). The first internal command ICMD1 may be enabled to perform preset functions. Preset functions include control signal reference voltage setting, control signal termination resistance setting, chip selection signal training entry (CS training entry), chip selection signal training exit (CS training exit), and control signal training entry (CA training entry). and control signal training exit (CA training exit). The command decoder 33 may generate a second internal command (ICMD2) by decoding the second latch control signal (LCA2<1:L>). The second internal command ICMD2 may be enabled to perform preset functions.

The comparison output circuit 34 generates a first latch control signal (LCA1<1:L>) and a second latch control signal (LCA2<1:L) in synchronization with the second divided clock (CLKF1) and the fourth divided clock (CLKF2). >), and according to the comparison result, the first effective command (VCMD1) or the second effective command (VCMD2) can be generated from the first internal command (ICMD1) and the second internal command (ICMD2). The comparison output circuit 34 generates the same logic level combination of the first latch control signal (LCA1<1:L>) and the second latch control signal (LCA2<1:L>) in synchronization with the second divided clock (CLKF1). In this case, the first internal command (ICMD1) can be output as the first effective command (VCMD1). The comparison output circuit 34 generates the same logic level combination of the first latch control signal (LCA1<1:L>) and the second latch control signal (LCA2<1:L>) in synchronization with the fourth divided clock (CLKF2). In this case, the second internal command (ICMD2) can be output as the second effective command (VCMD2). A more detailed configuration and operation of the comparison output circuit 34 will be examined with reference to FIG. 3 as follows.

As shown in FIG. 3, the comparison output circuit 34 may include a first comparator 341, a second comparator 342, a first latch output circuit 343, and a second latch output circuit 344. there is.

The first comparator 341 performs a first comparison by comparing the first latch control signal (LCA1<1:L>) and the second latch control signal (LCA2<1:L>) in synchronization with the second divided clock (CLKF1). A pulse (CP1) can be generated. The first comparator 341 is a logic level combination of the first latch control signal (LCA1<1:L>) and the second latch control signal (LCA2<1:L>) input in synchronization with the second divided clock (CLKF1). In this case, an enabled first comparison pulse CP1 can be generated. In this embodiment, enabling the first comparison pulse CP1 means that it is generated as a pulse, and depending on the embodiment, the enabled first comparison pulse CP1 may correspond to a signal having a specific logic level.

The second comparator 342 performs a second comparison by comparing the first latch control signal (LCA1<1:L>) and the second latch control signal (LCA2<1:L>) in synchronization with the fourth divided clock (CLKF2). A pulse (CP2) can be generated. The second comparator 342 is a logic level combination of the first latch control signal (LCA1<1:L>) and the second latch control signal (LCA2<1:L>) input in synchronization with the fourth divided clock (CLKF2). In this case, an enabled second comparison pulse CP2 can be generated. In this embodiment, enabling the second comparison pulse CP2 means that it is generated as a pulse, and depending on the embodiment, the enabled first comparison pulse CP1 may correspond to a signal having a specific logic level.

The first latch output circuit 343 may generate a first valid command (VCMD1) from the first internal command (ICMD1) in response to the first comparison pulse (CP1). When the first comparison pulse CP1 is enabled, the first latch output circuit 343 may latch the first internal command ICMD1 and then output it as the first valid command VCMD1.

The second latch output circuit 344 may generate a second valid command (VCMD2) from the second internal command (ICMD2) in response to the second comparison pulse (CP2). When the second comparison pulse CP2 is enabled, the second latch output circuit 344 may latch the second internal command ICMD2 and then output it as the second effective command VCMD2.

Referring to FIG. 4, the training control circuit 6 may include a control signal synthesis unit 61 and an output latch 62.

The control signal synthesis unit 61 synthesizes the first latch control signal (LCA1<1:L>) and the second latch control signal (LCA2<1:L>) to create a first composite control signal (CA_SUM1) and a second composite control signal. A control signal (CA_SUM2) can be generated. The control signal synthesis unit 61 may generate a first composite control signal (CA_SUM1) by combining the first latch control signal (LCA1<1:L>). The first composite control signal CA_SUM1 may be generated with a logic level set according to the logic level combination of bits included in the first latch control signal LCA1<1:L>. For example, the first composite control signal (CA_SUM1) has a logic high level if the logic levels of the bits included in the first latch control signal (LCA1<1:L>) are all the same, and has a logic low level if they are not all the same. It can be set to have a level. The control signal synthesis unit 61 may generate a second composite control signal (CA_SUM2) by combining the second latch control signal (LCA2<1:L>). The second composite control signal CA_SUM2 may be generated with a logic level set according to the logic level combination of bits included in the second latch control signal LCA2<1:L>. For example, the second composite control signal (CA_SUM2) has a logic high level if the logic levels of the bits included in the second latch control signal (LCA2<1:L>) are all the same, and has a logic low level if they are not all the same. It can be set to have a level.

The output latch 62 generates a first composite control signal (CA_SUM1) or a second composite control signal (CA_SUM2) in response to the flag (TFLAG), the first latch chip selection signal (LCS1), and the second latch chip selection signal (LCS2). Can be output as a training result signal (TRS). The output latch 62 performs the first synthesis control when the first latch chip select signal (LCS1) is enabled while the flag (TFLAG) is enabled to perform the control signal training entry (CA training entry) function. The signal (CA_SUM1) can be output as a training result signal (TRS). The output latch 62 outputs the second composite control signal (CA_SUM2) as the training result signal (TRS) when the flag (TFLAG) is enabled and the second latch chip selection signal (LCS2) is enabled. You can. The output latch 62 can initialize the training result signal (TRS) to a preset logic level when the reset pulse (R_PUL) is enabled. The logic level at which the training result signal (TRS) is initialized may be set in various ways depending on the embodiment.

Referring to FIG. 5, a table related to the Joint Electron Device Engineering Council (JEDEC) specifications that defines the function of the effective command performed according to the logic level combination of the bits (CA0 to CA13) included in the control signal (CA). You can check it. The functions of the effective command include control signal reference voltage setting, control signal termination resistance setting, chip selection signal training entry (CS training entry), chip selection signal training exit (CS training exit), and control signal training entry (CA training entry). ) and control signal training exit (CA training exit) may be included. In the table according to this embodiment, the number of bits and bit levels included in the control signals (CA0 to CA13) can be set in various ways depending on the embodiment.

The control signal reference voltage setting function can be performed by setting the level of the reference voltage used to buffer the control signal (CA) in the input buffer (not shown) where the control signal (CA) is input while training is performed. there is. To perform the control signal reference voltage setting function, the logic level combination of 'H, H, L, H, L, L' is input through control signals (CA0~CA5), and through control signals (CA6~CA13) A signal necessary to set the reference voltage may be input. The logic level combination of the control signals (CA0 to CA5) input to perform the control signal reference voltage setting function can be set in various ways depending on the embodiment.

The control signal termination resistance setting function can be performed through an operation of setting the resistance value of a termination resistor connected to a pad (not shown) through which a control signal is input while training is performed. To perform the control signal termination resistance setting function, the logic level combination of 'H, H, L, H, L, H' is input through the control signals (CA0~CA5), and through the control signals (CA6~CA13) The signal necessary to set the resistance value of the termination resistor can be input. The logic level combination of the control signals (CA0 to CA5) input to perform the control signal termination resistance setting function can be set in various ways depending on the embodiment.

The chip select signal training entry (CS training entry) function can be performed to enter chip select signal training. To perform the chip selection signal training entry function, a logic level combination of 'H, H, L, H, H, L, L' is input through control signals (CA0 to CA6). When the chip selection signal training entry function is performed, any signal can be input through the control signals (CA7 to CA13), and this is indicated as a blank space in the table. The logic level combination of the control signals (CA0 to CA13) input to perform the chip selection signal training entry function can be set in various ways depending on the embodiment.

The chip select signal training exit (CS training exit) function may be performed to end chip select signal training. To perform the chip selection signal training escape function, a logic level combination of 'H, H, L, H, H, L, H' is input through control signals (CA0 to CA6). When the chip selection signal training escape function is performed, any signal can be input through the control signals (CA7 to CA13), and this is indicated as a blank space in the table. The logic level combination of the control signals (CA0 to CA13) input to perform the chip selection signal training escape function can be set in various ways depending on the embodiment.

The control signal training entry (CA training entry) function can be performed to enter control signal training. To perform the control signal training entry function, a logic level combination of 'H, H, L, H, H, H, L' is input through control signals (CA0 to CA6). When the control signal training entry function is performed, any signal can be input through the control signals (CA7 to CA13), and this is indicated as a blank space in the table. The logic level combination of the control signals (CA0 to CA13) input to perform the control signal training entry function can be set in various ways depending on the embodiment.

The control signal training exit (CA training exit) function can be performed to enter control signal training. To perform the control signal training escape function, a logic level combination of 'H, H, L, H, H, H, H' is input through control signals (CA0 to CA6). When the control signal training escape function is performed, any signal can be input through the control signals (CA7 to CA13), and this is indicated as a blank space in the table. The logic level combination of the control signals (CA0 to CA13) input to perform the control signal training escape function can be set in various ways depending on the embodiment.

The operation of performing a function by a valid command in a semiconductor device according to an embodiment of the present invention will be described in detail with reference to FIG. 6.

At time T12, the chip select signal CS, enabled at the logic low level in synchronization with the rising edge of the first divided clock CLKR1, is inverted buffered and output as the first latch chip select signal LCS1. At time T11, the chip select signal CS, enabled at the logic low level in synchronization with the rising edge of the third divided clock CLKR2, is inverted buffered and output as the second latch chip select signal LCS2.

At time T12, the logic level combination for performing the first function (F1) of the control signal (CA<1:L>) is latched in synchronization with the rising edge of the first divided clock (CLKR1) and the first internal command (ICMD1) is created with At time T11, the logic level combination for performing the first function (F1) of the control signal (CA<1:L>) is latched in synchronization with the rising edge of the third divided clock (CLKR2) and the second internal command (ICMD2) is created with

At time T13, the first internal command (ICMD1) and the second internal command (ICMD2) have the same logic level combination. This is the first latch control signal (LCA1<1:L>) used to generate the first internal command (ICMD1) and the second latch control signal (LCA2<1:L) used to generate the second internal command (ICMD2). Since the logic level combination of >) is the same, the first comparison pulse CP1 that is enabled in synchronization with the rising edge of the second divided clock CLKF1 is generated. The first internal command (ICMD1) is output as the first effective command (VCMD1) by the enabled first comparison pulse (CP1). Since the first valid command VCMD1 is generated in an enabled state, the first function F1 is performed. The first function (F1) is control signal reference voltage setting, control signal termination resistance setting, chip selection signal training entry (CS training entry), chip selection signal training exit (CS training exit), and control signal training entry (CA training entry). and control signal training exit (CA training exit). The second comparison pulse CP2 generated in synchronization with the rising edge of the fourth divided clock CLKF2 remains in a disabled state.

At time T15, the chip select signal CS, enabled at the logic low level in synchronization with the rising edge of the first divided clock CLKR1, is inverted buffered and output as the first latch chip select signal LCS1. At time T14, the chip select signal CS, enabled at the logic low level in synchronization with the rising edge of the third divided clock CLKR2, is inverted and buffered and output as the second latch chip select signal LCS2.

At time T15, the logic level combination for performing the third function (F3) of the control signal (CA<1:L>) is latched in synchronization with the rising edge of the first divided clock (CLKR1) and the first internal command (ICMD1) is created with At time T14, the logic level combination for performing the second function (F2) of the control signal (CA<1:L>) is latched in synchronization with the rising edge of the third divided clock (CLKR2), and the second internal command (ICMD2) is generated. is created with

At time T15, the first internal command (ICMD1) and the second internal command (ICMD2) have different logic level combinations. Since the first comparison pulse CP1 generated in synchronization with the rising edge of the second divided clock CLKF1 at time T16 remains in a disabled state, the first comparison pulse CP1 is enabled to perform a preset function. The command (VCMD1) and the second valid command (VCMD2) are not generated.

The control signal training operation of the semiconductor device configured as described above will be examined with reference to FIG. 7 as follows.

At time T21, a control signal (CA<1:L>) having a logic level combination for the first function (F1) is latched in synchronization with the chip select signal (CS) that is enabled and input at a timing set by training. The control signal (CA<1:L>) having the logic level combination for the first function (F1) is latched and then synthesized to generate a composite control signal (CA_SUM(F1)). At time T21, a reset pulse (R_PUL) enabled by the chip select signal (CS) transitioning from logic high level to logic low level is generated, and the training result signal (TRS) is at a level preset by the reset pulse (R_PUL). It is initialized as At time T22, the composite control signal (CA_SUM(F1)) is output as the training result signal (TRS) and is used to adjust the input timing of the control signal (CA<1:L>).

At time T23, a control signal (CA<1:L>) having a logic level combination for the third function (F3) is latched in synchronization with the chip select signal (CS) that is enabled and input at a timing set by training. The control signal (CA<1:L>) having the logic level combination for the third function (F3) is latched and then synthesized to generate a composite control signal (CA_SUM(F3)). At point T43, a reset pulse (R_PUL) enabled by the chip select signal (CS) transitioning from logic high level to logic low level is generated, and the training result signal (TRS) is at a level preset by the reset pulse (R_PUL). It is initialized as At time T44, the composite control signal (CA_SUM(F3)) is output as the training result signal (TRS) and is used to adjust the input timing of the control signal (CA<1:L>).

As described above, the semiconductor device according to this embodiment can initialize the training result signal (TRS) to a preset level according to the reset pulse (R_PUL) generated when the chip selection signal (CS) transitions in level. Therefore, when a control signal (CA<1:L>) with a different logic level combination is input to perform another function, the semiconductor device immediately sends the control signal (CA<1:L>) without performing training on the chip select signal (CS). L>) can be trained. As a result, training on control signals (CA<1:L>) with various logic level combinations can be performed at high speed. Additionally, control signals (CA<1:L>) having different logic level combinations can be trained using only the circuit that generates the reset pulse (R_PUL), thereby reducing the layout area.

Previously, the semiconductor device examined in FIG. 1 can be applied to electronic systems including memory systems, graphics systems, computing systems, and mobile systems. For example, referring to FIG. 8, the electronic system 1000 according to an embodiment of the present invention may include a data storage unit 1001, a memory controller 1002, a buffer memory 1003, and an input/output interface 1004. You can.

The data storage unit 1001 stores data received from the memory controller 1002 according to a control signal from the memory controller 1002, reads the stored data, and outputs it to the memory controller 1002. The data storage unit 1001 may include the semiconductor device shown in FIG. 1. Meanwhile, the data storage unit 1001 may include a non-volatile memory that can continue to store data without losing it even when the power is turned off. Non-volatile memory includes flash memory (NOR Flash Memory, NAND Flash Memory), Phase Change Random Access Memory (PRAM), Resistive Random Access Memory (RRAM), and Spin Transfer Torque Random. It can be implemented with Access Memory (STTRAM) and Magnetic Random Access Memory (MRAM).

The memory controller 1002 decodes commands applied from an external device (host device) through the input/output interface 1004 and controls data input/output to the data storage unit 1001 and buffer memory 1003 according to the decoded result. . In FIG. 8, the memory controller 1002 is shown as one block, but the memory controller 1002 includes a controller for controlling the data storage unit 1001 and a controller for controlling the buffer memory 1003, which is a volatile memory, independently. It can be configured.

The buffer memory 1003 can temporarily store data to be processed by the memory controller 1002, that is, data input and output to the data storage unit 1001. The buffer memory 1003 can store data (DATA) applied from the memory controller 1002 according to a control signal. The buffer memory 1003 reads the stored data and outputs it to the memory controller 1002. The buffer memory 1003 may include volatile memory such as dynamic random access memory (DRAM), mobile DRAM, and static random access memory (SRAM).

The input/output interface 1004 provides a physical connection between the memory controller 1002 and an external device (host), allowing the memory controller 1002 to receive control signals for data input and output from the external device and exchange data with the external device. It allows you to The input/output interface 1004 may include one of various interface protocols such as USB, MMC, PCI-E, SAS, SATA, PATA, SCSI, ESDI, and IDE.

The electronic system 1000 may be used as an auxiliary storage device or an external storage device of a host device. The electronic system 1000 includes solid state disk (SSD), USB memory (Universal Serial Bus Memory), Secure Digital (SD), mini Secure Digital card (mSD), and Micro Secure. Digital Card (micro SD), Secure Digital High Capacity (SDHC), Memory Stick Card, Smart Media Card (SM), Multi Media Card (MMC) , an embedded multi-media card (Embedded MMC; eMMC), a compact flash card (Compact Flash; CF), etc.

1: Input buffer circuit 2: Divided clock generator
3: Effective command generation circuit 4: Flag generation circuit
5: Reset pulse generation circuit 6: Training control circuit
7: Output pad 8: Operation control circuit
31: first input latch circuit 32: second input latch circuit
33: Command decoder 34: Comparison output circuit
331: first comparator 332: second comparator
333: first latch output circuit 334: second latch output circuit
61: Control signal synthesis unit 62: Output latch

Claims (20)

An effective command generation circuit that latches an internal chip selection signal and an internal control signal in synchronization with a divided clock to generate a latch chip selection signal and a latch control signal, and generates an effective command for performing a preset function from the latch control signal;
a reset pulse generation circuit that generates a reset pulse in response to an internal chip selection signal; and
A semiconductor device comprising a training control circuit that generates a training result signal from the latch control signal in response to a flag and initializes the training result signal in response to the reset pulse.
◈Claim 2 was abandoned upon payment of the setup registration fee.◈ The semiconductor device of claim 1, wherein the reset pulse generating circuit generates the reset pulse that is enabled in synchronization with a level transition point of the internal chip select signal.
◈Claim 3 was abandoned upon payment of the setup registration fee.◈ The method of claim 1, wherein the training control circuit is
A semiconductor device comprising an output latch that outputs a first composite control signal or a second composite control signal as the training result signal in response to the flag and the latch chip selection signal.
◈Claim 4 was abandoned upon payment of the setup registration fee.◈ The method of claim 3, wherein the divided clock includes a first divided clock generated in synchronization with a rising edge of the clock and a second divided clock generated in synchronization with a falling edge of the clock,
The latch chip selection signal includes a first latch chip selection signal latched in synchronization with the first divided clock,
The first composite control signal is generated by combining a first latch control signal generated by latching the internal control signal in response to the first divided clock and the first latch chip select signal.
◈Claim 5 was abandoned upon payment of the setup registration fee.◈ The semiconductor device of claim 1, wherein the preset functions include setting a control signal reference voltage, setting a control signal termination resistance, entering chip selection signal training, exiting chip selection signal training, entering control signal training, and exiting control signal training.
◈Claim 6 was abandoned upon payment of the setup registration fee.◈ The semiconductor device of claim 1, wherein the effective command is enabled when a logic level combination of the latch control signal is constant during N cycle periods of the clock, where N is set to a natural number.
◈Claim 7 was abandoned upon payment of the setup registration fee.◈ The semiconductor device of claim 1, wherein the divided clock is generated by dividing a clock, the period of the divided clock is N times greater than the period of the clock, and N is set to a natural number.
◈Claim 8 was abandoned upon payment of the setup registration fee.◈ According to claim 1,
The divided clock includes first to fourth divided clocks,
The first and third divided clocks are generated in synchronization with the rising edge of the clock,
The second and fourth divided clocks are generated in synchronization with the falling edge of the clock,
The second divided clock is slower in phase than the first divided clock,
The third divided clock is slower in phase than the second divided clock,
A semiconductor device wherein the fourth divided clock is set to have a slower phase than the third divided clock.
◈Claim 9 was abandoned upon payment of the setup registration fee.◈ The method of claim 1, wherein the divided clock includes first and third divided clocks generated in synchronization with a rising edge of the clock,
The effective command generation circuit is
The internal chip select signal is latched in synchronization with the first divided clock to generate a first latch chip select signal, and the internal chip select signal is latched in synchronization with the third divided clock to generate a second latch chip select signal. A semiconductor device including an input latch circuit that
◈Claim 10 was abandoned upon payment of the setup registration fee.◈ According to claim 1,
The divided clock includes first and third divided clocks generated in synchronization with the rising edge of the clock,
The latch chip selection signal includes a first latch chip selection signal latched in synchronization with the first divided clock and a second latch chip select signal latched in synchronization with the third divided clock,
The effective command generation circuit is
A first latch control signal is generated by latching the internal control signal in response to the first divided clock and the first latch chip select signal, and the internal control signal is generated in response to the third divided clock and the second latch chip select signal. A semiconductor device including an input latch circuit that latches a control signal to generate a second latch control signal.
◈Claim 11 was abandoned upon payment of the setup registration fee.◈ The method of claim 1, wherein the divided clock includes second and fourth divided clocks generated in synchronization with falling edges of the clock,
The latch control signal includes a first latch control signal and a second latch control signal, and the effective command generation circuit is
A comparison output circuit that generates a first effective command or a second effective command by comparing a logic level combination of the first latch control signal and the second latch control signal in synchronization with the second divided clock or the fourth divided clock. Including semiconductor devices.
◈Claim 12 was abandoned upon payment of the setup registration fee.◈ The method of claim 11, wherein the comparison output circuit is
a first comparator that generates a first comparison pulse that is enabled when the logic level combination of the first latch control signal and the second latch control signal is the same in synchronization with the second divided clock; and
A semiconductor device comprising a first latch output circuit that outputs a first internal command as the first effective command in response to the first comparison pulse.
an effective command generation circuit that latches an internal control signal in synchronization with a divided clock to generate a latch control signal, and generates an effective command for performing a preset function from the latch control signal;
a reset pulse generation circuit that generates a reset pulse in response to an internal chip selection signal; and
A semiconductor device comprising a training control circuit that generates a training result signal from the latch control signal in response to a flag and initializes the training result signal in response to the reset pulse.
◈Claim 14 was abandoned upon payment of the setup registration fee.◈ The semiconductor device of claim 13, wherein the reset pulse generating circuit generates the reset pulse that is enabled in synchronization with a level transition point of the internal chip select signal.
◈Claim 15 was abandoned upon payment of the setup registration fee.◈ The method of claim 13, wherein the training control circuit
A semiconductor device comprising an output latch that outputs a first composite control signal or a second composite control signal as the training result signal in response to the flag and the latch chip selection signal.
◈Claim 16 was abandoned upon payment of the setup registration fee.◈ According to claim 15,
The divided clock includes a first divided clock generated in synchronization with a rising edge of the clock and a second divided clock generated in synchronization with a falling edge of the clock,
The latch chip selection signal includes a first latch chip selection signal latched in synchronization with the first divided clock,
The first composite control signal is generated by combining a first latch control signal generated by latching the internal control signal in response to the first divided clock and the first latch chip select signal.
◈Claim 17 was abandoned upon payment of the setup registration fee.◈ The semiconductor device of claim 13, wherein the preset functions include setting a control signal reference voltage, setting a control signal termination resistance, entering chip selection signal training, exiting chip selection signal training, entering control signal training, and exiting control signal training.
◈Claim 18 was abandoned upon payment of the setup registration fee.◈ The semiconductor device of claim 13, wherein the valid command is enabled when a logic level combination of the latch control signal is constant during N cycle periods of the clock, where N is set to a natural number.
◈Claim 19 was abandoned upon payment of the setup registration fee.◈ The method of claim 13, wherein the divided clock includes second and fourth divided clocks generated in synchronization with falling edges of the clock,
The latch control signal includes a first latch control signal and a second latch control signal,
The effective command generation circuit is
A comparison output circuit that generates a first effective command or a second effective command by comparing a logic level combination of the first latch control signal and the second latch control signal in synchronization with the second divided clock or the fourth divided clock. Including semiconductor devices.
◈Claim 20 was abandoned upon payment of the setup registration fee.◈ The method of claim 19, wherein the comparison output circuit is
a first comparator that generates a first comparison pulse that is enabled when the logic level combination of the first latch control signal and the second latch control signal is the same in synchronization with the second divided clock; and
A semiconductor device comprising a first latch output circuit that outputs a first internal command as the first effective command in response to the first comparison pulse.

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