KR102627459B1 - Integrated circuit including multi-layer conductiong line - Google Patents

Abstract

An integrated circuit including a plurality of layers stacked in a first direction is configured to operate in parallel, according to an exemplary embodiment of the present disclosure, and includes a plurality of unit circuits arranged in a second direction perpendicular to the first direction. , a control circuit configured to generate a control signal for controlling a plurality of unit circuits, and a multilayer conductor configured to transmit a control signal from the control circuit to the plurality of unit circuits, wherein the multilayer conductor includes wiring layers adjacent to each other. and may be integrally formed in the via layer and extend in the second direction.

Description

{INTEGRATED CIRCUIT INCLUDING MULTI-LAYER CONDUCTIONG LINE}

The technical idea of the present disclosure relates to an integrated circuit, and more specifically, to an integrated circuit including multilayer conductors.

As integrated circuits with high operating speeds are required, signal delay occurring in the wiring of the integrated circuit is considered important. Wiring that electrically interconnects two or more elements included in an integrated circuit may have resistance and may form capacitance with adjacent wiring. Signal delay may occur due to the resistance and capacitance of these wires, and as the resistance and capacitance increase, the signal delay may also increase. In addition, due to the miniaturization of semiconductor processes, the size of patterns included in wiring and the distance between adjacent patterns may decrease, and accordingly, the delay of signals occurring in wiring may further intensify, and even in integrated circuits. You can also limit the speed of operation.

The technical idea of the present disclosure provides a multilayer conductor that provides reduced delay and a high-density integrated circuit including the same.

In order to achieve the above object, an integrated circuit according to one aspect of the technical idea of the present disclosure includes a plurality of first patterns formed on a first wiring layer and a first via layer adjacent to the first wiring layer in a first direction. It may include a plurality of first vias, and a multilayer conductor including a first portion extending in a second direction perpendicular to the first direction in the first wiring layer and a second portion extending in a second direction in the first via layer. may be formed, and the first part and the second part may be formed integrally.

An integrated circuit according to one aspect of the technical idea of the present disclosure includes a plurality of first patterns formed on a first wiring layer, a plurality of first vias formed on a first via layer adjacent to the first wiring layer in a first direction, and a first wiring layer. 1 A first part extending from the wiring layer in a second direction perpendicular to the first direction, a second part extending from the first via layer in a second direction, and a second part extending from the first via layer in a second direction between the first part and the second part. 1 May include a multi-layer conductor including a barrier layer.

An integrated circuit including a plurality of layers stacked in a first direction according to an exemplary embodiment of the present disclosure is configured to operate in parallel and includes a plurality of unit circuits arranged in a second direction perpendicular to the first direction. , a control circuit that generates a control signal for controlling a plurality of unit circuits, and a multilayer conductor that provides a control signal from the control circuit to the plurality of unit circuits, wherein the multilayer conductor includes interconnection layers and via layers adjacent to each other. It may be integrally formed and extend in the second direction.

According to example embodiments of the present disclosure, an integrated circuit may include space-efficient interconnections while having reduced interconnection delays due to multilayer conductors.

Additionally, according to example embodiments of the present disclosure, an integrated circuit may have improved operating speed while maintaining a high degree of integration due to the multilayer conductors.

Additionally, according to example embodiments of the present disclosure, an integrated circuit may have improved operational reliability due to the multilayer conductors.

The effects that can be obtained from the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned are exemplary examples of the present disclosure from the description of the exemplary embodiments of the present disclosure below. The embodiments can be clearly derived and understood by those skilled in the art. That is, unintended effects resulting from implementing the exemplary embodiments of the present disclosure may also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

The drawings attached to this specification may not be to scale for convenience of illustration, and may show components exaggerated or reduced.
1 is a diagram schematically showing an integrated circuit 10 according to an exemplary embodiment of the present disclosure.
Figure 2 is a diagram showing the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
3A and 3B are diagrams showing examples of multilayer conductors according to example embodiments of the present disclosure.
Figure 4 is a diagram schematically showing a process of forming a multilayer conductor according to an exemplary embodiment of the present disclosure.
5A and 5B are diagrams showing examples of multilayer conductors according to example embodiments of the present disclosure.
6A to 6E are diagrams showing examples of multilayer conductors according to example embodiments of the present disclosure.
7A and 7B are diagrams showing examples of multilayer conductors according to example embodiments of the present disclosure.
8A and 8B are diagrams showing examples of multilayer conductors according to example embodiments of the present disclosure.
Figure 9 is a block diagram showing a memory device according to an exemplary embodiment of the present disclosure.
FIG. 10 is a diagram illustrating a portion of the layout of the memory device of FIG. 9 according to an exemplary embodiment of the present disclosure.
Figure 11 is a block diagram showing an image sensor according to an exemplary embodiment of the present disclosure.
Figure 12 is a block diagram showing a display device according to an exemplary embodiment of the present disclosure.
Figure 13 is a block diagram showing a system-on-chip (SoC) according to an exemplary embodiment of the present disclosure.

1 is a diagram schematically showing an integrated circuit 10 according to an exemplary embodiment of the present disclosure. Specifically, FIG. 1 is a block diagram of the integrated circuit 10 in which some conductors 14 and 16 included in the layout of the integrated circuit 10 are additionally shown. In this specification, the Z-axis direction is the direction in which a plurality of layers are stacked in the semiconductor process in which the integrated circuit 10 is manufactured and may be referred to as the first direction or vertical direction, and the X-axis direction and Y-axis direction are the second directions. and a third direction, respectively. A component placed in the +Z direction relative to other components may be referred to as being above the other component, and a component placed in the -Z direction relative to other components may be referred to as being below the other component. You can. Additionally, among the surfaces of components, the surface exposed in the +Z direction may be referred to as the top surface, the surface exposed in the -Z direction may be referred to as the bottom surface, and the surface exposed in the X-axis or Y-axis direction may be referred to as the top surface. It can be referred to as a side. Unless otherwise specified in this specification, the length of an element may refer to the length in an extending direction, and the width of an element may refer to the length in a direction perpendicular to the extending direction. Additionally, the height of a component may refer to its length in the Z-axis direction. In the drawings showing a layout among the drawings of this specification, only some layers may be shown for convenience of illustration.

The integrated circuit 10 may refer to any device manufactured through a semiconductor process. For example, the integrated circuit 10 may be a memory device including a plurality of memory cells, a processor including at least one core, a sensor that detects an external signal, or a system-on-chip. It may be a device that includes multiple functional blocks, such as a System-on-Chip (SoC). As shown in FIG. 1, the integrated circuit 10 may include a control circuit 12 and a plurality of unit circuits U1,..., Un (n is an integer greater than 1), and a plurality of unit circuits U1,..., Un. It may include conductors 14 and 16.

The plurality of unit circuits (U1,..., Un) may each have the same structure and may be configured to operate in parallel. As a non-limiting example, the plurality of unit circuits U1,..., Un may be memory cells that store data in a memory device, as will be described later with reference to FIG. 9, and with reference to FIG. 11. As will be described later, they may be pixels that detect light in an image sensor, or, as will be described later with reference to FIG. 12, they may be pixels that output light in a display device. Parallel operations by these plurality of unit circuits (U1,..., Un) may be required to be performed simultaneously, and when the error between the times when the parallel operations are performed is large, the integrated circuit 10 Operation speed may decrease and even malfunction may occur.

The control circuit 12 may generate a control signal (CTR) for controlling a plurality of unit circuits (U1,..., Un). For example, the control circuit 12 may generate a control signal (CTR) having a variable voltage and/or current to control the operations of the plurality of unit circuits (U1,..., Un). As shown in FIG. 1, a plurality of unit circuits (U1,..., Un) may be arranged adjacent to each other, while the control circuit 12 has a plurality of unit circuits (U1,..., It can be placed adjacent to one side of Un). Additionally, the plurality of unit circuits U1,..., Un may be electrically connected to the first conductor 14 extending in the A control signal (CTR) can be received. Due to the delay of the control signal (CTR) in the first conductor 14, the control signal (CTR) generated by the control circuit 12 may reach the first unit circuit (U1) first, and the nth unit The circuit (Un) can finally be reached. Accordingly, parallel operations of the first unit circuit U1 and the nth unit circuit Un may be performed respectively at different times.

As shown in FIG. 1, the delay of the control signal (CTR) occurring in the first conductor 14 is determined by the resistance value (RP) of the first conductor 14 and the resistance value (RP) disposed adjacent to the first conductor 14. It may depend on the capacitance (CP) formed with the second conductor 16. The resistance value (RP) may be proportional to the length (L) of the first conductor 14 and inversely proportional to the width (W) of the first conductor 14, while the capacitance (CP) may be proportional to the length (L) of the first conductor 14. ) and may be inversely proportional to the distance (S) between the second conductors (16). Accordingly, in order to reduce the delay of the control signal (CTR) occurring in the first conductor 14, the first conductor 14 may be required to have a short length (L) and a wide width (W), A large distance S between the first conductor 14 and the second conductor 16 may be required. However, the reduction in the length (L) of the first conductor 14 may be limited due to the number and size of the plurality of unit circuits (U1,..., Un), and the width (W) and distance (S) The increase may be limited due to spatial constraints of the integrated circuit 10.

As will be described below with reference to the drawings, the first conductor 14 that transmits the control signal (CTR) to the plurality of unit circuits (U1,..., Un) includes a multi-layer conductor. This can be done, and accordingly, while having a low resistance value (RP), the distance (S) to the adjacent second conductor 16 can be maintained or increased. Accordingly, the first conductor 14 can provide reduced delay, and the error between the points in time when parallel operations of the first unit circuit U1 and the nth unit circuit Un are performed can be significantly reduced. You can. Additionally, in some embodiments, due to the reduced width W of first conductor 14, second conductor 16 may have an increased width, resulting in increased operating speed of integrated circuit 10. And/or operation reliability may be improved.

Figure 2 is a diagram showing the layout of an integrated circuit according to an exemplary embodiment of the present disclosure. Specifically, FIG. 2 shows parts of the M2 layer, V2 layer, and M3 layer among the plurality of layers included in the layout of the integrated circuit 20. As described above with reference to FIG. 1 , the integrated circuit 20 of FIG. 2 may include a multilayer conductor ML to transmit control signals to a plurality of unit circuits operating in parallel. For convenience of illustration, FIG. 2 shows only one multilayer conductor ML and some other patterns included in the layout of the integrated circuit 20.

The integrated circuit 20 may include a plurality of wiring layers and a plurality of via layers as part of a plurality of layers stacked in the Z-axis direction (or first direction). The wiring layer may include a plurality of patterns, and the via layer may include a plurality of vias. For example, as shown in FIG. 2, as a wiring layer, a first pattern (M21) and a second pattern (M22) extending in the Y-axis direction from the M2 layer may be formed, and from the M3 layer in the X-axis direction. It may include an extended third pattern (M31) and a fourth pattern (M32). Additionally, a first via (V21) and a second via (V22) may be formed in the V2 layer as a via layer, and the first via (V21) may be connected to the first pattern (M21) and the third pattern (M31). Meanwhile, the second via V22 may be connected to the second pattern M22 and the fourth pattern M32. The patterns and vias may be spaced apart from each other by a minimum distance determined based on the semiconductor process for manufacturing the integrated circuit 20. For example, as shown in FIG. 2, the first pattern (M21) and the second pattern (M22) of the M2 layer are spaced apart at a first distance (S1) in the X-axis direction and the third pattern (M31) of the M3 layer ) and the second distance S2 between the fourth pattern M32 in the Y-axis direction may be greater than or equal to the minimum separation distance determined by the semiconductor process.

The multilayer conductor ML may have a structure extending together in the X-axis direction (or the second direction) in two or more adjacent layers. For example, as shown in FIG. 2, the multilayer conductor ML includes a first part P1 extending in the X-axis direction from the M2 layer, a second part P2 extending in the X-axis direction from the V2 layer, and It may include a third part (P3) extending in the X-axis direction from the M3 layer. Although the multilayer conductor ML in FIG. 2 is shown extending together in the /V2 or V2/M3), and may extend together in the X-axis direction in four or more consecutive layers, as will be described later with reference to FIGS. 8A and 8B. Accordingly, the multilayer conductor ML may have a reduced resistance value compared to a structure extending from a single layer and a structure connecting parts extending from two wiring layers with vias. As shown in FIG. 2, the multilayer conductor ML may have a length (L) in the X-axis direction, a width (W) in the Y-axis direction, and a height (H) in the Z-axis direction. You can.

It should be noted that the heights of the M2 layer, V2 layer, and M3 layer shown in FIG. 2, that is, the lengths in the Z-axis direction, are merely examples and may be different from those shown in FIG. 2. In addition, hereinafter, exemplary embodiments of the present disclosure will be described mainly with reference to the M2 layer, V2 layer, and M3 layer, but multilayer conductors according to exemplary embodiments of the present disclosure are also formed in other wiring layers and via layers. What can be done will be understood.

3A and 3B are diagrams showing examples of multilayer conductors according to example embodiments of the present disclosure. Specifically, FIGS. 3A and 3B show multilayer conductors 30a and 30b integrally formed from two adjacent layers with a length L in the X-axis direction. Hereinafter, overlapping content in the description of FIGS. 3A and 3B will be omitted.

Referring to FIG. 3A, the multilayer conductor 30a may include a first part (P1) extending in the X-axis direction from the M3 layer and a second part (P2) extending in the X-axis direction from the V2 layer. The first part (P1) and the second part (P2) may be formed integrally. As used herein, an 'integrally formed component' may refer to something formed continuously from the same material, and an integrally formed component may be indicated by a single outline in the drawings. For example, as will be described later with reference to FIGS. 4, 5A, and 5B, the first portion (P1) of the M3 layer and the second portion (P2) of the V2 layer included in a single outline in FIG. 3A are made of the same material. , for example, may be made of a metal such as Al, Cu, etc., and the boundary between the first part (P1) and the second part (P2) (or the boundary between the M3 layer and the V2 layer) may also be made of the same material. On the other hand, unlike what is shown in FIG. 3A, different materials (eg, insulators, barrier layers, etc.) may be disposed between parts that are not integrally formed. In this specification, the multilayer conductor will be described as being composed of a metal such as Al or Cu, but the multilayer conductor may be composed of a conductive material different from the metal.

Due to the first portion (P1) and the second portion (P2) being formed integrally, the multilayer conductor 30a may have a reduced resistance value. As described above with reference to FIG. 1, expanding the width of the conductor is limited due to space constraints, so in order to reduce the resistance of the conductor, unlike the multilayer conductor 30a of FIG. 3A, the same wiring layer is used in two or more wiring layers. Conductive lines extending in one direction and comprising patterns interconnected via vias may be considered. However, in the case of these conductors, the decrease in resistance of the conductors may be limited due to the resistance provided by the via in the Z-axis direction as well as the resistance of the pattern of the wiring layer and the barrier layer between vias. In particular, as the semiconductor process becomes more refined, the decrease in resistance becomes weaker. It can happen. On the other hand, as shown in FIG. 3A, the multilayer conductor 30a integrally formed from two or more adjacent layers can be free from the influence of the resistance value of the via and the resistance value of the barrier layer, and the resistance value is reduced despite the miniaturized semiconductor process. It can have a resistance value of

As shown in FIG. 3A, an interlayer insulator IL may be disposed on the lower surface of the multilayer conductor 30a. The interlayer insulator IL may insulate the multilayer conductor 30a (or the second portion P2) from other patterns formed on the M2 layer. As described above with reference to FIG. 2, a via layer such as the V2 layer can be formed with vias to interconnect the patterns of adjacent wiring layers (i.e., the M2 layer and the M3 layer), so the vias formed in the via layer Differently from this, an interlayer insulator IL may be disposed to insulate the second portion P2 extending in the X-axis direction from the V2 layer from the patterns of the M2 layer adjacent to the V2 layer. In some embodiments, the interlayer insulator IL may be referred to as an interlayer insulator film, an interlayer dielectric, or the like.

Referring to FIG. 3B, the multilayer conductor 30b may include a first part (P1) extending in the X-axis direction from the M2 layer and a second part (P2) extending in the X-axis direction from the V2 layer. The first part (P1) and the second part (P2) may be formed integrally. For example, the first part (P1) of the M2 layer and the second part (P2) of the V2 layer included in a single outline in FIG. 3B may be made of the same material, for example, a metal such as Cu, and the first part ( The boundary between the P1) and the second part P2 (or the boundary between the M2 layer and the V2 layer) may also be made of the same metal.

As shown in FIG. 3B, an interlayer insulator IL may be disposed on the upper surface of the multilayer conductor 30b. As described above, the V2 layer may be formed with vias for interconnecting the patterns of the adjacent M2 layer and M3 layer. Therefore, unlike the vias formed in the V2 layer, the second layer extending in the X-axis direction from the V2 layer An interlayer insulator IL may be disposed to insulate the portion P2 from the patterns of the M3 layer adjacent to the V2 layer. Accordingly, the patterns disposed in the M3 layer on the multilayer conductor 30b can be insulated from the multilayer conductor 30b.

Figure 4 is a diagram schematically showing a process of forming a multilayer conductor according to an exemplary embodiment of the present disclosure. Specifically, FIG. 4 sequentially shows cross-sections cut along the direction in which the multilayer conductor 30a extends, that is, a plane perpendicular to the X-axis direction, according to the process of forming the multilayer conductor 30a of FIG. 3A. Below, FIG. 4 will be explained with reference to FIG. 3A.

In some embodiments, the multilayer conductor 30a may be formed using a damascene process. The damascene process can refer to a technique that creates a space through etching, fills it with the material that makes up the pattern to be formed, and then polishes it to finally complete the formation of the pattern. In particular, a technique of simultaneously forming vias and patterns by simultaneously etching two adjacent layers, such as a via layer and a wiring layer, filling them with metal, and then polishing them, may be referred to as a dual damascene process.

Referring to FIG. 4, in step S41, an operation of etching a portion of the V2 layer and the M3 layer may be performed. For example, a portion of the V2 layer and the M3 layer may be etched depending on the length (L) and width (W) of the multilayer conductor 30a. Then, in step S42, an operation to form a barrier layer can be performed. The barrier layer can prevent the metal, oxygen, or moisture constituting the multilayer conductor 30a from diffusing to the outside, and accordingly, not only the insulators included in the V2 layer and the M3 layer, but also the interlayer insulating film between the V2 layer and the M3 layer can be protected. In some embodiments, the barrier layer may be made of a conductive material, such as Ti/TiN, Ta/TaN, etc., and may be formed by physical vapor deposition (PVD). Additionally, in some embodiments, a seed layer may be formed to fill the material after the barrier layer is formed, and the seed layer may be considered included in the barrier layer herein. For example, when the multilayer conductor 30a includes Cu, a seed layer for filling Cu may be formed by PVD using an electro plating method.

In step S43, a metal filling operation may be performed. For example, as described above, a seed layer may be disposed on the barrier layer, and an operation of filling the metal material by electroplating may be performed. Then in step S44, a polishing operation may be performed. For example, as shown in step S43 of FIG. 4, in step S43, a metal material can also be formed on the M3 layer, and not only the metal formed on the M3 layer by polishing such as CMP (Chemical Mechanical Polishing) Alternatively, the barrier layer can be removed, and then an interlayer insulating film can be formed. Accordingly, as shown in step S44 of FIG. 4, the multilayer conductor 30a has a first part (P1) extending in the X-axis direction from the M3 layer and a second part (P2) extending in the X-axis direction from the V2 layer. ), and the first part (P1) and the second part (P2) may be formed integrally. In some embodiments, as shown in FIG. 4, the first portion P1 and the second portion P2 may have substantially the same width W, as will be described later with reference to FIGS. 5A and 5B. As such, the first portion P1 and the second portion P2 may each have different widths.

5A and 5B are diagrams showing examples of multilayer conductors according to example embodiments of the present disclosure. Specifically, FIG. 5A shows an example of a cross section of the multilayer conductor 30a cut along a plane perpendicular to the An example of a cross section of the multilayer conductor 30b cut along a plane perpendicular to the extending X-axis direction is shown. Hereinafter, overlapping content in the description of FIGS. 5A and 5B will be omitted.

Referring to FIG. 5A, the multilayer conductor 30a may include a first part (P1) extending in the X-axis direction from the M3 layer and a second part (P2) extending in the X-axis direction from the V2 layer. The first part P1 and the second part P2 may each have different widths, that is, lengths in the Y-axis direction. For example, as shown in FIG. 5A, the first portion P1 as the upper portion of the multilayer conductor 30a has approximately a first width W1, while the lower portion of the multilayer conductor 30a has a second width W1. The portion P2 may approximately have a second width W2, and the second width W2 may be smaller than the first width W1. Additionally, in some embodiments, the side surfaces of the first part P1 and the second part P2 may be inclined surfaces that are not parallel to the Z-axis direction, as shown in FIG. 5A.

Similarly, referring to FIG. 5B, the multilayer conductor 30b may include a first portion (P1) extending in the X-axis direction from the M2 layer and a second portion (P2) extending in the X-axis direction from the V2 layer. And, the first part P1 and the second part P2 may have different widths, that is, lengths in the Y-axis direction. For example, as shown in FIG. 5B, the upper second portion P2 of the multilayer conductor 30b has approximately a second width W2, while the lower portion of the multilayer conductor 30b has a first width W2. The portion P1 may have approximately a first width W1, and the first width W1 may be smaller than the second width W2. Additionally, in some embodiments, the side surfaces of the first part P1 and the second part P2 may be inclined surfaces that are not parallel to the Z-axis direction, as shown in FIG. 5B.

6A to 6E are diagrams showing examples of multilayer conductors according to example embodiments of the present disclosure. Specifically, FIGS. 6A to 6E show multilayer conductors 60a, 60b, 60c, 60d having a length L in the X-axis direction and including portions extending together in the X-axis direction in each of three consecutive layers. 60e) is shown. Depending on the semiconductor process, multilayer conductors of various structures shown in FIGS. 6A to 6E can be formed, and a multilayer structure including parts extending together in three consecutive layers and not shown in FIGS. 6A to 6E. The fact that conductive wire is possible will also be understood from the structures shown in FIGS. 6A to 6E. Hereinafter, redundant content in the description of FIGS. 6A to 6E will be omitted.

Referring to FIG. 6A, the multilayer conductor 60a includes a first part (P1) extending in the X-axis direction from the M3 layer, a second part (P2) extending in the X-axis direction from the V2 layer, and an may include a third part (P3) extending to, and the first part (P1), the second part (P2), and the third part (P3) may be formed integrally. As described above with reference to FIG. 3A, the integrally formed first part (P1), second part (P2), and third part (P3) may be made of the same material, such as metal, and the first part (P1) ), the boundaries between the second part (P2) and the third part (P3) may also be made of the same metal. In some embodiments, multilayer conductor 60a may be formed using a damascene process, as described above with reference to FIG. 4 .

Referring to FIG. 6b, the multilayer conductor 60b has a first part (P1) extending in the X-axis direction from the M3 layer, a second part (P2) extending in the X-axis direction from the V2 layer, and a may include a third part (P3) extending to , and the first part (P1) and the second part (P2) may be formed integrally. That is, as shown in FIG. 6B, the first part (P1) and the second part (P2) included in a single outline at the top of the multilayer conductor 60b may be formed integrally, while the multilayer conductor 60b The third part (P3) included in another single outline below may not be formed integrally with the first part (P1) and the second part (P2). In some embodiments, a different material, such as a barrier layer, may be disposed between the second portion (P2) and the third portion (P3) of the multilayer conductor 60b. On the other hand, unlike shown in FIG. 6B, the first part (P1) of the M3 layer and the third part (P3) of the M2 layer are instead of the second part (P2) of the V2 layer extending in the X-axis direction. Compared to the case of interconnection through at least one via of the V2 layer, the multilayer conductor 60b of FIG. 6B not only has a barrier layer omitted between the V2 layer and the M3 layer, but also a second portion (P2) extended in the X-axis direction. Due to this, it may have a low resistance value.

Referring to FIG. 6C, the multilayer conductor 60c includes a first part (P1) extending in the X-axis direction from the M2 layer, a second part (P2) extending in the X-axis direction from the V2 layer, and an may include a third part (P3) extending to, and the first part (P1) and the second part (P2) may be formed integrally. That is, as shown in FIG. 6C, the first part (P1) and the second part (P2) included in a single outline below the multilayer conductor 60c may be formed integrally, while the multilayer conductor 60c The third part (P3) included in another single outline above may not be formed integrally with the first part (P1) and the second part (P2). In some embodiments, a different material, such as a barrier layer, may be disposed between the second portion (P2) and the third portion (P3) of the multilayer conductor 60c. On the other hand, unlike shown in FIG. 6C, the first part (P1) of the M2 layer and the third part (P3) of the M3 layer are instead of the second part (P2) of the V2 layer extending in the X-axis direction. Compared to the case of interconnection through at least one via of the V2 layer, the multilayer conductor 60c of FIG. 6C not only has a barrier layer omitted between the M2 layer and the V2 layer, but also a second portion (P2) extended in the X-axis direction. Due to this, it may have a low resistance value.

Referring to FIG. 6d, the multilayer conductor 60d has a first part (P1) extending in the X-axis direction from the M3 layer, a second part (P2) extending in the X-axis direction from the V2 layer, and a may include a third part (P3) extending to, and the first part (P1), the second part (P2), and the third part (P3) may be formed individually. That is, as shown in FIG. 6D, the first part (P1), the second part (P2), and the third part (P3) included in each of the single outlines in the multilayer conductor 60d may not be formed integrally. there is. Accordingly, a different material, such as a barrier layer, may be disposed between the first portion (P1) and the second portion (P2) of the multilayer conductor 60d, while the second portion (P2) and the third portion (P3) Different materials, such as barrier layers, may also be disposed in between. On the other hand, unlike shown in FIG. 6D, the first part (P1) of the M3 layer and the third part (P3) of the M2 layer are instead of the second part (P2) of the V2 layer extending in the X-axis direction. Compared to the case of interconnection through at least one via of the V2 layer, the multilayer conductor 60d of FIG. 6D may have a low resistance value due to the second portion P2 extending in the X-axis direction.

Referring to FIG. 6e, the multilayer conductor 60e includes a first part (P1) extending in the X-axis direction from the M3 layer, a second part (P2) extending in the X-axis direction from the V2 layer, and an It may include a third part (P3) extending to. Similar to the multilayer conductor 60d of FIG. 6D, the first portion P1, second portion P2 and third portion P3 of FIG. 6E may be formed separately, while the first portion P1 , at least two of the second part (P2) and the third part (P3) may have different lengths. For example, as shown in Figure 6e, the first portion (P1) of the M3 layer and the third portion (P3) of the M2 layer may have a length (L) that matches the multilayer conductor 60e, while The second portion (P2) of the V2 layer may have a length (L') that is smaller than the length (L) of the multilayer conductor (60e).

7A and 7B are diagrams showing examples of multilayer conductors according to exemplary embodiments of the present disclosure. Specifically, Figure 7a shows an example of a cross section cut in a plane perpendicular to the Shows an example of a cross section cut in a vertical plane. Hereinafter, overlapping content in the description of FIGS. 7A and 7B will be omitted.

Referring to FIG. 7A, the multilayer conductor 60a includes a first part (P1) extending in the X-axis direction from the M3 layer, a second part (P2) extending in the X-axis direction from the V2 layer, and an It may include a third part (P3) extending to. As described above with reference to FIG. 6A, the first part (P1), the second part (P2), and the third part (P3) of the multilayer conductor 60a may be formed as one body. Accordingly, the first part (P1), the second part (P2), and the third part (P3) of the multilayer conductor 60a may be made of the same material, for example, metal, and the first part (P1), the second part (P1) The boundaries of the portion P2 and the third portion P3 may also be made of the same metal. In some embodiments, the first portion (P1), the second portion (P2), and the third portion (P3) of the multilayer conductor 60a may have substantially the same width (W) as shown in FIG. 7A. You can.

Referring to FIG. 7b, the multilayer conductor 60b includes a first part (P1) extending in the X-axis direction from the M3 layer, a second part (P2) extending in the X-axis direction from the V2 layer, and an It may include a third part (P3) extending to. As described above with reference to FIG. 6B, the first portion (P1) and the second portion (P2) may be formed integrally, while the third portion (P3) may be formed of the first portion (P1) and the second portion (P1). It may not be formed integrally with P2). Accordingly, as shown in FIG. 7b, the boundary between the first part P1 and the second part P2 at the top of the multilayer conductor 60b is made of the same metal, while at the bottom of the multilayer conductor 60b A barrier layer may be disposed at the boundary between the second part (P2) and the third part (P3).

In some embodiments, the first portion (P1), the second portion (P2), and the third portion (P3) of the multilayer conductor 60b may have different widths. For example, as shown in FIG. 7B, the first portion P1 of the M3 layer and the third portion P3 of the M2 layer may have approximately a first width W1, while the V2 layer may have a first width W1. The second portion P2 may approximately have a second width W2, and the second width W2 may be smaller than the first width W1. The lengths of the parts included in the multilayer conductor may be determined by considering the semiconductor process.

8A and 8B are diagrams showing examples of multilayer conductors according to example embodiments of the present disclosure. Specifically, FIGS. 8A and 8B show multilayer conductors 80a and 80b having a length L in the X-axis direction and including portions extending in the X-axis direction in each of four consecutive layers. Depending on the semiconductor process, multilayer conductors of the structures shown in FIGS. 8A and 8B can be formed, and multilayer conductors of a structure not shown in FIGS. 8A and 8B as a structure including parts extending together in four or more consecutive layers. The fact that conduction wire is possible will also be understood from the structures shown in FIGS. 8A and 8B. Hereinafter, overlapping content in the description of FIGS. 8A and 8B will be omitted.

Referring to FIG. 8A, the multilayer conductor 80a includes a first part (P1) extending in the X-axis direction from the M2 layer, a second part (P2) extending in the X-axis direction from the V2 layer, and an It may include a third part (P3) extending from the V3 layer and a fourth part (P4) extending in the X-axis direction. The first portion (P1), the second portion (P2), the third portion (P3), and the fourth portion (P4) may be formed integrally, and in some embodiments, the multilayer conductor 80a may be formed using a damascene process. can be formed. As shown in FIG. 8A, an interlayer insulator IL may be disposed on the upper surface of the multilayer conductor 80a, and thus the multilayer conductor 80a may be insulated from patterns formed on the wiring layer above the V3 layer. .

Referring to FIG. 8b, the multilayer conductor 80b has a first part (P1) extending in the X-axis direction from the M2 layer, a second part (P2) extending in the X-axis direction from the V2 layer, and an It may include a third part (P3) extending from the V3 layer and a fourth part (P4) extending in the X-axis direction. As shown in FIG. 8B, the first part (P1) and the second part (P2) may be formed integrally at the bottom of the multilayer conductor 80b, while the third part (P2) may be formed at the top of the multilayer conductor 80b. P3) and the fourth part (P4) may be formed integrally. Accordingly, a barrier layer may be disposed between the second part (P2) of the V2 layer and the third part (P3) of the M3 layer. Similar to the multilayer conductor 80a of FIG. 8A, an interlayer insulator IL may be disposed on the upper surface of the multilayer conductor 80b of FIG. 8B.

FIG. 9 is a block diagram illustrating a memory device according to an exemplary embodiment of the present disclosure, and FIG. 10 is a diagram illustrating a portion of the layout of the memory device of FIG. 9 according to an exemplary embodiment of the present disclosure. In some embodiments, the memory device 90 may be an example of the integrated circuit 10 of FIG. 1, and a series of memory cells C1,..., Cn may be included in a plurality of unit circuits U1 of FIG. 1. ,..., Un), and a plurality of word lines (WLs) in the memory device 90 may be implemented with multilayer conductors.

Referring to FIG. 9 , the memory device 90 may include a memory cell array 92, a row decoder 94, and a page buffer 96. The memory device 90 can receive commands and addresses from the outside, and can receive or output data. For example, the memory device 90 may receive commands such as a write command and a read command, and addresses corresponding to the commands. The memory device 90 may receive data in response to a write command and output data in response to a read command. The memory device 90 may be packaged as an independent memory device, or may be included together in a semiconductor package such as a system-on-chip or processor.

The memory cell array 92 may include a plurality of memory cells. For example, as shown in FIG. 9, the memory cell array 92 may include a series of memory cells (C1,..., Cn) arranged in one direction as SRAM (Static Random Access Memory) cells. (n is an integer greater than 1). The first memory cell C1 may include a cross-connected first inverter INV1 and a second inverter INV2, and the first inverter INV1 and the second inverter INV2 are connected during a write operation and a read operation. It may include a first transistor (T1) and a second transistor (T2) electrically connected to one bit line pair (BL11, BL21). Although Figure 9 illustrates an SRAM cell, other memories other than SRMA, such as flash memory, dynamic random access memory (DRAM), resistance random access memory (RRAM), and phase-change random access memory (PRAM), may also be used in multiple layers. It will be understood that a word line implemented as a conductive wire can be applied.

The memory cell array 92 may be connected to the row decoder 94 through a plurality of word lines (WLs) and to the page buffer 96 through a plurality of bit lines (BLs). A series of memory cells (C1,..., Cn) included in the memory cell array 92 may be connected to the kth word line (WLk) among the plurality of word lines (WLs), and in this way, one word line Data stored in a series of memory cells (C1,..., Cn) connected to or in a series of memory cells (C1,..., Cn) may be referred to as a page. As shown in FIG. 9, the k word line (WLk) implemented with a multilayer conductor is connected to the control electrodes (e.g., gate electrodes).

The row decoder 94 selects the kth word among the plurality of word lines WLs in order to select a series of memory cells C1,..., Cn among the plurality of memory cells included in the memory cell array 90. The line (WLk) can be activated. For example, the row decoder 94 may activate the kth word line (WLk) by increasing the voltage level of the kth word line (WLk). That is, the row decoder 94 may correspond to the control circuit 12 of FIG. 1. The page buffer 96 provides signals corresponding to data to be written in the selected series of memory cells C1,..., Cn to a plurality of bit lines BLs, or provides signals selected by the row decoder 94. Signals corresponding to data stored in a series of memory cells C1,..., Cn can be detected from the plurality of bit lines BLs.

The k-th word line (WLk) implemented with a multi-layer conductor may have a reduced resistance value, as described above with reference to the drawings, and accordingly, the row decoder 94 applies to the k-th word line (WKk) The difference between the times when a signal, for example, a raised voltage (or a dropped voltage) reaches the first memory cell C1 and the n-th memory cell Cn may be reduced, and as a result, the write of the memory device 90 may be reduced. Speed and read speed can be improved. Additionally, due to the reduced resistance value of the kth word line (WLk), the kth word line (WLk) may have a reduced width compared to the case where the kth word line (WLk) is not implemented with a multilayer conductor, and the kth word line (WLk) may be reduced. Examples having the same width will be described later with reference to FIG. 10.

Referring to the left side of FIG. 10, a first line (L1) to which a negative supply voltage (VSS) (or ground voltage) is applied on the boundaries of the first memory cell (C1') facing the Y-axis direction. and the second line L2 may extend in the In order to provide a stable negative supply voltage (VSS) to a series of memory cells including the first memory cell (C1'), a first line (L1) and a second line (L1) that provide a negative supply voltage (VSS) ( L2) may be arranged as shown in FIG. 10. The first line (L1) and the second line (L2) may have a first width (W1), while the k word line (WLk'), which is not implemented as a multilayer conductor, may have a second width (W2). there is. As described above, when the k-th word line (WLk') is implemented as a multi-layer conductor, the k-th word line (WLk') may have a width smaller than the second width (W2), and in the 'case' and 'Case B' represents examples in which the k-th word line (WLk') is implemented with a multi-layer conductor.

Referring to 'Case A' of FIG. 10, the first line L1a and the second line L2a provide a negative supply voltage VSS to a series of memory cells including the first memory cell C1a. The width W1a can be maintained (W1a = W1), while due to the width W2a of the kth word line WLka being reduced (W2a < W2), the kth word line WLka and the first line The distance between (L1a) may increase, and the distance between the kth word line (WLka) and the second line (L2a) may increase. For example, the distance S between the k word line (WLk') shown on the left side of FIG. 10 and the first line (L1) and the second line (L2), respectively, is the minimum distance between the patterns in the M2 layer. On the other hand, in 'case A' of FIG. 10, the distance (Sa) between the k word line (WLka) and the first line (L1a) and the second line (L2a), respectively, is the distance between the patterns in the M2 layer. It can be greater than the minimum separation distance. Accordingly, the capacitance formed by the k-th word line (WLka) with the first line (L1a) and the second line (L2a) may be reduced, and as a result, the delay occurring in the k-th word line (WLka) further increases. may decrease.

Referring to 'Case B' of FIG. 10, due to the reduced width W2b of the kth word line WLka (W2b < W2), a negative supply voltage VSS is applied to the first memory cell C1b. The width (W1b) of the first line (L1b) and the second line (L2b) provided may increase (W1b > W1). Accordingly, the resistance values of the first line (L1b) and the second line (L2b) may be reduced, resulting in a more stable negative supply voltage (VSS) to the series of memory cells including the first memory cell (C1b). This can be provided.

Figure 11 is a block diagram showing an image sensor according to an exemplary embodiment of the present disclosure. In some embodiments, the image sensor 110 may be an example of the integrated circuit 10 of FIG. 1, and a series of pixels (X1,..., ,..., Un), and at least some of the control lines (RSs, TGs, and SELs) for controlling a plurality of pixels in the image sensor 110 may be implemented as multilayer conductors.

Referring to FIG. 11 , the image sensor 110 may include a pixel array 112, a row driver 114, and a read circuit 116. The pixel array 112 may be connected to the row driver 114 through a plurality of control lines, that is, a plurality of reset lines (RSs), a plurality of transmission lines (TGs), and a plurality of select lines (SELs). , may be connected to the read circuit 116 through a plurality of output lines OLs. The row driver 114 may simultaneously or sequentially activate some of the reset lines (RSs), the transmission lines (TGs), and the selection lines (SELs) included in the pixel array 112. A plurality of pixels can be controlled, and the read circuit 116 can detect the intensity of light sensed in the pixel array 112 by detecting the voltage and/or current of the output lines OLs.

Pixel array 112 may include a plurality of pixels. For example, the pixel array 112 may include a series of pixels (X1,..., essence). That is, the first pixel (X1) may include four transistors (T3 to T6) and a photo-sensing device (PD). Although FIG. 11 illustrates a pixel of a 4T structure, it will be understood that control lines implemented with multilayer conductors can also be applied to an image sensor including pixels of a different structure, such as a 6-transistor (6T) structure. As shown in FIG. 11, the kth transmission line TGk may be connected to the control electrode (or gate electrode) of the transfer transistor T3, and the kth reset line RSk may be connected to the control electrode of the reset transistor T5. and the kth selection line (SELk) may be connected to the control electrode of the selection transistor (T6).

The operation of the image sensor 110 may be improved by implementing at least some of the plurality of control lines with multilayer conductors. For example, when a plurality of transmission lines (TGs) are implemented with multilayer conductors, the error between the section where light is detected at the first pixel (X1) and the section where light is detected at the nth pixel (Xn) is reduced. This can be done, and as a result, the accuracy of the image generated by the image sensor 110 can be improved. In addition, when the plurality of selection lines (SELs) are implemented with multilayer conductors, the timing of outputting a signal from the first pixel (X1) to the first output line (OL1) and the nth output from the nth pixel (Xn) The error between the time points at which the signal is output to the line OLn may be reduced, and accordingly, the readout speed by the readout circuit 116 may increase, and the image capture speed of the image sensor 110 may increase.

Figure 12 is a block diagram showing a display device according to an exemplary embodiment of the present disclosure. In some embodiments, display device 120 (or display panel 122) may be an example of integrated circuit 10 of Figure 1, with a series of pixels (X1',..., It may correspond to the unit circuits U1,..., Un of FIG. 1, and a plurality of scan lines SLs for controlling a plurality of pixels in the display device 120 may be implemented with multilayer conductors. .

Referring to FIG. 12 , the display device 120 may include a display panel 122, a scan driver 124, and a data driver 126. The display panel 122 may be connected to the scan driver 124 through a plurality of scan lines (SLs) and to the data driver 126 through a plurality of data lines (DLs). The scan driver 124 may activate one of the plurality of scan lines (SLs) to select a series of pixels as part of the plurality of pixels included in the display panel 122, and the data driver 126 may activate one of the plurality of scan lines (SLs). A series of pixels selected by the scan driver 124 may provide voltage and/or current to a plurality of data lines DLs according to the intensity of light to be output.

The display panel 122 may include a plurality of pixels. For example, the display panel 122 may include a series of pixels (X1',..., Xn') including light emitting devices (LEDs) (n is an integer greater than 1). That is, the first pixel (X1') may include two transistors (T7, T8), a capacitor (CAP), and an LED (LD). Although FIG. 12 illustrates a pixel with a structure including LEDs, a plurality of scan lines (SLs) implemented with multilayer conductors can also be applied to a display panel including a light emitting element different from an LED. You will understand. As shown in FIG. 12, the kth scan line SLk may be connected to the control electrode (or gate electrode) of the switch transistor T7.

The operation of the display device 120 can be improved by implementing the plurality of scan lines SLs using multilayer conductors. For example, the error between the time when the first pixel ( Not only can this be improved, but the speed at which images are updated on the display panel 122 can be increased.

Figure 13 is a block diagram showing a system-on-chip (SoC) according to an exemplary embodiment of the present disclosure. System-on-chip 130 may be an example of integrated circuit 10 of FIG. 1 and may include multilayer conductors according to example embodiments of the present disclosure. The system-on-chip 130 implements complex functional blocks such as IP (intellectual property) that perform various functions on a single chip, and is implemented together in two or more consecutive layers according to example embodiments of the present disclosure. Multilayer conductors including extending portions may be included in each functional block of the system-on-chip 130. Accordingly, while high space efficiency is achieved and delays occurring in wiring are reduced, the system-on-chip 130 can have high integration and high operating speed.

Referring to FIG. 13, the system-on-chip 130 includes a modem 132, a display controller 133, a memory 134, an external memory controller 135, a CPU (Central Processing Unit) 136, and a transaction unit. It may include a 137, a PMIC 138, and a graphic processing unit (GPU) 139, and each functional block of the system-on-chip 130 may communicate with each other through the system bus 131.

The CPU 136, which can generally control the operation of the system-on-chip 130, can control the operations of other functional blocks 132, 133, 134, 135, 137, 138, and 139. The modem 132 can demodulate a signal received from outside the system-on-chip 130 or modulate a signal generated inside the system-on-chip 130 and transmit it to the outside. . The external memory controller 135 may control the operation of transmitting and receiving data from an external memory device connected to the system-on-chip 130. For example, programs and/or data stored in an external memory device may be provided to the CPU 136 or GPU 139 under the control of the external memory controller 135. The GPU 139 can execute program instructions related to graphics processing. The GPU 139 may receive graphics data through the external memory controller 135, and may send graphics data processed by the GPU 139 to the outside of the system-on-chip 130 through the external memory controller 135. You can also send it. The transaction unit 137 can monitor data transactions of each functional block, and the PMIC 138 can control power supplied to each functional block according to the control of the transaction unit 137. The display controller 133 can transmit data generated inside the system-on-chip 130 to the display by controlling a display (or display device) outside the system-on-chip 130.

The memory 134 is a non-volatile memory, such as EEPROM (non-volatile memory such as an Electrically Erasable Programmable Read-Only Memory), flash memory, PRAM (Phase-change Random Access Memory), and RRAM (Resistance Random Access Memory). Memory), NFGM (Nano Floating Gate Memory), PoRAM (Polymer Random Access Memory), MRAM (Magnetic Random Access Memory), FRAM (Ferroelectric Random Access Memory), etc., and DRAM (Dynamic Random Access Memory) as volatile memory. ), SRAM (Static Random Access Memory), mobile DRAM, DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR (Low Power DDR) SDRAM, GDDR (Graphic DDR) SDRAM, RDRAM (Rambus Dynamic Random Access Memory), etc. It may also include . In some embodiments, as described above with reference to FIG. 9 and the like, a plurality of word lines for each selecting some of the plurality of memory cells included in the memory 134 may be implemented with multilayer conductors.

As above, exemplary embodiments have been disclosed in the drawings and specification. Although embodiments have been described in this specification using specific terms, this is only used for the purpose of explaining the technical idea of the present disclosure and is not used to limit the meaning or scope of the present disclosure as set forth in the claims. . Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present disclosure should be determined by the technical spirit of the attached patent claims.

Claims (20)

a plurality of first patterns formed on a first wiring layer;
a plurality of first vias formed in a first via layer adjacent to the first wiring layer in a first upward direction; and
A multilayer conductor including a first part extending from the first wiring layer in a second direction perpendicular to the first direction and a second part extending from the first via layer in the second direction,
The first part and the second part are integrally formed,
The plurality of first patterns are spaced apart from each other by at least a first distance,
The integrated circuit, wherein the multilayer conductors are spaced apart from the plurality of first patterns by a second distance greater than the first distance. In claim 1,
Further comprising a plurality of second patterns formed on a second wiring layer adjacent to the first via layer in the first direction,
The multilayer conductor further includes a third portion extending from the second wiring layer in the second direction to the same length as the first portion. In claim 2,
An integrated circuit, wherein the first part, the second part, and the third part are integrally formed. In claim 2,
The integrated circuit, wherein the multilayer conductor further includes a barrier layer between the first portion and the third portion. In claim 2,
Further comprising a plurality of second vias formed in a second via layer adjacent to the second wiring layer in the first direction,
The multilayer conductor further includes a fourth portion extending from the second via layer in the second direction. In claim 5,
An integrated circuit, wherein the first part, the second part, the third part, and the fourth part are integrally formed. In claim 5,
The integrated circuit, wherein the multilayer conductor further includes a barrier layer between the second portion and the third portion. In claim 1,
a plurality of second patterns formed on a second wiring layer adjacent to the first via layer in the first direction; and
An integrated circuit further comprising an interlayer insulator formed between the multilayer conductor and the second wiring layer. In claim 1,
The integrated circuit wherein the second portion has a width less than or equal to the width of the first portion. In claim 1,
The integrated circuit, wherein the second part has the same length as the first part. In claim 1,
configured to operate in parallel and comprising a plurality of unit circuits arranged in the second direction,
The multilayer conductor is electrically connected to control electrodes of transistors included in the plurality of unit circuits. delete In claim 1,
The integrated circuit is characterized in that the multilayer conductor is made of the same metal material in the first wiring layer and the first via layer. In claim 13,
The integrated circuit further comprising, on at least a portion of a surface of the multilayer conductor, a barrier layer configured to prevent diffusion of the metallic material when forming the multilayer conductor. a plurality of first patterns formed on a first wiring layer;
a plurality of first vias formed in a first via layer adjacent to the first wiring layer in a first upward direction; and
A first part extending from the first wiring layer in a second direction perpendicular to the first direction, a second part extending from the first via layer in the second direction, and between the first part and the second part. comprising a multilayer conductor including a first barrier layer extending in the second direction,
The plurality of first patterns are spaced apart from each other by at least a first distance,
The integrated circuit, wherein the multilayer conductors are spaced apart from the plurality of first patterns by a second distance greater than the first distance. In claim 15,
The first barrier layer is configured to prevent diffusion of the material constituting the first portion and/or the material constituting the second portion when forming the first portion and/or the second portion. integrated circuit. In claim 15,
Further comprising a plurality of second patterns formed on a second wiring layer adjacent to the first via layer in the first direction,
The multilayer conductor is,
a third part extending from the second wiring layer in the second direction to the same length as the first part; and
The integrated circuit further comprising a second barrier layer extending in the second direction between the second portion and the third portion. In claim 17,
The second barrier layer is configured to prevent diffusion of the material constituting the second portion and/or the material constituting the third portion when forming the second portion and/or the third portion. integrated circuit. In claim 15,
The integrated circuit, wherein the second part has the same length as the first part. delete

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