KR102626359B1 - Otp memory device for reducing short error in antifuse - Google Patents

Abstract

An OTP memory device that mitigates short-circuit faults in antifuses is published. The OTP memory device of the present invention includes a fuse array including a plurality of antifuse cells, each of which has an antifuse; A cell selection unit driven to select first to nth (where n is a natural number of 2 or more) antifuse cells among a plurality of antifuse cells of the fuse array at once according to a received selection address, wherein the first to nth The n antifuse cell includes a cell selection unit that is programmed according to activation of first to nth program signals; and a program driver that converts first to nth program data received at once into the first to nth program signals and provides them, wherein the first to nth program signals are the first to nth programs having active data values. and a program driver that is non-overlappingly activated according to data. In the OTP memory device of the present invention, first to nth program signals are non-overlappingly activated according to the first to nth program data having active data values. As a result, according to the OTP memory device of the present invention, the short-circuit error of the antifuse is reduced.

Description

OTP memory device that alleviates short circuit errors in antifuses {OTP MEMORY DEVICE FOR REDUCING SHORT ERROR IN ANTIFUSE}

The present invention relates to a one-time programmable (OTP) memory device, and particularly to an OPT memory device that alleviates short-circuit errors in antifuses.

Generally, an antifuse OTP memory device includes a plurality of antifuse cells arranged in a matrix structure of rows and columns, and each antifuse cell is configured with its own antifuse.

At this time, the antifuse cell is programmed depending on whether its built-in antifuse breaks down. That is, when a high voltage difference is applied across the antifuse, the insulating layer of the antifuse is destroyed, and thus the antifuse cell is electrically programmed.

Meanwhile, in an antifuse OTP memory device, a plurality of antifuse cells can be selected at once for programming. At this time, if the programming of a plurality of antifuse cells selected at once is carried out simultaneously, a large amount of current flows through the antifuse built into the antifuse cell for which programming was completed first. In this case, the antifuse built into the remaining antifuse cell may not be sufficiently short-circuited, that is, an antifuse short-circuit error may occur.

The purpose of the present invention is to provide an OPT memory device that alleviates anti-fuse short-circuit errors.

One aspect of the present invention for achieving the above object relates to an OTP memory device. The OTP memory device of the present invention includes a fuse array including a plurality of antifuse cells, each of which has an antifuse; A cell selection unit driven to select first to nth (where n is a natural number of 2 or more) antifuse cells among a plurality of antifuse cells of the fuse array at once according to a received selection address, wherein the first to nth The n antifuse cell includes a cell selection unit that is programmed according to activation of first to nth program signals; and a program driver that is enabled in response to activation of an enable signal and converts first to nth program data received at once into the first to nth program signals and provides them, wherein the first to nth program signals are and a program driver that is non-overlappingly activated according to the first to nth program data having active data values. The first to nth program data have a serial order. The program driver generates first to nth carry signals dependent on the first to nth program data, and the ith (where i is a natural number from 2 to n) carry signal has an active data value. According to the i program data, the (i-1)th carry signal is delayed by a certain delay time. In addition, activation of the first to nth program signals is suppressed according to activation of the corresponding first to nth carry signals.

In the OTP memory device of the present invention configured as described above, first to nth program signals are non-overlappingly activated according to the first to nth program data having active data values. As a result, according to the OTP memory device of the present invention, the short-circuit error of the antifuse is reduced.

A brief description of each drawing used in the present invention is provided.
1 is a diagram showing an OTP memory device according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating the program driver of FIG. 1 in detail.
FIG. 3 is a diagram showing the first conversion means of FIG. 2 in detail.
FIG. 4 is a diagram illustrating the ith conversion means of FIG. 2 in detail.
FIG. 5 is a diagram showing the timing of main signals in the program driver of FIG. 2.

In order to fully understand the present invention, its operational advantages, and the objectives achieved by practicing the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure will be thorough and complete and so that the spirit of the invention can be sufficiently conveyed to those skilled in the art.

Also, when understanding each drawing, it should be noted that like members are shown with the same reference numerals as much as possible. Additionally, detailed descriptions of well-known functions and configurations that are judged to unnecessarily obscure the gist of the present invention are omitted.

Meanwhile, in this specification, for components that perform the same configuration and function, reference signs are added in < > along with the same reference signs. At this time, these components are collectively referred to by reference signs. And, if individual distinction between them is necessary, '< >' is added after the reference sign.

When describing the content of the present invention throughout the specification, plural expressions may also be omitted. For example, even if it is composed of a plurality of signal lines, it can be expressed as 'signal lines', or it can be expressed in the singular as 'signal line'. This is also because when a signal line is made up of a bundle of several signal lines with the same properties, for example, data signals, there is no need to distinguish them into singular and plural. In this respect, this description is valid. Therefore, similar expressions should also be interpreted with the same meaning throughout the specification.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings.

1 is a diagram showing an OTP memory device according to an embodiment of the present invention. Referring to Figure 1, the OTP memory device of the present invention includes a fuse array 100, a cell selection unit 200, and a program driver 300, and preferably, a serial-to-parallel converter 400 and a clock divider. (500) is further provided.

The fuse array 100 is arranged in a matrix structure consisting of rows and columns, and includes a plurality of antifuse cells (FC), each of which has an antifuse (AF).

The cell selection unit 200 is driven to select n antifuse cells (FC) from among the plurality of antifuse cells (FC) of the fuse array 100 at once according to the received selection address (SADD). Here, n is a natural number of 2 or more, and in this embodiment, it is assumed to be '8'.

That is, the cell selection unit 200 can select one row according to the selection address (SADD), and at this time, the first to nth antifuse cells (FC<1:8>) connected to one row. These are selected all at once.

And, at both ends of the antifuse (AF) of the first to nth antifuse cells (FC<1:8>), there is a signal connected to “H” of the corresponding first to eighth program signals (XPDR<1:8>). Upon activation, a voltage difference higher than the breakdown voltage is applied. In this case, the thin gate oxide film that acts as an insulating layer for the antifuse (AF) yields, and as a result, the antifuse cell (FC) is electrically programmed.

In this embodiment, according to the generation of the program command signal (CMD), the cell selection unit 200 selects the first to nth antifuse cells (FC<1:8>) from the fuse array 100. It is driven to proceed with the program operation.

The program driving unit 300 converts the first to eighth program data (PDAT<1:8>) received at once into the first to eighth program signals (XPDR<1:8>) to display the fuse array (100). ) is provided.

In this embodiment, the first to eighth program signals (XPDR<1:8>) are “1” when the data value of the corresponding first to eighth program data (PDAT<1:8>) is “1”. It is activated with “H”. And, when the data value of the corresponding first to eighth program data (PDAT<1:8>) is “0”, the first to eighth program signals (XPDR<1:8>) are “L”. is deactivated.

Additionally, in this specification, a data value of “1” may be referred to as an ‘active data value’, and a data value of “0” may be referred to as an ‘inactive data value’.

FIG. 2 is a diagram illustrating the program driver 300 of FIG. 1 in detail. Referring to FIG. 2, the program driver 300 includes a shifting clock generating unit 310 and first to eighth conversion units 320<1:8>.

The shifting clock generating means 310 generates a shifting clock signal (SCLK). At this time, the shifting clock signal (SCLK) transitions according to the transition of the driving clock signal (DCLK) generated when the enable signal (XEN) is activated to “H”. In this embodiment, the shifting clock signal (SCLK) has the same phase as the driving clock signal (DCLK) when the enable signal (XEN) is activated to “H” (see FIG. 5).

Preferably, the shifting clock generating means 310 is implemented as an AND gate that inputs the enable signal (XEN) and the driving clock signal (DCLK) and outputs the shifting clock signal (SCLK).

The first to eighth conversion means (320<1:8>) are enabled in response to activation of the enable signal (XEN) to “H”, and the first to eighth carry signals (XCR<1: 8>) occurs.

The first conversion means (320<1>) receives the eighth carry signal (XCR<8>) and the first program data (PDAT<1>) and converts the first carry signal (XCR<1>) 1 Generates a program signal (XPDR<1>).

FIG. 3 is a diagram illustrating the first conversion means 320<1> of FIG. 2 in detail. Referring to FIG. 3, the first conversion means 320<1> specifically includes a first carry receiving unit 321<1>, a first carry generating unit 323<1>, and a first program signal generating unit. It is provided with (325<1>).

The first carry reception unit 321<1> is enabled in response to activation of the enable signal XEN to “H” and receives the eighth carry signal XCR<8> to perform the first reception Generates a preliminary signal (XPRE<1>).

At this time, the first reception preliminary signal (XPRE<1>) is controlled to the same logic state as the eighth carry signal (XCR<8>) in response to activation of the shifting clock signal (SCLK) to “H”, It is latched in response to deactivation of the shifting clock signal (SCLK) to “L”.

Additionally, the first reception preliminary signal (XPRE<1>) is deactivated to “L” in response to the deactivation of the enable signal (XEN) to “L”.

The first carry generation unit 323<1> receives the first reception preliminary signal XPRE<1> and generates the first carry signal XCR<1>.

At this time, the first carry signal (XCR<1>) is controlled to the same logic state as the first receive preliminary signal (XPRE<1>) in response to deactivation of the shifting clock signal (SCLK) to “L”, It is latched in response to activation of the shifting clock signal (SCLK) to “H”.

The first program signal generation unit 325<1> receives the first carry signal (XCR<1>) and the first program data (PDAT<1>) and receives the first program signal (XPDR<1>). ) occurs.

At this time, the first program signal (XPDR<1>) is deactivated to “L” according to the activation of the first carry signal (XCR<1>) to “H”, and the first carry signal (XCR<1>) is deactivated to “L”. ) is deactivated to "L", it is controlled to a logical state according to the first program data (PDAT<1>).

According to the first conversion means 320<1> of FIG. 3 as described above, the first carry signal XCR<1> is changed to “L” according to the deactivation of the enable signal XEN to “L”. It is a signal that is deactivated and is delayed by one cycle of the shifting clock signal (SCLK) with respect to the eighth carry signal (XCR<8>) when the enable signal (XEN) is activated to "H".

The first program signal (XPDR<1>) is deactivated to “L” according to the activation of the first carry signal (XCR<1>) to “H”.

And, when the first carry signal ( Controlled by logic state. That is, the first program signal (XPDR<1>) is activated to “H” when the data value of the first program data (PDAT<1>) is “1”, and the first program signal (PDAT<1>) is activated to “H”. When the data value of >) is “0”, it is deactivated as “L”.

For reference, in FIG. 3, the inverters (INV11 and INV14) are enabled when the shifting clock signal (SCLK) is “H”, and the inverters (INV12 and INV13) are enabled when the shifting clock signal (SCLK) is “L”. "Enabled when:

Referring again to FIG. 2, the i (where i is a natural number from 2 to n) conversion means 320<i> is configured to convert the (i-1) carry signal (XCR<i-1>) and the i-th program. Data (PDAT<i>) is received and an i-th carry signal (XCR<i>) and an i-th program signal (XPDR<i>) are generated.

FIG. 4 is a diagram illustrating the ith conversion means 320<i> of FIG. 2 in detail. Referring to FIG. 4, the i-th conversion means 320<i> specifically includes an i-th carry receiving unit 321<i>, an i-th carry generating unit 323<i>, and an i-th program signal generating unit. (325<i>).

The ith carry receiving unit 321<i> is enabled in response to activation of the enable signal (XEN) to “H”, and the (i-1)th carry signal (XCR<i-1>) is received to generate the ith reception preliminary signal (XPRE<i>).

At this time, the ith receive preliminary signal (XPRE<i>) is the same as the (i-1)th carry signal (XCR<i-1>) in response to activation of the shifting clock signal (SCLK) to “H”. It is controlled to a logic state and latched in response to deactivation of the shifting clock signal (SCLK) to “L”.

Additionally, the ith receive preliminary signal (XPRE<i>) is activated to “H” in response to the deactivation of the enable signal (XEN) to “L”.

The i-th carry generation unit 323<i> is configured to include the i-th program data (PDAT<i>), the ith reception preliminary signal (XPRE<i>), and the (i-1)-th carry signal (XCR<i>). -1>) is received to generate the ith carry signal (XCR<i>).

The ith carry generation unit 323<i> more specifically includes a generation preliminary generation part 323a and a muxer 323b.

The preliminary generation part 323a receives the ith preliminary signal to be received (XPRE<i>) and generates the preliminary preliminary signal to be generated (XPRG<i>). At this time, the ith generated preliminary signal (XPRG<i>) is controlled to the same logic state as the ith received preliminary signal (XPRE<1>) in response to deactivation of the shifting clock signal (SCLK) to “L”, It is latched in response to activation of the shifting clock signal (SCLK) to “H”.

The muxer 323b muxes the ith generated preliminary signal (XPRG<i>) and the (i-1)th carry signal (XCR<i-1>) to generate the ith carry signal (XCR<i>). occurs.

At this time, the ith carry signal ( It is controlled to the same logic state as the (i-1)th carry signal (XCR<i-1>) according to the data value of “0” of the ith program data (PDAT<i>).

The ith program signal generation unit 325<i> receives the ith carry signal (XCR<i>) and the ith program data (PDAT<i>) and receives the ith program signal (XPDR<i> ) occurs.

At this time, the ith program signal (XPDR<i>) is deactivated to “L” according to the activation of the ith carry signal (XCR<i>) to “H”, and the ith carry signal (XCR<i> ) is deactivated to "L", it is controlled to a logical state according to the ith program data (PDAT<i>).

For reference, in FIG. 4, the inverters (INV21 and INV24) are enabled when the shifting clock signal (SCLK) is “H”, and the inverters (INV22 and INV23) are enabled when the shifting clock signal (SCLK) is “L”. "Enabled when:

According to the i-th conversion means 320<i> of FIG. 4 as described above, the i-th carry signal (XCR<i>) is converted to the i-th program when the enable signal ( It is activated according to the active data value of data (PDAT<i>). Also, when the enable signal (XEN) is deactivated to “L”, the ith carry signal ( -1) Controlled to the same logic state as the carry signal (XCR<i-1>).

In other words, when the enable signal (XEN) is deactivated to “L”, the i th carry signal ( When the data value of the ith program data (PDAT<i>) is "0", it is activated as "H", and is in the same logic state as the (i-1)th carry signal (XCR<i-1>). It is controlled by

And, when the enable signal (XEN) is activated to “H”, the i-th carry signal ( -1) It is controlled in the same logic state as the logic state of the carry signal (XCR<i-1>), and the (i-1)th carry signal ( XCR<i-1>) is delayed by one cycle of the shifting clock signal (SCLK).

The ith program signal (XPDR<i>) is deactivated to “L” according to the activation of the ith carry signal (XCR<i>) to “H”. And, when the first carry signal ( Controlled by logic state. That is, the ith program signal (XPDR<i>) is activated to “H” when the data value of the ith program data (PDAT<i>) is “1”, and the ith program signal (PDAT<i> When the data value of >) is “0”, it is deactivated as “L”.

The operations and effects of the program driver 300 as described above are described with reference to FIG. 5.

FIG. 5 is a diagram showing the timing of main signals in the program driver 300 of FIG. 2, where data values of the first to eighth program data (PDAT<1:8>) are <0,0,1, This is the case where 0,1,1,0,0>.

First, the logic states of the first to eighth carry signals (XCR<1:8>) in the disable period (P_DIS) where the enable signal (XEN) is deactivated to “L” are described.

In the disable period (P_DIS), the logical state of the first carry signal (XCR<1>) is "L", and the data value of the second program data (PDAT<2>) is '0', so that the The logic state of the second carry signal (XCR<2>) is “L”. And, since the data value of the third program data (PDAT<3>) is '1', the third carry signal (XCR<3>) and the fourth to eighth carry signals (XCR<4:8) of the subsequent stage >)'s logical state is "H".

Next, the logic states of the first to eighth carry signals (XCR<1:8>) in the enable period (P_EN) section where the enable signal (XEN) is activated to “H” are described.

In the enable period (P_EN), the second program data (PDAT<2>), the fourth program data (PDAT<4>), the seventh program data (PDAT<7>) having a data value of '0', and The second carry signal (XCR<2>), the fourth carry signal (XCR<4>), the seventh carry signal (XCR<7>) and the eighth carry signal corresponding to the eighth program data (PDAT<8>) (XCR<8>) has the same phase as the previous carry signal (XCR).

That is, the second carry signal (XCR<2>) has the same phase as the first carry signal (XCR<1>), and the fourth carry signal (XCR<4>) has the same phase as the third carry signal (XCR<3>). and the seventh carry signal (XCR<7>) and the eighth carry signal (XCR<8>) have the same phase as the sixth carry signal (XCR<6>).

And, a third carry signal ( XCR<3>), the fifth carry signal (XCR<5>), and the sixth carry signal (XCR<6>) are signals that are delayed by one cycle of the shifting clock signal (SCLK) with respect to the preceding carry signal (XCR) am.

Next, the operation of the first to eighth carry signals (XCR<1:8>) in the enable period (P_EN) period is described in more detail.

The time point (t11) is the time when the shifting clock signal (SCLK) changes to “H” after the enable signal (XEN) is activated to “H” and is deactivated to “L”, and the disable period (P_DIS) The logic state of the eighth carry signal (XCR<8>) in is “H”.

Therefore, the logic state of the first and second carry signals (XCR<1> and XCR<2>) at the time t11 transitions to “H”.

The third and fourth carry signals (XCR<3> and XCR<4>) transition to “L” at time t11, and one cycle of the shifting clock signal (SCLK) has elapsed from time t11. At (t12), it transitions back to “H”.

The fifth carry signal ( transitions to

The sixth to eighth carry signals ( transitions back to “H”.

Continuing, the logical states of the first to eighth program signals XPDR<1:8> in the enable period P_EN in which the enable signal XEN is activated to “H” are described.

The first to eighth program signals (XPDR<1:8>) are the corresponding first to eighth program signals at the program timing when the corresponding first to eighth carry signals (XCR<1;8>) are "L". It is activated according to the active data value of data (PDAT<1:8>).

That is, the third program signal (XPDR<3>) is activated to “H” at the program timing (tPR<3>), and the fifth program signal (XPDR<5>) is activated at the program timing (tPR<5>). is activated to “H”, and the sixth program signal (XPDR<6>) is activated to “H” at the program timing (tPR<6>).

In summary, the program driver 300 generates first to eighth carry signals (XCR<1:8>) depending on the first to eighth program data (PDAT<1:8>), and at this time, The ith carry signal (XCR<i>) is connected to the (i-1)th carry signal (XCR<i-1>) according to the ith program data (PDAT<i>) having a data value of '1'. This is a signal that is delayed by one cycle of the shifting clock signal (SCLK).

In addition, activation of the first to eighth program signals (XPDR<1;8>) is suppressed according to the activation of the corresponding first to eighth carry signals (XCR<1:8>) to “H”.

In other words, the first to eighth program signals (XPDR<1:8>) are non-overlappingly activated according to the first to eighth program data (PDAT<1:8>) having active data values. .

In addition, it can be seen that the program timing (tPD) for the first to eighth program data (PDAT<1:8>) having active data values is performed continuously.

Referring again to FIG. 1, the serial-to-parallel converter 400 is driven in synchronization with the reference clock signal (RCLK) and receives an address-data muxing signal (XADM). At this time, the selection address (SADD) and the first to eighth input data (IDAT<1:8>) are selected from the external address (EADD) and the first to eighth input data (IDAT<1:8>) serially loaded into the address-data muxing signal (XADM). 8 Extract program data (PDAT<1:8>) and output in parallel.

Here, the setting signal (XSET) is a signal indicating the start of the reference clock signal (RCLK).

The implementation and operational effects of the serial-to-parallel converter 400 are obvious to those skilled in the art. Therefore, in this specification, for the sake of simplicity of explanation, detailed descriptions thereof are omitted.

In general, the reference clock signal (RCLK) is a clock that serves as a reference for the operation of the OTP memory device. Therefore, the reference clock signal RCLK has a very high frequency as the speed of the OTP memory device greatly increases.

On the other hand, in order to short-circuit the antifuse (AF) of the antifuse cell (FC), it is necessary to apply a voltage difference greater than the breakdown voltage to both ends for a considerable period of time.

Considering this, the OTP memory device of the present invention further includes a clock divider 500.

The clock divider 500 divides the received reference clock signal RCLK to generate the driving clock signal DCLK, and the driving clock signal DCLK is provided to the program driver 300.

That is, in the OTP memory device of the present invention, the program driver 300 is driven in synchronization with the relatively low driving clock signal (DCLK) instead of the relatively very high frequency reference clock signal (RCLK), thereby selecting the anti-clockwise signal. Programming of the fuse cell (FC) can be easily performed.

In summary, in the OTP memory device of the present invention, the first to eighth program signals (XPDR<1:8>) are connected to the first to eighth program data (PDAT<1:8>) having active data values. It is activated non-overlappingly. As a result, according to the OTP memory device of the present invention, the short-circuit error of the antifuse (AF) built into the antifuse cell (FC) can be reduced.

Additionally, in the OTP memory device of the present invention, the program timing (tPD) for the first to eighth program data (PDAT<1:8>) having active data values is performed continuously. As a result, according to the OTP memory device of the present invention, the decrease in operating speed is alleviated.

As described above, although the embodiments have been described with limited examples and drawings, various modifications and variations can be made by those skilled in the art from the above description. For example, the described techniques are performed in a different order than the described method, and/or components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or other components are used. Alternatively, appropriate results may be achieved even if substituted or substituted by an equivalent. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the attached registration claims.

Claims (10)

In the OTP memory device,
A fuse array including a plurality of antifuse cells each having an antifuse;
A cell selection unit driven to select first to nth (where n is a natural number of 2 or more) antifuse cells among a plurality of antifuse cells of the fuse array at once according to a received selection address, wherein the first to nth The n antifuse cell includes a cell selection unit that is programmed according to activation of first to nth program signals; and
A program driver that is enabled in response to activation of an enable signal and converts first to nth program data received at once into the first to nth program signals and provides them, wherein the first to nth program signals are active. and a program driver that is non-overlappingly activated according to the first to nth program data having data values,
The first to nth program data are
It has a series of sequences,
The program driving unit
Generates first to nth carry signals dependent on the first to nth program data, and the ith (where i is a natural number from 2 to n) carry signal is transmitted to the ith program data having an active data value. Accordingly, the (i-1) carry signal is delayed by a certain delay time,
The first to nth program signals are
OTP memory device, characterized in that activation is suppressed according to activation of the corresponding first to nth carry signals.
delete The method of claim 1, wherein the program driver
An OTP memory device characterized in that the first to nth program signals are activated in a non-overlapping manner according to the first to nth program data, and activated at respective program timings allocated separately by clocks of the driving clock signal. .
The method of claim 3, wherein the program driver
An OTP memory device, characterized in that it is driven to continuously perform the respective program timings for the first to nth program data having active data values.
The method of claim 3, wherein the OTP memory device
A serial-to-parallel converter that is driven in synchronization with a reference clock signal and receives an address-data muxing signal, comprising: an external address serially loaded into the address-data muxing signal; The OTP memory device further comprising the serial-to-parallel converter for extracting first to nth program data and outputting them in parallel.
The method of claim 5, wherein the OTP memory device
An OTP memory device further comprising a clock divider that divides a received reference clock signal to generate the driving clock signal.
The method of claim 3, wherein the program driver
Shifting clock generation means for generating a shifting clock signal, wherein the shifting clock signal transitions according to a transition of the driving clock signal generated when the enable signal is activated; and
First to nth conversion means that are enabled in response to activation of the enable signal and generate the first to nth carry signals, wherein the first conversion means receives the nth carry signal and first program data. generates a first carry signal and the first program signal, and the i-th (where i is a natural number from 2 to n) conversion means receives the (i-1)-th carry signal and the i-th program data and It has the first to nth conversion means for generating a carry signal and the ith program signal,
The first carry signal is
It is deactivated according to deactivation of the enable signal, and when the enable signal is activated, the shifting clock signal is delayed by a certain period with respect to the nth carry signal,
The first program signal is
It is deactivated according to activation of the first carry signal, and is controlled to a logical state according to the data value of the first program data when the first carry signal is deactivated,
The i-th carry signal is
When the enable signal is deactivated, it is activated according to the active data value of the ith program data, and when the enable signal is activated, the (i-1)th carry signal is activated according to the inactive data value of the ith program data. It has the same logic state as, and the shifting clock signal is delayed by a certain period with respect to the (i-1)th carry signal according to the active data value of the ith program data,
The ith program signal is
The OTP memory device is deactivated according to activation of the ith carry signal and controlled to a logical state according to the data value of the program data when the ith carry signal is deactivated.
The method of claim 7, wherein the first conversion means
A first carry reception unit that is enabled in response to activation of the enable signal and generates a first reception preliminary signal by receiving the nth carry signal, wherein the first reception preliminary signal is activated in response to activation of the shifting clock signal. The first carry receiving unit is controlled to the same logic state as the nth carry signal in response, is latched in response to deactivation of the shifting clock signal, and is deactivated in response to deactivation of the enable signal;
A first carry generating unit that receives the first reception preliminary signal and generates the first carry signal, wherein the first carry signal is in the same logic state as the first reception preliminary signal in response to deactivation of the shifting clock signal. The first carry generation unit is controlled and latched in response to activation of the shifting clock signal; and
A first program signal generating unit that receives the first carry signal and the first program data and generates the first program signal, wherein the first program signal is deactivated upon activation of the first carry signal, and the first program signal is deactivated upon activation of the first carry signal, 1 An OTP memory device comprising the first program signal generation unit controlled to a logic state according to the first program data when the carry signal is deactivated.
The method of claim 8, wherein the ith conversion means is
An i-th carry reception unit that is enabled in response to activation of the enable signal and generates an i-th reception preliminary signal by receiving the (i-1)th carry signal, wherein the i-th reception preliminary signal is the shifting clock The i-th carry is controlled to the same logic state as the (i-1)th carry signal in response to activation of the signal, is latched in response to deactivation of the shifting clock signal, and is activated in response to deactivation of the enable signal. receiving unit;
An i-th carry generating unit that receives the i-th program data, the i-th reception preliminary signal and the (i-1)-th carry signal and generates the i-th carry signal, wherein the i-th carry signal is the i-th program It is controlled to the same logic state as the ith generated preliminary signal according to the active data value of the data, and is controlled to the same logic state as the (i-1)th carry signal according to the inactive data value of the ith program data. The i-generated preliminary signal is controlled to the same logic state as the i-th received preliminary signal in response to deactivation of the shifting clock signal, and the i-th carry generation unit is latched in response to activation of the shifting clock signal; and
An i-th program signal generating unit that receives the i-th carry signal and the i-th program data and generates the i-th program signal, wherein the i-th program signal is deactivated upon activation of the i-th carry signal, and An OTP memory device comprising the i-th program signal generation unit that is controlled to a logical state according to the data value of the i-th program data in response to deactivation of the i-carry signal.
The method of claim 9, wherein the ith carry generating unit is
a generating preliminary generation part that receives the i-th receiving preliminary signal and generates the i-th generating preliminary signal; and
A muxer that generates the ith carry signal by muxing the ith generated preliminary signal and the (i-1)th carry signal, wherein the ith carry signal is generated according to the active data value of the ith program data. An OTP memory device comprising the muxer controlled by the logic state of an i-generated preliminary signal and controlled by the logic state of the (i-1)th carry signal according to the inactive data value of the ith program data.

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