KR102623951B1 - System for testing capacitor - Google Patents

Abstract

A capacitor inspection system is disclosed. The capacitor inspection system includes a power supply unit, a charging/discharging unit, a data measurement unit, and a current chopping unit. The power supply unit supplies current of a preset size and shape, the charging/discharging unit charges and discharges the capacitor using the applied current, and the data measuring unit includes a data measuring unit that measures the voltage and current of the capacitor. At this time, the charging/discharging unit includes a current chopping unit that chops the current applied to the capacitor in a preset pattern. According to this configuration, the pattern of the current applied to the capacitor can be arbitrarily applied, making it possible to apply actual stress during system operation to the capacitor, thereby ensuring the reliability of the capacitor to be inspected.

Description

Capacitor Testing System {SYSTEM FOR TESTING CAPACITOR}

The present invention relates to an electrical device inspection system, and more specifically, to a system for inspecting the characteristics of a capacitor, a device used to obtain electrostatic capacity.

Recently, in the field of high-voltage, large-capacity converters, modular multilevel converters (MMC) have received attention and active research is being conducted. Modular multi-stage converter (MMC) is easy to expand the voltage level because a large number of sub-modules are connected in series, and has the advantage of being able to obtain excellent output due to the high voltage level even at low switching frequencies, such as high-voltage direct current (HVDC) transmission and invalidation. It is used in power compensator (STATCOM) and motor drive fields.

Figure 1 is a circuit diagram of a half-bridge converter for explaining submodules of a modular multi-stage converter (MMC). As shown in Figure 1, the half-bridge converter consists of two IGBT switches that operate complementary and a capacitor to store energy.

If the dark current direction is positive, when switch S1 is turned on, the dark current flows to the capacitor through freewheeling diode D1, thereby charging the capacitor. Since switch S2 bypasses the capacitor when turned on, the capacitor voltage does not change.

Conversely, if the dark current direction is negative, when switch S1 is turned on, the dark current flows into the capacitor, discharging the capacitor, and when switch S2 is turned on, the dark current flows into freewheeling diode D2 and bypasses the capacitor. There is no change in capacitor voltage. Therefore, the direction of the dark current when switch S1 is turned on determines the charging and discharging of the capacitor.

Figure 2 is a circuit diagram for explaining the configuration of a modular multi-stage converter (MMC). As shown in Figure 2, N sub-modules 11 and arm inductors 12 connected in series are connected to form an arm (node A-node B), and two arms are connected based on the AC output terminal to form one leg. Constructs (Node A - Node C).

The female inductor 12 serves to prevent a sudden increase in short-circuit current in the event of a short-circuit accident. The capacitor voltage of each submodule has the size of N equal divisions of the DC link voltage, and the voltage output from one arm is equal to the sum of the output voltages of each submodule constituting the arm.

It is very important to maintain the reliability of expensive capacitors used at high voltages, and for this purpose, tests are performed on various characteristics such as capacitor initial characteristics and rated capacity when developing capacitors.

However, the conventional test device can only apply a sine wave or a simple pulse waveform to the capacitor, so it was not possible to properly simulate the various operating conditions under which the capacitor operates and perform the test.

For example, in the case of MMC, the current is applied by chopping during operation. Moreover, in actual use, it is used in multiple stages, so the form of chopping applied to the capacitor changes in various ways. However, with conventional test devices, there was no way to test the stress caused by the current applied to the capacitor during actual MMC operation.

The present invention was devised to solve the above-described conventional problems, and various operating conditions that may occur during actual operation of the capacitor element can be applied to capacitors with various characteristics, thereby ensuring the reliability of the capacitor to be inspected. The purpose is to provide an inspection system that allows

To achieve the above object, the capacitor inspection system according to the present invention includes a power supply unit, a charging/discharging unit, a data measuring unit, and a current chopping unit.

The power supply unit supplies current of a preset size and shape, the charging/discharging unit charges and discharges the capacitor using the applied current, and the data measuring unit includes a data measuring unit that measures the voltage and current of the capacitor. At this time, the charging/discharging unit includes a current chopping unit that chops the current applied to the capacitor in a preset pattern.

According to this configuration, the pattern of the current applied to the capacitor can be arbitrarily applied, making it possible to apply actual stress during system operation to the capacitor, thereby ensuring the reliability of the capacitor to be inspected.

To this end, the charge/discharge unit is connected in series with the capacitor and includes a pair of switches connected in series in opposite directions, and the switches may include transistors and diodes connected in anti-parallel to each other.

Additionally, the charge/discharge unit may include a pair of switches at both ends of the capacitor, and the bypass path may be connected in parallel with the capacitor and a pair of switches at one end of the capacitor.

Additionally, the current chopping unit may chop the current applied to the capacitor by bypassing the current applied to the capacitor through a preset bypass path. According to this configuration, it is possible to prevent a very large voltage from being induced in the switch, and it is possible to efficiently chop the current flowing in the capacitor while reducing the stress on the switch.

Additionally, the current chopping unit is located in the bypass path and includes a pair of switches connected in series in opposite directions, and the switches may include transistors and diodes connected in anti-parallel to each other. Additionally, the current chopping unit may chop the current applied to the capacitor in a preset pattern by opening and closing one selected switch among a pair of switches included in the current chopping unit. According to this configuration, it is possible to easily implement chopping of various patterns that may actually occur when the levels of the multi-level converter are stacked.

Additionally, the capacitor inspection system may further include a capacity calculation unit that calculates the capacity of the capacitor using the voltage and current of the capacitor measured by the data measurement unit. According to this configuration, it is possible to estimate the capacitor capacity while applying the same chopped current waveform as the stress applied to the capacitor when constructing an actual converter.

At this time, the capacitor C _Test is,

Calculated by the equation, △ V _c1 and △ V _c2 are the difference between the maximum charging voltage of the capacitor during the sinusoidal half-cycle time △ T ₁ and △ T ₂ , respectively, and i _{c. av1} and i _{c. ac2} is the average current during △ T ₁ and △ T ₂ times, and f _p may be the frequency of the chopped sinusoidal current.

Additionally, the power supply unit may further include an inverter unit capable of converting direct current power into alternating current power, and an inverter control unit that controls the current and voltage in the capacitor using the inverter unit. At this time, the inverter unit includes an inductor connected to the charging and discharging unit, and by controlling the current flowing in the inductor, the current and voltage in the capacitor can be controlled. According to this configuration, by varying the voltage or current applied to the capacitor element, it is possible to provide various operating conditions that can be applied to the capacitor in actual use.

According to the present invention, the pattern of the current applied to the capacitor can be arbitrarily applied, making it possible to apply actual stress during system operation to the capacitor, thereby ensuring the reliability of the capacitor to be inspected.

In addition, it is possible to prevent a very large voltage from being induced in the switch, thereby reducing the stress on the switch and efficiently chopping the current flowing in the capacitor.

In addition, it is possible to easily implement chopping of various patterns that can actually occur when the levels of a multi-level converter are stacked.

In addition, it is possible to estimate the capacitor capacity while applying a chopped current waveform identical to the stress applied to the capacitor when constructing an actual converter.

Additionally, by varying the voltage or current applied to the capacitor element, it is possible to provide various operating conditions that can be applied to the capacitor in actual use.

Figure 1 is a circuit diagram of a half-bridge converter for explaining submodules of a modular multi-stage converter (MMC).
Figure 2 is a circuit diagram for explaining the configuration of a modular multi-stage converter (MMC).
3 is a schematic block diagram of a capacitor inspection system according to one embodiment of the present invention.
FIG. 4 is a diagram schematically showing an example of the structure of the capacitor inspection system controller of FIG. 3.
Figure 5 is a circuit diagram of a capacitor evaluation and diagnostic system that is an example implementation of the capacitor inspection system of Figure 3.
FIG. 6 is a diagram showing the switching waveform of the capacitor charging/discharging circuit of FIG. 5.
Figures 7 and 8 show switch operation modes when the inductor current is in the positive direction.
9 and 10 are inductors Diagram showing the switch operation mode when the current is in the negative direction.
FIG. 11 is a diagram showing simulation results performed using the method shown in FIG. 6.
12 is a diagram for explaining a capacitor capacity estimation method.

Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings.

Figure 3 is a schematic block diagram of a capacitor inspection system according to an embodiment of the present invention.

In Figure 3, the capacitor inspection system 100 includes a power supply unit 110, a charging/discharging unit 120, a data measuring unit 130, and a capacity calculating unit 140, and the charging/discharging unit 120 is a current Includes pin part 122. The power supply unit 110 includes an inverter unit 112 and an inverter control unit 114, and the inverter unit 112 further includes an inductor 113.

The power supply unit 110 supplies current of a preset size and shape. The inverter unit 112 converts direct current power into alternating current power, and the inverter control unit 114 uses the inverter unit 112 to control the current and voltage in the capacitor. At this time, the inverter unit 112 can control the current and voltage in the capacitor by controlling the current flowing in the inductor 113 connected to the charging and discharging unit 120.

According to this configuration, by varying the voltage or current applied to the capacitor element, it is possible to provide various operating conditions that can be applied to the capacitor in actual use.

The charge/discharge unit 120 charges and discharges the capacitor using the applied current. At this time, the charge/discharge unit 120 is connected in series with a capacitor and includes a pair of switches connected in series in opposite directions, and each switch may include a transistor and a diode connected in anti-parallel to each other.

The current chopping unit 122 chops the current applied to the capacitor in a preset pattern. At this time, the current chopping unit 122 may chop the current applied to the capacitor by bypassing the current applied to the capacitor through a preset bypass path. According to this configuration, it is possible to prevent a very large voltage from being induced in the switch, and it is possible to efficiently chop the current flowing in the capacitor while reducing the stress on the switch.

Additionally, the charging/discharging unit 120 may include a pair of switches at both ends of the capacitor, and in this case, the bypass path may be connected in parallel with the capacitor and a pair of switches at one end of the capacitor.

Additionally, the current chopping unit 122 is located in the bypass path and includes a pair of switches connected in series in opposite directions, and the switches may include transistors and diodes connected in anti-parallel to each other.

Additionally, the current chopping unit 122 may chop the current applied to the capacitor in a preset pattern by opening and closing one selected switch among a pair of switches included in the current chopping unit 122. According to this configuration, it is possible to easily implement chopping of various patterns that may actually occur when the levels of the multi-level converter are stacked.

The data measurement unit 130 measures the voltage and current of the capacitor, and the capacity calculation unit 140 calculates the capacity of the capacitor using the voltage and current of the capacitor measured by the data measurement unit 130. According to this configuration, it is possible to estimate the capacitor capacity while applying the same chopped current waveform as the stress applied to the capacitor when constructing an actual converter.

At this time, the capacitor C _Test is,

Calculated by the equation, △ V _c1 and △ V _c2 are the difference between the maximum charging voltage of the capacitor during the sinusoidal half-cycle time △ T ₁ and △ T ₂ , respectively, and i _{c. av1} and i _{c. ac2} is the average current during △ T ₁ and △ T ₂ times, and f _p may be the frequency of the chopped sinusoidal current.

Hereinafter, embodiments of the present invention will be described in more detail along with more specific examples.

The controller structure of the capacitor evaluation and diagnosis system proposed in the present invention is shown in Figure 4. FIG. 4 is a diagram schematically showing an example of the structure of the capacitor inspection system controller of FIG. 3. In FIG. 4, the inverter control unit 114 of FIG. 3 is implemented as a voltage control unit and a current control unit, and the inductor 113 is implemented as a filter unit.

In Figure 4, the magnitude of the voltage and current applied to the capacitor to be tested is controlled through voltage and current feedback in the inverter portion, and the inverter portion controls the current magnitude of the inductor of the filter portion.

The current chopping unit chops the current generated in the inverter unit without stressing the switch. At this time, the duty size and pattern of chopping are determined by the pulse control unit. Finally, the chopped current is applied to the capacitor to be tested through the current chopping unit.

FIG. 5 is a circuit diagram of a capacitor evaluation and diagnosis system that is an implementation example of the capacitor inspection system of FIG. 3. In Figure 5, the charge/discharge unit of Figure 3 is implemented as a capacitor charge/discharge test circuit.

The system proposed in Figure 5 consists of an inverter unit and a capacitor charge/discharge test circuit. The capacitor to be tested ( C _test ) is connected to the capacitor charge/discharge test circuit. The inverter unit controls the size and shape of the current flowing in the inductor L.

The capacitor charge/discharge test circuit consists of six switches ( S1 ~ S6), which are connected to the test capacitor to apply chopping current I _{c _test} and DC voltage to C _test . The switching pattern of the switch was proposed as shown in Figure 6 so that the chopping current I _{c_test} can be passed through the switch without stress.

FIG. 6 is a diagram showing the switching waveform of the capacitor charging/discharging circuit of FIG. 5. The proposed capacitor charge/discharge circuit consists of six switches, and each switching waveform varies depending on the inductor current I _L direction.

The switching characteristic of the proposed method is that there is no dead time in the switching signal. Normally, when S1 and S2 signals are operated complementary, a dead time is placed between the signals to allow time for all switches to turn off, but the proposed circuit does not have a dead time. Instead of dead time, the switching pattern was designed so that the I _L current flowing in the circuit always flows continuously.

If the current flow of I _L is interrupted, a very large voltage is induced in the switch, causing the switch to be destroyed. Therefore, the proposed method can efficiently chop the current flowing in the capacitor while reducing the stress on the switch.

Figures 7 and 8 are diagrams showing the switch operation mode when the inductor current is in the positive direction. FIG. 7 shows a switching pattern when the inductor current is in a positive direction in a charging mode, and FIG. 8 shows a switching pattern when the inductor current is in a positive direction in a bypass mode.

7 and 8, S2 and S6 are turned on when the sinusoidal current is in the positive direction at time T ₁ . S1, S3, and S5 always remain OFF. At this time, the switch that performs PWM switching is S4, and according to the switching operation of S4, the I _L current is chopped and the current I _{c _Test} flowing in the capacitor flows.

As shown in Figure 7, when S4 is turned off, the current flows through the capacitor through the diode of S1, switch S2, diode S5, and switch of S6. At this time, voltage is charged to the capacitor.

As shown in Figure 8, when S4 is turned on, the current of I _L is bypassed through the diode of S1, the switch S2, the diode of S3, and the switch of S4. At this time, the current flowing in the capacitor is 0, and the discharge path of the capacitor is blocked by the diode of S5, so the voltage is not discharged.

9 and 10 are inductors This diagram shows the switch operation mode when the current is in the negative direction. FIG. 9 shows a switching pattern when the inductor current is in a discharge mode in a negative direction, and FIG. 10 shows a switching pattern when the inductor current is in a bypass mode in a negative direction.

9 and 10, S1 and S3 are turned on when the sinusoidal current is in the negative direction at time T ₂ . S2, S4, and S6 always remain OFF. At this time, the switch that performs PWM switching is S5, and according to the switching operation of S5, the I _L current is chopped and the current I _{c _Test} flowing in the capacitor flows.

As shown in Figure 9, when S5 is turned on, current flows through the diode of S6, switch S5, diode S2, and switch of S1 to the capacitor. At this time, voltage is discharged to the capacitor.

As shown in Figure 10, when S5 is turned off, the current of I _L is bypassed through the diode of S4, the switch S3, the diode of S2, and the switch of S1. At this time, the current flowing in the capacitor is 0, and the discharge path of the capacitor is blocked by the diode of S4, so the voltage is not discharged.

The switching pattern of the proposed circuit allows the current I _L flowing in the circuit to flow continuously without giving dead time to the switch operation, and using this characteristic, the current flowing in the capacitor can be stably chopped.

FIG. 11 is a diagram showing simulation results performed using the method shown in FIG. 6. In Figure 11, it can be seen that the current flowing in the capacitor is well chopped according to the switching pattern, as shown in the experimental waveform, and the DC voltage applied to the capacitor is also well controlled.

In addition, the capacitor evaluation and diagnosis system proposed in Figure 5 can simultaneously estimate capacitor capacity while performing capacitor charging and discharging tests. Figure 12 is a diagram for explaining a capacitor capacity estimation method.

As shown in FIG. 12, the capacity of the capacitor can be measured in real time by measuring the voltage ( V _{c_Test} ) and flowing current ( I _{c _Test} ) of the capacitor to be tested during system operation.

Using the capacitor current and voltage relationship equation above, the difference between the charging voltage ( V _{c _Test} ) of the capacitor, △ V _c1 and △ V _c2 , can be measured. The current flowing in the capacitor ( I _{c _Test} ) can be used to determine the size of the current peak in the inverter section, and the average amount of current can be calculated using the current chopping pattern in the current chopping section. The chopped sinusoidal current has a frequency f _p , △ T ₁ and △T ₂ and the average current over time is i _{c. av1} and i _c. If defined as _ac2 , the capacitor C _Test can be calculated as follows.

Using the above formula, capacitor charge/discharge testing and capacitor capacity estimation can be performed simultaneously.

According to the present invention, the same chopping current and voltage as the current flowing when configuring the actual converter can be applied to the capacitor, and the capacity of the capacitor can be estimated in real time at the same time as the capacitor charging and discharging test. Additionally, the stress on the switch can be minimized when chopping the sinusoidal current flowing in the capacitor.

Accordingly, various voltage and current stresses applied to the capacitor during actual converter operation can be simulated, and at the same time, changes in capacitor capacity can be measured, so performance tests and capacitor stress tolerance tests can be performed when producing various initial capacitors. It becomes possible.

Although the present invention has been described in terms of some preferred embodiments, the scope of the present invention should not be limited thereby, but should extend to modifications and modifications of the above embodiments as supported by the claims.

11: submodule
12: female inductor
100: Capacitor inspection system
110: power supply unit
112: Inverter unit
113: inductor
114: Inverter control unit
120: Charge/discharge unit
122: Current chopping unit
130: data measurement unit
140: Capacity calculation unit

Claims (12)

A power supply unit that supplies current of a preset size and shape;
a charging/discharging unit that charges and discharges the capacitor using the applied current; and
It includes a data measurement unit that measures the voltage and current of the capacitor,
The charging/discharging unit is a capacitor inspection system including a current chopping unit that chops the current applied to the capacitor in a preset pattern,
The current chopping unit is a capacitor inspection system characterized in that it chops the current applied to the capacitor by bypassing the current applied to the capacitor to a preset bypass path.
delete In claim 1,
The charge/discharge unit is connected in series with the capacitor,
It includes a pair of switches connected in series in opposite directions,
A capacitor inspection system, wherein the switch includes a transistor and a diode connected in anti-parallel to each other.
In claim 3,
The current chopping unit is located in the bypass path,
It includes a pair of switches connected in series in opposite directions,
A capacitor inspection system, wherein the switch includes a transistor and a diode connected in anti-parallel to each other.
In claim 4,
A capacitor inspection system, wherein the charge/discharge unit includes the pair of switches at both ends of the capacitor.
In claim 5,
The bypass path is connected in parallel with the capacitor and the pair of switches on one end of the capacitor.
In claim 6,
A capacitor inspection system, wherein the current chopping unit chops the current applied to the capacitor in a preset pattern by opening and closing one selected switch among a pair of switches included in the current chopping unit.
In claim 1,
A capacitor inspection system further comprising a capacity calculation unit that calculates the capacity of the capacitor using the voltage and current of the capacitor measured by the data measurement unit.
In claim 8,
The capacitance C _Test of the capacitor is,



Calculated by the equation, △ V _c1 and △ V _c2 are the difference between the maximum charging voltage of the capacitor during the sinusoidal half-cycle time △ T ₁ and △ T ₂ , respectively, and i _{c. av1} and i _c. A capacitor inspection system, wherein _ac2 is the average current during △ T ₁ and △T ₂ times, and f _p is the frequency of the chopped sinusoidal current.
In claim 1,
A capacitor inspection system, wherein the power supply unit includes an inverter unit capable of converting direct current power to alternating current power.
In claim 10,
A capacitor inspection system further comprising an inverter control unit that controls the current and voltage in the capacitor using the inverter unit.
In claim 11,
The inverter unit includes an inductor connected to the charging and discharging unit,
A capacitor inspection system, characterized in that the current and voltage in the capacitor are controlled by controlling the current flowing in the inductor.

Images