KR102617678B1 - Selective memory coalescing device and method according to a class of load instruction - Google Patents

Abstract

The memory bonding device of the present invention relates to a selective memory bonding device in GPU. A classifier that classifies memory read commands as ND-load or D-load according to whether they are vulnerable to external attacks, and a memory bonding device according to the memory read command. It may include a load/store unit (LSU) that generates a request, a jointer that joins the generated memory request, and a dummy generator that generates a dummy memory request when the memory read instruction is classified as ND-load.

Description

Selective memory coalescing device and method according to a class of load instruction}

The present invention relates to a memory splicing device and method, which combines memory requests and selectively generates dummy memory requests based on vulnerabilities in memory read commands.

Memory splicing is a method to reduce the performance overhead of memory instructions that occurs due to the warp-level execution model in the GPU. Among the memory requests generated by performing a memory read command by warp in the GPU, according to one standard. This is a technology that performs cache access by bundling some or all of the memory requests and reducing the number of memory requests that need to be executed. GPUs can improve performance by shortening the time required for memory requests through memory bonding.

However, security vulnerabilities may occur depending on memory coalescence, and it may be vulnerable to external attacks such as coalescing unit side-channel attacks. As an example, in the case of a correlation-based AES attack that uses the correlation between the execution time and the number of memory requests for AES (Advanced Encryption Standard) running on GPUs, the attacker uses AES on GPUs. After execution, the execution time it takes for plaintext to become ciphertext through AES encryption and the number of memory requests generated as a result of memory splicing are obtained, and the AES encryption key value can be inferred using the correlation between them.

As in this example, memory splicing has a problem in that the encryption key can be inferred due to the correlation between the time taken for encryption and the number of memory requests generated as a result of memory splicing, making it vulnerable to attacks using this. Therefore, a technology that prevents inferring the relationship between the number of memory requests generated according to memory splicing and the time required for encryption has become necessary.

The selective memory splicing device and method according to an embodiment of the present invention selects memory read commands that are vulnerable to external attacks, and the memory requests generated accordingly generate additional dummy memory requests, allowing the attacker to determine the correct number of memory requests. We want to strengthen security by making it impossible to find out.

In addition, we aim to prevent unnecessary performance degradation by not generating additional dummy memory requests for memory read commands that are not vulnerable to external attacks.

The memory bonding device according to an embodiment of the present invention relates to a selective memory bonding device in a GPU. If the memory read command is a user-dependent instruction vulnerable to external attack, it is ND-load (non-deterministic load), and external attack is prevented. A classifier that classifies a system-dependent instruction that is not vulnerable to a D-load (deterministic load), a load/store unit (LSU) that generates a memory request according to a memory read instruction, a jointer that joins the generated memory request, and a memory read instruction. If is classified as ND-load, it may include a dummy generator that generates a dummy memory request.

Additionally, according to one embodiment, the classifier may classify the memory read command into the ND-load or the D-load depending on whether the memory read command includes a dependent index.

In addition, according to one embodiment, the classifier may classify a memory read command as the ND-load if it includes a user-dependent index, and classify it as the D-load if it includes a system-dependent index. .

In addition, according to one embodiment, the user directly specifies a plurality of memory areas, sets the classifier to classify the memory area as ND-load or D-load depending on whether the memory area includes a memory read command, and the classifier determines the memory area. If the read command includes a memory area designated by the user, it may be classified as ND-load or D-load depending on the setting.

In addition, according to one embodiment, the register and each bit are allocated to the register, and further include a security bit table initialized to false, so that when data retrieved according to a memory request is stored in the register, the data is stored in the register. If it is fetched, the value of the bit assigned to the register is changed to true, and the classifier executes the ND-load or D-load memory read command depending on whether the value of the bit assigned to the register accessed by the memory request is true or false. It can be characterized by classification by load.

Additionally, according to one embodiment, the dummy generator may be characterized in that it generates a number of dummy memory requests such that the sum of the number of dummy memory requests and memory requests concatenated by the splicer is always a preset number.

Additionally, according to one embodiment, the dummy generator may sequentially use address values that do not overlap within the range of existing address values of memory requests and set them as the address of the dummy memory request.

Additionally, according to one embodiment, the dummy generator sets an address adjacent to the existing address values as the address of the dummy memory request when there are not enough addresses to assign to the dummy memory request within the range of existing address values of the memory requests. It can be characterized as:

The memory bonding method according to an embodiment of the present invention relates to a selective memory bonding method in GPU. If the memory read command is a user-dependent instruction vulnerable to external attacks, it is ND-load, and the memory read command is ND-load, and is a system-dependent instruction that is not vulnerable to external attacks. If it is an instruction, a classification step to classify it as D-load, a memory request generation step to generate a memory request according to the memory read instruction, a splicing step to join the generated memory request, and if the memory read instruction is classified as ND-load, a dummy memory It may include a dummy creation step that creates a request.

Additionally, according to one embodiment, the classification step may be characterized by classifying the memory read command into the ND-load or the D-load depending on whether a dependent index is included.

Additionally, according to one embodiment, the classification step may be characterized by classifying the memory read command as the ND-load if it includes a user-dependent index, and classifying it as the D-load if it includes a system-dependent index. there is.

In addition, according to one embodiment, the user directly specifies a plurality of memory areas, and further includes setting the memory areas to be classified as ND-load or D-load in the classification step depending on whether the memory area includes a memory read command. And, the classification step may be characterized by classifying it as ND-load or D-load depending on the setting when the memory read command includes a memory area designated by the user.

In addition, according to one embodiment, the register and each bit are allocated to the register, and further include a security bit table initialized to false, so that when data retrieved according to a memory request is stored in the register, the data is stored in the register. If it is fetched, the value of the bit assigned to the register is changed to true, and in the classification step, a memory read command is executed according to whether the value of the bit assigned to the register accessed by the memory request is true or false. It can be characterized by classification as -load.

Additionally, according to one embodiment, the dummy generation step may be characterized by generating a number of dummy memory requests such that the sum of the dummy memory requests and the number of memory requests concatenated by the splicer is always a preset number. .

Additionally, according to one embodiment, the dummy creation step may be characterized by sequentially using address values that do not overlap within the range of existing address values of memory requests and setting them as the address of the dummy memory request.

Additionally, according to one embodiment, the dummy creation step sets an address adjacent to the existing address values as the address of the dummy memory request when there are not enough addresses to assign to the dummy memory request within the range of existing address values of the memory requests. It can be characterized as:

The selective memory splicing device and method according to an embodiment of the present invention selects memory read commands that are vulnerable to external attacks, and the memory requests generated accordingly generate additional dummy memory requests, allowing the attacker to determine the correct number of memory requests. Security can be strengthened by making it impossible to find out.

Additionally, additional dummy memory requests are not generated for memory read commands that are not vulnerable to external attacks, preventing unnecessary performance degradation.

1 is a block diagram of a memory bonding device of the present invention according to an embodiment.
Figure 2 is a memory read command according to one embodiment.
3 is a memory read command according to one embodiment.
Figure 4 is a block diagram illustrating a process in which a combiner combines memory requests according to one embodiment.
Figure 5 is a block diagram of LSU according to one embodiment.
Figure 6 is a diagram showing the address value of each memory request according to one embodiment.
FIG. 7A is a graph comparing execution times of a memory bonding device according to one embodiment and another memory bonding device.
FIG. 7B is a graph comparing energy consumption of a memory bonding device according to one embodiment and another memory bonding device.
Figure 8 is a flow chart of the memory bonding method of the present invention according to one embodiment.

The advantages and features of the present invention and methods for achieving them will become clear with reference to the embodiments described below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. The present embodiments are merely provided to ensure that the disclosure of the present invention is complete and to be understood by those skilled in the art. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The terms used in this specification will be briefly explained, and the present invention will be described in detail.

The terms used in the present invention are general terms that are currently widely used as much as possible while considering the function in the present invention, but this may vary depending on the intention or precedent of a person working in the art, the emergence of new technology, etc. In addition, in certain cases, there are terms arbitrarily selected by the applicant, and in this case, the meaning will be described in detail in the description of the relevant invention. Therefore, the terms used in the present invention should be defined based on the meaning of the term and the overall content of the present invention, rather than simply the name of the term.

When it is said that a part "includes" a certain element throughout the specification, this means that, unless specifically stated to the contrary, it does not exclude other elements but may further include other elements. In addition, terms such as “unit”, “module”, “unit”, etc. used in the specification mean a unit that processes at least one function or operation, and include software, hardware components such as FPGA or ASIC, or software and hardware. It can be implemented by combining . However, terms such as “part”, “module”, and “unit” are not limited to software or hardware. A “part”, “module”, “unit”, etc. may be configured to reside on an addressable storage medium and may be configured to reproduce on one or more processors. Accordingly, as an example, terms such as "part", "module", and "unit" refer to components such as software components, object-oriented software components, class components, and task components, and processes. Contains fields, functions, properties, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. .

Below, with reference to the attached drawings, embodiments of the present invention will be described in detail so that those skilled in the art can easily implement the present invention. In order to clearly explain the present invention in the drawings, parts unrelated to the description are omitted. Terms containing ordinal numbers, such as “first”, “second”, etc., may be used to describe various components, but the components are not limited by the terms. Terms are used to separate one component from another. It is used for distinguishing purposes only. For example, a first component may be named a second component without departing from the scope of the present invention, and similarly, the second component may also be named a first component. The term “and/or” includes a combination of a plurality of related items or any one item among a plurality of related items.

The various systems, devices, storage media, modules and mechanisms described herein may be implemented in a dedicated computing device, or one or more computing chips of one or more dedicated computing devices.

Hereinafter, the selective memory bonding device 1 and method of the present invention will be described.

Figure 1 is a block diagram of a memory bonding device 1 of the present invention according to an embodiment.

The memory coalescing device 1 of the present invention can generate a memory request and perform memory coalescing according to a memory load instruction. Additionally, the memory bonding device 1 may additionally generate dummy memory requests in order to always maintain a constant number of memory requests generated accordingly.

The memory bonding device 1 of the present invention selects memory read commands that are vulnerable to attacks and memory read commands that are not vulnerable to attacks, and instead of generating dummy memory requests for all memory read commands, it selects memory read commands that are vulnerable to attacks. You can create a dummy memory request only when executing. Here, a memory read instruction vulnerable to attack can be expressed as a non-deterministic memory load instruction (ND-load), and a memory read instruction not vulnerable to attack can be expressed as a deterministic memory load instruction (D-load). Additionally, the memory read command (ND-load), which is vulnerable to external attacks, can be mixed with user-dependent commands, and the memory read command (D-load), which is not vulnerable to external attacks, can be mixed with system-dependent commands. This will become clear through the explanation given later.

The memory read command is a command that accesses memory such as a cache. It reads data from global memory, one of the GPU's memory hierarchies, and copies it to a register or shared memory. You can order it to be done. The memory read command can be stored in an instruction buffer (I-Buffer), etc. and used when accessing memory.

The memory bonding device 1 of the present invention can operate on a streaming multiprocessor (SM), which is a collection of streaming processors (SPs), which are the smallest unit cores of a GPU. Additionally, warp of the present invention refers to the basic execution unit of a streaming multiprocessor.

The memory splicing device 1 of the present invention relates to a selective memory splicing device 1 that can operate on a GPU, and includes a sorter 100, a load/store unit (LSU) 200, a splicer 210, and a dummy generator. It may include (230). According to one embodiment, the jointer 210 and the dummy generator 230 may be included in the LSU (200). Additionally, the memory bonding device 1 may further include an instruction buffer (I-buffer), a scoreboard and execution units, a security bit table 300, and a register 400. The instruction buffer, scoreboard, and execution unit that may be included in the memory bonding device 1 of the present invention are devices for operating the device of the present invention, and their configuration and role are similar to that of a general memory device, so detailed description will be omitted. do.

The classifier 100 may classify memory read commands according to whether they are vulnerable to attack. Here, the attack may mean a coalescing unit side-channel attack such as the correlation-based AES attack described above. The classifier 100 can classify memory read commands into memory read commands (ND-load) that are vulnerable to attacks or memory read commands (D-load) that are not vulnerable to attacks. The memory bonding device 1 of the present invention determines whether to generate a dummy memory request depending on whether the memory read command is vulnerable to attack or not, thereby preventing unnecessary dummy memory creation requests and thereby preventing performance degradation. there is.

The classifier 100 selects a memory read command (ND-load) vulnerable to attack if the memory read command is a user-dependent command vulnerable to external attacks, and a command (D-load) not vulnerable to attacks if the memory read command is a system-dependent command not vulnerable to external attacks. ) can be classified as: The user-dependent command and the system-dependent command may be determined depending on whether the number of memory requests generated depending on the user may vary based on contents such as code included in the corresponding memory read command. In other words, a user-dependent command is a memory read command in which the number of memory requests generated can change depending on the user, and a system-dependent command means a memory read command in which the number of memory requests generated does not change depending on the user and is always constant. You can.

The classifier 100 can classify memory read commands according to various methods.

According to one embodiment, the classifier 100 may determine whether or not the memory is vulnerable depending on the dependency of the index included in the memory read command.

With reference to FIGS. 2 and 3, the process of determining vulnerability depending on the dependency of the index included in the memory read command will be described.

Figure 2 is a memory read command according to one embodiment.

The memory read command in FIG. 2 is a memory read command according to AES that operates on the GPU. According to Figure 2, the index of the pt array included in the memory read command can be derived from tid, and tid can be calculated using the thread id and/or block id assigned to threads existing in the warp. there is. The GPU Kernel generally accesses the array by assigning a thread id and/or block id to the thread, and calculates tid using the thread id and block id. GPUs frequently use array-type data in which multiple threads parallelly use indexes calculated by thread ID and/or block ID for the elements of the array data. Since the value of the thread id and/or block id does not change depending on the user and is often maintained at the same value, the index calculated from the thread id and/or block id may have a very formal form. Therefore, an index whose value does not change depending on the user, such as using a thread id and/or block id, can be defined as a user-independent index or system-dependent index. When accessing array data using a system-dependent index like this, almost the same number of memory requests are generated through the LSU 200 and the joiner 210. In other words, because the number of memory requests generated rarely changes depending on the index value used, this type of memory read command may occupy an almost fixed amount of execution time in the entire kernel execution time. Therefore, it is difficult for an attacker to perform an attack on this type of memory request using the correlation between the number of memory requests and execution time. As described above, the classifier 100 may classify a type of memory read command using a system-dependent index as a memory read command (D-load) that is not vulnerable to attacks.

Figure 3 shows a memory read command according to another embodiment.

The memory read command in FIG. 3 is a memory read command according to AES that operates on the GPU. According to Figure 3, Te0 included in the memory read command uses the result of calculating pt and rek as an index. Therefore, unlike the memory read command (D-load), which is not vulnerable to the above-mentioned attack, the form of data access to Te0 varies depending on the encryption key used for rek and pt. In other words, when loading data of Te0, the index of the memory read command executed is determined according to the user's data value. Since it is determined according to the user's data value as above, an index whose value changes depending on the user can be defined as a user-dependent index. The user-dependent index may include a memory area where the user can change the memory value, and representative examples include global, local, and shared memory areas. When data is accessed using a user-dependent index, the LSU 200 and the combiner 210 may generate a different number of memory requests depending on the value of the data. Different numbers of memory requests can make it vulnerable to attacks using the correlation between the number of memory requests and execution time. As described above, the classifier 100 may classify a type of memory read command using a user-dependent index as a memory read command (ND-load) that is vulnerable to attack.

According to another embodiment, the classifier 100 may determine vulnerability depending on whether the memory read command includes a memory area pre-designated by the user.

According to an embodiment, the user can directly designate a plurality of memory areas and set the classifier 100 to determine whether the memory area is vulnerable to an attack depending on whether a memory read command is included in the corresponding memory area. If the memory read command includes a memory area previously designated by the user, the classifier 100 classifies it as a memory read command (ND-load) that is vulnerable to attack or a memory read command (D-load) that is not vulnerable to attack, depending on the user setting. It can be classified as: For example, if the user specifies a memory area whose value is likely to change, and the classifier 100 determines which memory read command includes the corresponding memory area, the corresponding memory read command is classified as a memory read command ( ND-load). In addition, as another example, the user specifies a memory area whose value is not likely to change, and the classifier 100 determines which memory read command is not vulnerable to attack if a memory read command includes the memory area. It can be classified as a memory read command (D-load).

When determining attack vulnerability based on whether the user directly specifies a memory area and includes it, more detailed settings are required based on the user's direct judgment, compared to determining vulnerability based on whether the system-dependent index and user-dependent index are included. It may have the effect of being possible.

Referring again to FIG. 1, the process of determining vulnerability to attack using the secure bit table (secure bit table, 300) will be described.

According to an embodiment, the memory bonding device 1 of the present invention may further include a register 400 and a security bit table 300. One set of security bit tables 300 may be included for each streaming multiprocessor. Each bit 310 of the security bit table 300 may have a false or true value, and all bits 310 may be initialized to false. Additionally, each bit 310 may be allocated to correspond to each register 400.

When the memory bonding device 1 of the present invention writes data retrieved by executing a memory read command to the register 400, if the data is retrieved from a specific memory area, the bit 310 assigned to the register 400 ) can be changed to true. For example, if the data is taken from a memory area vulnerable to attack, the value of bit 310 allocated to the register 400 in which the data is recorded can be changed to true. Here, the memory area vulnerable to attack may mean the memory area included in the user-dependent index mentioned above.

In addition, when the memory bonding device 1 executes the memory read command again, if the data of the register 400 in which the value of the assigned bit 310 is true is used, the fetched data is assigned to the register 400 to be written. The value of bit 310 can be changed to true. Through the above process, the memory bonding device 1 can change the value of each bit 310 of the security bit table 300 to true.

The classifier 100 may determine whether the memory read command is vulnerable to attack depending on whether the value of the bit 310 assigned to the register 400 accessed by the memory request is true or false. For example, the classifier 100 may classify a memory read instruction that accesses the register 400 in which the value of the allocated bit 310 is true as a memory read instruction (ND-load) that is vulnerable to attack. On the other hand, a memory read instruction that accesses a register with an assigned value of false can be classified as a memory read instruction (D-load) that is not vulnerable to attacks.

The LSU 200 may generate a memory request according to a memory read command. The LSU 200 can perform functions such as reading or writing memory from the GPU, calculating a memory address, and reading or writing data in an appropriate cache. That is, the LSU 200 may receive a memory read command, calculate the memory address where the relevant data is stored in order to process the memory read task, and generate a memory request based on this.

The LSU 200 includes an address generation unit (AGU 270), and when a warp executes a memory read command, the AGU 270 can calculate the request address of each thread.

The LSU 200 may generate a number of memory requests corresponding to the number of threads of the warp, and may generate each memory request in response to each thread. For example, if there are 32 threads in a warp to perform a memory read command, memory requests as many as 32, which is the number of threads in the warp, can be generated.

Additionally, the LSU 200 may include a memory request queue 250. The memory request queue 250 may store memory requests generated by the LSU 200 and spliced by the splicer 210, which will be described later, and dummy memory requests generated by the dummy generator 230, and wait until they are performed.

The LSU 200 according to one embodiment may further include a splicer 210 and a dummy generator 230.

The jointer 210 will be described with reference to FIG. 4 .

Splicer 210 may concatenate memory requests. Memory splicing is a method to improve memory access performance in the GPU, and the splicer 210 can splice some or all of the memory requests generated according to the thread of the warp for performing the memory read command in the LSU 200. .

FIG. 4 is a diagram illustrating a process in which the combiner 210 combines memory requests according to one embodiment.

In the embodiment of Figure 4, it can be assumed that a single warp includes four threads, and thus four memory requests are generated in the LSU 200. In this embodiment, the memory requests of Thread 1 and Thread 2 can be combined into a single memory request at address 0x1X since the addresses of Thread 1 and Thread 2 are in the range 0x10 to 0x1F. Accordingly, the splicer 210 may concatenate some of the 4 memory requests from the warp's threads to create a total of 3 memory requests.

The combiner 210 may transmit the combined memory request to the memory request queue 250 and wait until the memory request is performed.

The standards for splicing memory requests are not limited to the above example, and various standards can be applied.

The dummy generator 230 will be described with reference to FIG. 5 .

Figure 5 is a block diagram of LSU 200 including dummy generator 230 according to one embodiment.

The dummy generator 230 may generate a dummy memory request. Here, a dummy memory request has the same form as a regular memory request, such as having a memory request address, but unlike a real memory request, it can be defined as a fake memory request with no purpose, such as not fetching data.

The dummy generator 230 is included in the LSU 200 and may generate a dummy memory request according to a warp that performs a memory read command. That is, when the LSU 200 wants to generate a memory request according to a warp, the dummy generator 230 can also generate a dummy memory request accordingly.

The dummy memory request generated through the dummy generator 230 may be stored in the memory request queue 250 together with the memory request generated by the LSU 200 and spliced by the splicer 210 and prepared for execution.

The dummy generator 230 may adjust the number of dummy memory requests so that the number of memory requests stored in the memory request queue 250 is always constant. That is, the dummy generator 230 may generate as many dummy memory requests as the sum of the dummy memory requests and the number of memory requests spliced by the splicer 210 always returns to a preset number. Accordingly, the dummy generator 230 can generate the dummy memory requests by adjusting the number of dummy memory requests according to the number of memory requests spliced by the splicer 210. For example, assuming that the number of memory requests generated by the LSU 200 is always kept constant at 8, if 5 memory requests are generated as a result of memory splicing, the dummy generator 230 generates the dummy memory request. You can create 3 so that the total number of memory requests generated is 8. Accordingly, the same number of memory requests may always exist in the memory request queue 250 regardless of the type of memory read command. Through this, the memory bonding device 1 of the present invention allows the attacker to always observe the same number of memory requests, and prevents the attacker from knowing the actual number of memory requests, so that the encryption key is generated by the correlation between the execution time and the number of memory requests. It can make inference impossible.

The dummy generator 230 may generate a dummy memory request by adjusting its characteristics to have similar characteristics to a general memory request. For example, a dummy memory request can be created so that the waiting time to retrieve data is the same or similar to the waiting time of a general memory request. This is to prevent an attacker from distinguishing between dummy memory requests and real memory requests. If the characteristics, such as waiting time, of a dummy memory request are significantly different from regular memory requests, the attacker can differentiate between them and infer the number of real memory requests. Because you can.

The dummy generator 230 according to one embodiment may generate a dummy memory request depending on whether the memory read command is vulnerable to external attack. In other words, a dummy memory request may or may not be generated depending on whether the memory read command is a memory read command (ND-load) that is vulnerable to attack or a memory read command (D-load) that is not vulnerable to attack. Here, whether a memory read command (ND-load) that is vulnerable to an attack and a memory read command (D-load) that is not vulnerable to an attack may be determined based on what was previously classified by the classifier 100.

The dummy generator 230 according to an embodiment may generate a dummy memory request when the performed memory read command is classified as a memory read command (ND-load) vulnerable to attack. In the case of a memory read command (ND-load) that is vulnerable to attack, the number of memory requests generated through the LSU 200 and the adapter 210 may be different, so it may be generally vulnerable to external attacks. In this case, the dummy generator 230 can generate a dummy memory request so that a certain number of memory requests are always generated, thereby preventing external attacks.

Conversely, the dummy generator 230 according to one embodiment may not generate a dummy memory request if the memory read command being performed is classified as a memory read command (D-load) that is not vulnerable to attack. In the case of a memory read command (D-load) that is not vulnerable to attacks, the number of memory requests generated through the LSU 200 and the joint 210 is constant, so it may generally not be vulnerable to external attacks. In this case, creating dummy memory may cause unnecessary performance degradation by creating unnecessary memory requests. Accordingly, the dummy generator 230 may not generate a dummy memory in the case of a memory read command (D-load) that is not vulnerable to attack.

Referring to FIG. 6, an embodiment of a process in which the dummy generator 230 generates a dummy memory request will be described.

Figure 6 is a diagram showing the address value of each memory request.

According to one embodiment, when creating a dummy memory, the dummy generator 230 may create it by setting the address value of the dummy memory request. The dummy generator 230 can find the address value of the dummy memory request within a range accessible to the memory read command being performed in the corresponding warp. Referring to the embodiment of FIG.

The dummy generator 230 may sequentially use address values that do not overlap within the range of existing address values. Additionally, if there is no address value available within the existing address value range, the difference between address values can be minimized as much as possible by using a nearby address value and setting it as the address of the dummy memory request. Referring to the embodiment of FIG. ) can be found and set to the address of the dummy memory request to be created. If there are not enough addresses to allocate to additional dummy memory requests within the memory address range, addresses of adjacent blocks such as 0x30 and 0xA0 can be allocated and set. The dummy generator 230 can generate a dummy memory request to have similar characteristics to existing real memory requests by setting the address of the dummy memory request in this way.

Hereinafter, the performance of the memory bonding device 1 of the present invention will be described with reference to FIGS. 7A and 7B.

Figure 7a is a graph comparing the execution time of the memory bonding device 1 according to an embodiment of the present invention and another memory bonding device 1.

According to FIG. 7A, it can be seen that the execution time of GhostLeg-ND and GhostLeg-Key, which are memory bonding devices 1 according to different embodiments of the present invention, is significantly reduced compared to other memory bonding devices 1. You can. Therefore, it can be seen that the memory bonding device 1 of the present invention has improved performance in terms of speed compared to the existing memory bonding device 1.

Figure 7b is a graph comparing the energy consumption of the memory bonding device 1 according to an embodiment of the present invention and another memory bonding device 1.

According to Figure 7b, the execution time of GhostLeg-ND and GhostLeg-Key, which are memory bonding devices 1 according to different embodiments of the present invention, shows significantly reduced energy consumption compared to other memory bonding devices 1. You can. Therefore, it can be seen that the memory bonding device 1 of the present invention has improved performance in terms of energy consumption compared to the existing memory bonding device 1.

The memory bonding method of the present invention will be described with reference to FIG. 8.

Figure 8 is a flow chart of the memory bonding method of the present invention according to one embodiment.

The memory bonding method of the present invention may include a classification step (S110) in which memory read commands are classified into ND-load or D-load depending on whether they are vulnerable to external attacks. Additionally, the memory bonding method may include a memory request generation step (S120) of generating a memory request according to a memory read command. Additionally, the memory splicing method may include a splicing step (S130) of splicing the generated memory request. Additionally, the memory joining method may include a dummy generation step of generating a dummy memory request when the memory read command is classified as ND-load.

Additionally, the classification step may be characterized by determining vulnerability depending on whether the memory read command includes a dependent index.

Additionally, in the classification step, if a memory read command contains a user-dependent index, it is classified as a memory read command (ND-load) vulnerable to attack, and if it contains a system-dependent index, it is classified as a non-vulnerable memory read command. can do.

In addition, the memory splicing method allows the user to directly specify multiple memory areas and determine whether the memory area is vulnerable to attack in the classification stage depending on whether the memory area is included in the memory read command. If it includes a memory area designated by the user, it can be classified into a memory read command (ND-load) that is vulnerable to attack or a read command that is not vulnerable to attack, depending on the setting.

In addition, the register 400 and each bit 310 are allocated to the register, and further include a security bit table 300 initialized to false, so that when data retrieved according to a memory request is stored in the register, the data is If it is from a memory area, the value of bit 310 assigned to the register is changed to true, and the classification step reads the memory depending on whether the value of bit 310 assigned to the register accessed by the memory request is true or false. It may be characterized by determining whether the command is vulnerable to attack.

Additionally, the dummy creation step may be characterized by generating a dummy memory request when the memory read command is classified as a memory read command (ND-load) vulnerable to attack.

Additionally, the dummy generation step may be characterized by generating a number of dummy memory requests such that the sum of the dummy memory requests and the number of memory requests spliced by the splicer 210 always reaches a preset number.

Additionally, the dummy creation step may be characterized by sequentially using address values that do not overlap within the range of existing address values of memory requests and setting them as the address of the dummy memory request.

In addition, the dummy creation step may be characterized by setting an address adjacent to the existing address values as the address of the dummy memory request when there are not enough addresses to be assigned to the dummy memory request within the range of existing address values of the memory requests. .

Those skilled in the art related to the embodiments of the present invention will understand that the above-described material may be implemented in a modified form without departing from its essential characteristics. Therefore, the disclosed methods should be considered from an illustrative rather than a restrictive perspective. The scope of the present invention is indicated in the claims, not the detailed description of the invention, and all differences within the equivalent scope should be construed as being included in the scope of the present invention.

1: Memory bonding device
100: Sorter
200: LSU
210: adapter
230: Dummy Generator
250: Memory request queue
270:AGU
300: Security bit table
310: bit
400: register

Claims (16)

Regarding a selective memory bonding device in GPU,
A classifier that classifies the memory read command as ND-load if it is a user-dependent command that is vulnerable to external attacks, and as D-load if it is a system-dependent command that is not vulnerable to external attacks;
a load/store unit (LSU) that generates a memory request according to the memory read command;
a joiner that joins the generated memory requests; and
a dummy generator that generates a dummy memory request when the memory read command is classified as the ND-load;
A memory bonding device comprising: According to paragraph 1,
The classifier is,
A memory joining device characterized in that it is classified into the ND-load or the D-load depending on whether the memory read command includes a dependent index. According to paragraph 2,
The classifier is,
A memory bonding device characterized in that if the memory read command includes a user-dependent index, it is classified as the ND-load, and if it includes a system-dependent index, it is classified as the D-load. According to paragraph 1,
The user directly specifies a plurality of memory areas and sets the classifier to classify the memory areas into the ND-load or the D-load depending on whether the memory area is included in the memory read command,
The classifier is,
When the memory read command includes the memory area designated by the user, the memory bonding device is classified as the ND-load or the D-load according to the setting. According to paragraph 1,
register; and
a security bit table in which each bit is allocated to the register and initialized to false; Including further,
When storing data retrieved according to the memory request in the register, if the data is retrieved from a specific memory area, change the value of the bit assigned to the register to true,
The classifier is,
A memory bonding device characterized in that the memory read command is classified as the ND-load or the D-load depending on whether the value of the bit allocated to the register accessed by the memory request is true or false. According to paragraph 1,
The dummy generator is,
A memory splicing device characterized in that it generates a number of dummy memory requests such that the sum of the number of the dummy memory requests and the number of memory requests spliced by the splicer is always a preset number. According to clause 6,
The dummy generator is,
A memory joining device, characterized in that sequentially using address values that do not overlap within the range of existing address values of the memory requests and setting them as the address of the dummy memory request. In clause 7,
The dummy generator is,
If there are not enough addresses to be assigned to the dummy memory request within the range of the existing address values of the memory requests, a memory bonding device that sets an address adjacent to the existing address values as the address of the dummy memory request. . Concerning a selective memory bonding method in GPU,
A classification step where the memory read command is classified as ND-load if it is a user-dependent command that is vulnerable to external attacks, and as D-load if it is a system-dependent command that is not vulnerable to external attacks;
A memory request generation step of generating a memory request according to the memory read command;
A splicing step of splicing the generated memory requests; and
a dummy generation step of generating a dummy memory request when the memory read command is classified as ND-load;
A memory splicing method comprising: According to clause 9,
The classification step is,
A memory splicing method characterized in that it is classified into the ND-load or the D-load depending on whether the memory read command includes a dependent index. According to clause 10,
The classification step is,
A memory joining method, characterized in that if the memory read command includes a user-dependent index, it is classified as the ND-load, and if it includes a system-dependent index, it is classified as the D-load. According to clause 9,
It further includes a step of allowing the user to directly designate a plurality of memory areas and classifying the memory areas into the ND-load or the D-load in the classification step depending on whether the memory area includes the memory read command,
The classification step is,
A memory splicing method characterized in that, when the memory read command includes the memory area designated by the user, it is classified into the ND-load or the D-load according to the setting. According to clause 9,
register and
Each bit is allocated to the register, and further includes a security bit table initialized to false,
When storing data retrieved according to the memory request in the register, if the data is retrieved from a specific memory area, change the value of the bit assigned to the register to true,
The classification step is,
A memory bonding method characterized in that the memory read command is classified as the ND-load or the D-load depending on whether the value of the bit allocated to the register accessed by the memory request is true or false. According to clause 9,
The dummy creation step is,
A memory splicing method, characterized in that generating a number of dummy memory requests such that the sum of the number of the dummy memory requests and the number of memory requests spliced in the splicing step is always a preset number. According to clause 14,
The dummy creation step is,
A memory splicing method characterized by sequentially using address values that do not overlap within the range of existing address values of the memory requests and setting them as the address of the dummy memory request. According to clause 15,
The dummy creation step is,
When there are not enough addresses to be assigned to the dummy memory request within the range of the existing address values of the memory requests, a memory joining method is set to an address adjacent to the existing address values as the address of the dummy memory request. .