KR102612947B1 - Method and apparatus for controlling unified L2 cache-TLB memory - Google Patents

Abstract

A method and device for controlling an integrated L2 cache-translation index buffer memory according to a preferred embodiment of the present invention is an L2 cache-translation index buffer in which an L2 cache and an L2 translation lookaside buffer (TLB) are integrated into one. By dynamically changing the capacity of the L2 cache and the capacity of the L2 conversion index buffer based on the characteristics of the application running on the core including memory, energy consumed due to a decrease in the L2 conversion index buffer failure rate can be reduced, and the L2 conversion index buffer can be reduced. The energy consumed in main memory can be reduced due to a reduction in main memory access due to conversion index buffer failure.

Description

{Method and apparatus for controlling unified L2 cache-TLB memory}

The present invention relates to a method and device for controlling an integrated L2 cache-translation lookaside buffer memory, and more specifically, to controlling the capacity of the L2 cache and the L2 translation lookaside buffer (TLB) built into the core. , methods and devices.

FIG. 1 is a diagram for explaining a conventional CPU structure, and FIG. 2 is a diagram for explaining the failure rate for each application in the CPU structure shown in FIG. 1.

As shown in Figure 1, conventional CPUs, GPUs, etc. have an L2 cache and an L2 translation lookaside buffer (TLB) hierarchically organized. In general, the capacity of the translation index buffer and cache is equal to "L1 translation index buffer < L1 cache < L2 translation index buffer < L2 cache < L3 cache."

As shown in Figure 2, applications running on the core have various architectural access characteristics. Applications such as blackscholes have low conversion index buffer and cache miss rates and a small working set size, so they do not require many main memory accesses. On the other hand, in the case of applications such as canneal and streamcluster, the working set size is large and the L2 conversion index buffer and L2 cache failure rate is very high due to the characteristic of accessing large amounts of data. And, in the case of applications such as canneal and streamcluster, energy consumption increases significantly as memory accesses increase due to cache and translation index buffer failures. In other words, as the L2 conversion index buffer and L2 cache with fixed capacity are used, the performance of the application deteriorates.

The purpose of the present invention is to achieve L2 based on the characteristics of an application running on a core that includes an L2 cache-translation index buffer memory in which an L2 cache and an L2 translation lookaside buffer (TLB) are integrated into one. The object is to provide a control method and device for an integrated L2 cache-translation index buffer memory that dynamically changes the capacity of the cache and the capacity of the L2 translation index buffer.

Other unspecified objects of the present invention can be additionally considered within the scope that can be easily inferred from the following detailed description and its effects.

A control method of an integrated L2 cache-translation index buffer memory according to a preferred embodiment of the present invention for achieving the above object is a control method of a control device including one or more processors including a core, wherein the core includes an L2 cache-translation lookaside buffer memory in which an L2 cache and an L2 translation lookaside buffer (TLB) are integrated into one, and the processor acquires access characteristics of an application running on the core. step; and dynamically changing, by the processor, the capacity of the L2 cache and the capacity of the L2 conversion index buffer based on the access characteristics of the application.

Here, the dynamic change step selects one of a plurality of preset capacity configuration environments based on the access characteristics of the application, and dynamically changes the capacity of the L2 cache and the capacity of the L2 conversion index buffer according to the selected capacity configuration environment. This can be done by changing it to .

Here, the plurality of capacity configuration environments include: a first capacity configuration environment in which the capacity of the L2 conversion index buffer is smaller than the capacity of the L2 cache; a second capacity configuration environment in which the capacity of the L2 conversion index buffer is equal to the capacity of the L2 cache; and a third capacity configuration environment in which the capacity of the L2 conversion index buffer is larger than the capacity of the L2 cache.

Here, in the third capacity configuration environment, the capacity of the L2 cache may be 0 KB.

Here, the first capacity configuration environment consists of the L2 conversion index buffer with a capacity of 32 KB and the L2 cache with a capacity of 256 KB, and the second capacity configuration environment includes the L2 conversion index buffer with a capacity of 256 KB. It consists of an L2 translation index buffer, the L2 cache with a capacity of 128 KB, and a write buffer with a capacity of 32 KB, and the third capacity configuration environment includes the L2 translation index buffer with a capacity of 256 KB and a write buffer with a capacity of 32 KB. It may be composed of a write buffer with capacity.

Here, in the dynamic change step, if the number of times that the access characteristic of the application is smaller than the preset first threshold is greater than the preset reference number, the capacity of the L2 cache and the L2 conversion index buffer are changed according to the first capacity configuration environment. The capacity of the L2 cache is dynamically changed, and if the number of times the access characteristic of the application is greater than the first threshold and less than the preset second threshold is greater than the reference number, the capacity of the L2 cache is determined according to the second capacity configuration environment. and dynamically change the capacity of the L2 conversion index buffer, and if the number of times that the access characteristic of the application is greater than the second threshold is greater than the reference number, the capacity of the L2 cache and the Dynamically change the capacity of the L2 translation index buffer, and change the capacity of the L2 cache and the capacity of the L2 translation index buffer according to one of the first capacity configuration environment, the second capacity configuration environment, and the third capacity configuration environment. When dynamically changed, the number of times the access characteristics of the application are compared with at least one of the first threshold and the second threshold may be initialized.

Here, the access characteristics of the application may include the L2 cache miss rate.

Here, the L2 cache-conversion index buffer memory may include a plurality of memories having different structures.

A computer program according to a preferred embodiment of the present invention for achieving the above technical problem is stored in a computer-readable storage medium and executes any one of the above-described integrated L2 cache-conversion index buffer memory control methods on the computer.

In order to achieve the above object, a control device for an integrated L2 cache-translation lookaside buffer memory according to a preferred embodiment of the present invention adjusts the capacity of the L2 cache and the capacity of the L2 translation lookaside buffer (TLB). A control device for dynamically changing, comprising: a memory storing one or more programs for dynamically changing the capacity of the L2 cache and the capacity of the L2 conversion index buffer; And one or more processors, including a core, and performing an operation to dynamically change the capacity of the L2 cache and the capacity of the L2 conversion index buffer according to the one or more programs stored in the memory, The core includes an L2 cache-conversion index buffer memory in which the L2 cache and the L2 conversion index buffer are integrated into one, and the processor acquires access characteristics of an application running on the core and determines the access characteristics of the application. Based on this, the capacity of the L2 cache and the capacity of the L2 conversion index buffer are dynamically changed.

Here, the processor selects one of a plurality of preset capacity configuration environments based on the access characteristics of the application, and dynamically changes the capacity of the L2 cache and the capacity of the L2 conversion index buffer according to the selected capacity configuration environment. You can.

Here, the plurality of capacity configuration environments include: a first capacity configuration environment in which the capacity of the L2 conversion index buffer is smaller than the capacity of the L2 cache; a second capacity configuration environment in which the capacity of the L2 conversion index buffer is equal to the capacity of the L2 cache; and a third capacity configuration environment in which the capacity of the L2 conversion index buffer is larger than the capacity of the L2 cache.

Here, if the number of times that the access characteristic of the application is smaller than the first preset threshold is greater than the preset reference number, the processor determines the capacity of the L2 cache and the capacity of the L2 conversion index buffer according to the first capacity configuration environment. Dynamically changes, and if the number of times that the access characteristics of the application are greater than the first threshold and less than the preset second threshold is greater than the reference number, the capacity of the L2 cache and the The capacity of the L2 conversion index buffer is dynamically changed, and if the number of times the access characteristic of the application is greater than the second threshold is greater than the reference number, the capacity of the L2 cache and the L2 conversion are determined according to the third capacity configuration environment. The capacity of the index buffer is dynamically changed, and the capacity of the L2 cache and the capacity of the L2 translation index buffer are dynamically changed according to one of the first capacity configuration environment, the second capacity configuration environment, and the third capacity configuration environment. When changed, the number of times the access characteristics of the application are compared with at least one of the first threshold and the second threshold can be initialized.

According to a control method and device for an integrated L2 cache-translation index buffer memory according to a preferred embodiment of the present invention, an L2 cache-translation index in which an L2 cache and an L2 translation lookaside buffer (TLB) are integrated into one. By dynamically changing the capacity of the L2 cache and the capacity of the L2 conversion index buffer based on the characteristics of the application running on the core including the buffer memory, energy consumed due to a decrease in the L2 conversion index buffer failure rate can be reduced. The energy consumed in main memory can be reduced due to a reduction in main memory access due to L2 conversion index buffer failure.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

1 is a diagram for explaining a conventional CPU structure.
FIG. 2 is a diagram for explaining the failure rate for each application in the CPU structure shown in FIG. 1.
Figure 3 is a block diagram for explaining a control device of an integrated L2 cache-translation index buffer memory according to a preferred embodiment of the present invention.
Figure 4 is a flowchart illustrating a control method of an integrated L2 cache-translation index buffer memory according to a preferred embodiment of the present invention.
Figure 5 is a diagram for explaining an example of a capacity control operation of an L2 cache-translation index buffer memory according to a preferred embodiment of the present invention.
Figure 6 is a diagram for explaining the performance of the capacity control operation of the L2 cache-translation index buffer memory according to a preferred embodiment of the present invention, and shows the L2 conversion index buffer failure rate for each application.
Figure 7 is a diagram for explaining the performance of a capacity control operation of an L2 cache-translation index buffer memory according to a preferred embodiment of the present invention, and shows energy consumption for each application.
Figure 8 is a diagram for explaining the performance of a capacity control operation of an L2 cache-translation index buffer memory according to a preferred embodiment of the present invention, and shows memory access energy consumption for each application.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. The present embodiments are merely provided to ensure that the disclosure of the present invention is complete and to provide a general understanding of the technical field to which the present invention pertains. It is provided to fully inform those with knowledge of the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Unless otherwise defined, all terms (including technical and scientific terms) used in this specification may be used with meanings that can be commonly understood by those skilled in the art to which the present invention pertains. Additionally, terms defined in commonly used dictionaries are not interpreted ideally or excessively unless clearly specifically defined.

In this specification, terms such as “first” and “second” are used to distinguish one component from another component, and the scope of rights should not be limited by these terms. For example, a first component may be named a second component, and similarly, the second component may also be named a first component.

In this specification, identification codes (e.g., a, b, c, etc.) for each step are used for convenience of explanation. The identification codes do not describe the order of each step, and each step is clearly ordered in a specific order in context. Unless specified, it may occur differently from the specified order. That is, each step may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the opposite order.

In this specification, expressions such as “have,” “may have,” “includes,” or “may include” indicate the presence of the corresponding feature (e.g., a numerical value, function, operation, or component such as a part). indicates, does not rule out the presence of additional features.

Hereinafter, a preferred embodiment of a control method and device for an integrated L2 cache-translation index buffer memory according to the present invention will be described in detail with reference to the attached drawings.

First, a control device for an integrated L2 cache-translation index buffer memory according to a preferred embodiment of the present invention will be described with reference to FIG. 3.

Figure 3 is a block diagram for explaining a control device of an integrated L2 cache-translation index buffer memory according to a preferred embodiment of the present invention.

Referring to Figure 3, the control device (hereinafter referred to as 'control device') 100 of the integrated L2 cache-translation index buffer memory according to a preferred embodiment of the present invention includes an L2 cache and an L2 translation index buffer. The capacity of the L2 cache and the capacity of the L2 translation index buffer are dynamically changed based on the characteristics of the application running on the core that includes the L2 cache-translation index buffer memory (lookaside buffer, TLB) integrated into one.

To this end, the control device 100 may include one or more processors 110, a computer-readable storage medium 130, and a communication bus 150.

The processor 110 includes one or more cores and can control the control device 100 to operate. For example, the processor 110 may execute one or more programs 131 stored in the computer-readable storage medium 130. One or more programs 131 may include one or more computer-executable instructions, which, when executed by the processor 110, cause the control device 100 to determine the capacity of the L2 cache and the L2 conversion index buffer. It may be configured to perform operations to dynamically change capacity.

Here, the core may include an L2 cache-conversion index buffer memory in which an L2 cache and an L2 conversion index buffer are integrated into one. At this time, the L2 cache-conversion index buffer memory may include a plurality of memories with different structures. For example, the L2 cache-translation index buffer memory may include a hybrid memory of energy-efficient memory cells such as static random access memory (SRAM) and magnetic random access memory (MRAM).

The computer-readable storage medium 130 is configured to store computer-executable instructions or program code, program data, and/or other suitable forms of information for dynamically changing the capacity of the L2 cache and the capacity of the L2 conversion index buffer. The program 131 stored in the computer-readable storage medium 130 includes a set of instructions executable by the processor 110. In one embodiment, computer-readable storage medium 130 includes memory (volatile memory, such as random access memory, non-volatile memory, or an appropriate combination thereof), one or more magnetic disk storage devices, optical disk storage devices, flash It may be memory devices, other types of storage media that can be accessed by control device 100 and store desired information, or a suitable combination thereof.

Communication bus 150 interconnects various other components of control device 100, including processor 110 and computer-readable storage medium 130.

Control device 100 may also include one or more input/output interfaces 170 and one or more communication interfaces 190 that provide interfaces for one or more input/output devices. The input/output interface 170 and communication interface 190 are connected to the communication bus 150. An input/output device (not shown) may be connected to other components of the control device 100 through the input/output interface 170.

Next, a control method of the integrated L2 cache-translation index buffer memory according to a preferred embodiment of the present invention will be described with reference to FIG. 4.

Figure 4 is a flowchart illustrating a control method of an integrated L2 cache-translation index buffer memory according to a preferred embodiment of the present invention.

Referring to FIG. 4, the processor 110 of the control device 100 may acquire access characteristics of an application running on the core (S110).

Here, the access characteristics of the application may include L2 cache miss rate, L2 conversion index buffer miss rate, etc.

Thereafter, the processor 110 may dynamically change the capacity of the L2 cache and the capacity of the L2 conversion index buffer based on the access characteristics of the application (S130).

That is, the processor 110 selects one of a plurality of preset capacity configuration environments based on the access characteristics of the application, and dynamically changes the capacity of the L2 cache and the capacity of the L2 conversion index buffer according to the selected capacity configuration environment. .

Here, the plurality of capacity configuration environments include a first capacity configuration environment in which the capacity of the L2 translation index buffer is smaller than the capacity of the L2 cache, a second capacity configuration environment in which the capacity of the L2 translation index buffer is the same as the capacity of the L2 cache, and an L2 translation index. A third capacity configuration environment may be included in which the buffer capacity is larger than the L2 cache capacity. At this time, the third capacity configuration environment may have an L2 cache capacity of 0 KB.

For example, a plurality of capacity configuration environments can be configured as shown in [Table 1] below.

Capacity Configuration Environment

Primary Capacity Configuration Environment

Secondary Capacity Configuration Environment

Tertiary Capacity Configuration Environment

L2 conversion index buffer

32 KB

128KB

256KB

L2 cache

256KB

128KB

-

write buffer

-

32 KB

32 KB

In more detail, if the number of times the access characteristic of the application is smaller than the first preset threshold is greater than the preset reference number, the processor 110 controls the capacity of the L2 cache and the capacity of the L2 conversion index buffer according to the first capacity configuration environment. can be changed dynamically.

And, if the access characteristics of the application are greater than the first threshold and the number of times less than the preset second threshold is greater than the reference number, the processor 110 determines the capacity of the L2 cache and the L2 conversion index buffer according to the second capacity configuration environment. Capacity can be changed dynamically.

Additionally, if the number of times the access characteristics of the application are greater than the second threshold is greater than the reference number, the processor 110 may dynamically change the capacity of the L2 cache and the capacity of the L2 conversion index buffer according to the third capacity configuration environment.

In addition, when the capacity of the L2 cache and the capacity of the L2 translation index buffer are dynamically changed according to one of the first capacity configuration environment, the second capacity configuration environment, and the third capacity configuration environment, the processor 110 sets the first threshold value. and the number of times the access characteristics of the application are compared with at least one of the second threshold values may be initialized.

Here, when the access characteristic of the application is “L2 cache failure rate”, the first threshold may be set to “0.5 (50%)” and the second threshold may be set to “0.8 (80%)”.

Next, an example of a capacity control operation of an L2 cache-translation index buffer memory according to a preferred embodiment of the present invention will be described with reference to FIG. 5.

Figure 5 is a diagram for explaining an example of a capacity control operation of an L2 cache-translation index buffer memory according to a preferred embodiment of the present invention.

Referring to FIG. 5, the present invention can dynamically partition the L2 conversion index buffer and L2 cache by considering the L2 conversion index buffer and L2 cache access characteristics (failure rate, etc.) of the application running on the core.

Here, the L2 cache-conversion index buffer memory included in the core may have a hybrid structure of SRAM and MRAM. MRAM has similar read performance to SRAM, but consumes much less energy.

Partitioning of the L2 conversion index buffer and L2 cache according to the present invention can be performed according to the three environments set as follows and can be operated by the algorithm below.

< 3 environments >

Baseline Config: First capacity configuration environment (L2 TLB: 32 KB, L2 cache: 256 KB, Write Buffer: 0)

Half-L2$ Config: Second capacity configuration environment (L2 TLB: 128 KB, L2 cache: 128 KB, Write Buffer: 32 KB)

Bypass-L2$ Config: Third capacity configuration environment (L2 TLB: 256 KB, L2 cache: 0, Write Buffer: 32 KB)

< Algorithm >

1. Monitor the L2 cache miss rate (L2$ miss rate) of the application for each specific epoch T

2. if (L2$ miss rate < threshold _low )

then Baseline Config Counter++;

else if (L2$ miss rate > threshold _low )

if (L2$ miss rate < threshold _high )

then Half-L2$ Config Counter++;

else if (L2$ missrate > threshold _high )

then Bypass-L2$ Config Counter++;

3. If all bits are "1111", partitioning of the L2 conversion index buffer and L2 cache is applied according to the environment, and all counters consisting of 4 bits (Baseline Config Counter, Half-L2$ Config Counter, and Bypass- Reset L2$ Config Counter.

4. Repeat from step 1

Here, threshold _low represents the first threshold and can be set to “0.5 (50%)”. threshold _high represents the second threshold and can be set to “0.8 (80%)”.

Next, the performance of the capacity control operation of the L2 cache-translation index buffer memory according to the preferred embodiment of the present invention will be described with reference to FIGS. 6 to 8.

Figure 6 is a diagram for explaining the performance of the capacity control operation of the L2 cache-translation index buffer memory according to a preferred embodiment of the present invention, showing the L2 conversion index buffer failure rate for each application, and Figure 7 is a preferred embodiment of the present invention. This is a diagram to explain the performance of the capacity control operation of the L2 cache-conversion index buffer memory according to , showing energy consumption for each application, and Figure 8 shows the capacity control of the L2 cache-conversion index buffer memory according to a preferred embodiment of the present invention. This diagram is intended to explain operational performance and shows memory access energy consumption for each application.

“Baseline” shown in FIGS. 6 to 8 represents a conventional structure (a structure in which the L2 cache and the L2 translation index buffer have fixed capacities), and “Proposed” represents the L2 cache-translation index buffer memory according to the present invention. Indicates the structure to which the capacity control operation is applied (a structure that dynamically changes the capacity of the L2 cache and the capacity of the L2 conversion index buffer based on the access characteristics of the application).

Referring to FIG. 6, when applying the capacity control operation of the L2 cache-conversion index buffer memory according to the present invention, the L2 conversion index buffer failure rate of applications such as canneal is reduced by about half from 50% to 27%, and streamcluster Applications such as can confirm that the L2 conversion index buffer failure rate is reduced to almost 0%.

Referring to FIG. 7, it can be seen that when applying the capacity control operation of the L2 cache-translation index buffer memory according to the present invention, the energy consumed is reduced due to a decrease in the L2 conversion index buffer failure rate.

In addition, referring to FIG. 8, when applying the capacity control operation of the L2 cache-translation index buffer memory according to the present invention, the energy of the main memory consumed due to a decrease in main memory access due to L2 conversion index buffer failure is reduced. You can check that.

Operations according to the present embodiments may be implemented in the form of program instructions that can be performed through various computer means and recorded on a computer-readable storage medium. A computer-readable storage medium refers to any medium that participates in providing instructions to a processor for execution. A computer-readable storage medium may include program instructions, data files, data structures, or combinations thereof. For example, there may be magnetic media, optical recording media, memory, etc. A computer program may be distributed over networked computer systems so that computer-readable code can be stored and executed in a distributed manner. Functional programs, codes, and code segments for implementing this embodiment can be easily deduced by programmers in the technical field to which this embodiment belongs.

These embodiments are intended to explain the technical idea of the present embodiment, and the scope of the technical idea of the present embodiment is not limited by these examples. The scope of protection of this embodiment should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of this embodiment.

100: control device,
110: processor,
130: computer-readable storage medium,
131: program,
150: communication bus,
170: input/output interface,
190: communication interface

Claims (13)

A method in which a control device including one or more processors including a core controls an integrated L2 cache-translation index buffer memory,
The core includes an L2 cache-translation lookaside buffer memory in which an L2 cache and an L2 translation lookaside buffer (TLB) are integrated into one,
Obtaining, by the processor, access characteristics of an application running on the core; and
Including, by the processor, dynamically changing the capacity of the L2 cache and the capacity of the L2 conversion index buffer based on the access characteristics of the application,
The dynamically changing step includes selecting one of a plurality of preset capacity configuration environments by comparing the access characteristics of the application with at least one of a preset first threshold and a second threshold, and selecting one according to the selected capacity configuration environment. Dynamically changing the capacity of the L2 cache and the capacity of the L2 conversion index buffer,
When the capacity of the L2 cache and the capacity of the L2 conversion index buffer are dynamically changed according to one of the plurality of capacity configuration environments, at least one of the first threshold value and the second threshold value and the access characteristics of the application are changed. Consists of initializing the number of comparisons,
Control method of integrated L2 cache-translation index buffer memory. delete In paragraph 1:
The plurality of capacity configuration environments are,
a first capacity configuration environment in which the capacity of the L2 conversion index buffer is smaller than the capacity of the L2 cache;
a second capacity configuration environment in which the capacity of the L2 conversion index buffer is equal to the capacity of the L2 cache; and
a third capacity configuration environment in which the capacity of the L2 conversion index buffer is larger than the capacity of the L2 cache;
A control method of an integrated L2 cache-translation index buffer memory comprising. In paragraph 3,
The third capacity configuration environment is,
The capacity of the L2 cache is 0 KB,
Control method of integrated L2 cache-translation index buffer memory. In paragraph 4,
The first capacity configuration environment is,
It consists of the L2 conversion index buffer with a capacity of 32 KB and the L2 cache with a capacity of 256 KB,
The second capacity configuration environment is,
It consists of the L2 conversion index buffer with a capacity of 128 KB, the L2 cache with a capacity of 128 KB, and a write buffer with a capacity of 32 KB,
The third capacity configuration environment is,
Consisting of the L2 conversion index buffer with a capacity of 256 KB and a write buffer with a capacity of 32 KB,
Control method of integrated L2 cache-translation index buffer memory. In paragraph 3,
The dynamically changing step is,
If the number of times that the access characteristics of the application are smaller than a preset first threshold is greater than the preset reference number, dynamically change the capacity of the L2 cache and the capacity of the L2 conversion index buffer according to the first capacity configuration environment,
If the access characteristic of the application is greater than the first threshold and the number of times less than the preset second threshold is greater than the reference number, the capacity of the L2 cache and the capacity of the L2 conversion index buffer according to the second capacity configuration environment. changes dynamically,
When the number of times that the access characteristic of the application is greater than the second threshold is greater than the reference number, the capacity of the L2 cache and the capacity of the L2 conversion index buffer are dynamically changed according to the third capacity configuration environment.
Control method of integrated L2 cache-translation index buffer memory. In paragraph 1:
The access characteristics of the application are,
Including L2 cache miss rate,
Control method of integrated L2 cache-translation index buffer memory. In paragraph 1:
The L2 cache-translation index buffer memory,
Containing a plurality of memories with different structures,
Control method of integrated L2 cache-translation index buffer memory. A computer program stored in a computer-readable storage medium for executing the control method of the integrated L2 cache-translation index buffer memory according to any one of claims 1, 3 to 8 on a computer. A control device that dynamically changes the capacity of the L2 cache and the capacity of the L2 translation lookaside buffer (TLB),
a memory storing one or more programs for dynamically changing the capacity of the L2 cache and the capacity of the L2 conversion index buffer; and
One or more processors including a core and performing an operation to dynamically change the capacity of the L2 cache and the capacity of the L2 conversion index buffer according to the one or more programs stored in the memory,
The core includes an L2 cache-translation index buffer memory in which the L2 cache and the L2 translation index buffer are integrated into one,
The processor acquires the access characteristics of the application running on the core and dynamically changes the capacity of the L2 cache and the capacity of the L2 conversion index buffer based on the access characteristics of the application,
The processor selects one of a plurality of preset capacity configuration environments by comparing the access characteristics of the application with at least one of a preset first threshold and a second threshold, and configures the L2 cache according to the selected capacity configuration environment. Dynamically change the capacity and capacity of the L2 conversion index buffer,
When the capacity of the L2 cache and the capacity of the L2 conversion index buffer are dynamically changed according to one of the plurality of capacity configuration environments, at least one of the first threshold value and the second threshold value and the access characteristics of the application are changed. To reset the number of comparisons,
Control unit for integrated L2 cache-translation index buffer memory. delete In paragraph 10:
The plurality of capacity configuration environments are:
a first capacity configuration environment in which the capacity of the L2 conversion index buffer is smaller than the capacity of the L2 cache;
a second capacity configuration environment in which the capacity of the L2 conversion index buffer is equal to the capacity of the L2 cache; and
a third capacity configuration environment in which the capacity of the L2 conversion index buffer is larger than the capacity of the L2 cache;
Control unit of integrated L2 cache-translation index buffer memory comprising. In paragraph 12:
The processor,
If the number of times that the access characteristics of the application are smaller than a preset first threshold is greater than the preset reference number, dynamically change the capacity of the L2 cache and the capacity of the L2 conversion index buffer according to the first capacity configuration environment,
If the access characteristic of the application is greater than the first threshold and the number of times less than the preset second threshold is greater than the reference number, the capacity of the L2 cache and the capacity of the L2 conversion index buffer according to the second capacity configuration environment. changes dynamically,
If the number of times that the access characteristic of the application is greater than the second threshold is greater than the reference number, dynamically changing the capacity of the L2 cache and the capacity of the L2 conversion index buffer according to the third capacity configuration environment.
Control unit for integrated L2 cache-translation index buffer memory.

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