KR102611828B1 - Reed-solomon decoder for error correction - Google Patents

Abstract

The Reed-Solomon decoder according to the present invention is a syndrome calculator that calculates a syndrome from a received codeword (Codeword) R(x), and an error location generator that generates an error location polynomial Λ(x) from the syndrome and the received codeword. A polynomial generator, a Chien search unit for finding the root of the error location polynomial Λ(x) using a Chien search algorithm, and an error value polynomial generated by the error location polynomial generator based on the syndrome and the received codeword. and an adder that corrects an error in the received codeword using the error position and the error value, wherein the differentiation of the error position polynomial is defined by the equation below, , the differentiation of the error location polynomial sets the even power term of the error location polynomial to '0' and is a symbol term (x=x _j ^-1 ) containing at least one error provided by the Chien search unit. Includes division operations.

Description

Reed-Solomon decoder for error correction {REED-SOLOMON DECODER FOR ERROR CORRECTION}

The present invention relates to communication systems, and more specifically to Reed-Solomon encoders and decoders for error correction.

There are two types of errors that occur in a communication environment: random error and burst error. The Viterbi code, Turbo code, or LDPC code is suitable for handling random errors, and the Reed-Solomon (R-S) code is suitable for handling burst errors. The R-S code belongs to the category of forward error correction codes and is optimized for burst error correction rather than random error correction. R-S code provides a compromise between efficiency and complexity and can be easily implemented using hardware or a Field Programmable Gate Array (FPGA).

In high-speed communication, an R-S encoder or decoder is required to provide high error correction ability and reliability while being easy to implement in hardware.

The purpose of the present invention is to implement a Reed-Solomon codec that provides real-time processing speed by taking advantage of the system parameters, efficiency and complexity that can be implemented in hardware.

The Reed-Solomon decoder according to the present invention for achieving the above object is a syndrome calculator that calculates a syndrome from a received codeword (Codeword) R(x), and an error location polynomial Λ(x) from the syndrome and the received codeword. ), an error location polynomial generation unit that generates, a Chien search unit that finds the root of the error location polynomial Λ(x) using a Chien search algorithm, and an error location polynomial generator based on the syndrome and the received codeword. an error value calculation unit that generates an error value using an error value polynomial generated by using the derivative of the error position polynomial, and an adder that corrects an error in the received codeword using the error position and the error value. Including, the differentiation of the error location polynomial is Equation It is defined as, the differentiation of the error location polynomial sets the even power term of the error location polynomial to '0', and the symbol term containing at least one error provided by the Chien search unit (x=x _j ^- The operation of dividing by ¹ ) is used.

According to the embodiment of the present invention described above, it is possible to provide a Reed-Solomon codec that provides real-time processing speed by utilizing system parameters, efficiency, and complexity that can be implemented in hardware.

1 is a block diagram briefly showing a modem system including an encoder and a decoder according to an embodiment of the present invention.
Figure 2 shows an example block diagram of a Reed-Solomon (RS) encoder with an LFSR structure implemented according to a generating polynomial.
Figure 3 is a block diagram showing an example of a Reed-Solomon decoder (RS Decoder) according to an embodiment of the present invention.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and are to be regarded as providing additional explanation of the claimed invention. Reference signs are indicated in detail in preferred embodiments of the invention, examples of which are indicated in the reference drawings. Wherever possible, the same reference numerals are used in the description and drawings to refer to the same or similar parts.

1 is a block diagram briefly showing a modem system including an encoder and a decoder according to an embodiment of the present invention. Referring to FIG. 1, the modem system 1000 of the present invention may include a transmitter 1100 and a receiver 1300. Transmitter 1100 includes an encoder 1110, a mapper 1130, and a modulator 1150. And the receiver 1300 may include a demodulator 1310, a demapper 1330, and a decoder 1350. Here, the channel 1200 may be, for example, at least one of wired, wireless, and optical communication channels that provide an Additive White Gaussian Noise (AWGN) and fading environment. Here, the processing process for the analog signal will be omitted.

The transmitter 1100 includes an encoder 1110, a mapper 1130, and a modulator 1150 to process data S(t) provided in the form of a bit stream and transmit it to the channel 1200. The encoder 1110 receives data S(t) from a general purpose multiplexer. The modulator then generates a data frame for transmission to the antenna through a digital-to-analog converter (DAC) and analog radio frequency device.

Here, the encoder 1110 may include two forward error correction code (Error Correction Code) type encoders. One is a Reed-Solomon (RS) encoder and the other is a Low Density Parity Check (LDPC) encoder. The encoder 1110 may use an RS encoder and an LDPC encoder for a high-order modulated QAM signal, and a single LDPC encoder may be used for a low-order QAM signal. The encoder 1110 adds parity symbols and bits to the input data symbols and bits, respectively, to configure RS-encoded data and LDPC-encoded data for forward error correction. The encoded data bits are delivered to the mapper 1130 to map the bits to symbols according to the selected modulation method.

The mapper 1130 blocks the encoded data bits into real signals (I) and imaginary signals (Q). The mapper 1130 maps the blocked real signal (I) and the imaginary signal (Q) to signal points on the signal constellation. The mapper 1130 takes the encoded bit stream (S _k ) and divides it into m-bit groups. Then, each m-bit group is mapped to one of the signal points of the signal constellation using Gray code mapping rules. At this time, the bit stream (S _k ) is generated as shown in Equation 1 below.

In the above equation, 'S _k,i (i=0, 1, 2, …, m-1)' represents the ith bit of the symbol to be coded by gray code mapping, and 'I _k ' and 'Q _k ' are each k Indicates the inphase and quadrature components of the th symbol.

The receiver 1300 may include a demodulator 1310, a demapper 1330, and a decoder 1350. The demodulator 1310 may perform amplification, filtering, frequency down-conversion, digitization, etc. on the signal received through the channel 1200. That is, the demodulator 1310 receives a symbolic data stream from an analog-to-digital converter (ADC). The demodulator 1310 performs a frequency and timing (symbol and frame) synchronization process while maintaining an automatic gain control (AGC) process for the received symbols. After obtaining synchronization, the demodulator 1310 performs an equalization process through an equalizer to mitigate channel effects on the received symbols.

The received symbol (R _k ) processed by filtering of the equalizer is delivered to the demapper (1330, or Slicer). The demapper 1330 converts the received symbol 'R _k ' into a soft decision value of the corresponding bit stream through a soft decision process. For example, the demapper 1330 generates a soft decision value of the bit stream by applying the log likelihood ratio (LLR) to the received symbol 'R _k '. The log likelihood ratio (LLR) provides a calculation method to derive the likelihood that the bit is '0' or '1' for each bit in a data stream.

The decoder 1350 generates received data R(t) from the data stream generated by the demapper 1330. The decoder 1350 calculates a syndrome from the received data using an RS decoder, and detects and corrects errors by calculating the error location and error value. In particular, the error location polynomial and error value can be calculated using the Euclidean algorithm.

The modem system 1000 in a wireless communication system uses a forward error correction function in which redundant information is added to the signal so that the receiver 1300 can detect and correct errors that may occur in transmission through the noisy channel 1200. Correction: hereinafter referred to as FEC) coding technology is used. The R-S code is a type of FEC code and has proven to be a good compromise between efficiency and complexity. The R-S code is a non-binary cyclic code whose symbols consist of m-bit sequences. Here, m is a positive integer with a value greater than 2. This makes the R-S code particularly good at handling burst errors. Additionally, the R-S code is a block code. That is, the message to be transmitted is separated into separate data blocks. Each block of data includes parity protection information added to form a self-contained codeword. Additionally, the R-S code is a systematic code. That is, the encoding process does not change the message symbols, and parity is added as a separate part of the block. R-S codes are linear and cyclic codes. Cyclic codes are widely used in data communication systems because their encoder and decoder circuits are relatively simple in structure.

In RS code, choosing different parameters for your code provides different levels of protection and affects the complexity of the implementation. RS code can be described as (n, k) code. Here, n is the length of the entire code, and k represents the information length of the message (or block). Generally, n≤2 ^m -1, where m is the number of bits of the symbol. (n, k) In RS code, 'nk' parity symbol and maximum 't= 'Symbol errors can be corrected.

The modem system 1000 described above may be implemented using Field-Programmable-Gate-Arrays (FPGA) or Application Specific Integrated Circuit (ASIC). In addition, the encoder 1110 and decoder 1350 use the algorithm of the present invention to implement the LDPC encoder and LDPC decoder, respectively.

Figure 2 shows an example block diagram of a Reed-Solomon (R-S) encoder with a linear feedback shift register (LFSR) structure implemented according to a generating polynomial. Referring to FIG. 2, the R-S encoder 1110 encodes k message bits {m(0), m(1),... , n-k parity bits for m(k-1)} {p(0), p(1), … , p(n-k-1)}. Afterwards, a codeword can be formed by combining n-k parity bits and message bits.

Here, the registers will start from a reset state of 0 and receive the message polynomial m(x). Then, the operation is performed by combining with the generation polynomial g(x) through the LFSR structure, and when the input of the message symbol m(x) is finished, the values remaining in the register are connected to the back of the message symbol m(x) as parity symbols and output sequentially. do.

The values of the message and parity symbol of the RS code are elements of the Galois field. Therefore, for a code based on m-bit symbols, the Galois field has 2 ^m elements. In the present invention, a (255, k, t) RS code is used in which the 'k=255-2t' symbol of the input packet is extended to a 2t parity symbol to generate a code block length of 255 symbols. In the case of this code, the Galois field has 256 (m = 8) elements, and in the present invention, 256 elements of GF (2 ⁸ = 256) are constructed using the field generation polynomial (or primitive polynomial) of Equation 2 below. did.

The (n, k) RS code is constructed by forming the generating polynomial g(x) with the argument 'nk=2t'. The roots of the generating polynomial g(x) are continuous elements of the Galois field. Selecting consecutive elements maximizes the distance property of the code. The generation polynomial g(x) of the t error correction RS code of length '2 ^m -1' can be expressed as Equation 3 below.

Here, 'α' is the primitive element of GF(2 ^m ). The primitive element 'α' is the primitive root of the generating polynomial.

K message symbols forming a message to be encoded in one block can be expressed as a message polynomial M(x) with degree k-1. That is, the message polynomial can be expressed as Equation 4 below.

Here, each coefficient of the message polynomial (M _k-1 , ..., M ₁ , M ₀ ) is an m-bit message symbol and is an element of GF(2 ^m ). To encode a message, the message polynomial M(x) must be multiplied by 'x ^nk ' and the result divided by the generating polynomial g(x). Then, the quotient q(x) and the remainder r(x), which is the degree up to 'nk-1', are generated. These results can be explained through Equation 5 below.

Using the remainder r(x) generated by division, the transmitted codeword T(x) can be expressed by combining M(x) and r(x) as shown in Equation 6 below.

It shows that the transmission codeword T(x) is generated in the systematic form required by the codeword of the R-S code. In other words, the R-S code means that encoding is possible without changing the message. By adding a remainder r(x), the encoded message polynomial is always divisible by the generating polynomial g(x) without a remainder.

Encoding of the R-S code can be obtained by using the message polynomial M(x) and the generation polynomial g(x) to generate the parity polynomial r(x) and then combining the message and the remainder as shown in Equation 5 and Equation 6. The operation of dividing the message polynomial M(x) by the generating polynomial g(x) can be easily implemented by the polynomial division operation in the Galois field.

In the present invention, a division operation between polynomials can be performed using a hardware encoder. Hardware encoders operate on pipelined data. Division calculations are performed by applying the presented message symbols one at a time. Pipeline division calculations can be performed using linear feedback shift register (LFSR) encoders, allowing the encoding to perform real-time processing.

Figure 3 is a block diagram showing an example of a Reed-Solomon decoder (R-S Decoder) according to an embodiment of the present invention. Referring to Figure 3, the R-S decoder 1350 of the present invention includes a syndrome calculator 1351, an error location polynomial generator 1352, a Chien search unit 1353, an error value calculation unit 1354, and an AND gate 1355. , a delay line 1356, and an adder 1357. The R-S decoder 1350 may be implemented as a hardware-based Reed-Solomon (R-S) decoder for the purpose of high speed and low power to support a high-speed backhaul communication system.

The first operation procedure of the RS decoder 1350 is to calculate the syndrome value (S) from the input codeword (received data) R(x). Then, using the Euclidean algorithm, we need to find the coefficients of the error location polynomial (Λ ₁ ,…, Λ _υ ) and the coefficients of the error value (or magnitude) polynomial ( ₁ ,…, Ω _υ ).

The error location is identified by Chien Search, and the error value is calculated using the 'Forney algorithm'. All symbols of the received codeword are used in these calculations. Therefore, the message (or received data) must be stored until the calculation results are available. Then, the error is corrected by adding each error value to the symbol at the error position of the received data (or codeword) (modulo 2 method).

R-S codes are block, systematic and recursive codes with finite field size (n, k). Accordingly, the R-S decoder 1350 restores the transmission data T(x) encoded by the R-S encoder from the signal received through the communication channel. Channel 1200 (see FIG. 1) may have error data E(x) added to a signal transmitted in a communication environment. Therefore, the received data R(x) can be expressed as Equation 7 below.

Here, T(x) is the codeword transmitted from the transmitter 1100, and each coefficient (E _n-1 ,..., E ₁ , E ₀ ) is m- expressed as an element of the Galois field GF(2 ^m ). It is a bit error symbol and corresponds to the error position of the codeword determined according to the size of x. 't= If it exceeds ', the channel code capacity is exceeded, and in this case, error correction is not possible. On the other hand, the RS decoder 1350 has the number of error symbols 't= If there are less than 1, the error can be corrected using procedures such as calculating the syndrome, finding the error location polynomial, determining the location of the error, and calculating the error value.

The syndrome calculator 1351 calculates the syndrome (S) from the received data R (x). The syndrome calculation procedure by the syndrome calculator 1351 is as follows. The syndrome (S) can be obtained by dividing the received data polynomial R(x) by each factor 'x+α ⁱ ' of the generating polynomial g(x). This procedure is expressed in Equation 8.

This creates the quotient Q _i (x) and the remainder 'S _i '. The remaining S _i is defined as the syndrome that occurs due to this division. The syndrome 'S _i ' can be expressed as Equation 9 below by reconstructing Equation 8.

The syndrome 'S _i ' is summarized in Equation 10 below when 'x=α ⁱ ' in Equation 9.

Here, the coefficients (R _n-1 , ..., R ₁ , R ₀ ) represent the symbols of the received codeword. The physical meaning of Equation 10 is that instead of dividing the received data polynomial R(x) by 'x+α ⁱ ' to obtain the remainder, each syndrome value is calculated by substituting 'x=α ⁱ ' into the received data polynomial R(x). That you can get it. In addition, 'x+α ⁱ ' is a factor of the generating polynomial g(x) defined in the transmission codeword T(x). thus, and This holds true. As a result, the syndrome can be expressed as Equation 11 below.

Considering Equation 11 above, it can be seen that the syndrome 'S _i ' value depends only on the error pattern and is not affected by the data value. Additionally, if no error occurs, all syndrome values are '0'.

The error location polynomial generator 1352 calculates the error location using the syndrome 'S _i '. First, the error pattern E(x) can be expressed as Equation 12 below.

Here, 'e ₁ ,… , e _υ 'is the power square root of x, 'υ' is the error position of the codeword, and Y ₁ ,… , Y _υ represents the error value at that location. Combining Equation 11 and Equation 12 results in Equation 13 below.

here, is known as an error detector. and corresponds to a syndrome. Corresponds to the power root of x and varies depending on the generating polynomial.

The error location polynomial generator 1352 generates the error number and error location of the received data R(x) using the error location polynomial of Equation 14 below.

The error location polynomial Λ(x) is constructed to have an argument of 'υ' of the form (1+x _j x), so that the inverse of the error location ( ) as the root. Therefore, as shown in Equation 15 below, there is a root 'x _j ^-1 ' that makes the error location polynomial Λ(x) 0 for each error.

In the present invention, on both sides of Equation 15 By multiplying and collecting the sum of all errors and all terms, the simultaneous equations of Equation 16 or Equation 17 below are obtained.

The 2t set of simultaneous linear equations contains the unknown coefficient 'υ' of the error location polynomial Λ(x). The simultaneous equations of Equation 16 and Equation 17 can be used to find the coefficients (Λ ₁ , ..., Λ _υ ) of the error location polynomial Λ(x). There are several ways to find the coefficients of the error location polynomial. For example, the Berlekamp algorithm and the Euclidean algorithm are known to be the most efficient algorithms for calculating the coefficients of the error location polynomial.

Berlekamp's algorithm is a concise and efficient algorithm for finding coefficients using a microprocessor. The Euclidean algorithm used in the present invention may be a more efficient algorithm for finding coefficients by implementing it in hardware for high-speed data and low-power applications. Therefore, in the following, Berlekamp's algorithm will be briefly described and the Euclidean algorithm will be described in detail. In the present invention, we will use the Euclidean algorithm to implement the error location polynomial and the related process to implement the R-S decoder in a hardware-based system for high-speed and low-power purposes.

Berlekamp's algorithm is an efficient recursive method for solving Equation 15 or Equation 16. This is done by iterating the approximation to the error location polynomial starting from Λ(x)=1. Then, at each step, the error value is obtained by substituting the approximation coefficient into the equation corresponding to the corresponding 'υ' value. The errors are then used to improve the correction polynomial, which serves to improve the approximated Λ(x). The process ends when the approximate error location polynomial is found to be consistent with the remaining equations.

On the other hand, the Euclidean algorithm is another efficient algorithm for obtaining the coefficients of the error location polynomial. This algorithm uses the relationship between error and syndrome expressed in the form of an equation based on the polynomial Λ(x). The Euclidean algorithm is also called the Key Equation and requires two new polynomials: the syndrome and error magnitude polynomials. The process of calculating the coefficient of the error location polynomial by applying the Euclidean algorithm is as follows.

First, the syndrome polynomial S(x) can be defined as Equation 18 below.

Here, the coefficients (S _2t , ..., S ₁ ) are 2t syndrome values calculated from the received codewords. And the error size polynomial Ω(x) can be defined as Equation 19.

And the key equation can be defined as Equation 20 below using the error location polynomial Λ(x), the error size polynomial Ω(x), and the syndrome polynomial S(x).

In the Key Equation, the coefficient of the error size polynomial can be expressed as Equation 21 below.

To apply the Euclidean algorithm for solving the key equation, use the method of finding the greatest common divisor d of the two elements a and b in Equation 22 below.

Here, u and v are coefficients generated by the Euclidean algorithm. The degree of the product of the syndrome polynomial S(x) and the error location polynomial Λ(x) is '2t+v-1'. Therefore, it can be expressed as follows. The product of the syndrome polynomial S(x) and the error location polynomial Λ(x) can be expressed as Equation 23 below.

The syndrome polynomials S(x) and x ^2t correspond to the a and b terms of Equation 23. The Euclidean algorithm proceeds by dividing x ^2t by the syndrome polynomial S(x) to obtain the remainder. Then the syndrome polynomial S(x) becomes the dividend and the remainder becomes the divisor that provides the new remainder. This process continues until the remainder becomes less than t. At this point, the remaining Ω(x) and the multiplication factor Λ(x) can be used in calculations.

The Chien search unit 1353 calculates the solution of the error location polynomial. That is, the Chien search unit 1354 can find the root by finding the coefficient values (Λ ₁ ,..., Λυ) of the error location polynomial Λ(x). Let us assume that the error location polynomial Λ(x) is written in the form of Equation 24 below.

here, in other words, If , the function value of the error location polynomial Λ(x) becomes '0'. Therefore, 'x ₁ ,… , x _υ ' can be calculated by a trial-and-error operation known as Chien search. Here, all possible values of the roots (field values α ⁱ , 0≤i≤n-1) are substituted into the equation, and the equation can be solved. That is, the error location is identified.

The error value calculation unit 1354 calculates the error value Y _j using the error size polynomial Ω(x). For this purpose, the Forney algorithm for calculating error values can be used. Forney's algorithm uses differentiation with respect to the error location polynomial Λ(x). The differentiation for the error location polynomial Λ(x) can be expressed as Equation 25 below.

This sets the even terms of the error location polynomial Λ(x) to 0, It is the same as dividing by Forney's algorithm uses error values Y ₁ , … , It is very efficient in calculating Y _υ and can be very easily implemented in hardware. here, silver is the derivative of the error location polynomial Λ(x).

Using Chien Search, you can find a symbol containing an error, calculate the error value of the error, and then add the error polynomial E(x) to the received signal polynomial R(x) to correct the error. It should be noted that, in general, the highest term of the received polynomial corresponds to the first symbol of the received codeword.

The syndrome calculator 1351 of the present invention can calculate the syndrome corresponding to each root 'α ⁱ ' of the generating polynomial by dividing the received polynomial R(x) by x+α ⁱ or estimating R(α ⁱ ). In the direct division process for calculating the syndrome, the syndrome calculation process of Equation 9 has a very similar form to Equation 5 used in RS encoding. Therefore, following the same reasoning for the RS encoder implementation, the polynomial division operation can be performed in the present invention using a hardware syndrome calculator.

The hardware syndrome calculator operates on pipelined data, so division calculations are made using the received symbols one at a time as they are presented. Pipeline division calculations are performed using a conventional linear feedback shift register (LFSR), which allows the syndrome calculator 1351 to perform real-time processing. For polynomial division, only one feedback term is required, with only one multiplier and one register. In the present invention, the syndrome 'S _i ' is calculated using a single feedback shift register (SFSR). It is necessary to calculate the syndrome of the 2t set, S _i (for i= 1, …, 2t). The syndrome calculator 1351 implemented in hardware of the present invention is implemented as a parallel pipeline syndrome circuit for high speed and low power consumption.

As discussed earlier in the description of the Euclidean algorithm, the first step in finding the error location polynomial is to find the syndrome polynomial. After obtaining the syndrome S _i (for i= 1, …, 2t), the syndrome polynomial is given as Equation 26 below.

As explained in Equation 23, the Euclidean algorithm consists of dividing x ^2t by S(x) to generate a remainder. Then S(x) becomes the dividend and the remainder becomes the divisor that provides the new remainder. This process continues until the degree of the remainder becomes smaller than t. At this point, the remainder Ω(x) and the multiplication factor Λ(x) can be used as terms in the calculation. Ω(x) is the error magnitude (or value) polynomial and Λ(x) is the error location polynomial. Additionally, both Ω(x) and Λ(x) are outputs of the Euclidean algorithm of the error location polynomial generator 1352.

Equation 23 used in the Euclidean algorithm has a similar form to Equation 5 used in the encoding process. However, there is a difference in the content of these two equations. In Equation 5, there are two known pieces of information and unknown information that is the remainder of r(x). On the other hand, Equation 23 has two known information and two unknown information, which are the error location polynomial Λ(x) and the error value (or magnitude) polynomial Ω(x).

In the direct division process for calculating the error value polynomial, the calculation process of Equation 24 has a similar form to Equation 5 used in R-S encoding. However, the Euclidean algorithm requires a division and multiplication process to calculate the error location polynomial. In the present invention, a polynomial division process and a polynomial multiplication process are performed using a hardware-based error value polynomial calculator and a hardware-based error location polynomial, respectively.

The hardware-based error value polynomial calculator operates on pipelined data, so division calculations are made using the received symbols one by one. The hardware-based error location polynomial calculator also operates on pipelined data, so multiplication calculations are made using the received symbols one by one. Pipeline division and multiplication are performed using four conventional single feedback shift registers (SFSR), which allows the Euclidean algorithm to perform real-time processing.

In the Chien search unit 1353, the root of the error location polynomial Λ(x) is calculated. The roots of the error location polynomial Λ(x) are solved using Chien search after finding the coefficients (Λ ₁ ,…, Λ _υ ) of the error location polynomial. The error location polynomial Λ(x) is described in Equation 14 described above. then , in other words, If , the function value becomes 0. The roots are x ₁ , … , is discovered through trial and _error depending on the ^value of .

The hardware calculation of the two polynomials Ω(x) and Λ'(x) can be performed in a similar way to the Chien search. In particular, the function value is calculated for each symbol position of the codeword in successive clock cycles. The error is corrected by adding the error value Y(x) to the received data R(x) at the point where the x value is located.

As above, embodiments are disclosed in the drawings and specifications. Although specific terms are used here, they are used only for the purpose of describing the present invention and are not used to limit the meaning or scope of the present invention described in the patent claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the attached patent claims.

Claims (3)

In the Reed-Solomon decoder:
A syndrome calculator that calculates a syndrome from the received codeword R(x);
An error location polynomial generator that generates an error location polynomial Λ(x) from the syndrome and the received codeword ( );
a Chien search unit that finds the root of the error location polynomial Λ(x) to find the error location using the Chien search algorithm;
an error value calculation unit that generates an error value using an error value polynomial generated by the error location polynomial generator based on the syndrome and the received codeword, and a differential of the error location polynomial; and
An adder that corrects an error in the received codeword using the error location and the error value,
The differentiation of the error location polynomial is defined by the equation below,
[Equation]

The differentiation of the error location polynomial sets the even power term of the error location polynomial to '0' and divides by the symbol term (x=x _j ^-1 ) containing at least one error provided by the Chien search unit. operations are used,
^The received codeword R(x) is a field generation polynomial ( ) Reed-Solomon decoder generated from. According to claim 1,
The coefficients of the error location polynomial Λ(x) are calculated using Berlekamp's algorithm or Euclidean algorithm,
A Reed-Solomon decoder to which the Forney algorithm is applied, which uses differentiation of the error position polynomial to find a solution to the error value polynomial. According to claim 1,
The syndrome calculator is a Reed-Solomon decoder that includes a single feedback shift register using a feedback method using one multiplier and one register.

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