KR102610430B1 - Binary neural network and its operation method - Google Patents

Abstract

The present invention relates to a synapse string composed of a plurality of synapse elements connected in series, wherein the synapse string includes a bit line (BL) extending in a first direction, and a plurality of bit lines (BL) extending in a second direction perpendicular to the first direction. It includes a word line (WL) and a synapse element disposed in an area where the bit line and the word line intersect, wherein the synapse element is connected to a first transistor unit, a second transistor unit, and the first transistor unit. A first fixed electrode, a second fixed electrode spaced apart from the first fixed electrode and connected to the second transistor unit, and a conductive beam bent between the first fixed electrode and the second fixed electrode to form a conductive path. It is characterized in that it includes a nano electromechanical memory cell including a.

Description

Binary neural network and its operation method}

The present invention relates to a binary neural network and its operating method, and more specifically, to a binary neural network array and operating method using nanoelectromechanical memory (NEM) devices.

Recently, as power consumption in integrated circuits based on the von Neumann architecture has increased significantly and heat generation problems have become more serious, many attempts have been made to imitate the nervous system of animals. In particular, technology that mimics the nervous system of animals has made it possible to improve cognitive and judgment functions by enabling cognitive functions and learning while significantly reducing power consumption. Accordingly, an opportunity arose to replace or significantly improve the functionality of the existing von Neumann type integrated circuit. Therefore, interest in this has increased and the need for research has emerged. The basic function of neurons is to transmit information to other cells by generating electrical spikes when they receive stimulation above the threshold, and the part that transmits signals between protrusions is called a synapse. Recently, binary neural networks, which perform forward and backward propagation by limiting the values of synapses and neurons to the values of -1 and 1, are being actively studied. Binary neural networks are advantageous in terms of area and power by eliminating multipliers. Recently, there has been an attempt to implement a binary neural network using RRAM devices. Here, the 2T2R structure was used as a synapse, and a structure for XNOR operation was designed using this structure and used in a binary neural network. Additionally, there has recently been an attempt to implement a binary neural network using logic gate logic. However, implementing a binary neural network using logic gates according to the above-described technology has good reliability, but has the disadvantage of low integration due to the use of multiple devices.

Korean Patent Publication No. 10-2020-0110582 relates to a synapse string, including first and second cell strings each having a plurality of memory cell elements connected in series; and first switch elements each connected to one of both ends of the first and second cell strings, wherein the memory cell elements of the first cell string and the memory cell elements of the second cell string have a one-to-one correspondence with each other. A pair of memory cell elements corresponding one-to-one has one terminal electrically connected to each other to form one synapse-mimicking element, and the terminals of the memory cell elements corresponding one-to-one electrically connected to each other are read. , or a terminal to which a pass voltage is applied or a program or erase (Program/Erase) voltage is applied, and the plurality of pairs of memory cell elements included in the first and second cell strings are a plurality of terminals. It consists of a synapse-mimicking element.

Korean Patent Publication No. 10-2020-0110582 (2020. 09. 24.)

An embodiment of the present invention seeks to provide a binary neural network and a method of operating the same that reduce the number of cells and power consumption for forming an array of a binary neural network by performing an XNOR operation using nano electromechanical memory cells.

One embodiment of the present invention can increase the integration of a binary neural network array and improve reliability by using a minimum number of nano electromechanical memory cells. In addition, since the durability and reliability of nano-electromechanical memory cells are excellent, we aim to provide a binary neural network and its operation method that can form a stable binary neural network array.

Among embodiments, a binary neural network according to an embodiment of the present invention includes a synapse string composed of a plurality of synapse elements connected in series, wherein the synapse string includes a bit line (BL) extending in a first direction, and a bit line (BL) extending in the first direction. It includes a plurality of word lines (WL) arranged to extend in a second direction perpendicular to the and a synapse element disposed in an area where the bit line and the word line intersect, wherein the synapse element is connected to the first transistor unit and the first transistor unit. 2 transistor units, a first fixed electrode connected to the first transistor unit, a second fixed electrode spaced apart from the first fixed electrode and connected to the second transistor unit, the first fixed electrode and the second fixed electrode. It is characterized by comprising a nano-electromechanical memory cell including a conductive beam that is bent between electrodes to form a conductive path.

One end of the synapse string further includes a CSA block (current sense amplifier) connected to the bit line.

The first transistor unit and the second transistor unit are composed of MOSFETs, one end of the first transistor unit and the second transistor unit is connected to the bit line, and the gate terminal of the first transistor unit and the second transistor unit is Each is connected to a different word line.

The CSA block has two input terminals,

A first input terminal connected to one end of the bit line of the synapse string to receive currents (I _BL ) generated from each synapse element, and a second input terminal connected to the output terminal of the reference current source to receive a reference current (I _REF ) It includes an input terminal, compares the two currents, and sequentially outputs the comparison results (Neuron output).

The nano electromechanical memory cell is a terminal to which a program or read voltage is applied, and the nano electromechanical memory cell and the MOSFET perform an XNOR operation.

In addition, the method of operating a binary neural network according to an embodiment of the present invention is

A synapse array disposed in an area where a bit line and a plurality of word lines intersect, and including a synapse element composed of a nano electromechanical memory cell including two MOSFETs and a conductive beam, wherein a specific voltage is applied to the bit line and the word line. Programming a weight of '+1' or '-1' by applying a weight, inputting a specific voltage to the word line according to a determined input value while the weight is programmed, and the weight and When the product of the input value is '+1', a voltage is applied to the fixed electrode to which the conductive beam is connected and the output value is expressed as '+1', and when the product of the weight and the input value is '-1', the conductive beam This includes a step where a voltage is applied to the unconnected fixed electrode and the output value is expressed as '-1'.

The step of programming the weight is performed row by row of the synapse array, and high and low voltages are applied to two adjacent word lines, respectively, and a high voltage is applied to a specific bit line and a low voltage is applied to the remaining bit lines to create a weight ( Weight) '+1' is programmed, or a low voltage and a high voltage are applied to the two adjacent word lines, respectively, and a high voltage is applied to a specific bit line and a low voltage is applied to the remaining bit lines to obtain a weight. It includes the step of programming ‘-1’.

If the current value (I _BL ) flowing in the bit line is greater than the reference current value (I _REF ), the output value (Output) becomes '+1', and the current value (I _BL ) flowing in the bit line is greater than the reference current value (I REF). If it is not greater than I _REF ), the output value is expressed as '-1'.

When the current size when current flows in each nano electromechanical memory cell is set to I _on , the reference current value (I _REF ) is characterized by (N/2) XI _on .

The nano electromechanical memory cell is composed of a plurality of layers, and the output value obtained from the bit line of the first layer sequentially becomes the input value of the second layer.

The disclosed technology can have the following effects. However, since it does not mean that a specific embodiment must include all of the following effects or only the following effects, the scope of rights of the disclosed technology should not be understood as being limited thereby.

The binary neural network and its operating method according to an embodiment of the present invention perform an there is.

The binary neural network and its operating method according to an embodiment of the present invention can achieve the effect of increasing the integration of the binary neural network array and improving reliability by using a minimum number of nano electromechanical memory cells. In addition, since the durability and reliability of the nano-electromechanical memory cells are excellent, it is possible to construct a stable binary neural network array.

1 is a conceptual diagram showing a synapse string and synapse array of a binary neural network according to the present invention.
Figure 2 is a diagram for explaining a program operation of a nano electromechanical memory cell of a binary neural network according to an embodiment of the present invention.
Figure 3 is a diagram for explaining the XNOR operating principle of a nano electromechanical memory cell of a binary neural network according to an embodiment of the present invention.
Figure 4 is a diagram for explaining the programming process of a binary neural network according to an embodiment of the present invention.
Figure 5 is a diagram explaining the operating principle of one synapse string among the synapse arrays of a binary neural network according to an embodiment of the present invention.
Figure 6 shows a synapse string of a binary neural network according to an embodiment of the present invention.
Figure 7 is a diagram for explaining the reading process of a binary neural network according to an embodiment of the present invention.

Since the description of the present invention is only an example for structural or functional explanation, the scope of the present invention should not be construed as limited by the examples described in the text. In other words, since the embodiments can be modified in various ways and can have various forms, the scope of rights of the present invention should be understood to include equivalents that can realize the technical idea. In addition, the purpose or effect presented in the present invention does not mean that a specific embodiment must include all or only such effects, so the scope of the present invention should not be understood as limited thereby.

Meanwhile, the meaning of the terms described in this application should be understood as follows.

Terms such as “first” and “second” are used to distinguish one component from another component, and the scope of rights should not be limited by these terms. For example, a first component may be named a second component, and similarly, the second component may also be named a first component.

When a component is referred to as being “connected” to another component, it should be understood that it may be directly connected to the other component, but that other components may exist in between. On the other hand, when a component is referred to as being “directly connected” to another component, it should be understood that there are no other components in between. Meanwhile, other expressions that describe the relationship between components, such as "between" and "immediately between" or "neighboring" and "directly neighboring" should be interpreted similarly.

Singular expressions should be understood to include plural expressions unless the context clearly indicates otherwise, and terms such as “comprise” or “have” refer to implemented features, numbers, steps, operations, components, parts, or them. It is intended to specify the existence of a combination, and should be understood as not excluding in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

For each step, identification codes (e.g., a, b, c, etc.) are used for convenience of explanation. The identification codes do not explain the order of each step, and each step clearly follows a specific order in context. Unless specified, events may occur differently from the specified order. That is, each step may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the opposite order.

All terms used herein, unless otherwise defined, have the same meaning as commonly understood by a person of ordinary skill in the field to which the present invention pertains. Terms defined in commonly used dictionaries should be interpreted as consistent with the meaning they have in the context of the related technology, and cannot be interpreted as having an ideal or excessively formal meaning unless clearly defined in the present application.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. Hereinafter, the same reference numerals will be used for the same components in the drawings, and duplicate descriptions of the same components will be omitted.

Figure 1 is a conceptual diagram showing a synapse string and synapse array of a binary neural network according to the present invention. Figure 1a shows a synapse string each having a plurality of memory cell elements connected in series, and Figure 1b shows a plurality of synapse strings. This shows the constructed synapse array.

Referring to FIG. 1A, one synapse string 100 includes a bit line (BL) extending in a first direction and a plurality of word lines (WL ₀ to WL) extending in a second direction perpendicular to the first direction. _N ), and a synapse element 110 is located in each area where the bit line and the word line intersect. Additionally, a CSA block (current sense amplifier) connected to a bit line is provided at one end of the synapse string 100.

Referring to FIG. 1B, the synapse array 150 includes several synapse strings 100 including synapse elements 110 arranged along the word line direction. Each synapse element 110 consists of two MOSFETs (TR1, TR2) and one nano electromechanical memory (NEM) cell, and the nano electromechanical memory cell is a terminal to which a program or read voltage is applied. It is desirable to be The nano electromechanical memory cell and MOSFET constituting one synapse element 110 are configured to perform an XNOR operation. At this time, it is possible to receive two voltages as one input through the conductive beam of the nano electromechanical memory cell and perform an

A peripheral circuit is formed at one end of the synapse array 150, and a CSA block connected to the bit line of the synapse string 100 is disposed in the peripheral circuit. The CSA block has two input terminals, one input terminal is connected to one end of the bit line of the synapse string and receives currents (I _BL ) generated from each synapse element from the basic synapse string, and the other input terminal is connected to the output terminal of the reference current source and receives the reference current (I _REF ) from the reference current source. The CSA block compares the synaptic string currents and reference currents for each synaptic element and sequentially outputs the comparison results (Neuron output).

Figure 2 is a diagram for explaining a program operation of a nano electromechanical memory cell of a binary neural network according to an embodiment of the present invention.

The program operation principle of the nano electromechanical memory cell is a bit line (BL ₀ ) to which a voltage is applied and two word lines to which opposing voltages are applied, the first word line (WL ₀ ) and the second word line (WL _0'). ) can be explained through.

First, in order to program a weight of '+1' to the synapse element as shown in Figure 2a, a high voltage is applied to the bit line, a high voltage is applied to the first word line, and a low voltage is applied to the second word line. Volatge) is authorized. Accordingly, the conductive beam 200 is shorted to the first fixed electrode (L1) due to the applied voltage, and a weight of '+1' is programmed.

Conversely, in order to program a weight of '-1' to the synapse element as shown in Figure 2b, a high voltage is applied to the bit line, a low voltage is applied to the first word line, and a high voltage is applied to the second word line. Accordingly, the conductive beam 200 is short-circuited to the second fixed electrode L2 due to the applied voltage, and a weight of '-1' is programmed. As explained through Figures 2a and 2b, the weight value can have two values, '+1' or '-1', and as shown in Table 1 below, V _BL0 is High, V _WL0 is High, and V _BL0' If a low voltage is applied to , the weight value can be defined as +1, and if a high voltage is applied to V _BL0 , low to V _WL0 , and high voltage to V _BL0 ', the weight value can be defined as -1. .

<Table 1>

Additionally, the voltage for reading the nano electromechanical memory cell can be explained with reference to <Table 2> below.

As shown in Table 2, when a medium voltage is applied to V _BL0 , medium to V _WL0 , and low voltage to V _BL0' , the input value (Input) is defined as +1, medium to V _BL0 , low to Vw _L0 , and V _BL0 ' When a medium voltage is applied, the input value (Input) can be defined as -1. At this time, the magnitude relationship of the voltage application value may be V(High, ~ 0.7V) > V(Medium ~ 0.5V) > V(Low, 0V). The reason why the voltage used for the input value (Input) is lower than the voltage used when programming is to apply the input value (Input) without changing the position of the programmed conductive beam.

<Table 2>

Figure 3 is a diagram to explain the XNOR operating principle of the nano electromechanical memory cell of the binary neural network according to an embodiment of the present invention. The XNOR operating principle of the nano electromechanical memory cell is that each nano electromechanical memory cell is '+ It can be explained in the programmed state as 1' and '-1'.

First, referring to FIGS. 3A and 3B, in order to input the input value (Input) '+1' with the weight programmed into the nano electromechanical memory cell, the first word line (W) is used as shown in <Table 2>. Medium voltage and low voltage are applied to _L0 ) and the second word line (W _L0' ), respectively.

At this time, as shown in Figure 3a, if the product of the input value and the weight is '+1', a voltage is applied to the first fixed electrode (L1) to which the conductive beam is connected (short), causing a current to flow in the bit line, Accordingly, the output value (Output) expresses '+1'.

On the other hand, as shown in Figure 3b, if the product of the input value and the weight is '-1', a voltage is applied to the first fixed electrode L1 to which the conductive beam is not connected (open), so that no current flows in the bit line. and, accordingly, the output value (Output) expresses '-1'.

In addition, referring to FIGS. 3C and 3D, in order to input the input value (Input) '-1' with the weight programmed into the nano electromechanical memory cell, the first word line (W) is used as shown in <Table 2>. Low voltage and medium voltage are applied to _L0 ) and the second word line (W _L0' ), respectively.

At this time, as shown in Figure 3c, if the product of the input value and the weight is '+1', a voltage is applied to the second fixed electrode (L2) to which the conductive beam is connected (short), causing a current to flow in the bit line, Accordingly, the output value (Output) expresses '+1'.

On the other hand, as shown in Figure 3d, if the product of the input value (Input) and the weight (Weight) is '-1', voltage is applied to the second fixed electrode (L2) to which the conductive beam is not connected (open), so that no current flows in the bit line. Therefore, the output value (Output) expresses ‘-1’. The XNOR operation principle of the nano electromechanical memory cell described in FIGS. 3A to 3D can be defined as shown in <Table 3>.

<Table 3>

Figure 4 is a diagram for explaining the programming process of a binary neural network according to an embodiment of the present invention, and shows a binary neural network synapse array of N (Input) X M (Output). Here, the binary neural network program proceeds row by row.

First, as shown in Figure 4a, a high voltage is applied to V _WL0 and a low voltage is applied to V _BL0' in the first time period (T ₀ to T ₁ ), and the weight '+1' is programmed. A high voltage is applied to the bit lines (BL ₀ , BL ₁ ) of the nano electromechanical memory cell and a low voltage is applied to the remaining bit lines to program the weight '+1'.

Subsequently, as shown in Figure 4b, a low voltage is applied to V _WL0 and a high voltage is applied to V _BL0' in the second time period (T ₁ to T ₂ ), and the nano electric machine to program the weight '-1' A high voltage is applied to the memory bit line (BL _K ) and a low voltage is applied to the remaining bit lines to program the weight '-1'. Afterwards, weights appropriate for each nano electromechanical memory cell are programmed on a row-by-row basis using the method shown in FIGS. 4A and 4B.

Figure 5 is a diagram explaining the operating principle of one synapse string among the synapse arrays of a binary neural network according to an embodiment of the present invention.

Figure 5 shows a state in which weights are programmed to each nano electromechanical memory cell in one synapse string in which multiple synapse elements are connected in series. At this time, voltage is applied to the input values (Input ₁ to Input _N ) according to the input value (Input) of '+1' or '-1' (see <Table 2>). When the input value (Input) is applied, if the product of the input value (Input) and the weight (Weight) becomes '+1', current flows through the conductive beam 500 connected (short) in each nano electromechanical memory cell. do. Conversely, when the product of the input value and the weight is '-1', voltage is applied to the unconnected (open) conductive beam in each nano electromechanical memory cell and current does not flow. In this way, the current flowing in the bit line is determined through the current in the nano electromechanical memory cell through which current flows and the nano electromechanical memory cell through which current does not flow. As a result, if the current value (I _BL ) flowing in the bit line is greater than the reference current value (I _REF ), the output value (Output) becomes '+1', and the current value (I _BL ) flowing in the bit line is greater than the reference current value (I REF). If it is not greater than I _REF ), it becomes '-1'. At this time, when the current size when current flows in each nano electromechanical memory cell is set to I _on , the reference current value (I _REF ) becomes (N/2) XI _on .

Figure 6 shows a synapse string of a binary neural network according to an embodiment of the present invention, and represents the first string of each layer.

Referring to Figure 6, the first synapse string of each layer is shown. A nano electromechanical memory cell in which current flows according to the input value and weight in the first synapse string of the first layer. The current flowing in the bit line is determined by the current in the nano electromechanical memory cell where excess current does not flow. At this time, if the current value (I _BL ) flowing through the bit line is greater than the reference current value (I _REF ), the output value (Output) becomes '+1', and then the first input value (Input) of the second layer ), medium voltage and low voltage are applied to W _L0 and W _L0' of the second layer, respectively. Conversely, if the current value (I _BL ) flowing through the bit line is less than the reference current value (I _REF ), the output value (Output) becomes '-1', and then the first input value (Input) of the second layer is '-1'. To input -1', low voltage and medium voltage are applied to W _L0 and W _L0' of the second layer, respectively. Through the above principle, the output values obtained from the bit lines (BL ₀ to BL _K ) of the first layer sequentially become the input values (Input ₀ to Input _K ) of the second layer.

Figure 7 is a diagram for explaining the reading process of a binary neural network according to an embodiment of the present invention, and shows a binary neural network synapse array of N (Input) X K (Output).

Referring to FIG. 7, when each binary neural network array corresponds to the first layer, the read process is performed simultaneously by applying a medium voltage to all bit lines.

When a medium voltage is applied to all bit lines, the current flows to each bit line through the nano electromechanical memory cells through which current flows and the nano electromechanical memory cells through which current does not flow, depending on the input value and weight. The current is determined. At this time, if the current value (I _BL ) flowing in the bit line is greater than the reference current value (I _REF ), the output value becomes '+1', and conversely, the current value (I _BL ) flowing in the bit line is greater than the reference current value (I _REF ). ), the output value becomes '-1', and the output value obtained from the bit lines (BL ₀ ~ BL _K ) of the first layer is transmitted to the input value (Input) of the next second layer in order. becomes the input value (Input ₀ ~ Input _K ).

As described above, by using nano electromechanical memory cells, a binary neural network capable of low power, high integration, and high performance can be implemented.

Although the present invention has been described above with reference to preferred embodiments, those skilled in the art may make various modifications and changes to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. You will understand that you can do it.

100: synapse string
110: synapse element
150: synapse array
200: conductive beam

Claims (10)

In a synaptic string consisting of a plurality of synaptic elements connected in series,
The synapse string includes a bit line (BL) extending in a first direction;
a plurality of word lines (WL) extending in a second direction perpendicular to the first direction; and
It includes a synapse element disposed in an area where the bit line and the word line intersect, and the synapse element is
a first transistor unit and a second transistor unit each of which has a drain terminal connected to the bit line and a gate terminal connected to a different word line;
a first fixed electrode connected to the source terminal of the first transistor unit;
a second fixed electrode spaced apart from the first fixed electrode and connected to a source terminal of the second transistor unit; and
A binary neural network comprising a nano-electromechanical memory cell including a conductive beam that is bent between the first fixed electrode and the second fixed electrode to form a conductive path.
According to paragraph 1,
A binary neural network further comprising a CSA block (Current sense amplifier) connected to the bit line at one end of the synapse string.
According to paragraph 1,
The first transistor unit and the second transistor unit
A binary neural network characterized by being composed of MOSFETs.
According to paragraph 2,
The CSA block has two input terminals,
a first input terminal connected to one end of the bit line of the synapse string and receiving currents (I _BL ) generated from each synapse element; and
A binary neural network that includes a second input terminal that is connected to the output terminal of the reference current source and receives a reference current (I _REF ), and compares the two currents to sequentially output the comparison results (Neuron output).
According to paragraph 3,
The nano electromechanical memory cell includes a terminal to which a program or read voltage is applied, and the nano electromechanical memory cell and the MOSFET perform an XNOR operation.
It is placed in the area where the bit line and multiple word lines intersect.
A nano electric machine including two MOSFETs, each drain terminal of which is connected to the bit line, a gate terminal of which is connected to a different word line, and a source terminal of which is connected to a different fixed electrode, and a conductive beam connected to the ground (GND). In the synapse array including a synapse element composed of memory cells,
Programming a weight of '+1' or '-1' into the nano electromechanical memory cell by applying a specific voltage to the bit line and the word line;
Inputting a specific voltage to the word line according to a determined input value while the weight is programmed; and
When the product of the weight and the input value is '+1', a voltage is applied to the fixed electrode to which the conductive beam is connected among the different fixed electrodes, and the output value is expressed as '+1', and the product of the weight and the input value is In the case of '-1', a voltage is applied to the fixed electrode to which the conductive beam is not connected among the different fixed electrodes, and the output value is expressed as '-1'.
A method of operating a binary neural network comprising:
The method of claim 6, wherein programming the weights includes
Proceeds row by row of the synapse array,
Apply high and low voltages to two adjacent word lines, respectively, and program the weight '+1' by applying high voltage to a specific bit line and low voltage to the remaining bit lines, or
A step of applying low and high voltages to two adjacent word lines, respectively, and applying high voltage to a specific bit line and low voltage to the remaining bit lines to program the weight '-1'.
A method of operating a binary neural network comprising:
According to clause 6,
If the current value (I _BL ) flowing in the bit line is greater than the reference current value (I _REF ), the output value (Output) becomes '+1', and the current value (I _BL ) flowing in the bit line is greater than the reference current value (I REF). A binary neural network operation method characterized in that the output value is expressed as '-1' if it is not greater than I _REF ).
According to clause 8,
A method of operating a binary neural network, characterized in that when the current size when current flows in each nano electromechanical memory cell is set to I _on , the reference current value (I _REF ) is (N/2) XI _on .
According to clause 6,
The nano electromechanical memory cell is composed of multiple layers,
A method of operating a binary neural network, characterized in that the output value obtained from the bit line of the first layer sequentially becomes the input value of the second layer.