KR102602806B1 - Recursive resonant switched dc-dc converter with tri-coupled inductor and operation method therefor - Google Patents

Abstract

According to the present invention, a three-stage circuit that outputs an input voltage as an output voltage corresponding to a set step-up ratio, wherein the three-stage circuit is connected sequentially, and each end is connected to a switched capacitor circuit and one end is connected to the switched capacitor circuit and the other end is connected to the switched capacitor circuit. A stage includes a first to third stage circuit including an inductor connected to an output node; and a zero current detector that controls the off point of at least one switch included in the switched capacitor circuit to correspond to the point in time when the current of the inductor of the third stage circuit becomes zero current.

Description

Recursive resonance switched capacitor DC-DC converter using triple coupled inductor and its operation method {RECURSIVE RESONANT SWITCHED DC-DC CONVERTER WITH TRI-COUPLED INDUCTOR AND OPERATION METHOD THEREFOR}

The present invention relates to a recursive resonance type switched capacitor direct current-direct current converter using a triple-coupled inductor and a method of operating the same.

As integrated circuits gradually pursue higher integration and higher performance, the amount of power consumed is increasing, and accordingly, power transfer circuits (PMIC) with high power density are required. However, the switched capacitor transformer used in conventional highly integrated power transmission circuits has limitations in output power in a limited area. For example, the conventional recursive resonance structure has a high step-up ratio, but has the problem of using a bulky external inductor element and supplying a low output current.

Republic of Korea Patent Publication No. 10-2020-0022021 Republic of Korea Patent Publication No. 10-2020-0064557

Various embodiments of the present invention use a triple-coupled inductor to have a multiple step-up ratio, and the inductor is integrated inside the chip to achieve high integration, high output, and a wide voltage range. A recursive resonance type switched capacitor DC-DC converter using a triple-coupled inductor and its operation method.

In addition, various embodiments of the present invention provide a recursive resonant switched capacitor DC-DC converter using a triple-coupled inductor that can control the switching point when zero current flows in the inductor to reduce transmission loss, and a method of operating the same. It is for this purpose.

The technical problems to be achieved in the various embodiments of the present invention are not limited to the matters mentioned above, and other technical problems not mentioned are those that are within the scope of ordinary knowledge in the technical field from the various embodiments of the present invention described below. Can be considered by those who have.

In one embodiment of the present invention, a three-stage circuit that outputs an input voltage as an output voltage corresponding to a set step-up ratio, wherein the three-stage circuit is sequentially connected, each stage having a switched capacitor circuit and one stage having the switched capacitor circuit. It includes a first stage to a third stage circuit including an inductor connected to an output node and the other end connected to the output node; and a zero current detector that controls the off point of at least one switch included in the switched capacitor circuit to correspond to the point in time when the current of the inductor of the third stage circuit becomes zero current.

For example, the switched capacitor circuit converts a voltage corresponding to half of the upper level voltage and lower level voltage applied to the switched capacitor circuit according to a switching operation into the output voltage of each of the first to third stage circuits. Can be printed.

For example, the higher level voltage applied to the first stage circuit is the input voltage, the lower level voltage is ground, and the higher level voltage applied to the second stage circuit is the input voltage or the first is the output voltage of the stage circuit, the lower level voltage is the ground or the output voltage of the first stage circuit, and the upper level voltage applied to the third stage circuit is the input voltage or the output voltage of the second stage circuit. , the lower level voltage may be ground or the output voltage of the second stage circuit.

For example, the zero current detector may include a comparator that compares the voltage of one end of the inductor of the third stage circuit between a first time point and a second time point after the first time point and outputs a comparison result; a digital signal control unit that controls a digital signal to control the off point based on the comparison result; and a delay control unit that adjusts the delay at the off point based on the digital signal.

For example, the comparator determines that the off time is early when the voltage corresponding to the first time point is greater than the voltage corresponding to the second time point, and the voltage corresponding to the first time point is greater than the voltage corresponding to the second time point. If it is less than the corresponding voltage, it can be determined that the off time is slow.

For example, if the digital signal controller determines that the off point is fast, it turns up the digital signal for controlling the off point by 1 bit, and if it determines that the off point is slow, it turns the digital signal down by 1 bit. You can.

For example, the delay adjuster sets a leading delay defined on the time axis from the on point of the at least one switch, and adjusts an adjustable delay defined from the leading delay to the off point based on the digital signal. You can.

For example, it may further include a switch control unit connected to the zero current detector and controlling the at least one switch based on the switching pulse signal generated based on the digital signal and the step-up ratio.

In another embodiment of the present invention, an operation method performed by a DC-DC converter including a three-stage circuit including a first stage circuit to a third stage circuit and a zero current detector, wherein the input voltage is adjusted to a set step-up ratio. outputting a corresponding output voltage; and controlling the off point of at least one switch included in the three stage circuit to correspond to the point in time when the current of the inductor of the third stage circuit becomes zero current.

For example, comparing the voltage of one end of the inductor of the third stage circuit between a first time point and a second time point after the first time point and outputting a comparison result; controlling a digital signal for controlling the off point based on the comparison result; and adjusting the delay at the off point based on the digital signal.

The various embodiments of the present invention described above are only some of the preferred examples of the present invention, and various examples reflecting the technical features of the various embodiments of the present invention will be described in detail below by those skilled in the art. Can be derived and understood based on detailed explanation.

According to various embodiments of the present invention, the following effects are achieved.

According to various embodiments of the present invention, a recursive resonant switched capacitor direct current using a triple-coupled inductor has a multiple step-up ratio using a triple-coupled inductor, and has high integration, high output, and a wide voltage range by integrating the inductor inside the chip. -A direct current converter and its operating method can be provided.

In addition, a recursive resonance type switched capacitor DC-DC converter using a triple-coupled inductor that can control the switching point when zero current flows in the inductor to reduce transmission loss and a method of operating the same can be provided.

The drawings attached below are intended to aid understanding of various embodiments of the present invention and provide various embodiments of the present invention along with a detailed description. However, the technical features of various embodiments of the present invention are not limited to specific drawings, and the features invented in each drawing may be combined to form a new embodiment. Reference numerals in each drawing refer to structural elements.
1 is a circuit diagram of a DC-DC converter according to an embodiment of the present invention.
Figure 2 shows a triple-coupled inductor according to an embodiment of the present invention.
Figure 3 is for explaining the operation of each stage included in the three-stage circuit.
FIGS. 4A to 4E are for explaining the operation of the three-stage circuit according to each step-up ratio.
Figure 5 shows a specific circuit diagram of the zero current detector.
Figure 6 is for explaining the delay controlled by the delay control unit.
Figures 7a and 7b are for explaining the specific operation of the zero current detector.
Figure 8 shows simulation results of the DC-DC converter of the present invention.
Figure 9 is a flowchart of a method of operating a DC-DC converter according to an embodiment of the present invention.
Figure 10 is a flowchart of a method of operating a zero current detector according to an embodiment of the present invention.

Hereinafter, implementations according to the present invention will be described in detail with reference to the attached drawings. The detailed description set forth below together with the accompanying drawings is intended to describe exemplary implementations of the invention and is not intended to represent the only implementation form in which the invention may be practiced. The following detailed description includes specific details to provide a thorough understanding of the invention. However, one skilled in the art will recognize that the present invention may be practiced without these specific details.

Terms such as first or second may be used to describe various components, but the components should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another component, for example, a first component may be named a second component, without departing from the scope of rights according to the concept of the present invention, Similarly, the second component may also be referred to as the first component.

In various embodiments of the present invention, “/” and “,” should be interpreted as indicating “and/or.” For example, “A/B” can mean “A and/or B.” Furthermore, “A, B” may mean “A and/or B.” Furthermore, “A/B/C” may mean “at least one of A, B and/or C.” Furthermore, “A, B, C” may mean “at least one of A, B and/or C.”

1 is a circuit diagram of a DC-DC converter according to an embodiment of the present invention.

Referring to FIG. 1, the DC-DC converter 10 includes a three-stage circuit 100 and a zero current detector 200.

The three-stage circuit 100 outputs the input voltage as an output voltage corresponding to the step-up ratio according to the set step-up ratio.

The three-stage circuit 100 includes first to third stage circuits 110a to 110c sequentially connected. The output terminal of the first stage circuit 110a is connected to the input terminal of the second stage circuit 110b and the input terminal of the third stage circuit 110c, and the output terminal of the second stage circuit 110b is connected to the third stage circuit 110c. connected to the input terminal of

A first voltage application switch SWV1 is provided between the first stage circuit 110a and the second stage circuit 110b, and a 2-1 switch is provided between the first stage circuit 110a and the third stage circuit 110c. A voltage application switch (SWV2_1) may be provided, and a 2-2 voltage application switch (SWV2_2) may be provided between the second stage circuit 110b and the third stage circuit 110c. The first voltage application switch SWV1 connects the output voltage Vint1 of the first stage circuit 110a to the input terminal (capacitor included in the second stage circuit 110b) of the second stage circuit 110b through a switching operation. Applying the voltage, the 2-1 voltage application switch SWV2_1 applies the output voltage Vint1 of the first stage circuit 110a to the input terminal (third stage circuit 110c) of the third stage circuit 110c by a switching operation. is applied to the included capacitor), and the 2-2 voltage application switch (SWV2_2) applies the output voltage (Vint2) of the second stage circuit (110b) to the input terminal (third stage) of the third stage circuit (110c) by a switching operation. It is applied to the capacitor included in the circuit 110c.

By the voltage application switches described above, each of the first to third stage circuits 110a to 110c can receive the upper level voltage (VH) and the lower level voltage (VL). For example, the upper level voltage (VH) applied to the first stage circuit 110a is the input voltage, and the lower level voltage (VL) is the ground. For example, the upper level voltage (VH) applied to the second stage circuit (110b) is the input voltage or the output voltage (Vint1) of the first stage circuit (110a), and the lower level voltage (VL) is the ground or the first stage circuit (110a). This is the output voltage (Vint1) of the stage circuit 110a. For example, the upper level voltage (VH) applied to the third stage circuit 110c is the input voltage or the output voltage (Vint2) of the second stage circuit 110b, and the lower level voltage (VL) is the ground or the second stage circuit 110b. This is the output voltage (Vint2) of the stage circuit 110b.

Each of the first to third stage circuits 110a to 110c includes a switched capacitor circuit, an inductor, and an output capacitor.

The switched capacitor circuit includes capacitors C1, C2, and C3, a pair of first switches SW1 and a pair of second switches SW2, and a pair of first switches SW1 and a pair of second switches. 2 The switch (SW2) charges and discharges the capacitors (C1, C2, C3) according to the switching operation switched by the switching pulse signal, and the upper level voltage (VH) and lower level voltage (VL) applied to the switched capacitor circuit. A voltage corresponding to half of is output as the output voltage of each of the first to third stage circuits 110a to 110c. The switched capacitor circuit may include an inversion circuit corresponding to an inversion phase (180 degree phase). The specific operation of the switched capacitor circuit will be described later.

The inductors (L1, L2, L3) have one end connected to the switched capacitor circuit and the other end connected to the output node. Output capacitors (Cout1, Cout2, Cout3) are connected to the output node. The inductor operates by resonating with the capacitor included in the switched capacitor.

According to one embodiment, the three inductors included in the three-stage circuit 100 may be triple coupled when integrated into a chip. Each inductor included in the first to third stage circuits 110a to 110c is referred to as L1 to L3. Since the output current transmitted from the last stage to the first stage of the three-stage circuit 100 in the DC-DC converter 10 is small, the resistance component generated in the inductor must also be distributed accordingly.

Figure 2 shows a triple-coupled inductor according to an embodiment of the present invention.

Figure 2 shows the DC-DC converter 10 from the perspective of an inductor when integrated into a chip. In the case of a triple-coupled inductor, the resistivity varies depending on the metal layer used in the CMOS (Complementary Metal-Oxide-Semiconductor) process (for example, the resistivity of the top metal layer is about 12 times lower than that of other metal layers), so it can be used in limited chips. The inductor resistance must be distributed efficiently among resources. Therefore, as shown in FIG. 2, the series resistance (DCR) of the triple-coupled inductor can be distributed as L1 > L2 > L3.

Returning to FIG. 1, the zero current detector 200 controls the off time of at least one switch included in the switched capacitor circuit to correspond to the time when the current of the inductor of the third stage circuit 110c becomes zero current.

The zero current detector 200 detects the time when I _L3 , which is the current of L3, becomes zero current, and compares the detected time with the off time of the switched capacitor circuit to determine whether the off time is fast or slow. In addition, as a result of the judgment, if the off time is fast or slow, various operations (delay setting operation, digital signal adjustment, switching pulse signal generation (Φ1, Φ2), etc.) are performed to control it to correspond to the time when the current becomes zero. A detailed description of the zero current detector 200 will be described later.

A comparator 300 for identifying the on point of at least one switch is connected to the zero current detector 200. The comparator 300 compares the output voltage of the three-stage circuit 100 with a preset reference voltage (V _REF ) and transmits the comparison result (CMP _DY,OUT ) to the zero current detector 200. The zero current detector 200 performs a delay setting operation when the on point is identified as a result of comparison.

The switching pulse signals Φ1 and Φ2 generated from the zero current detector 200 are applied to the switch control unit 400. The switch control unit 400 is connected to the zero current detector 200 and controls at least one switch based on the switching pulse signal and a set step-up ratio. For example, the switching pulse signals (Φ1, Φ2) are received and decoded, one step-up ratio among a plurality of step-up ratios is set according to the step-up ratio setting signal (MODE), and a three-stage circuit (100) is performed according to the set step-up ratio. ) generates a switching control signal (SW) to operate.

Below, the three-stage circuit 100 and the zero current detector 200 will be described in more detail.

Figure 3 is for explaining the operation of each stage included in the three-stage circuit.

Referring to FIG. 3, in the section Φ1 where the pair of first switches SW1 are turned on, the upper level voltage VH is charged in the capacitor. Next, in the section Φ2 where the pair of second switches SW2 are turned on, the lower level voltage VL is charged in the capacitor. As a result, due to charge sharing due to charging of the upper level voltage (VH) and lower level voltage (VL), the output voltage of the other end of the inductor is 1/2 of the sum of the upper level voltage (VH) and lower level voltage (VL). It is decided. Each stage of the three-stage circuit 100 changes the output voltage to the upper level voltage (VH) according to the charging of the capacitor according to the switching operation of the pair of first switches (SW1) and the pair of second switches (SW2) described above. It outputs as 1/2 of the sum of the and low level voltage (VL).

Based on the operation of each stage described above, the three-stage circuit 100 performs a transforming operation according to a set step-up ratio.

FIGS. 4A to 4E are for explaining the operation of the three-stage circuit according to each step-up ratio. Since the element values of each element included in the three-stage circuit 100 shown in FIGS. 4A to 4E are merely designed to transform voltage at a set step-up ratio, the embodiments of the present invention are not limited thereto.

Referring to FIG. 4A, for example, when the step-up ratio is set to 0.375V _IN (where V _IN is the input voltage), the first stage circuit 110a outputs 1/2 of the input voltage and ground as the output voltage. Output 0.5V _IN to the output terminal. The second stage circuit 110b receives the upper level voltage (VH) as V _IN and the lower level voltage (VL) as the output voltage (Vint1) of the first stage circuit (110a), and the input voltage and the first stage Since 1/2 of the output voltage (Vint1) of the circuit 110a is output as the output voltage, 0.75V _IN is output to the output terminal. The third stage circuit 110c receives the upper level voltage (VH) as the output voltage (Vint2) of the second stage circuit 110b and the lower level voltage (VL) as the ground, and 1/2 of the input voltage and the ground. Since 2 is output as the output voltage, 0.375V _IN is finally output.

Referring to FIG. 4b, for example, when the step-up ratio is set to 0.5V _IN , the first stage circuit 110a outputs 1/2 of the input voltage and ground as the output voltage, and thus outputs 0.5V _IN to the output terminal. The second stage circuit 110b receives the upper level voltage (VH) as V _IN and the lower level voltage (VL) as ground, and outputs 1/2 of the input voltage and ground as the output voltage, so 0.5V _IN It is output to the output terminal. The third stage circuit 110c receives the upper level voltage (VH) as V _IN and the lower level voltage (VL) as ground, and outputs 1/2 of the input voltage and ground as the output voltage, so the final voltage is 0.5V. Output _IN .

Referring to FIG. 4C, for example, when the step-up ratio is set to 0.625V _IN , the first stage circuit 110a outputs 1/2 of the input voltage and ground as the output voltage and thus outputs 0.5V _IN to the output terminal. The second stage circuit 110b receives the upper level voltage (VH) as the output voltage (Vint1) of the first stage circuit 110a and the lower level voltage (VL) as the ground, and 1/2 of the input voltage and the ground. Since 2 is output as the output voltage, 0.25V _IN is output to the output terminal. The third stage circuit 110c receives the upper level voltage (VH) as V _IN and the lower level voltage (VL) as the output voltage (Vint2) of the second stage circuit (110b), and the input voltage and ground 1 Since /2 is output as the output voltage, 0.625V _IN is ultimately output.

Referring to FIG. 4D, for example, when the step-up ratio is set to 0.75V _IN , the first stage circuit 110a outputs 1/2 of the input voltage and ground as the output voltage, and thus outputs 0.5V _IN to the output terminal. The second stage circuit 110b receives the upper level voltage (VH) as V _IN and the lower level voltage (VL) as ground, and outputs 1/2 of the input voltage and ground as the output voltage, so 0.5V _IN It is output to the output terminal. The third stage circuit 110c receives the upper level voltage (VH) as V _IN and the lower level voltage (VL) as the output voltage (Vint2) of the second stage circuit (110b), and the input voltage and ground 1 Since /2 is output as the output voltage, 0.75V _IN is ultimately output.

Referring to FIG. 4e, for example, when the step-up ratio is set to 0.875V _IN , the first stage circuit 110a outputs 1/2 of the input voltage and ground as the output voltage, and thus outputs 0.5V _IN to the output terminal. The second stage circuit 110b receives the upper level voltage (VH) as V _IN and the lower level voltage (VL) as the output voltage (Vint1) of the first stage circuit (110a), and the input voltage and ground 1 Since /2 is output as the output voltage, 0.75V _IN is output to the output terminal. The third stage circuit 110c receives the upper level voltage (VH) as V _IN and the lower level voltage (VL) as the output voltage (Vint2) of the second stage circuit (110b), and the input voltage and ground 1 Since /2 is output as the output voltage, 0.875V _IN is finally output.

Figure 5 shows a specific circuit diagram of the zero current detector.

Referring to FIG. 5, the zero current detector 200 includes a comparator 210, a digital signal control unit 220, and a delay adjuster 230.

The comparator 210 compares the voltage (hereinafter, also referred to as Vx) of one end of the inductor of the third stage circuit 110c between a first time point and a second time point after the first time point, and outputs the comparison result. Here, the first point in time may be referred to as the past point in time for convenience, and the second point in time may also be referred to as the present point in time. Based on the comparator 210 comparing Vx between different times, it can be determined whether the off time of the switched capacitor is slow or fast.

Specifically, the comparator 210 receives Vx as input, and receives Vx as is at the negative input terminal and receives input through a switching operation at the positive input terminal. The switch connected to the positive input terminal performs a switching operation in accordance with the off point (T _ON,end ) of the switched capacitor circuit, and causes the voltage corresponding to the first point of Vx to be applied to the positive input terminal. Additionally, a voltage corresponding to the second point in time of Vx is applied to the negative input terminal. The voltage corresponding to the second time point, that is, the voltage of Vx at the current time point, may be sampled by the clock signal (ZCD _CLK ).

The comparator 210 determines that the off time is early when the voltage corresponding to the first time point is greater than the voltage corresponding to the second time point, and when the voltage corresponding to the first time point is smaller than the voltage corresponding to the second time point, the comparator 210 determines that the off time is early. The off point is judged to be slow. The comparator 210 transmits the judgment result according to the judgment to the digital signal control unit 220.

The digital signal control unit 220 controls a digital signal to control the off point based on the comparison result. For example, the digital signal control unit 220 may be implemented as a bi-directional shift register, but is not limited thereto.

The digital signal control unit 220 generates a digital signal for controlling the delay at the off point. For example, if the off point is determined to be fast, it increases the digital signal for controlling the off point by 1 bit, and when the off point is determined to be fast, the digital signal for controlling the off point is slow. If it is determined that this is the case, the digital signal can be downgraded by 1 bit.

The delay control unit 230 adjusts the delay at the off point based on the digital signal. Specifically, the delay control unit 230 first inputs the ON point (T _ON,start ) identified from the comparator 300 as the set (S) signal of the SR latch, and turns on at least one switch based on the output result. Set the preceding delay (Predefined DL(delay)) defined on the time axis from the starting point.

Figure 6 is for explaining the delay controlled by the delay control unit.

As shown in FIG. 6, the delay control unit 230 sets a preceding delay defined from the time when I _L3 , which is the inductor current of L3 described above, increases from 0, that is, the time when it is turned on. Thereafter, the delay control unit 230 adjusts the adjustable delay (Adaptive DL), which is defined as the time from the end of the preceding delay to the off time, based on the digital signal.

Based on the operations of the zero current detector 200 described above, the current I _L3 of the inductor of the third stage circuit 110c may be controlled to correspond to the point at which the current becomes zero.

Figures 7a and 7b are for explaining the specific operation of the zero current detector.

Referring to FIG. 7A, the zero current detector 200 sets an advance delay from the on time as described above, and then determines whether the off time does not coincide with the time when I _L3 becomes zero current. For example, as shown in Figure 7a, when the Vx voltage at the off point (T _ON,end ) is greater than the Vx voltage of ZCD _CLK , the zero current detector 200 determines that the off point is early (short) and generates a digital signal. Increase the delay by 1-bit up. This is because when the off time is fast, switching ends when I _L3 is positive and the voltage of Vx drops due to the properties of the inductor.

For example, as shown in Figure 7b, when the Vx voltage at the off point (T _ON,end ) is smaller than the Vx voltage of ZCD _CLK , the zero current detector 200 determines that the off point is slow (long) and generates a digital signal. Reduce the delay by increasing 1-bit. This is because when the off point is slow, switching ends when I _L3 is negative and the voltage of Vx rises due to the properties of the inductor.

Figure 8 shows simulation results of the DC-DC converter of the present invention.

Referring to FIG. 8, as described above, according to the DC-DC converter 10 according to various embodiments of the present invention, Vx of the third stage circuit 110c increases with time in the zero current detector 200. Since it is controlled by , it can be seen that the voltage drop level gradually decreases in the on section of the switching pulse. Additionally, it can be seen that the optimal switching pulse width is adjusted as the width of the switching pulse gradually increases.

According to the various embodiments of the present invention described above, converter operation can be performed using resonance by integrating passive elements, such as inductors and capacitors, into a chip, resulting in higher efficiency compared to the existing switched capacitor DC-DC converter 10. It can have over output power density. In addition, compared to the existing switched capacitor DC-DC converter 10, it can operate with a larger number of step-up ratios, so it can operate efficiently over a wider range. Additionally, transmission loss can be reduced by detecting when zero current flows in the inductor and adjusting the off point to the point of zero current.

Below, the operating method of the above-described DC-DC converter 10 will be described. Detailed description of parts that overlap with the above description will be omitted.

Figure 9 is a flowchart of a method of operating a DC-DC converter according to an embodiment of the present invention.

Referring to FIG. 9, in S110, the DC-DC converter 10 outputs the input voltage as an output voltage corresponding to the set step-up ratio.

In S120, the DC-DC converter 10 controls the off time of at least one switch included in the three stage circuit 100 to correspond to the time when the current of the inductor of the third stage circuit 110c becomes zero current. .

Figure 10 is a flowchart of a method of operating a zero current detector according to an embodiment of the present invention.

Referring to FIG. 10, in S210, the zero current detector 200 compares the voltage of one end of the inductor of the third stage circuit 110c between the first time point and the second time point and outputs the comparison result.

In S220, the zero current detector 200 controls a digital signal to control the off point based on the comparison result.

In S230, the zero current detector 200 adjusts the delay at the off point based on the digital signal.

It is clear that examples of the proposed method in the above description can also be included as one of the implementation methods of the present invention, and thus can be regarded as a type of proposed method. Additionally, the proposed methods described above may be implemented independently, but may also be implemented in the form of a combination (or merge) of some of the proposed methods.

Claims (10)

A three-stage circuit that outputs the input voltage as an output voltage corresponding to the set step-up ratio,
Here, the three-stage circuit is sequentially connected and includes a first to third stage circuit each including a switched capacitor circuit and an inductor whose one end is connected to the switched capacitor circuit and the other end is connected to an output node; and
Comprising a zero current detector that controls the off point of at least one switch included in the switched capacitor circuit to correspond to the point in time when the current of the inductor of the third stage circuit becomes zero current,
DC-DC converter.
According to paragraph 1,
The switched capacitor circuit outputs a voltage corresponding to half of the upper level voltage and the lower level voltage applied to the switched capacitor circuit according to the switching operation as the output voltage of each of the first to third stage circuits,
DC-DC converter.
According to paragraph 2,
The upper level voltage applied to the first stage circuit is the input voltage, and the lower level voltage is ground,
The higher level voltage applied to the second stage circuit is the input voltage or the output voltage of the first stage circuit, and the lower level voltage is the ground or the output voltage of the first stage circuit,
The upper level voltage applied to the third stage circuit is the input voltage or the output voltage of the second stage circuit, and the lower level voltage is the ground or the output voltage of the second stage circuit,
DC-DC converter.
According to paragraph 1,
The zero current detector includes a comparator that compares the voltage of one end of the inductor of the third stage circuit between a first time point and a second time point after the first time point and outputs a comparison result;
a digital signal control unit that controls a digital signal to control the off point based on the comparison result; and
Comprising a delay control unit that adjusts the delay at the off point based on the digital signal,
DC-DC converter.
According to paragraph 4,
The comparator determines that the off time is earlier when the voltage corresponding to the first time point is greater than the voltage corresponding to the second time point, and the voltage corresponding to the first time point is greater than the voltage corresponding to the second time point. If the off point is small, it is judged to be slow,
DC-DC converter.
According to clause 5,
The digital signal control unit increases the digital signal for controlling the off point by 1 bit when it is determined that the off point is fast, and downs the digital signal by 1 bit when it is determined that the off point is slow.
DC-DC converter.
According to paragraph 4,
The delay adjuster sets a leading delay defined on the time axis from the on point of the at least one switch, and adjusts an adjustable delay defined from the leading delay to the off point based on the digital signal,
DC-DC converter.
According to paragraph 4,
Further comprising a switch control unit connected to the zero current detector and controlling the at least one switch based on the switching pulse signal generated based on the digital signal and the step-up ratio,
DC-DC converter.
An operating method performed by a DC-DC converter including a three-stage circuit including a first stage circuit to a third stage circuit and a zero current detector, comprising:
Outputting the input voltage as an output voltage corresponding to the set step-up ratio; and
Comprising the step of controlling the off point of at least one switch included in the three stage circuit to correspond to the point in time when the current of the inductor of the third stage circuit becomes zero current,
How a DC-DC converter works.
According to clause 9,
Comparing the voltage of one end of the inductor of the third stage circuit between a first time point and a second time point after the first time point, and outputting a comparison result;
controlling a digital signal for controlling the off point based on the comparison result; and
Further comprising adjusting the delay at the off point based on the digital signal,
How a DC-DC converter works.

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