KR102598015B1 - Content Addressable Memory and Match Line Sense Amplifier Therefor - Google Patents

Abstract

The present invention divides the power supply voltage and the match line in response to a precharge bar signal that is activated at a low level in the precharge phase of a search operation consisting of a precharge phase and a search phase and deactivated at a high level before the search phase. A precharge unit connecting the first and second match lines, respectively, connected between the power supply voltage and the first node, and independently applying the power supply voltage to the first node in response to the voltage levels of each of the first and second match lines. It is connected between a match detection unit and a first node and an output node and an output node and a ground voltage, and is connected to the first node and an output node or an output node and a ground voltage in response to a precharge signal having an opposite phase to the precharge bar signal. Energy consumption can be reduced by including a selectively connected output unit, and a CAM that enables high-speed search and a matchline sense amplifier for this are provided.

Description

{Content Addressable Memory and Match Line Sense Amplifier Therefor}

The present invention relates to a NOR-type content-addressable memory and a matchline sense amplifier therefor, and to a NOR-type content-addressable memory that can improve search speed while reducing power consumption and a matchline sense amplifier therefor.

Content addressable memory (hereinafter referred to as CAM) is a memory that has a plurality of CAM cells to store data. It refers to a memory configured to accept data as input and output an address where the approved data is stored. CAM is used in a variety of applications that require high-speed search, such as search engines in network routers, image processing, or neural networks.

In addition, CAM is a memory that searches memory cells where the authorized data is stored and outputs addresses. Multiple CAM cells perform searches in different operation methods depending on the connected form of the match line, and are divided into NAND type and NOR type depending on the search operation method. It is divided into

Figure 1 is a diagram for explaining the CAM cell connection configuration and search operation of a NAND type CAM.

As shown in Figure 1, in the case of the NAND type, a plurality of CAM cells (Cells) are connected in series on a match line (ML), and each of the plurality of CAM cells (Cells) connected in series corresponds to the applied data. It turns on/off depending on the bit value and operates as a switch that electrically connects the match lines (ML) connected to both sides. And the sensing units (SE) are distributed on both sides of the match line (ML). The sensing unit (SE) includes a precharge transistor (PT) connected to one side of the match line (ML) and a discharge transistor (DT) connected to the other side.

In NAND type CAM, the search operation consists of a precharge phase and a match evaluation phase. In the precharge phase, the precharge bar signal (PREB) is activated to the ground voltage level. As the precharge bar signal (PREB) is activated to the ground voltage level, the precharge transistor (PT) is turned on in response to the precharge bar signal (PREB), and the discharge transistor (DT) is turned on in response to the precharge bar signal (PREB). It turns off in response.

The turned-on precharge transistor (PT) pulls up one side of the connected match line (ML) to the power supply voltage (V _DD ) level. On the other hand, the turned-off discharge transistor (DT) blocks the connection between the other side of the match line (ML) and the ground voltage. In other words, the dispose transistor (DT) floats the other side of the match line (ML). At this time, match lines (ML) arranged between adjacent CAM cells (Cells) are also in a floating state.

In the subsequent search stage, the precharge bar signal (PREB) is deactivated at the power supply voltage (V _DD ) level, which has a voltage level higher than the ground voltage. Accordingly, the precharge transistor (PT) is turned off and the discharge transistor (DT) is turned on. As the dispose transistor (DT) is turned on, the other side of the match line (ML) is pulled down to the ground voltage level.

Additionally, in the search step, each bit value of data to be searched is applied to each corresponding CAM cell in a plurality of CAM cells. Accordingly, each of the multiple CAM cells is turned on when the applied bit value and the pre-stored bit value match (M) and electrically connect the match lines (ML) on both sides, whereas when the bit value is mismatched (mismatch), each of the multiple CAM cells turns on. , it turns off and blocks the connection between the match lines (ML) of both sides. Therefore, if all bit values of the data to be searched are identical and match the bit values stored in multiple CAM cells (Cells) connected to the corresponding match line (ML), the precharged voltage on one side of the match line (ML) is dissipated. It is pulled down to ground voltage through a terminal transistor (DT). Accordingly, the match line sensing output (MLSO) output from one side of the match line (ML) becomes the ground voltage level and is output as a value of "0".

On the other hand, if a mismatch occurs because the bit value stored in at least one CAM cell among multiple CAM cells is different from the applied bit value, a mismatch occurs in the CAM cell in which the mismatch occurred. As the electrical connection of the match line (ML) is cut off, one side of the match line (ML) maintains the precharged voltage level, and the match line sensing output (MLSO) is set to "1", which is the ground voltage (V _DD ) level. It is output as a value.

Figure 2 is a diagram for explaining the CAM cell connection configuration and search operation of a NOR type CAM.

In the case of NOR type CAM, unlike NAND type CAM, multiple CAM cells are connected in parallel on a match line (ML). Each of the multiple CAM cells connected in parallel turns on/off according to the corresponding bit value of the applied data and operates as a switch that electrically connects the match line (ML) and the ground voltage. And in the NOR type CAM, the sensing unit (SE) is connected to one side of the match line (ML). The sensing unit (SE) includes a precharge transistor (PT) and an inverter (INV).

In NOR type CAM, the search operation also consists of a precharge stage and a search stage, and in the precharge stage, the precharge bar signal (PREB) is activated at the ground voltage level. Accordingly, the precharge transistor (PT) is turned on in response to the precharge bar signal (PREB) to pull up the match line (ML) to the power voltage (V _DD ) level. In NOR type CAM, the match line (ML) is not disconnected by the CAM cell (Cell), so the entire match line (ML) is precharged to the power supply voltage (V _DD ) level.

In the subsequent search step, the precharge bar signal (PREB) is deactivated at the power supply voltage (V _DD ) level, and the precharge transistor (PT) is turned off in response to the precharge bar signal (PREB). And each bit value of the data to be searched is applied to each corresponding CAM cell in the plurality of CAM cells. Each of the multiple CAM cells (Cells) is turned off when the applied bit value matches the pre-stored bit value (M), independently blocking the electrical connection between the match line (ML) and the ground voltage, while the bit value is turned off. If there is a mismatch, it is turned on and electrically connects the match line (ML) and the ground voltage. Therefore, if at least one bit value of the data to be searched mismatches the bit value stored in a plurality of CAM cells connected to the corresponding match line (ML), the match line (ML) mismatches. It is pulled down to ground voltage through the CAM cell (Cell), and the inverter (INV) connected to one side of the match line (ML) inverts the voltage level of the match line (ML) and sets the match line sensing output (MLSO) to "1. Outputs the value of ".

On the other hand, if all bit values stored in multiple CAM cells match all bit values of the applied data, all CAM cells connected to the corresponding match line (ML) are between the match line (ML) and the ground voltage. Since it electrically blocks the connection, the match line (ML) maintains the precharged power supply voltage (V _DD ) level. Accordingly, the inverter (INV) inverts the voltage level of the match line (ML) and outputs the match line sensing output (MLSO) as a value of “0”.

As a result, for both NAND type and NOR type CAM, the match line sensing output is output from the match line (ML) of the row depending on whether the data stored in the multiple CAM cells of the CAM array matches the applied data row by row. (MLSO) is output as different values, allowing the matched address to be accurately identified.

However, in NAND type CAM, the current of the match line (ML) is configured to flow to the ground voltage only when all CAM cells connected to the same match line (ML) are matched. Therefore, the NAND type has the advantage of low energy consumption because current does not flow even if a mismatch occurs in only one cell. However, as the discharge path of the match line (ML) is configured in series, each bit of data is searched sequentially, so search is possible. The downside is that it is slow.

On the other hand, in NOR type CAM, even if a mismatch occurs in only one CAM cell among multiple CAM cells connected to the match line (ML), current flows and a change in the voltage level of the match line (ML) occurs, enabling fast search speed. However, in a CAM including a cell array in which multiple CAM cells are arranged, a mismatch occurs in most match lines (ML) and current flows, so there is a problem that the energy consumed is very large.

In other words, since both NAND type and NOR type CAM have advantages and disadvantages, NAND type or NOR type is selectively used depending on the purpose of CAM utilization. However, recently, not only has the amount of data to be searched increased, but also the number of bits of data that must be determined to match has increased, leading to a continued demand for CAM that can perform searches at high speed while reducing power consumption.

Korean Registered Patent No. 10-1557926 (registered on September 30, 2015)

The purpose of the present invention is to provide a CAM capable of reducing energy consumption and a matchline sense amplifier for the same.

Another object of the present invention is to provide a CAM capable of performing a faster search in a NOR CAM capable of high-speed search and a matchline sense amplifier therefor.

In order to achieve the above object, the matchline sense amplifier for CAM according to an embodiment of the present invention is activated at a low level in the precharge phase of a search operation consisting of a precharge phase and a search phase, and is activated at a high level before the search phase. a precharge unit connecting the power supply voltage and the first and second match lines, respectively, in response to the precharge bar signal being deactivated at the level; a match detection unit connected between the power voltage and a first node and independently applying the power voltage to the first node in response to the voltage levels of each of the first and second match lines; and connected between the first node and the output node and the output node and the ground voltage, and in response to a precharge signal having an opposite phase to the precharge bar signal, the first node and the output node or the output node and the It includes an output unit that selectively connects to ground voltage.

The precharge unit includes a first precharge transistor connected between the power supply voltage and the first match line and to which the precharge bar signal is applied to a gate; and a second precharge transistor connected between the power voltage and the second match line and receiving the precharge bar signal as a gate.

The match detection unit includes a first match transistor connected between a first node between the power voltages and a gate connected to the first match line; and a second match transistor connected in parallel with the first match transistor between the first nodes between the power voltages and the gate connected to the second match line.

The output unit includes a first output transistor connected between the first node and the output node and receiving the precharge signal as a gate; and a second output transistor connected between the output node and the ground voltage, to which the precharge signal is applied to a gate.

The CAM has a plurality of CAM cells connected in parallel between the corresponding match lines among the first and second match lines and the corresponding source lines among the first and second source lines dividing the source lines, and a word line. It is activated according to the voltage level applied through the bit line pair in the search step and is implemented as a NOR type CAM that electrically connects the corresponding match line and the corresponding source line depending on whether the bit value applied through the bit line pair matches the stored bit value. It can be.

The matchline sense amplifier includes an inverter whose input terminal is connected to the output node; and a discharge unit connecting the first and second source lines to the ground voltage in response to the output of the inverter.

The discharge unit includes a first discharge transistor connected between the first source line and the ground voltage and whose gate is connected to the output terminal of the inverter; and a second discharge transistor connected between the second source line and the ground voltage, and whose gate is connected to the output terminal of the inverter in common with the first discharge transistor.

A CAM according to another embodiment of the present invention for achieving the above object includes a plurality of match lines extending in a first direction, a plurality of word lines, and a plurality of bit line pairs extending in a second direction perpendicular to the first direction. A number of CAM cells defined by; and a corresponding match line among the plurality of match lines is connected between the divided first and second match lines to precharge the first and second match lines, and a bit of data applied to the plurality of bit line pairs. A plurality of match line sense amplifiers detecting a voltage drop of a match line that occurs depending on whether there is a match between the value and the bit value stored in the corresponding CAM cells, each of the plurality of match line sense amplifiers performing a precharge stage and a search operation. In response to a precharge bar signal that is activated at a low level in the precharge step of the search operation consisting of steps and deactivated at a high level before the search step, the power supply voltage and the first and second match lines are respectively connected to the first and second match lines. A precharge unit that precharges the first and second match lines; a match detection unit connected between the power voltage and a first node and independently applying the power voltage to the first node in response to the voltage levels of each of the first and second match lines; and connected between the first node and the output node and the output node and the ground voltage, and in response to a precharge signal having an opposite phase to the precharge bar signal, the first node and the output node or the output node and the It includes an output unit that selectively connects to ground voltage.

Therefore, in the CAM according to an embodiment of the present invention and the match line sense amplifier for the same, the match line is not connected to one side, but the match line is divided into two, and the divided match lines are connected on both sides to prevent mismatch in each of the divided match lines. Not only can energy consumption be reduced by allowing currents to individually flow to ground, but power consumption for precharge can also be reduced by allowing divided match lines to be individually precharged. In addition, the division of the match line reduces the number of CAM cells connected to the divided match line, enabling high-speed operation due to low capacitance. In addition, even if a mismatch occurs in all divided match lines, the voltage level of each match line is prevented from dropping to the ground voltage level, thereby further reducing power consumption for precharge.

Figure 1 is a diagram for explaining the CAM cell connection configuration and search operation of a NAND type CAM.
Figure 2 is a diagram for explaining the CAM cell connection configuration and search operation of a NOR type CAM.
Figure 3 shows an example of a CAM including a matchline sense amplifier according to an embodiment of the present invention.
Figure 4 shows an example of the CAM cell of Figure 3.
FIG. 5 is a diagram for explaining the precharge operation of the CAM of FIG. 3.
FIG. 6 shows a timing diagram for explaining the precharge operation of the CAM of FIG. 5.
FIG. 7 is a diagram for explaining the initial operation of the CAM search step of FIG. 3.
FIG. 8 shows a timing diagram for explaining the initial operation of the search step of the CAM of FIG. 7.
FIG. 9 is a diagram for explaining the CAM search step of FIG. 3.
FIG. 10 shows a timing diagram for explaining the search step of the CAM of FIG. 9.

In order to fully understand the present invention, its operational advantages, and the objectives achieved by practicing the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, the present invention will be described in detail by explaining preferred embodiments of the present invention with reference to the accompanying drawings. However, the present invention may be implemented in many different forms and is not limited to the described embodiments. In order to clearly explain the present invention, parts that are not relevant to the description are omitted, and the same reference numerals in the drawings indicate the same members.

Throughout the specification, when a part "includes" a certain element, this does not mean excluding other elements, unless specifically stated to the contrary, but rather means that it may further include other elements. In addition, terms such as "... unit", "... unit", "module", and "block" used in the specification refer to a unit that processes at least one function or operation, which is hardware, software, or hardware. and software.

Figure 3 shows an example of a CAM including a matchline sense amplifier according to an embodiment of the present invention.

In the CAM according to this embodiment, a plurality of CAM cells are each connected in parallel to a match line (ML). That is, the CAM according to this embodiment basically has a NOR type CAM structure.

Referring to FIG. 3, a plurality of CAM cells (Cells) correspond to a corresponding match line (ML) among a plurality of match lines extending in the first direction in the CAM cell array and a corresponding match line (ML) among a plurality of source lines extending in the first direction. It is connected in parallel between the source lines (ScL). Additionally, a plurality of CAM cells (Cells) are connected to a corresponding word line (WL) among a plurality of word lines extending in the first direction along with the match line (ML) and the source line (ScL). Additionally, a plurality of CAM cells (Cells) are connected to corresponding bit line pairs among a plurality of bit line pairs (BLB/BL) extending in a second direction perpendicular to the first direction.

Here, the word line (WL) is activated according to the address applied along with the data to activate a plurality of CAM cells (Cells) connected to the corresponding match line (ML). In other words, the word line (WL) performs the function of selecting and activating a number of CAM cells (Cells) in the CAM cell array on a row-by-row basis. And the multiple bit line pairs (BLB/BL) transmit the corresponding bit values from the applied data to each of the multiple CAM cells (Cells). That is, the multiple bit line pairs (BLB/BL) perform the function of transmitting bit values according to data to each of the multiple CAM cells (Cells) activated in row units by the word line (WL).

In the NOR type CAM of FIG. 2, it is explained that a plurality of CAM cells are connected in parallel between the match line (ML) and the ground voltage. However, CAM cells can be implemented using CMOS, a volatile device, or MTJ (Magnetic Tunnel Junction) or ReRAM (Resistive RAM), which are non-volatile devices, as well as using ferroelectric transistor (Ferroelectric FET) devices. It can be. FeFET devices have excellent compatibility with CMOS circuits, and compared to other existing non-volatile memories, they have a high ON/OFF ratio (10 ¹⁵ ), fast write speed (10 ns), and excellent durability (10 ¹⁰ cycle) and low write power consumption, showing excellent performance. In addition, the 3 terminal structure of source-gate-drain has a very low possibility of read/write failure due to different read/write paths, and has the advantage of simple write circuit structure, which has been actively researched as a memory device in recent years. there is.

As such, the CAM cell can be implemented using various devices such as CMOS devices, MTJ devices, ReRAM devices, and FeFET devices, and depending on the device configuration of the CAM cell, the CAM cell array is shown in FIG. 3. As described above, not only the match line (ML) but also the source line (ScL) may be further arranged. However, as mentioned above, the source line (ScL) may be omitted depending on the element configuration of the CAM cell (Cell). In this case, each of the multiple CAM cells (Cell) has a voltage between the corresponding match line (ML) and the ground voltage. can be connected in parallel.

In addition, multiple word lines and multiple bit line pairs are the basic configuration of a CAM cell array. In FIG. 2, word lines (WL) and multiple bit line pairs (BLB/BL) are omitted for convenience of explanation, but in FIG. 3, the word lines (WL) and multiple bit line pairs (BLB/BL) are omitted. It is indicated to clearly explain the operation of the sense amplifier (SA).

Also, although not shown, depending on the structure of the CAM cell, the bit value of the data to be stored in the CAM cell is a bit value stored in the CAM cell separately from the bit line pair (BLB/BL) to which it is applied. A plurality of search line pairs (SL/SLB) to which bit values of search data are applied to compare whether or not a match may be further provided. The plurality of search line pairs (SL/SLB) may be formed separately from the plurality of bit line pairs (BLB/BL) in a pattern extending in the second direction. Here, it is assumed that the bit value of the search data is also applied to the corresponding CAM cell (Cell) through multiple bit line pairs (BLB/BL), so the multiple search line pairs (SL/SLB) are omitted.

Meanwhile, in this embodiment, the sense amplifier (SA) is connected between the match lines (ML). That is, in this embodiment, the match line ML is divided into first and second match lines ML and connected to both sides of the sense amplifier SA. And, corresponding to the match line (ML) divided into the first and second match lines (ML), the source line (ScL) is also divided into the first and second source lines (ScL1, ScL2) to be connected to both sides of the sense amplifier (SA). connected to

And, according to the divided first and second match lines (ML) and first and second source lines (ScL1, ScL2), the corresponding plurality of CAM cells (Cells) can also be divided into first and second cell groups. . Here, as an example, it is assumed that 64 CAM cells (Cell ₀ to Cell ₆₃ ) are connected in parallel to each matchline (ML), of which 32 CAM cells (Cell ₀ to Cell ₃₁ ) are divided into the first cell group. , it is assumed that the remaining 32 CAM cells (Cell ₀ to Cell ₃₁ ) are divided into a second cell group. Here, it is desirable for the same number of CAM cells (Cells) to be placed on both sides of the sense amplifier (SA) for equal operation.

Referring to FIG. 3, the sense amplifier (SA) according to this embodiment includes two precharge transistors (PT1, PT2), two match transistors (MT1, MT2), two output transistors (OT1, OT2), and two Includes discharge transistors (DT1, DT2) and inverter (INV).

First, the two precharge transistors (PT1, PT2) are respectively connected between the power supply voltage (V _DD ) and the corresponding match line among the divided first and second match lines (ML1, ML2). The first precharge transistor (PT1) is connected between the power supply voltage (V _DD ) and the first match line (ML1), and the second precharge transistor (PT2) is connected between the power supply voltage (V _DD ) and the second match line (ML2). ) can be implemented with a PMOS transistor connected between the The first and second precharge transistors (PT1, PT2) receive the precharge bar signal (PREB) through the gate, and are activated according to the level of the applied precharge bar signal (PREB) to generate the first and second match lines ( Precharge by pulling up ML1 and ML2) to the power supply voltage (V _DD ) level, respectively. The CAM search operation according to this embodiment may be comprised of a precharge step and a search step, and the precharge bar signal (PREB) is applied at a low level (e.g., ground voltage level) in the precharge step to connect the first and While the second precharge transistors PT1 and PT2 are activated, in the search step, a high level (eg, power supply voltage level) is applied to deactivate the first and second precharge transistors PT1 and PT2.

Meanwhile, the two match transistors (MT1, MT2) are connected in parallel between the power supply voltage (V _DD ) and the first node (Nd1), and each gate is connected to a corresponding match line of the two match lines (ML1, ML2). It can be implemented with a PMOS transistor connected to . The first match transistor MT1, whose gate is connected to the first match line ML1, applies the power voltage V _DD to the first node Nd1 according to the voltage level of the first match line ML1, and the gate is The second match transistor MT2 connected to the second match line ML12 applies the power supply voltage V _DD to the first node Nd1 according to the voltage level of the second match line ML2. Therefore, when the voltage level of at least one of the first and second match lines ML1 and ML2 falls below a certain level, the two match transistors MT1 and MT2 change the power supply voltage V _DD to the first It is applied to the node (Nd1). That is, the two match transistors MT1 and MT2 operate as sensing transistors that sense the voltage levels of the two match lines ML1 and ML2 and adjust the voltage level of the first node Nd1.

Two output transistors (OT1, OT2) are connected in series between the first node (Nd1) and the ground voltage, and each receives a precharge signal (PRE) through its gate. Here, the precharge signal (PRE) is a signal that has a phase opposite to the precharge bar signal (PREB), and may have a high level in the precharge stage and a low level in other times.

Among the two output transistors (OT1, OT2), the first output transistor (OT1) connected between the first node (Nd1) and the second node (Nd2) is implemented as a PMOS transistor, and the second node (Nd2) and the ground voltage The second output transistor OT2 connected therebetween may be implemented as a PMOS transistor. Since the first output transistor OT1 is implemented as a PMOS transistor and the second output transistor OT2 is implemented as a PMOS transistor, the first output transistor OT1 is turned off in the precharge stage and the first node Nd1 While the voltage is not applied to the second node (Nd2), it is turned on in the search phase so that the voltage of the first node (Nd1) is applied to the second node (Nd2).

Meanwhile, the second output transistor OT2 is turned on in the precharge phase to pull down the voltage level of the second node Nd2 to the ground voltage level, and is turned off in the search phase so that the voltage level of the second node Nd2 is pulled down to the ground voltage level. It is output as a matchline sensing output (MLSO). That is, in this embodiment, the second node (Nd2) is an output node where the match line sensing output (MLSO) of the sense amplifier (SA) is output.

The inverter INV is connected between the second node Nd2 and the third node Nd3 and inverts the voltage level of the second node Nd2, which is an output node, and applies it to the third node Nd3. Here, the inverter (INV) detects the match line sensing output (MLSO) and reflects it to the third node (Nd3).

The two discharge transistors (DT1, DT2) are each connected between the corresponding source line of the two source lines (ScL1, ScL2) and the ground voltage, and the gate is the third node (Nd3) to which the output of the inverter (INV) is connected. are commonly connected to Accordingly, the two discharge transistors (DT1, DT2) are turned on or off in response to the output of the inverter (INV) to drop or maintain the voltage of the corresponding source lines (ScL1, ScL2). When the inverter (INV) outputs a high level, the first and second discharge transistors (DT1, DT2) are turned on and electrically connect the first and second source lines (ScL1, ScL2) and the ground voltage to discharge the first and second discharge transistors (DT1, DT2). The voltage level of the second source lines (ScL1, ScL2) is lowered, and when the inverter (INV) outputs a low level, it is turned off to block the connection between the first and second source lines (ScL1, ScL2) and the ground voltage. Thus, the first and second source lines ScL1 and ScL2 maintain voltage.

In Figure 3, the two precharge transistors (PT1, PT2) can be called the precharge section, the two match transistors (MT1, MT2) are the match detection section, the two output transistors (OT1, OT2) are the output section, and the two The discharge transistors (DT1, DT2) can be called discharge parts.

Here, the inverter (INV) and two discharge transistors (DT1, DT2) are components to further reduce the power consumption of the CAM, and may be omitted in some cases.

Figure 4 shows an example of the CAM cell of Figure 3.

FIG. 4 shows a ternary CAM (hereinafter referred to as TCAM) cell having a 2F2T configuration including two FeFETs (F1, F2) and two access transistors (T1, T2) as an example of a CAM cell. did.

CAM can be divided into binary CAM and ternary CAM (hereinafter referred to as TCAM) depending on the data storage method. The binary CAM is configured so that each CAM cell can store state information in one of two states: logic '1' state and logic '0' state. On the other hand, TCAM is configured to additionally store the logic '0' state and logic '1' state as well as the 'X' (don't care) state. TCAM has the advantage of providing flexibility in search by allowing the 'X' state to be additionally stored.

Referring to FIG. 4, in a TCAM cell constructed using FeFET, two FeFETs (F1, F2) are connected in parallel between the corresponding match line (ML) and the corresponding source line (ScL). And the two FeFETs (F1, F2) can be implemented as type II FeFETs.

FeFET has a relatively low threshold voltage state (Low V _TH State: LVT state) at a variable threshold voltage (V _TH ) when logic '1' is stored, and when logic '0' is stored, it has a variable threshold voltage state (V TH). Among the threshold voltages (V _TH ), it has a relatively high threshold voltage state (High V _TH State: hereinafter referred to as HVT state). At this time, unlike the general type I FeFET, where LVT has a negative voltage level and HVT has a positive voltage level, both LVT and HVT have a positive voltage level by using metal gate engineering during FeFET manufacturing. The type II FeFET can easily determine the state of the FeFET (F1, F2) by using the power supply voltage (V _DD ) having a voltage level between LVT and HVT.

Among the two access transistors (T1, T2), the first access transistor (T1) is connected between the gate of the first FeFET (F1) and the corresponding bit line bar (BLB), and the second access transistor (T2) is connected to the second access transistor (T2). It is connected between the gate of the FeFET (F2) and the corresponding bit line (BL). And the gates of the first and second access transistors T1 and T2 are commonly connected to the corresponding word line WL.

The two FeFETs (F1, F2) are in the LVT or HVT state by the voltage applied through the bit line pair (BLB/BL) depending on the data to be stored during the write operation, and the logic corresponding to the data is stored, and the search operation is performed. During light operation, the voltage level of the match line (ML) is adjusted by electrically connecting or blocking the match line (ML) and the source line (ScL) according to the LVT or HVT status set.

As described above, data '0', '1', and 'X (don' care)' may be stored in the TCAM cell. When data '0' is stored, the first FeFET (F1), whose gate is connected to the bit line bar (BLB) through the first access transistor (T1), has an LVT state corresponding to logic '1', and the gate is The second FeFET (F2) connected to the bit line (BL) has an HVT state corresponding to logic '0'. And when data '1' is stored, the first FeFET (F1) has an HVT state, and the second FeFET (F2) has an HVT state. Additionally, when data 'X' is stored, both the first and second FeFETs (F1, F2) are in the HVT state.

In addition, the gates of the two access transistors (T1, T2) are commonly connected to the word line (WL), and the gates of the two FeFETs (F1, F2) and the bit line pair are connected according to the voltage level applied to the word line (WL). By electrically connecting (BLB/BL), the TCAM cell is activated. The bit line bar (BLB) and bit line (BL) of the bit line pair (BLB/BL) are lines to which voltage corresponding to the data to be searched is applied during the search operation of the TCAM, and are the search line (SL) and search line, respectively. It can be called a bar (SLB), and the bit line pair (BLB/BL) can also be called a search line pair (SL/SLB).

In Figure 4, a TCAM cell implemented using FeFET is described as an example of a CAM cell. However, as described above, a CAM cell can be implemented using various devices such as a CMOS device, an MTJ device, a ReRAM device, and a FeFET device. .

Below, the CAM search operation according to this embodiment will be described step by step.

FIG. 5 is a diagram for explaining the precharge operation of the CAM of FIG. 3, and FIG. 6 is a timing diagram for explaining the precharge operation of the CAM of FIG. 5.

Referring to Figures 5 and 6, in the precharge stage, the word line (WL) is first activated and applied to a high level so that a plurality of CAM cells (Cell ₀ to Cell ₆₃ ) of the match line (ML) are selected. And the precharge bar signal (PREB) is applied at a low level, and the precharge signal (PRE) is applied at a high level. Accordingly, the first and second precharge transistors (PT1, PT2) are all turned on in response to the low level precharge bar signal (PREB), thereby turning the first and second match lines (ML1, ML2) to the power supply voltage (V _DD) , respectively. ) level to precharge, and the second output transistor OT2 is turned on in response to the high level precharge signal PRE to pull down the second node Nd2 to the ground voltage level.

At this time, the first and second match transistors (MT1, MT2) are turned off as the first and second match lines (ML1, ML2) are precharged to the power supply voltage (V _DD ) level, and the power supply voltage (V _DD ) The connection between the first node (Nd1) is blocked, and the second output transistor (OT2) closes the connection between the first node (Nd1) and the second node (Nd2) in response to the high level precharge signal (PRE). Block it. Since the voltage level of the second node (Nd2), which is an output node, is pulled down to the ground voltage level, the match line sensing output (MLSO) of the sense amplifier (SA) has a ground voltage level and is output as a value of "0".

Then, the inverter INV inverts the ground voltage level of the second node Nd2 and applies a high level voltage (here, the power supply voltage V _DD level) to the third node Nd3, and thus the first and second The discharge transistors DT1 and DT2 are turned on to pull down the first and second source lines ScL1 and ScL2 to the ground voltage level.

At this time, to prevent multiple CAM cells (Cell ₀ to Cell ₆₃ ) from connecting the match line (ML) and source line (ScL) regardless of the stored bit value, all bit line pairs (BLB/BL) have designated voltage levels. approved. Here, it is assumed that a plurality of CAM cells (Cell ₀ to Cell ₆₃ ) are implemented as the CAM cells shown in FIG. 4, and a ground voltage corresponding to “0” is applied to all bit line pairs (BLB/BL) to Ensure that none of the CAM cells (Cell ₀ to Cell ₆₃ ) connect the match line (ML) and source line (ScL).

Therefore, in the precharge stage, both the first and second match lines (ML1, ML2) are precharged to the power supply voltage (V _DD ) level, and the first and second source lines (ScL1, ScL2) are both at the ground voltage level. . Then, the second node (Nd2) becomes the ground voltage level and the match line sensing output (MLSO) outputs “0”, and the third node (Nd3) has the power supply voltage (V _DD ).

And before the precharge step ends, that is, right before the search step is performed, the precharge bar signal (PREB) transitions to a high level, and the precharge signal (PRE) transitions to a low level. Therefore, at the end of the precharge phase, the first and second precharge transistors PT1 and PT2 are turned off to block the connection between the power supply voltage V _DD and the first and second match lines ML1 and ML2. And the second output transistor OT2 is turned off to block the connection between the second node Nd2 and the ground voltage, while the first output transistor OT1 is turned on to connect the first node Nd1 and the second node ( Connect Nd2) electrically.

FIG. 7 is a diagram for explaining the initial operation of the CAM search step of FIG. 3, and FIG. 8 is a timing diagram for explaining the initial operation of the CAM search step of FIG. 7.

As mentioned above, the search operation of the CAM is largely divided into two stages, a precharge stage and a search stage, but in the present invention, the sense amplifier (SA) is further equipped with an inverter (INV) and two discharge transistors (DT1, DT2). So that the first and second match lines (ML1, ML2) and the first and second source lines (ScL1, ScL2) have a balanced voltage level (V _A ) between the power supply voltage (V _DD ) level and the ground voltage level. Therefore, in order to explain this easily, the initial operation of the search stage will be described separately by dividing it into a transition stage.

As shown in FIG. 8, the word line (WL) remains activated at a high level even during the search phase. And the bit value corresponding to the data to be searched is applied to the bit line pair (BLB/BL). If a bit value of "0" is to be applied, a ground voltage corresponding to logic '0' is applied to the bit line bar (BLB), and a power supply voltage (corresponding to logic '1') is applied to the bit line (BL). V _DD ) is applied. On the other hand, when a bit value of "1" is to be applied, the power supply voltage (V DD ) corresponding to logic '1' is applied to the bit line bar (BLB), and the power voltage (V _DD ) corresponding to logic '0' is applied to the bit line (BL). A corresponding ground voltage is applied.

Accordingly, among a number of CAM cells (Cell ₀ to Cell ₆₃ ), the CAM cells whose bit values applied to the bit line pair (BLB/BL) match the stored bit values are connected to the corresponding match lines (ML1, ML2) and the corresponding source line. Without connecting (ScL1, ScL2), the mismatched CAM cell connects the corresponding match lines (ML1, ML2) and the corresponding source lines (ScL1, ScL2). In Figure 7, assuming that a mismatch occurred in the first CAM cell (Cell ₀ ) among the plurality of CAM cells (Cell ₀ to Cell ₆₃ ), the first match line (ML1) and the first source line (ScL1) are connected. A case where this happens is shown.

And just before the search step starts, at the end of the precharge step, the precharge bar signal (PREB) has already transitioned to high level, and the precharge signal (PRE) has transitioned to low level, so that the first and second precharge transistors (PT1, PT2) and the second output transistor (OT2) are turned off, and the first output transistor (OT1) is turned on to electrically connect the first node (Nd1) and the second node (Nd2). .

Therefore, since the two discharge transistors (DT1, DT2) are already turned on in the precharge stage, and the voltage level of the second node (Nd2) has not changed, the two discharge transistors (DT1, DT2) are in a transition state. Even in this stage, it is still turned on, and therefore the first and second source lines ScL1 and ScL2 are connected to the ground voltage.

Therefore, among the first and second match lines (ML1, ML2), the first match line (ML1) is electrically connected to the ground voltage through the first CAM cell (Cell ₀ ) in which the mismatch occurred and the first source line (ScL1). When connected, the precharged power voltage level of the first match line ML1 begins to drop. However, since no mismatch occurred in the plurality of CAM cells (Cell ₃₂ to Cell ₆₃ ) connected to the second match line (ML2), the second match line (ML2) and the second source line (ScL2) were not connected, thereby 2 Match line (ML2) maintains the precharged voltage level.

As the first match line ML1 drops, the first match transistor MT1, the gate of which is connected to the first match line ML1, is gradually turned on, and the power supply voltage V _DD is applied to the first node Nd1. do. That is, the voltage level of the first node Nd1 gradually increases. On the other hand, the second match transistor MT2, whose gate is connected to the second match line ML2, remains turned off and does not affect the first node Nd1.

Meanwhile, the second output transistor OT2 is already turned off by the precharge signal PRE, and the first output transistor OT1 is turned on to electrically connect the first node Nd1 and the second node Nd2. Since it is connected, the voltage level of the match line sensing output (MLSO) of the second node (Nd2) also gradually increases.

FIG. 9 is a diagram for explaining the CAM search step in FIG. 3, and FIG. 10 is a timing diagram for explaining the CAM search step in FIG. 9.

In the search step of FIG. 9, as the match line sensing output (MLSO) of the second node (Nd2) gradually increases, when the match line sensing output (MLSO) exceeds a certain level, the output of the inverter (INV) changes from a high level to a low level. level transitions, and accordingly, both discharge transistors (DT1 and DT2) are turned off, and the first match line (ML1) and first source line (ScL1) are connected to the first CAM cell (Cell) in which a mismatch occurred. Since they are electrically connected through ₀ ), they are equalized at the same constant voltage level (V _A ). Here, the voltage level ( _VA ) at which the first match line (ML1) and the first source line (ScL1) are equalized is called the equalized voltage level.

At this time, the equalized voltage level (V _A ) is the voltage level when the first precharge transistor (PT1) is turned on so that the output of the inverter (INV) is inverted, so the voltage level of the first and second precharge transistors (PT1 and PT2) is The voltage level is lower than the threshold voltage, and therefore the first precharge transistor PT1 remains turned on. Accordingly, the matchline sensing output (MLSO) rises to the power supply voltage (V _DD ) level and is output.

Meanwhile, the second match line ML2 and the second source line ScL2 maintain the precharged power voltage V _DD and ground voltage levels, respectively.

As a result, the sense amplifier for CAM according to this embodiment is connected between the corresponding match lines (ML) in the NOR type CAM, and divides the match lines (ML) into first and second match lines (ML1 and ML2). , the precharged voltage is configured to be discharged only at the match line to which the CAM cell in which a mismatch occurred in the divided first and second match lines ML1 and ML2 is connected. Therefore, discharge does not occur in a matchline where a mismatch does not occur, and thus power consumption for precharge does not occur in the subsequent precharge stage, thereby reducing energy consumption. In addition, the match line (ML) is divided into first and second match lines (ML1, ML2), and the capacitance of each of the divided first and second match lines (ML1, ML2) is reduced, thereby reducing power consumption for precharge. It can be further reduced, and the discharge speed is also faster, so the search speed can be improved. In addition, by using an inverter (INV) and discharge transistors (DT1, DT2), the voltage level does not pull down to the ground voltage level even in the match line where a mismatch occurs, but only drops to the equal voltage level (V _A ), thereby saving energy. Consumption can be further reduced.

The present invention has been described with reference to the embodiments shown in the drawings, but these are merely illustrative, and those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom.

Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the attached claims.

SA: Sense Amplifier ML: Matchline
ScL: source line WL: word line
BLB/BL: Bit line pair PT1, PT2: Precharge transistor
MT1, MT2: Match transistors OT1, OT2: Output transistors
DT1, DT2: Discharge transistor INV: Inverter

Claims (17)

A first and second splitting the power supply voltage and match line in response to a precharge bar signal that is activated at a low level in the precharge step of the search operation consisting of a precharge step and a search step and deactivated at a high level before the search step. A precharge unit connecting each second match line;
a match detection unit connected between the power voltage and a first node and independently applying the power voltage to the first node in response to the voltage levels of each of the first and second match lines; and
It is connected between the first node and the output node and the output node and the ground voltage, and is connected to the first node and the output node or the output node and the ground in response to a precharge signal having an opposite phase to the precharge bar signal. Matchline sense amplifier for CAM (Content Addressable Memory) with output for selective voltage connection. The method of claim 1, wherein the precharge unit
a first precharge transistor connected between the power voltage and the first match line and to which the precharge bar signal is applied to a gate; and
A matchline sense amplifier for CAM including a second precharge transistor connected between the power voltage and the second matchline and to which the precharge bar signal is applied to a gate. The method of claim 2, wherein the match detection unit
a first match transistor connected between a first node between the power voltages and having a gate connected to the first match line; and
A match line sense amplifier for CAM including a second match transistor connected in parallel with the first match transistor between the first nodes between the power voltages and the gate connected to the second match line. The method of claim 3, wherein the output unit
a first output transistor connected between the first node and the output node and having the precharge signal applied to its gate; and
A matchline sense amplifier for a CAM connected between the output node and the ground voltage, the precharge signal applied to a gate, and including a second output transistor. The CAM of claim 4, wherein the first and second precharge transistors, the first and second match transistors, and the first output transistor are implemented as PMOS transistors, and the second output transistor is implemented as an NMOS transistor. Matchline Sense Amplifier. The method of claim 4, wherein the CAM is
A plurality of CAM cells are connected in parallel between the corresponding match lines among the first and second match lines and each corresponding source line among the first and second source lines dividing the source lines, and applied through the word line. A CAM implemented as a NOR type CAM that is activated according to the voltage level and electrically connects the corresponding match line and the corresponding source line depending on whether the bit value applied through the bit line pair in the search step matches the stored bit value. Matchline Sense Amplifier. The method of claim 6, wherein the matchline sense amplifier
an inverter whose input terminal is connected to the output node; and
A matchline sense amplifier for CAM further comprising a discharge unit connecting the first and second source lines to the ground voltage in response to the output of the inverter. The method of claim 7, wherein the discharge unit
a first discharge transistor connected between the first source line and the ground voltage and whose gate is connected to the output terminal of the inverter; and
A matchline sense amplifier for CAM including a second discharge transistor connected between the second source line and the ground voltage, and whose gate is connected to the output terminal of the inverter in common with the first discharge transistor. The method of claim 8, wherein the first and second discharge transistors are
Matchline sense amplifier for CAM implemented with NMOS transistors. A plurality of CAM (Content Addressable Memory) cells defined by a plurality of match lines extending in a first direction, a plurality of word lines, and a plurality of bit line pairs extending in a second direction perpendicular to the first direction; and
Among the plurality of match lines, a corresponding match line is connected between the divided first and second match lines to precharge the first and second match lines, and the bit value of the data applied to the plurality of bit line pairs It includes a plurality of match line sense amplifiers that detect the voltage drop of the match line that occurs depending on whether there is a match between the bit values stored in the corresponding CAM cells,
Each of the plurality of matchline sense amplifiers
The power supply voltage and the first and second match lines are activated in response to a precharge bar signal that is activated at a low level in the precharge phase of the search operation consisting of a precharge phase and a search phase and deactivated at a high level before the search phase. precharge units respectively connected to precharge the first and second match lines;
a match detection unit connected between the power voltage and a first node and independently applying the power voltage to the first node in response to the voltage levels of each of the first and second match lines; and
It is connected between the first node and the output node and the output node and the ground voltage, and is connected to the first node and the output node or the output node and the ground in response to a precharge signal having an opposite phase to the precharge bar signal. CAM with output for selective connection of voltage. The method of claim 10, wherein the precharge unit
a first precharge transistor connected between the power voltage and the first match line and to which the precharge bar signal is applied to a gate; and
A CAM including a second precharge transistor connected between the power voltage and the second match line and to which the precharge bar signal is applied to a gate. The method of claim 11, wherein the match detection unit
a first match transistor connected between a first node between the power voltages and having a gate connected to the first match line; and
A CAM including a second match transistor connected in parallel with the first match transistor between the first nodes between the power supply voltages, and whose gate is connected to the second match line. The method of claim 12, wherein the output unit
a first output transistor connected between the first node and the output node and having the precharge signal applied to its gate; and
A CAM connected between the output node and the ground voltage, to which the precharge signal is applied to a gate, and including a second output transistor. The method of claim 13, wherein the CAM is
The plurality of CAM cells are divided into first and second cell groups, and the corresponding match lines among the first and second match lines and the corresponding source lines among the plurality of source lines extending in the first direction are divided into first and second cell groups. A CAM implemented as a NOR type connected in parallel between corresponding source lines among the second source lines. The method of claim 14, wherein each of the first and second cell groups
Each of the included at least one CAM cells is activated according to the voltage level applied through the corresponding word line, and in the search step, the bit value applied through the corresponding bit line pair among the plurality of bit line pairs and the stored bit value are activated. CAM electrically connects the corresponding match line and the corresponding source line depending on whether or not there is a match. The method of claim 15, wherein the matchline sense amplifier
an inverter whose input terminal is connected to the output node; and
The CAM further includes a discharge unit connecting the first and second source lines to the ground voltage in response to the output of the inverter. The method of claim 16, wherein the discharge unit
a first discharge transistor connected between the first source line and the ground voltage and whose gate is connected to the output terminal of the inverter; and
A CAM including a second discharge transistor connected between the second source line and the ground voltage, and whose gate is connected to the output terminal of the inverter in common with the first discharge transistor.