KR102591303B1 - Negative voltage generating circuit in semiconducetor memory device for reducing over boosting phenomenon - Google Patents

Abstract

A negative voltage generation circuit for a semiconductor memory device that alleviates the overboosting phenomenon is published. The negative voltage generation circuit of the present invention is driven so that the voltage level of the negative voltage signal falls after the stability confirmation signal is activated. Accordingly, according to the negative voltage generation circuit of the present invention, before the voltage level of the driving reference signal rises to the set level, the voltage level of the negative voltage signal that may be generated when the pumping operation is performed drops excessively. The phenomenon, that is, the overboosting phenomenon, can be alleviated.

Description

Negative voltage generation circuit of a semiconductor memory device that alleviates overboosting phenomenon {NEGATIVE VOLTAGE GENERATING CIRCUIT IN SEMICONDUCETOR MEMORY DEVICE FOR REDUCING OVER BOOSTING PHENOMENON}

The present invention relates to semiconductor memory devices, and more particularly to negative voltage generation circuits.

A semiconductor memory device has internal voltage generation circuits that receive an externally applied power voltage and generate the voltage necessary to perform the operation of the semiconductor memory device.

The negative voltage generation circuit is one of these internal voltage generation circuits, and generates a negative voltage signal with a negative level through a pumping operation. Additionally, the negative voltage generation circuit is generally configured to lower the voltage level of the negative voltage signal by pumping it so that it becomes lower than the voltage of the reference signal being compared.
In addition, the technology for lowering the voltage level of a negative voltage signal through pumping has been published in a significant number of prior art documents, and in particular, it was published on September 17, 2001 under the name of 'Substrate bias voltage generation circuit of a semiconductor memory device'. It is described in detail in Registered Patent Publication No. 10-0294584 published in .
That is, in FIGS. 1, 2, and paragraph numbers [0022] to [0024] of Patent Registration No. 10-0294584, “When an output signal from a detector connected to a semiconductor substrate is applied to the oscillator, the oscillator operates at a predetermined frequency. The branch generates an oscillation signal, and the clock signal generator supplies a clock signal, which is an alternating current signal generated from the oscillator, that is, a clock signal that is a rectangular signal obtained from the oscillation signal, to the charge pump circuit, and the charge pump circuit supplies the clock signal to the charge pump circuit. A technique is described and shown by pumping charges into a terminal connected to a semiconductor substrate in response to a signal, whereby the substrate bias voltage (VBB) is brought to a negative voltage level.

Meanwhile, the voltage level of the reference signal is stabilized by rising to a set level after a certain time has elapsed from the activation of the global enable signal.

However, when the negative voltage generation circuit performs a pumping operation before the voltage level of the reference signal rises to the set level, a phenomenon in which the voltage level of the negative voltage signal falls excessively, that is, an over boosting phenomenon, occurs. It can happen.

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(patent literature)
1) Registered Patent Publication No. 10-0294584, Announcement Date: September 17, 2001
2) U.S. Patent Publication No. 5,343,088, registration date: August 30, 1994
3) Patent Publication No. 10-1993-0007650, Announcement Date: June 14, 1993
4) Publication Patent Publication 10-2000-0055320, published on September 5, 2000
5) Patent Publication No. 10-1993-0007645, Announcement Date: August 14, 1993
6) Patent Publication No. 10-1996-0006378, Announcement Date: May 15, 1996
7) Publication of Patent Publication 10-2002-0010825, published on February 6, 2002
8) Publication of Patent Publication 10-2003-0069303, published on August 27, 2003
9) Publication of Patent Publication 10-2005-0078611, published on August 5, 2005
10) Publication of Patent Publication 10-2007-0003051, published on January 5, 2007

The purpose of the present invention is to provide a negative voltage generation circuit for a semiconductor memory device that alleviates overboosting.

One aspect of the present invention for achieving the above object is a negative voltage generator circuit that generates a negative voltage signal, wherein the negative voltage signal is driven to have a negative (-) level through a pumping operation. It's about. The negative voltage generation circuit of the present invention is a negative voltage generation block that is enabled in response to activation of a stability confirmation signal and is driven so that the negative voltage signal has a level corresponding to the voltage level of the driving reference signal, wherein the driving reference signal The negative voltage generation block, the voltage of which is raised to a set level upon activation of a global enable signal; and a stability capacitor, one end of which is connected to a positive voltage signal, the positive voltage signal being driven to have a positive level corresponding to the voltage level of the stability reference signal, and a stability confirmation signal generating the stability confirmation signal. As a block, the stability confirmation signal is activated in response to the voltage of the positive voltage signal reaching a voltage level corresponding to the voltage level of the stability reference signal, and the stability capacitor has a capacitance greater than the capacitance applied to the driving reference signal. and the stability confirmation block in which the voltage of the stability reference signal is raised to a set voltage level upon activation of the global enable signal.

The negative voltage generation circuit of the present invention configured as described above is driven so that the voltage level of the negative voltage signal falls after the stability confirmation signal is activated. Accordingly, according to the negative voltage generation circuit of the present invention, before the voltage level of the driving reference signal rises to the set level, the voltage level of the negative voltage signal that may be generated when the pumping operation is performed drops excessively. The phenomenon, that is, the overboosting phenomenon, can be alleviated.

A brief description of each drawing used in the present invention is provided.
1 is a diagram showing a negative voltage generation circuit according to an embodiment of the present invention.
FIG. 2 is a diagram specifically showing the stability confirmation block of FIG. 1.
3A and 3B are diagrams showing examples of the setting generation unit of FIG. 2.
FIG. 4 is a diagram specifically showing the stability confirmation unit of FIG. 2.
FIG. 5 is a diagram showing the timing of main signals in the negative voltage generation circuit of FIG. 1.

In order to fully understand the present invention, its operational advantages, and the objectives achieved by practicing the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure will be thorough and complete and so that the spirit of the invention can be sufficiently conveyed to those skilled in the art.

Also, when understanding each drawing, it should be noted that like members are shown with the same reference numerals as much as possible. Additionally, detailed descriptions of well-known functions and configurations that are judged to unnecessarily obscure the gist of the present invention are omitted.

Meanwhile, multiple expressions for each component may also be omitted. For example, even if it is composed of a plurality of signal lines, it can be expressed as 'signal lines', or it can be expressed in the singular as 'signal line'. This is also because when a signal line is made up of a bundle of several signal lines with the same properties, for example, data signals, there is no need to distinguish them into singular and plural. In this respect, this description is valid. Therefore, similar expressions should also be interpreted with the same meaning throughout the specification.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings.

1 is a diagram showing a negative voltage generation circuit according to an embodiment of the present invention. The negative voltage generation circuit of FIG. 1 generates a negative voltage signal (VNEG). The negative voltage signal VNEG is driven to have a negative (-) level by the pumping operation of the negative voltage generating circuit of FIG. 1.

Referring to Figure 1, the negative voltage generation circuit of the present invention includes a negative voltage generation block 100 and a stability confirmation block 200, and preferably further includes a reference voltage generation block (BKGRF).

The reference voltage generation block (BKGRF) generates the driving reference signal (VREFD) and the stability reference signal (VREFS). At this time, as shown in FIG. 5, the driving reference signal (VREFD) and the stability reference signal (VREFS) each have a voltage (Vrfd) at a level set in response to activation of the global enable signal (GEN) to “H”. , Vrfs), the voltage level rises (see t11 in FIG. 5).

The negative voltage generation block 100 is enabled in response to activation of the stability confirmation signal (XSTA) provided by the stability confirmation block 200 to “H”, and the negative voltage signal (VNEG) is a driving reference signal ( It is driven to have a negative target level (Vtagn), which is a level corresponding to the voltage level of VREFD).

The negative voltage generation block 100 specifically includes a voltage detection unit 110, a detection generation unit 120, a logic operation unit 130, and a negative voltage pumping unit 140, and further includes a negative voltage capacitor (CPN). Equipped with

The negative voltage capacitor CPN is formed between the negative voltage signal VNEG and the ground voltage VSS, and serves to store the voltage of the negative voltage signal VNEG.

The voltage detection unit 110 receives the power supply voltage (VDD) and the negative voltage signal (VNEG) and generates a negative feedback signal (VFBN).

More specifically, the voltage sensing unit 110 includes a first negative feedback resistor 111 and a second negative feedback resistor 112.

The first negative feedback resistor 111 is formed between the power supply voltage (VDD) and the negative feedback signal (VFBN), and the second negative feedback resistor 112 is formed between the negative feedback signal (VFBN) and the negative voltage. It is formed between signals (VNEG).

Accordingly, the voltage of the negative feedback signal (VFBN) is a divided voltage between the power supply voltage (VDD) and the voltage of the negative voltage signal (VNEG).

The detection generator 120 generates a sound detection signal (XDETN) by comparing the voltage of the sound feedback signal (VFBN) and the driving reference signal (VREFD). At this time, the negative detection signal (XDETN) is activated to “H” as the voltage of the negative feedback signal (VFBN) is higher than the voltage of the driving reference signal (VREFD). And, when the voltage of the negative feedback signal (VFBN) is lower than the voltage of the driving reference signal (VREFD), the negative detection signal (XDETN) is deactivated to “L” (see t12 in FIG. 5).

The logic operation unit 130 receives the sound detection signal (XDETN) and generates a sound pumping enable signal (XPEN). Preferably, the logic operation unit 130 performs an AND operation of the stability confirmation signal (XSTA) and the sound detection signal (XDETN) provided from the stability confirmation block 200 to generate the sound pumping enable signal (XPEN). It is implemented as an AND gate that generates.

Accordingly, the sound pumping enable signal (XPEN) is activated to “H” upon activation of the sound detection signal (XDETN) to “H” according to the activation of the stability confirmation signal (XSTA) to “H”. (see t13 in FIG. 5).

The negative voltage pumping unit 140 is enabled according to the activation of the negative pumping enable signal XPEN to “H” and is driven to lower the voltage of the negative voltage signal VNEG.
The implementation of the negative voltage pumping unit 140 is obvious to those skilled in the art. Therefore, in this specification, for simplicity of explanation, detailed description thereof is omitted.

Meanwhile, before the voltage level of the driving reference signal (VREFD) rises to the set level (Vrfd), the negative voltage generation block 100 performs a pumping operation to lower the voltage level of the negative voltage signal (VNEG). When performing the pumping operation, the voltage level of the negative voltage signal VNEG may excessively drop, that is, an overboosting phenomenon may occur (see t14 in FIG. 5).

The negative voltage generation circuit of the present invention includes a stability confirmation block 200 that provides the stability confirmation signal (XSTA) in order to reduce the over-boosting phenomenon of the negative voltage signal (VNEG).

Still referring to Figure 1, the stability check block 200 includes a stability capacitor (CPS), one end of which is connected to the positive voltage signal (VPOS). In addition, the stability check block 200 is driven so that the positive voltage signal VPOS has a positive (+) level, and generates the stability check signal XSTA.

At this time, the stability confirmation signal (XSTA) is activated to “H” in response to the voltage of the positive voltage signal (VPOS) reaching a voltage level corresponding to the voltage level of the stability reference signal (VREFS) (see FIG. 5 ).

The stability capacitor (CPS) has a capacitance greater than the parasitic capacitance applied to the driving reference signal (VREFD). At this time, the stability capacitor (CPS) is activated by “H” of the stability confirmation signal (XSTA) after the driving reference signal (VREFD) rises to the set level (Vrfd).

FIG. 2 is a diagram specifically showing the stability confirmation block 200 of FIG. 1. Referring to FIG. 2, the stability verification block 200 includes a positive voltage generator 210 and an initial activation response unit 230.

The positive voltage generator 210 includes the stability capacitor (CPS), pumps the positive voltage signal (VPOS) so that the positive feedback signal (VFBP) has the voltage of the stable reference signal (VREFS), and stabilizes the positive voltage signal (VPOS). Generates a pumping signal (XPUMS).

More specifically, the positive voltage generator 210 includes a positive voltage detection unit 211, a stability generation unit 213, a positive voltage pumping unit 215, and the stability capacitor (CPS).

The positive voltage detection unit 211 receives the ground voltage (VSS) and the positive voltage signal (VPOS) and generates the positive feedback signal (VFBP).

The positive voltage sensing unit 211 includes a first positive feedback resistor 211a and a second positive feedback resistor 211b. The first positive feedback resistor 211a is formed between the positive feedback signal VFBP and the positive voltage signal VPOS, and the second positive feedback resistor 211b is formed between the ground voltage VSS and the positive voltage signal. It is formed between signals (VPOS).

Accordingly, the voltage of the positive feedback signal (VFBP) is a divided voltage between the ground voltage (VSS) and the positive voltage signal (VPOS).

The stability generation unit 213 generates the stability pumping signal (XPUMS) by comparing the voltage of the positive feedback signal (VFBP) and the stability reference signal (VREFS). At this time, the stable pumping signal (XPUMS) is activated to “H” as the voltage of the positive feedback signal (VFBP) is lower than the voltage of the stable reference signal (VREFS) (see t15 in FIG. 5), and the positive feedback signal (VFBP) is activated to “H” (see t15 in FIG. 5). As the voltage of the signal VFBP is higher than the voltage of the stable reference signal VREFS, it is deactivated to “L” (see t16 in FIG. 5).

The positive voltage pumping unit 215 is enabled upon activation of the stability pumping signal (XPUMS) to “H” and is driven to increase the voltage of the positive voltage signal (VPOS).
The implementation of this positive voltage pumping unit 215 is obvious to those skilled in the art. Therefore, in this specification, for simplicity of explanation, detailed description thereof is omitted.

The stability capacitor (CPS) is formed between the positive voltage signal (VPOS) and the ground voltage (VSS).

As a result, according to the positive voltage generator 210, the stable pumping signal (XPUMS) is set to “H” when the voltage level of the positive voltage signal (VPOS) is lower than the voltage level of the stable reference signal (VREFS). It is activated. Thereafter, when the voltage level of the positive voltage signal (VPOS) becomes higher than the level (Vtagp) corresponding to the voltage level of the stability reference signal (VREFS) due to the pumping operation of the positive voltage pumping unit 215, the stable The pumping signal (XPUMS) is disabled with "L".

Continuing to refer to FIG. 2, the first active response unit 230 receives the stability pumping signal (XPUMS) and generates the stability confirmation signal (XSTA). And, the first active response unit 230 includes a setting generation unit 231 and a stability confirmation unit 233.

The setting generation unit 231 receives the stable pumping signal (XPUMS) and generates a setting signal (XSET).

FIGS. 3A and 3B are diagrams showing examples of the setting generating unit 231 of FIG. 2, respectively. Referring to FIGS. 3A and 3B, the setting generating unit 231 includes the setting preliminary generating means (231a/231c) and setting latch means (231b/231d).

The setting preliminary generation means (231a/231c) receives the stable pumping signal (XPUMS) and generates a setting preliminary signal (XSPB). At this time, activation of the setting preliminary signal (XSPB) to “L” occurs when the setting signal (XSET) is deactivated to “L”, and is latched by the setting latch means (231b/231d).

The setting latch means 231b/231d is enabled in response to activation of the global enable signal GEN to “H” and receives the setting preliminary signal XSPB to generate the setting signal XSET. .

At this time, activation of the setting signal (XSET) to “H” occurs in response to activation of the setting preliminary signal (XSPB) to “L” and is latched. And, deactivation of the setting signal (XSET) to “L” occurs in response to deactivation of the global enable signal (GEN) to “L”.

As a result, according to the setting generating unit 231, as shown in FIGS. 3A and 3B, activation of the setting signal (XSET) to “H” is responsive to activation of the stable pumping signal to “H”. occurs (see t17 in FIG. 5), and deactivation of the setting signal (XSET) to “L” occurs in response to deactivation of the global enable signal (GEN) to “L” (see t18 in FIG. 5).

Referring again to FIG. 2, the stability confirmation unit 233 receives the setting signal (XSET) and the stability pumping signal (XPUMS) and generates the stability confirmation signal (XSTA).

FIG. 4 is a diagram specifically showing the stability confirmation unit 233 of FIG. 2. Referring to FIG. 4, the stability confirmation unit 233 includes a confirmation pre-generation means 233a and a confirmation latch means 233b.

The preliminary confirmation generation means 233a receives the setting signal (XSET) and the stable pumping signal (XPUMS) and generates a preliminary confirmation signal (XPCB). At this time, the activation of the confirmation preliminary signal (XPCB) to “L” occurs in response to the deactivation of the stable pumping signal (XPUMS) to “L”, which occurs in the “H” activation state of the setting signal (XSET). .

The confirmation latch means 233b is enabled in response to activation of the global enable signal (GEN) to “H”, and receives the confirmation preliminary signal (XPCB) to generate the stability confirmation signal (XSTA).

At this time, activation of the stability confirmation signal (XSTA) to “H” occurs in response to activation of the confirmation preliminary signal to “L” and is latched. And, deactivation of the stability confirmation signal (XSTA) to “L” occurs in response to deactivation of the global enable signal (GEN) to “L”.

As a result, according to the stability confirmation unit 233 as shown in FIG. 4, the activation of the stability confirmation signal (XSTA) to “H” occurs in the activation state of the setting signal (XSET) to “H”. Generated in response to deactivation of the stable pumping signal (XPUMS) to “L” (see t19 in FIG. 5). And, deactivation of the stability confirmation signal (XSTA) to “L” occurs in response to deactivation of the global enable signal (GEN) to “L” (see t20 in FIG. 5).

In summary, according to the first activation response unit 230, activation of the stability confirmation signal (XSTA) to “H” occurs in response to deactivation of the stability pumping signal (XPUMS) to “L”, and the stability confirmation Deactivation of the signal (XSTA) to “L” occurs in response to deactivation of the global enable signal (GEN) to “L”.

That is, according to the first activation response unit 230, activation of the stability confirmation signal (XSTA) to “H” occurs in response to deactivation of the first stability pumping signal (XPUMS) to “L”. And, while the global enable signal (GEN) is in the activated state of “H”, even if a transition of the stability pumping signal (XPUMS) occurs (see t21 in FIG. 5), the stability confirmation signal (XSTA) is still Maintain the status of "H".

The negative voltage generation circuit of the present invention configured as described above is activated by “H” of the stability confirmation signal (XSTA) and is driven so that the voltage level of the negative voltage signal (VNEG) decreases.

That is, the negative voltage generation block 100 is disabled in a state before being activated by “H” of the stability confirmation signal (XSTA), that is, in a state where the stability confirmation signal (XSTA) is “L”.

Accordingly, according to the negative voltage generation circuit of the present invention, the negative voltage signal (VNEG) that can be generated when a pumping operation is performed before the voltage level of the driving reference signal (VREFD) is raised to a set level. The phenomenon in which the voltage level drops excessively, that is, the over boosting phenomenon, can be alleviated.

As described above, although the embodiments have been described with limited examples and drawings, various modifications and variations can be made by those skilled in the art from the above description. For example, the described techniques are performed in a different order than the described method, and/or components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or other components are used. Alternatively, appropriate results may be achieved even if substituted or substituted by an equivalent. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the attached registration claims.

Claims (10)

A negative voltage generating circuit that generates a negative voltage signal, wherein the negative voltage signal is driven to have a negative (-) level through a pumping operation,
A negative voltage generation block that is enabled in response to activation of a stability confirmation signal and driven so that the negative voltage signal has a level corresponding to the voltage level of the driving reference signal, wherein the voltage of the driving reference signal is that of the global enable signal. The negative voltage generation block that rises to a set level upon activation; and
A stability check block that includes a stability capacitor, one end of which is connected to a positive voltage signal, the positive voltage signal being driven to have a positive level corresponding to the voltage level of the stability reference signal, and generating the stability confirmation signal. As, the stability confirmation signal is activated in response to the voltage of the positive voltage signal reaching a voltage level corresponding to the voltage level of the stability reference signal, and the stability capacitor has a capacitance greater than the capacitance applied to the driving reference signal. and the stability confirmation block, wherein the voltage of the stability reference signal is raised to a set level upon activation of the global enable signal.
The method of claim 1, wherein the negative voltage generation block is
a voltage detection unit to which a power supply voltage and the negative voltage signal are applied and generating a negative feedback signal, wherein the voltage of the negative feedback signal is a divided voltage between the power supply voltage and the voltage of the negative voltage signal;
A detection generator that generates a sound detection signal by comparing the voltage of the negative feedback signal and the driving reference signal, wherein the negative detection signal is activated when the voltage of the negative feedback signal is higher than the voltage of the driving reference signal. Detection generator;
A negative logic operation unit that receives the sound detection signal and generates a sound pumping enable signal, wherein the sound pumping enable signal is activated according to activation of the stability confirmation signal when the sound detection signal is activated. ; and
A negative voltage generation circuit comprising a negative voltage pumping unit enabled by activation of the negative pumping enable signal and driven to lower the voltage of the negative voltage signal.
The method of claim 2, wherein the voltage detection unit
a first negative feedback resistor formed between the power voltage and the negative feedback signal; and
A negative voltage generation circuit comprising a second negative feedback resistor formed between the negative feedback signal and the negative voltage signal.
The method of claim 2, wherein the negative voltage generation block is
A negative voltage generation circuit further comprising a negative voltage capacitor, one end of which is connected to the negative voltage signal.
The method of claim 1, wherein the stability confirmation block is
A positive voltage generator that includes the stable capacitor, pumps the positive voltage signal so that the positive feedback signal has the voltage of the stable reference signal, and generates a stable pumping signal, wherein the voltage of the positive feedback signal is the positive voltage. The positive voltage generator has a level corresponding to the voltage of the signal, and the stable pumping signal is activated in response to the voltage of the positive feedback signal reaching the voltage of the stable reference signal; and
An initially active response unit that receives the stability pumping signal and generates the stability confirmation signal, wherein activation of the stability confirmation signal occurs in response to deactivation of the stability pumping signal, and deactivation of the stability confirmation signal occurs in response to the global inactivation signal. A negative voltage generating circuit comprising the first activation response portion generated in response to deactivation of the enable signal.
The method of claim 5, wherein the positive voltage generator
A positive voltage sensing unit to which a ground voltage and the positive voltage signal are applied, and generating the positive feedback signal, wherein the voltage of the positive feedback signal is a divided voltage between the ground voltage and the voltage of the positive voltage signal. unit;
A stability generation unit that generates the stable pumping signal by comparing the voltage of the positive feedback signal and the stable reference signal, wherein the stable pumping signal is activated as the voltage of the positive feedback signal is lower than the voltage of the stable reference signal. the stable generating unit;
a positive voltage pumping unit enabled according to activation of the stable pumping signal and driven to increase the voltage of the positive voltage signal; and
A negative voltage generation circuit comprising the stability capacitor formed between the positive voltage signal and the ground voltage.
The method of claim 5, wherein the first active response unit
A setting generating unit that receives the stable pumping signal and generates a setting signal, wherein activation of the setting signal occurs in response to activation of the stable pumping signal, and deactivation of the setting signal occurs in response to deactivation of the global enable signal. The setting generation unit generated by: and
A stability confirmation unit that receives the setting signal and the stability pumping signal and generates the stability confirmation signal, wherein activation of the stability confirmation signal occurs in response to deactivation of the stability pumping signal occurring in an activation state of the setting signal, and , Negative voltage generation circuit comprising the stability confirmation unit, wherein deactivation of the stability confirmation signal is generated in response to deactivation of the global enable signal.
The method of claim 7, wherein the setting generating unit is
Setting preliminary generation means for receiving the stable pumping signal and generating a setting preliminary signal, wherein activation of the setting preliminary signal occurs in response to activation of the stable pumping signal generated during deactivation of the setting signal. ; and
A setting latch means that is enabled in response to activation of the global enable signal and generates the setting signal by receiving the setting preliminary signal, wherein activation of the setting signal occurs in response to activation of the setting preliminary signal to latch. and the setting latch means, wherein deactivation of the setting signal occurs in response to deactivation of the global enable signal.
The method of claim 7, wherein the stability confirmation unit
Confirmation preliminary generation means for receiving the setting signal and the stable pumping signal and generating a confirmation preliminary signal, wherein activation of the confirmation preliminary signal occurs in response to deactivation of the stable pumping signal generated in an activated state of the setting signal said confirmation pre-generating means; and
Confirmation latch means, enabled in response to activation of the global enable signal, receiving the confirmation preliminary signal and generating the stable confirmation signal, wherein activation of the stable confirmation signal occurs in response to activation of the confirmation preliminary signal. and latched, and deactivation of the stability confirmation signal is generated in response to deactivation of the global enable signal.
The method of claim 1, wherein the negative voltage generating circuit is
A reference voltage generation block that generates the driving reference signal and the stability reference signal, wherein the driving reference signal and the stability reference signal each have a voltage level raised in response to activation of the global enable signal. A negative voltage generating circuit further comprising:

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