KR102578889B1 - Semiconductor package including antenna - Google Patents

Abstract

The semiconductor package of the present disclosure includes a lower insulating layer; a ground layer disposed on the lower insulating layer; an upper insulating layer disposed on the ground layer; a ground wall extending vertically from the ground layer to define a plurality of antenna placement spaces within the upper insulating layer; A first antenna module disposed in a first antenna arrangement space among the plurality of antenna arrangement spaces, comprising: a first lower antenna patch disposed inside the upper insulating layer; and a first upper antenna patch arranged to be vertically spaced apart from the first lower antenna patch inside the upper insulating layer; a second antenna module disposed on top of the first antenna module in the first antenna placement space, the second lower antenna patch disposed on top of the first upper antenna patch inside the upper insulating layer; and a second upper antenna patch disposed within the upper insulating layer to be vertically spaced apart from the second lower antenna patch. and a third antenna module disposed in a second antenna arrangement space that is separated from the first antenna arrangement space among the plurality of antenna arrangement spaces.

Description

Semiconductor package including an antenna {SEMICONDUCTOR PACKAGE INCLUDING ANTENNA}

The technical idea of the present invention relates to a semiconductor package, and more specifically, to a semiconductor package including an antenna for transmitting and receiving wireless signals.

In electronic devices, integrated circuits are widely applied due to their advantages of small size, light weight, high reliability, and ease of mass production. An integrated circuit package device can integrate all components required by a circuit with a specific function into one chip and package the chip on a package substrate. Components may include elements such as semiconductors, resistors, and capacitors, and connecting wires between elements. If the chip needs to receive or transmit wireless signals, an antenna may be placed on the integrated circuit package device.

One of the problems to be solved by the technical idea of the present disclosure is to provide a semiconductor package including an antenna.

In order to solve the above-described problem, an exemplary embodiment of the present disclosure includes a lower insulating layer; a ground layer disposed on the lower insulating layer; an upper insulating layer disposed on the ground layer; a ground wall extending vertically from the ground layer to define a plurality of antenna placement spaces within the upper insulating layer; A first antenna module disposed in a first antenna arrangement space among the plurality of antenna arrangement spaces, comprising: a first lower antenna patch disposed inside the upper insulating layer; and a first upper antenna patch arranged to be vertically spaced apart from the first lower antenna patch inside the upper insulating layer; a second antenna module disposed on top of the first antenna module in the first antenna placement space, the second lower antenna patch disposed on top of the first upper antenna patch inside the upper insulating layer; and a second upper antenna patch disposed within the upper insulating layer to be vertically spaced apart from the second lower antenna patch. and a third antenna module disposed in a second antenna arrangement space separated from the first antenna arrangement space among the plurality of antenna arrangement spaces.

In an exemplary embodiment, a redistribution line pattern disposed between the first antenna module and the second antenna module; a first redistribution via pattern vertically passing through at least a portion of the ground layer and the upper insulating layer and connected to the first lower antenna patch; a second redistribution via pattern extending vertically from the redistribution line pattern and connected to the second lower antenna patch; and a third redistribution via pattern connected to the redistribution line pattern by passing through the ground layer, at least a portion of the upper insulating layer, the first lower antenna patch, and the first upper antenna patch in a vertical direction. It is characterized by including.

In an exemplary embodiment, a side surface of the third redistribution via pattern is horizontally spaced apart from the first lower antenna patch and the first upper antenna patch.

In an exemplary embodiment, the side surface of the first redistribution via pattern and the side surface of the third redistribution via pattern are spaced apart from the ground layer in the horizontal direction.

In an exemplary embodiment, the third antenna module includes a PIFA antenna, and the semiconductor package is connected to the third antenna module by vertically passing through the ground layer and at least a portion of the upper insulating layer. It is characterized in that it further includes a fourth redistribution via pattern.

In an exemplary embodiment, the ground pattern extends inside the lower insulating layer and is connected to the ground layer and the ground wall.

In an exemplary embodiment, a redistribution line pattern disposed between the first antenna module and the second antenna module; a first redistribution via pattern vertically passing through at least a portion of the ground layer and the upper insulating layer and connected to the first lower antenna patch; a second redistribution via pattern extending vertically from the redistribution line pattern and connected to the second lower antenna patch; and a third redistribution via pattern disposed outside the first antenna module, passing through at least a portion of the ground layer and the upper insulating layer, and connected to the redistribution line pattern. .

In an exemplary embodiment, a first redistribution line pattern disposed between the first antenna module and the second antenna module; a second redistribution line pattern extending from an upper part of the first redistribution line pattern and connected to the second upper antenna patch; a first redistribution via pattern vertically passing through at least a portion of the ground layer and the upper insulating layer and connected to the first lower antenna patch; a second redistribution via pattern extending vertically from the first redistribution line pattern and connected to the second lower antenna patch; a third redistribution via pattern disposed outside the first antenna module, passing through at least a portion of the ground layer and the upper insulating layer, and connected to the first redistribution line pattern; and a fourth redistribution via pattern disposed outside the first antenna module, passing through at least a portion of the ground layer and the upper insulating layer, and connected to the second redistribution line pattern. .

In an exemplary embodiment, the cross-sectional areas of the first lower antenna patch and the first upper antenna patch are larger than the cross-sectional areas of the second lower antenna patch and the second upper antenna patch.

In an exemplary embodiment, the vertical separation distance between the first lower antenna patch and the first upper antenna patch is 100 micrometers to 200 micrometers, and the distance between the second lower antenna patch and the second upper antenna patch is 100 micrometers to 200 micrometers. The vertical separation distance is characterized in that it is 100 micrometers to 200 micrometers.

In an exemplary embodiment, the vertical separation distance between the first upper antenna patch and the second lower antenna patch is 100 micrometers to 400 micrometers.

In an exemplary embodiment, the first antenna module and the second antenna module are provided in plural numbers, and the plurality of first antenna modules include a row of M, which is an integer of 1 or more, and a column of N, which is an integer of 2 or more, It is arranged in an M*N matrix shape composed of N components, and the plurality of second antenna modules are arranged on top of the first antenna module to overlap the first antenna module in the vertical direction.

Additionally, in an exemplary embodiment of the present disclosure, a semiconductor package including an antenna package, the package substrate; The antenna package mounted on the package substrate, comprising: a lower insulating layer; a ground layer disposed on the lower insulating layer; an upper insulating layer disposed on the ground layer; a ground wall extending vertically from the ground layer to define a plurality of antenna placement spaces within the upper insulating layer; A first antenna module disposed in a first antenna arrangement space among the plurality of antenna arrangement spaces, comprising: a first lower antenna patch disposed inside the upper insulating layer; and a first upper antenna patch arranged to be vertically spaced apart from the first lower antenna patch inside the upper insulating layer; a second antenna module disposed on top of the first antenna module in the first antenna placement space, the second lower antenna patch disposed on top of the first upper antenna patch inside the upper insulating layer; and a second upper antenna patch disposed within the upper insulating layer to be vertically spaced apart from the second lower antenna patch. and a third antenna module disposed in a second antenna arrangement space among the plurality of antenna arrangement spaces, which is separated from the first antenna arrangement space. a semiconductor chip mounted on the package substrate; and a molding layer disposed on the package substrate and surrounding the antenna package and the semiconductor chip.

In an exemplary embodiment, the molding layer covers side and top surfaces of the antenna package.

In an exemplary embodiment, the molding layer exposes at least a portion of a top surface and a side surface of the antenna package.

In an exemplary embodiment, the level of the top surface of the molding layer is higher than the level of the top surface of the first upper antenna patch of the first antenna module and the level of the lower surface of the second lower antenna patch of the second antenna module. It is characterized by a lower

A semiconductor package according to an exemplary embodiment of the present disclosure may include a plurality of antenna modules, so that the semiconductor package may perform communication within a wide frequency band.

Additionally, the semiconductor package according to an exemplary embodiment of the present disclosure may include a ground layer and a ground wall configured to separate a plurality of antenna modules, thereby improving interference between communication signals of the plurality of antenna modules included in the semiconductor package. It can be.

1 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure.
FIG. 2 is a cut cross-sectional view of the region indicated by II-II' in FIG. 1.
Figure 3 is a cross-sectional view of the area indicated by 'A' in Figure 1.
Figure 4 is a cross-sectional view of the area indicated by 'B' in Figure 1.
5 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure.
Figure 6 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure.
7 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure.
8 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure.
FIG. 9 is a cut cross-sectional view of the area indicated by IX-IX' in FIG. 8.
FIG. 10 is a cross-sectional view of the area indicated by X-X' in FIG. 8.
FIG. 11 is a cut cross-sectional view of the area indicated by XI-XI' in FIG. 8.
FIG. 12 is a cross-sectional view of the area indicated by XII-XII' in FIG. 8.
13 is a plan view of a semiconductor package according to an exemplary embodiment of the present disclosure.
Figure 14 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure.
15 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure.

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the exemplary embodiments of the present disclosure may be modified in various other forms, and the scope of the present disclosure should not be construed as being limited to the embodiments described in detail below. The exemplary embodiments of the present disclosure are preferably interpreted as being provided to more completely explain the concept of the present disclosure to those with average knowledge in the art. Identical symbols refer to identical elements throughout. Furthermore, various elements and areas in the drawings are schematically drawn. Accordingly, the concept of the present disclosure is not limited by the relative sizes or spacing drawn in the accompanying drawings.

Terms such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, a first component may be named a second component, and conversely, the second component may be named a first component without departing from the scope of the present disclosure.

The terminology used in this disclosure is only used to describe specific embodiments and is not intended to limit the concept of this disclosure. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, expressions such as “comprises” or “has” are intended to indicate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but are not intended to indicate the presence of one or more other features or It should be understood that this does not preclude the presence or addition of numbers, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical terms and scientific terms, have the same meaning as commonly understood by those skilled in the art in the technical field to which the concept of the present disclosure pertains. Additionally, commonly used terms, as defined in dictionaries, should be interpreted to have meanings consistent with what they mean in the context of the relevant technology, and should not be used in an overly formal sense unless explicitly defined herein. It will be understood that this is not to be interpreted.

1 is a cross-sectional view of a semiconductor package 10 according to an exemplary embodiment of the present disclosure. Additionally, FIG. 2 is a cross-sectional view of the area indicated by II-II' in FIG. 1.

Referring to FIGS. 1 and 2 together, the semiconductor package 10 of the present disclosure includes a lower insulating layer 110, a ground layer 120, an upper insulating layer 130, a ground wall 140, and a first antenna module ( 230), second antenna module 250, third antenna module 270, redistribution line pattern 330, first to fourth redistribution via patterns (351, 353, 355, 357), ground pattern (413) ), and may include a package connection terminal 450.

Additionally, the first antenna module 230 may include a first lower antenna patch 233 and a first upper antenna patch 235, and the second antenna module 250 may include a second lower antenna patch 253 and It may include a second upper antenna patch 255.

The lower insulating layer 110 may be a layer of insulating material extending in the horizontal direction. In an exemplary embodiment, the lower insulating layer 110 is made of a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are impregnated into glass fibers together with an inorganic filler, prepreg, or ABF ( It may contain at least one material selected from Ajinomoto Build-up Film (FR-4), BT (Bismaleimide Triazine), and PID (Photo Imagable Dielectric). However, the material of the lower insulating layer 110 is not limited to the above.

Hereinafter, the horizontal direction may be defined as a direction parallel to the direction in which the upper and lower surfaces of the lower insulating layer 110 extend (for example, the width direction of the lower insulating layer 110), and the vertical direction may be defined as the direction in which the lower insulating layer 110 extends. The upper and lower surfaces of 110 may be defined in a direction perpendicular to the direction in which they extend (for example, the thickness direction of the lower insulating layer 110).

The ground layer 120 may be arranged to extend in the horizontal direction on the lower insulating layer 110. For example, the ground layer 120 may be disposed between the lower insulating layer 110 and the upper insulating layer 130. In an exemplary embodiment, the material of the ground layer 120 may include copper (Cu). However, it is not limited to this, and the ground layer 120 may include various types of metal materials.

The upper insulating layer 130 may be a layer of insulating material extending in the horizontal direction on the ground layer 120. In an exemplary embodiment, the upper insulating layer 130 is made of a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are impregnated into glass fibers together with an inorganic filler, prepreg, or ABF ( It may contain at least one material selected from Ajinomoto Build-up Film (FR-4), BT (Bismaleimide Triazine), and PID (Photo Imagable Dielectric). However, the material of the upper insulating layer 130 is not limited to the above.

The ground wall 140 may extend in a vertical direction from the ground layer 120 and pass through the upper insulating layer 130. For example, the top surface of the ground wall 140 may be on the same plane as the top surface of the upper insulating layer 130. However, without being limited to the above, the top surface of the ground wall 140 may be at a lower level than the top surface of the upper insulating layer 130.

Referring to FIG. 2 , the ground wall 140 may define a plurality of antenna placement spaces (A1_a to A1_d, A2) within the upper insulating layer 130. That is, the plurality of antenna placement spaces (A1_a to A1_d, A2) may be divided by the ground wall 140.

In an exemplary embodiment, the ground wall 140 may surround any one of the plurality of first antenna modules 230 and any one of the plurality of second antenna modules 250. Additionally, the ground wall 140 may surround the third antenna module 270.

In an exemplary embodiment, the ground wall 140 may define a plurality of first antenna placement spaces A1_a to A1_d and a second antenna placement space A1_e within the upper insulating layer 130. The plurality of first antenna placement spaces (A1_a to A1_d) may provide a space where the first antenna module 230 and the second antenna module 250 are placed, and the second antenna placement space (A2) may provide a space where the first antenna module 230 and the second antenna module 250 are placed. A space in which the antenna module 270 is placed may be provided.

In an exemplary embodiment, the second antenna placement space A2 may be provided at an edge of the semiconductor package 10 . In addition, when the semiconductor package 10 is viewed from a plan view, the plurality of first antenna arrangement spaces A1_a to A1_d may be provided in a rectangular shape, and the second antenna arrangement space A2 may be provided in a curved shape. It can be. For example, the second antenna placement space A2 may be shaped to surround some (A1_c, A1_d) of the plurality of first antenna placement spaces (A1_a to A1_d).

In an example embodiment, ground wall 140 may be integrated with ground layer 120. Additionally, the material of the ground wall 140 may include copper (Cu). However, it is not limited to this, and the ground layer 120 may include various types of metal materials.

The first antenna module 230 may include a first lower antenna patch 233 and a first upper antenna patch 235. The first antenna module 230 may be configured to perform communication within a relatively low frequency band. Additionally, a plurality of first antenna modules 230 may be provided, and each of the first antenna modules 230 may be disposed in the first antenna arrangement spaces A1_a to A1_d.

The first lower antenna patch 233 may have a structure and shape suitable for performing communication in a predetermined wavelength band. In an example embodiment, the first lower antenna patch 233 may be an active antenna pattern. For example, the first lower antenna patch 233 may be configured to emit or receive a wireless signal in a millimeter wavelength band. Additionally, the first lower antenna patch 233 may function as a radiator and/or a director of the antenna.

The first upper antenna patch 235 may be arranged to be vertically spaced apart from the first lower antenna patch 233 inside the upper insulating layer 130. In an example embodiment, the first upper antenna patch 235 may be a parasitic antenna pattern. For example, the first upper antenna patch 235 may function to expand the bandwidth of wireless communication using the first lower antenna patch 233.

In an exemplary embodiment, the first upper antenna patch 235 may have the same shape as the first lower antenna patch 233 in plan view, and the first upper antenna patch 235 and the first lower antenna patch (233) can be overlapped in the vertical direction. In another example embodiment, the shape of the first upper antenna patch 235 may be different from the shape of the first lower antenna patch 233.

In an exemplary embodiment, the first lower antenna patch 233 and the first upper antenna patch 235 may have a polygonal shape, such as a circle or a square, in plan view. However, without being limited to the above, the first lower antenna patch 233 and the first upper antenna patch 235 may have a line shape in plan view. Additionally, in an exemplary embodiment, the first lower antenna patch 233 and the first upper antenna patch 235 may have a cross or a plus (+) shape when viewed from a plan view.

In an exemplary embodiment, the vertical separation distance between the first lower antenna patch 233 and the first upper antenna patch 235 may be about 100 micrometers to about 200 micrometers. However, the vertical separation distance between the first lower antenna patch 233 and the first upper antenna patch 235 is not limited to the above.

In an exemplary embodiment, the first lower antenna patch 233 and the first upper antenna patch 235 may include a conductive material. For example, the first lower antenna patch 233 and the first upper antenna patch 235 may include metal such as copper (Cu) or aluminum (Al).

Additionally, the thickness of the first lower antenna patch 233 and the first upper antenna patch 235 may each be about 3 micrometers to about 20 micrometers. For example, the thickness of the first lower antenna patch 233 and the first upper antenna patch 235 may each be 6 micrometers.

The second antenna module 250 may include a second lower antenna patch 253 and a second upper antenna patch 255. The second antenna module 250 may be configured to perform communication within a relatively high frequency band. For example, the second antenna module 250 may perform communication within a higher frequency band than the first antenna module 230.

Additionally, a plurality of second antenna modules 250 may be provided, and each of the second antenna modules 250 may be disposed in the first antenna arrangement spaces A1_a to A1_d. In an exemplary embodiment, the second antenna module 250 may be disposed in the first antenna arrangement space A1_a to A1_d so as to be on top of the first antenna module 230.

The second lower antenna patch 253 may have a structure and shape suitable for performing communication in a predetermined wavelength band. In an example embodiment, the second lower antenna patch 253 may be an active antenna pattern. For example, the second lower antenna patch 253 may be configured to emit or receive a wireless signal in a millimeter wavelength band. Additionally, the first lower antenna patch 253 may function as a radiator and/or a director of the antenna.

The second upper antenna patch 255 may be arranged to be vertically spaced apart from the second lower antenna patch 253 inside the upper insulating layer 130. In an example embodiment, the second upper antenna patch 255 may be a parasitic antenna pattern. For example, the second upper antenna patch 255 may function to expand the bandwidth of wireless communication using the first lower antenna patch 253.

In an exemplary embodiment, the second upper antenna patch 255 may have the same shape as the second lower antenna patch 253 in plan view, and the second upper antenna patch 255 and the second lower antenna patch (253) can be overlapped in the vertical direction. In another example embodiment, the shape of the second upper antenna patch 255 may be different from the shape of the first lower antenna patch 253.

In an exemplary embodiment, the second lower antenna patch 253 and the second upper antenna patch 255 may have a polygonal shape, such as a circle or a square, in plan view. However, without being limited to the above, the second lower antenna patch 253 and the second upper antenna patch 255 may have a line shape in plan view.

In an exemplary embodiment, the vertical separation distance between the second lower antenna patch 253 and the second upper antenna patch 255 may be about 100 micrometers to about 200 micrometers. However, the vertical separation distance between the second lower antenna patch 253 and the second upper antenna patch 255 is not limited to the above.

In an exemplary embodiment, the second lower antenna patch 253 and the second upper antenna patch 255 may include a conductive material. For example, the second lower antenna patch 253 and the second upper antenna patch 255 may include metal such as copper (Cu) or aluminum (Al).

Additionally, the thickness of the second lower antenna patch 253 and the second upper antenna patch 255 may each be about 3 micrometers to about 20 micrometers. For example, the thickness of the second lower antenna patch 253 and the second upper antenna patch 255 may each be 6 micrometers.

In an exemplary embodiment, when the semiconductor package 10 is viewed from a planar perspective, the horizontal cross-sectional areas of the first lower antenna patch 233 and the first upper antenna patch 235 of the first antenna module 230 are: It may be larger than the horizontal cross-sectional area of the second lower antenna patch 253 and the second upper antenna patch 255 of the second antenna module 250.

However, it is not limited to the above, and the horizontal cross-sectional area of the first lower antenna patch 233 and the first upper antenna patch 235 of the first antenna module 230 is greater than that of the second lower antenna patch 250. It may be smaller than the horizontal cross-sectional area of the antenna patch 253 and the second upper antenna patch 255. In addition, the horizontal cross-sectional area of the first lower antenna patch 233 and the first upper antenna patch 235 of the first antenna module 230 is the second lower antenna patch 253 and the first upper antenna patch 250 of the second antenna module 250. It may be substantially equal to the horizontal cross-sectional area of the second upper antenna patch 255.

In an exemplary embodiment, the vertical separation distance between the first upper antenna patch 235 of the first antenna module 230 and the second lower antenna patch 253 of the second antenna module 250 is about 100 micrometers. It may be from about 400 micrometers.

The third antenna module 270 may be placed in the second antenna placement space A2. In an example embodiment, the third antenna module 270 may include a Planar Inverted F antenna (PIFA) antenna.

In an exemplary embodiment, the third antenna module 270 may be disposed at substantially the same level as the second upper antenna patch 255 of the second antenna module 250. For example, the third antenna module 270 may have a curved line shape.

The redistribution line pattern 330 may extend in the horizontal direction within the upper insulating layer 130. Specifically, the redistribution line pattern 330 may extend in the horizontal direction between the first antenna module 230 and the second antenna module 250. Additionally, the redistribution line pattern 330 may be connected to a second redistribution via pattern 353 and a third redistribution via pattern 355, which will be described later.

In an exemplary embodiment, the material of the redistribution line pattern 330 may include copper (Cu). However, it is not limited to this, and the material of the redistribution line pattern 330 is nickel (Ni), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), and tantalum (Ta). , indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru) It may be a metal such as a metal or an alloy thereof.

The first redistribution via pattern 351 passes through at least a portion of the lower insulating layer 110, the ground layer 120, and the upper insulating layer 130 in the vertical direction to form the first antenna module 230. It can be connected to the lower antenna patch 233.

In an exemplary embodiment, a plurality of first redistribution via patterns 351 may be provided, and the plurality of first redistribution via patterns 351 may contact the lower surface of the first lower antenna patch 233. there is.

The second redistribution via pattern 353 may extend in the vertical direction from the redistribution line pattern 330 and be connected to the second lower antenna patch 253 of the second antenna module 250.

In an exemplary embodiment, a plurality of second redistribution via patterns 353 may be provided, and the plurality of second redistribution via patterns 353 may contact the lower surface of the second lower antenna patch 253. there is.

The third redistribution via pattern 355 is at least the lower insulating layer 110, the ground layer 120, the first lower antenna patch 233, the first upper antenna patch 235, and the upper insulating layer 130. A portion may be connected to the redistribution line pattern 330 by passing in the vertical direction.

In an exemplary embodiment, the third redistribution via pattern 355 may be insulated from the ground layer 120. For example, when the semiconductor package 10 is viewed from a planar perspective, the third redistribution via pattern 355 can pass through the ground layer 120, and a side of the redistribution via pattern 355 is connected to the ground. It may not be in contact with the layer 120. In other words, when the semiconductor package 10 is viewed from a planar perspective, there may be a clearance between the third redistribution via pattern 355 and the ground layer 120. In an exemplary embodiment, the space between the third redistribution via pattern 355 and the ground layer 120 may be filled with an insulating material.

The fourth redistribution via pattern 357 may be connected to the third antenna module 270 by passing through at least a portion of the lower insulating layer 110, the ground layer 120, and the upper insulating layer 130 in the vertical direction. there is.

In an exemplary embodiment, the first to third redistribution via patterns 351, 353, and 355 may be disposed in the first antenna arrangement space (A1_a, A1_b, A1_c, A1_d), and the fourth redistribution via pattern ( 357) may be placed in the second antenna placement space A2.

In an exemplary embodiment, the material of the first to fourth redistribution via patterns 351, 353, 355, and 357 may include copper (Cu). However, it is not limited thereto, and the materials of the first to fourth redistribution via patterns 351, 353, 355, and 357 include nickel (Ni), gold (Au), silver (Ag), aluminum (Al), and tungsten (W). ), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be) ), gallium (Ga), ruthenium (Ru), etc., or alloys thereof.

The ground pattern 413 may extend in the horizontal direction within the lower insulating layer 110 and may be electrically connected to the ground layer 120 and the ground wall 140. In an exemplary embodiment, the material of the ground pattern 413 is nickel (Ni), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), and indium. (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), etc. It may be a metal or an alloy thereof.

The package connection terminal 450 may be disposed on the lower insulating layer 110. In an exemplary embodiment, the package connection terminal 450 may be electrically connected to the first, third, and fourth redistribution via patterns 351, 355, and 357, and the ground pattern 413.

For example, the package connection terminal 450 connected to the first, third, and fourth redistribution via patterns 351, 355, and 357 controls the operation of the first antenna module 230 and the second antenna module 250. It may be a terminal provided for. Additionally, the package connection terminal 450 connected to the ground pattern 413 may be a terminal provided for grounding.

In an exemplary embodiment, the package connection terminal 450 may be a solder ball made of a metal material including at least one of tin (Sn), silver (Ag), copper (Cu), and aluminum (Al).

The semiconductor package 10 according to an exemplary embodiment of the present disclosure may include a plurality of antenna modules 230, 250, and 270, so that the semiconductor package 10 can perform communication within a wide frequency band. there is.

In addition, the semiconductor package 10 according to an exemplary embodiment of the present disclosure may include a ground layer 120 and a ground wall 140 surrounding a plurality of antenna modules 230, 250, and 270, so that the ground Communication signal interference between the first antenna modules 230 arranged and separated in the horizontal direction by the wall 140 and communication signal interference between the second antenna modules 250 may be improved.

Figure 3 is a cross-sectional view of the area indicated by 'A' in Figure 1. Additionally, Figure 4 is a cross-sectional view of the area indicated by 'B' in Figure 1.

Referring to FIG. 3, the third redistribution via pattern 355 of the semiconductor package 10 according to an exemplary embodiment of the present disclosure is the first lower antenna patch 233 of the first antenna module 230 and the first lower antenna patch 233 of the first antenna module 230. It can pass through the upper antenna patch 235 in the vertical direction. Additionally, when the semiconductor package 10 is viewed from a planar perspective, the third redistribution via pattern 355 may be spaced apart from the first lower antenna patch 233 and the first upper antenna patch 235 in the horizontal direction.

In an exemplary embodiment, a separation space between the third redistribution via pattern 355 and the first lower antenna patch 233, and a space between the third redistribution via pattern 355 and the first upper antenna patch 235 The spacing space may be filled with an insulating material. For example, the insulating material may include at least one of a thermosetting resin such as an epoxy resin and a thermoplastic resin such as polyimide. However, the type of the insulating material is not limited to the above.

Referring to FIG. 4, the first redistribution via pattern 351 and the third redistribution via pattern 355 of the semiconductor package 10 according to an exemplary embodiment of the present disclosure are aligned with the ground layer 120 in the vertical direction. You can pass. Additionally, when the semiconductor package 10 is viewed from a plan view, the first redistribution via pattern 351 and the third redistribution via pattern 355 may be spaced apart from the ground layer 120 in the horizontal direction.

In an exemplary embodiment, the space between the first redistribution via pattern 351 and the ground layer 120 and the space between the third redistribution via pattern 355 may be filled with an insulating material.

Figure 5 is a cross-sectional view of a semiconductor package 20 according to an exemplary embodiment of the present disclosure.

Referring to FIG. 5, the semiconductor package 20 according to an exemplary embodiment of the present disclosure includes a lower insulating layer 110, a ground layer 120, an upper insulating layer 130, a ground wall 140, and a first antenna. Module 230, second antenna module 250, third antenna module 270, redistribution line pattern 330, first to fourth redistribution via patterns (351, 353, 355a, 357), ground pattern It may include (413), and a package connection terminal (450).

Hereinafter, overlapping content between the semiconductor package 10 of FIGS. 1 to 4 and the semiconductor package 20 of FIG. 5 will be omitted and the differences will be mainly explained.

The third redistribution via pattern 355a may be disposed outside the first lower antenna patch 233 and the first upper antenna patch 235 of the first antenna module 230. In other words, the third redistribution via pattern 355a does not pass through the first lower antenna patch 233 and the first upper antenna patch 235, but passes through the first lower antenna patch 233 and the first upper antenna. It may be placed outside the patch 235.

In an exemplary embodiment, a plurality of third redistribution via patterns 355a may be provided. At least one of the plurality of third redistribution via patterns 355a may be disposed on one side of the first antenna module 230. Additionally, at least one of the plurality of third redistribution via patterns 355a may be disposed on the other side of the first antenna module 230 that is opposite to the one side.

However, without being limited to the above, all of the plurality of third redistribution via patterns 355a may be disposed on one side of the first antenna module 230. In other words, the plurality of third redistribution via patterns 355a may be disposed on one side of the first antenna module 230 and may not be disposed on the other side opposite to the one side.

The plurality of third redistribution via patterns 355a of the semiconductor package 20 according to an exemplary embodiment of the present disclosure are connected to the first lower antenna patch 233 and the first upper antenna patch of the first antenna module 230. It can be disposed outside the first antenna module 230 without passing through 235, so that the plurality of third redistribution via patterns 355a do not interfere with wireless communication of the first antenna module 230. You may not.

Figure 6 is a cross-sectional view of a semiconductor package 30 according to an exemplary embodiment of the present disclosure.

Referring to FIG. 6, the semiconductor package 30 according to an exemplary embodiment of the present disclosure includes a lower insulating layer 110, a ground layer 120, an upper insulating layer 130, a ground wall 140, and a first antenna. Module 230, second antenna module 250, third antenna module 270, first redistribution line pattern 330, second redistribution line pattern 333, first to fifth redistribution via patterns It may include (351, 353, 355b, 357, 359b), a ground pattern (413), and a package connection terminal (450).

Hereinafter, overlapping content between the semiconductor package 10 of FIGS. 1 to 4 and the semiconductor package 30 of FIG. 6 will be omitted and the differences will be mainly explained.

The first redistribution line pattern 330 of the present disclosure may be disposed between the first antenna module 230 and the second antenna module 250. Specifically, the first redistribution line pattern 330 will be disposed between the first upper antenna patch 235 of the first antenna module 230 and the second lower antenna patch 253 of the second antenna module 250. You can.

Additionally, the second redistribution line pattern 333 of the present disclosure may be disposed on top of the first redistribution line pattern 330 and may extend in the horizontal direction within the upper insulating layer 130.

In an exemplary embodiment, the second redistribution line pattern 333 may be disposed on the same plane as the second upper antenna patch 255 of the second antenna module 250. Additionally, a portion of the second redistribution line pattern 333 may be connected to the second upper antenna patch 255.

In an exemplary embodiment, the third redistribution via pattern 355b may be disposed outside the first antenna module 230. Additionally, the third redistribution via pattern 353b passes through at least a portion of the lower insulating layer 110, the ground layer 120, and the upper insulating layer 130 in the vertical direction to form the first redistribution line pattern 330. ) can be connected to.

That is, the third redistribution via pattern 355b may be connected to the second lower antenna patch 253 of the second antenna module 250 through the first redistribution line pattern 330.

In an exemplary embodiment, the fifth redistribution via pattern 359b may be disposed outside the first antenna module 230 and the second antenna module 250. Additionally, the fifth redistribution via pattern 359b passes through at least a portion of the lower insulating layer 110, the ground layer 120, and the upper insulating layer 130 in the vertical direction to form the second redistribution line pattern 333. ) can be connected to.

That is, the fifth redistribution via pattern 359b may be connected to the second upper antenna patch 255 of the second antenna module 250 through the second redistribution line pattern 333.

Figure 7 is a cross-sectional view of the semiconductor package 1 according to an exemplary embodiment of the present disclosure.

The semiconductor package 1 of FIG. 7 may be a package-on-package type semiconductor package in which the upper semiconductor package 10 is mounted on the lower semiconductor package 50. For example, the upper semiconductor package 10 may be a semiconductor package including an antenna module, and the lower semiconductor package 50 may be a semiconductor package including a semiconductor chip electrically connected to the antenna module of the upper semiconductor package 10. It can be.

Since the upper semiconductor package 10 overlaps with the content described with reference to FIGS. 1 to 4, detailed information will be omitted.

Referring to FIG. 7 , the lower semiconductor package 50 may include a semiconductor chip 500, a passive element 550, a wiring structure 600, a ground wall 670, and an external connection terminal 650.

The semiconductor chip 500 of the lower semiconductor package 50 may include a plurality of various types of individual devices. For example, the plurality of individual devices may be various microelectronic devices, such as a metal-oxide-semiconductor field effect transistor (MOSFET) such as a complementary metal-oxide-semiconductor transistor (CMOS transistor), a large scale system LSI, etc. integration), image sensors such as CIS (CMOS imaging sensor), MEMS (micro-electro-mechanical system), active devices, passive devices, etc.

In exemplary embodiments, the semiconductor chip 500 is a communication semiconductor chip electrically or signal-transmittably connected to the first and second antenna modules 230 and 250 of the upper semiconductor package 10, and the first and It may include a signal processing circuit for processing wireless signals transmitted and received through the second antenna modules 230 and 250. For example, the semiconductor chip 500 may include a radio-frequency integrated circuit (RFIC).

In example embodiments, the semiconductor chip 500 may be, for example, a memory chip. The memory chip is, for example, a volatile memory semiconductor chip 500 such as Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM), Phase-change Random Access Memory (PRAM), or Magnetoresistive Random Access Memory (MRAM). ), it may be a non-volatile memory chip such as FeRAM (Ferroelectric Random Access Memory), or RRAM (Resistive Random Access Memory).

Alternatively, in example embodiments, the semiconductor chip 500 may be a logic chip. For example, the semiconductor chip 500 may be a Central Processor Unit (CPU), Micro Processor Unit (MPU), Graphic Processor Unit (GPU), or Application Processor (AP).

The lower semiconductor package 50 may include one semiconductor chip 500 or two or more semiconductor chips 500. Two or more semiconductor chips 500 included in the lower semiconductor package 50 may be the same type of semiconductor chip or may be different types of semiconductor chips. In example embodiments, the lower semiconductor package 50 may be a system in package (SIP) in which different types of semiconductor chips and various electronic components are electrically connected to each other and operate as one system.

The passive element 550 may be electrically connected to the semiconductor chip 500. In an exemplary embodiment, the passive element 550 may perform the function of at least one of a capacitor, an inductor, and a resist.

The wiring structure 600 may include an insulating layer 610, a wiring line pattern 633, and a wiring via pattern 635.

In an exemplary embodiment, the insulating layer 610 may be a layer of insulating material surrounding the semiconductor chip 500 and the passive element 550. For example, the insulating layer 610 is made of a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are impregnated into glass fiber together with an inorganic filler, prepreg, ABF (Ajinomoto Build- up Film), FR-4, BT (Bismaleimide Triazine), and PID (Photo Imagable Dielectric).

Additionally, the wiring line pattern 633 may be a wiring pattern extending horizontally within the insulating layer 610, and the wiring via pattern 635 may be a wiring pattern extending vertically within the insulating layer 610. there is.

The wiring line pattern 633 and the wiring via pattern 635 may be electrically connected to the semiconductor chip 500 and the passive element 550. In addition, the wiring line pattern 633 and the wiring via pattern 635 are electrically connected to the first antenna module 230 and the second antenna module 250 of the upper semiconductor package 10 through the package connection terminal 450. You can.

Accordingly, the semiconductor chip 500 may be electrically connected to the first and second antenna modules 230 and 250 of the upper semiconductor package 10 through the wiring line pattern 633 and the wiring via pattern 635.

The ground wall 670 of the lower semiconductor package 50 may surround the insulating layer 610. Additionally, the ground wall 670 of the lower semiconductor package 50 may be connected to a package connection terminal 450 that is electrically connected to the ground layer 120 and the ground wall 140 of the upper semiconductor package 10.

The external connection terminal 650 may be a terminal provided to electrically connect the semiconductor package 1 to an external device. In an exemplary embodiment, the external connection terminal 650 may be a solder ball made of a metal material including at least one of tin (Sn), silver (Ag), copper (Cu), and aluminum (Al).

In an exemplary embodiment, some of the external connection terminals 650 may be electrically connected to the wiring line pattern 633 and the wiring via pattern 635 of the lower semiconductor package 50. Additionally, some of the external connection terminals 650 may be electrically connected to the ground wall 670.

Figure 8 is a cross-sectional view of a semiconductor package 60 according to an exemplary embodiment of the present disclosure.

In addition, FIG. 9 is a cross-sectional view of the area indicated by IX-IX' in FIG. 8, FIG. 10 is a cross-sectional view of the area indicated by X-X' in FIG. 8, and FIG. 11 is a cross-sectional view of the area indicated by It is a cross-sectional view of the region, and FIG. 12 is a cross-sectional view of the region indicated by XII-XII' in FIG. 8.

Referring to FIGS. 8 to 12 together, the semiconductor package 60 according to an exemplary embodiment of the present disclosure includes a lower insulating layer 110, a ground layer 120, an upper insulating layer 130, and a ground wall 140. , first antenna module 230, second antenna module 250, third antenna module 270, redistribution line pattern 330, first to fourth redistribution via patterns (351, 353, 355, 357). ), a ground pattern 413, and a package connection terminal 450.

Hereinafter, overlapping content between the semiconductor package 10 of FIGS. 1 to 4 and the semiconductor package 60 of FIGS. 8 to 12 will be omitted and the differences will be mainly described.

The semiconductor package 60 according to an exemplary embodiment of the present disclosure may include a plurality of first antenna modules 230 and a plurality of second antenna modules 250. In an exemplary embodiment, when the semiconductor package 60 is viewed from a plan view, the plurality of first antenna modules 230 and the plurality of second antenna modules 250 have a row of M, which is an integer of 1 or more, and It can be arranged in the form of an M * N matrix consisting of M x N elements, including N columns, which are integers of 2 or more.

In an exemplary embodiment, as shown in FIGS. 9 to 12, a plurality of first antenna modules 230 and a plurality of second antenna modules 250 may be provided in numbers of four each, and the plurality of Each of the first antenna modules 230 and the plurality of second antenna modules 250 may be arranged in a 2*2 matrix shape composed of 4 elements including 2 rows and 2 columns.

However, it is not limited to the above, and as shown in FIGS. 1 to 4, a plurality of first antenna modules 230 and a plurality of second antenna modules 250 may be provided in numbers of four each, Each of the plurality of first antenna modules 230 and the plurality of second antenna modules 250 may be arranged in a 1 * 4 matrix shape consisting of 4 elements including a row of 1 and a column of 4. there is.

In an exemplary embodiment, the ground wall 140 may define a plurality of antenna placement spaces (A1_a to A1_d, A2) within the upper insulating layer 130. Additionally, among the plurality of antenna arrangement spaces (A1_a to A1_d, A2), the first antenna arrangement spaces (A1_a to A1_d) may be arranged in a matrix shape. Additionally, each of the plurality of first antenna placement spaces A1_a to A1_d may include a first antenna module 230 and a second antenna module 250.

Referring to FIG. 9, each of the plurality of second upper antenna patches 255 may be disposed in each of the plurality of first antenna arrangement spaces A1_a to A1_d. Additionally, each of the plurality of second upper antenna patches 255 may be separated by a ground wall 140.

Additionally, the third antenna module 270 may be placed in the second antenna patch space A2. Additionally, the third antenna module 270 may be distinguished from the plurality of second upper antenna patches 255 by the ground wall 140. In an exemplary embodiment, the third antenna module 270 may be disposed at substantially the same level as the plurality of second upper antenna patches 255.

Referring to FIG. 10, each of the plurality of second lower antenna patches 253 may be disposed in each of the plurality of first antenna arrangement spaces A1_a to A1_d, and the plurality of second upper antenna patches 255 and may be spaced apart in a vertical direction. Additionally, each of the plurality of second lower antenna patches 253 may be separated by a ground wall 140.

In an exemplary embodiment, the plurality of second lower antenna patches 253 may be electrically connected to the second redistribution via pattern 353. Additionally, the third antenna module 270 of FIG. 9 may be electrically connected to the fourth redistribution via pattern 357.

Referring to FIG. 11, each of the plurality of first upper antenna patches 235 may be disposed in each of the plurality of first antenna arrangement spaces A1_a to A1_d. Additionally, each of the plurality of first upper antenna patches 235 may be separated by a ground wall 140.

In an exemplary embodiment, the third redistribution via pattern 355 may pass through the first upper antenna patch 235 in the vertical direction. Additionally, when the semiconductor package 60 is viewed from a planar perspective, the third redistribution via pattern 355 may be spaced apart from the first upper antenna patch 235 in the horizontal direction.

Referring to FIG. 12, each of the plurality of first lower antenna patches 233 may be disposed in each of the plurality of first antenna arrangement spaces A1_a to A1_d, and the plurality of first upper antenna patches 235 and may be spaced apart in a vertical direction. Additionally, each of the plurality of first lower antenna patches 233 may be separated by a ground wall 140.

In an exemplary embodiment, the third redistribution via pattern 355 may pass through the first lower antenna patch 233 in the vertical direction. Additionally, when the semiconductor package 60 is viewed from a planar perspective, the third redistribution via pattern 355 may be spaced apart from the first lower antenna patch 233 in the horizontal direction. Additionally, the first redistribution via pattern 351 may be electrically connected to the first lower antenna patch 233.

FIG. 13 is a plan view of a semiconductor package 70 according to an exemplary embodiment of the present disclosure.

Referring to FIG. 13 , the semiconductor package 70 may include a first antenna module 230a, a second antenna module 230b, and a third antenna module 270a.

The first antenna module 230 and the second antenna module 250 described with reference to FIGS. 1 to 12 may overlap each other in the vertical direction. That is, the second antenna module 250 may be placed on top of the first antenna module 230.

However, the first antenna module 230a and the second antenna module 230b in FIG. 13 may not overlap in the vertical direction. That is, the second antenna module 230b may not be placed on top of the first antenna module 230a, but may be placed at substantially the same level as the first antenna module 230a.

Additionally, the first antenna module 230a, the second antenna module 250a, and the third antenna module 270a may be separated by a ground wall 140. Accordingly, interference between communication signals of the first to third antenna modules 230a, 250a, and 270a can be improved.

Figure 14 is a cross-sectional view of the semiconductor package 2 according to an exemplary embodiment of the present disclosure.

Referring to FIG. 14 , the semiconductor package 2 may include a package substrate 1000, an antenna package 10, a semiconductor chip 500a, and a molding layer 1100.

The package substrate 1000 may be a substrate for mounting the antenna package 10 and the semiconductor chip 500a. In an example embodiment, package substrate 1000 may include a printed circuit board (PCB). However, it is not limited to the above, and the package substrate 1000 may include a wafer or a carrier.

The antenna package 10 may be a semiconductor package including an antenna module. Since the content related to the antenna package 10 overlaps with the content described with reference to FIGS. 1 to 13, detailed information will be omitted.

The semiconductor chip 500a is a communication semiconductor chip connected electrically or capable of transmitting signals to the first and second antenna modules 230 and 250, and transmits and receives wireless signals through the first and second antenna modules 230 and 250. It may include a signal processing circuit for processing signals. For example, the semiconductor chip 500a may include a radio-frequency integrated circuit (RFIC).

In example embodiments, the semiconductor chip 500a may be, for example, a memory chip. The memory chip is, for example, a volatile memory semiconductor chip 500 such as Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM), Phase-change Random Access Memory (PRAM), or Magnetoresistive Random Access Memory (MRAM). ), it may be a non-volatile memory chip such as FeRAM (Ferroelectric Random Access Memory) or RRAM (Resistive Random Access Memory).

Alternatively, in example embodiments, the semiconductor chip 500a may be a logic chip. For example, the semiconductor chip 500a may be a Central Processor Unit (CPU), Micro Processor Unit (MPU), Graphic Processor Unit (GPU), or Application Processor (AP).

The semiconductor chip 500a may be electrically connected to the package substrate 1000 through the chip connection terminal 540.

The molding layer 1100 may be disposed on the package substrate 1000 and surround the antenna package 10 and the semiconductor chip 500a. In an exemplary embodiment, the molding layer 1100 may cover both the side and top surfaces of the antenna package 10 and the side and top surfaces of the semiconductor chip 500a.

In an exemplary embodiment, the material of molding layer 1100 may include epoxy molding compound (EMC). However, the material of the molding layer 1100 is not limited to the above.

Figure 15 is a cross-sectional view of the semiconductor package 3 according to an exemplary embodiment of the present disclosure.

Referring to FIG. 15 , the semiconductor package 2 may include a package substrate 1000, an antenna package 10, a semiconductor chip 500a, and a molding layer 1100a.

Hereinafter, overlapping content between the semiconductor package 2 of FIG. 14 and the semiconductor package 3 of FIG. 15 will be omitted and the differences will be mainly explained.

The molding layer 1100a may be disposed on the package substrate 1000 and cover at least a portion of the side surface of the antenna package 10 and at least a portion of the side surface of the semiconductor chip 500a. Additionally, the molding layer 1100a may expose the top surface of the antenna package 10 and the top surface of the semiconductor chip 500a.

In an example embodiment, the level of the top surface of the molding layer 1100a may be at a higher level than the first antenna module 230 and a lower level than the second antenna module 250. In other words, the level of the upper surface of the molding layer 1100a may be between the first upper antenna patch 235 of the first antenna module 230 and the second lower antenna patch 253 of the second antenna module 250. there is.

The level of the upper surface of the molding layer 1100a may be at a higher level than the first antenna module 230 and a lower level than the second antenna module 250, so that the wireless communication performance of the second antenna module 250 This can be improved.

As above, exemplary embodiments have been disclosed in the drawings and specification. In this specification, embodiments have been described using specific terms, but this is only used for the purpose of explaining the technical idea of the present disclosure and is not used to limit the meaning or scope of the present disclosure described in the claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present disclosure should be determined by the technical spirit of the attached claims.

Claims (17)

lower insulating layer;
a ground layer disposed on the lower insulating layer;
an upper insulating layer disposed on the ground layer;
a ground wall extending vertically from the ground layer to define a plurality of antenna placement spaces within the upper insulating layer;
a first antenna module disposed in a first antenna arrangement space among the plurality of antenna arrangement spaces;
a second antenna module disposed above the first antenna module in the first antenna placement space;
a third antenna module disposed in a second antenna arrangement space separated from the first antenna arrangement space among the plurality of antenna arrangement spaces;
a first redistribution via pattern extending vertically inside the upper insulating layer and electrically connected to the first antenna module; and
a second redistribution via pattern spaced apart from the first redistribution via pattern, extending vertically inside the upper insulating layer, and electrically connected to the second antenna module;
Including,
When viewed from the top, the second antenna module and the third antenna module are each surrounded by the ground wall, and the second antenna module and the third antenna module are spaced apart from each other with a part of the ground wall in between. Semiconductor package. According to claim 1,
The first antenna module is,
a first lower antenna patch disposed inside the upper insulating layer; And a first upper antenna patch disposed to be spaced apart from the first lower antenna patch in a vertical direction within the upper insulating layer,
The second antenna module is,
a second lower antenna patch disposed on top of the first upper antenna patch within the upper insulating layer; And a second upper antenna patch disposed to be vertically spaced apart from the second lower antenna patch inside the upper insulating layer,
A semiconductor package, wherein the first antenna module and the second antenna module are configured to perform communication in different frequency bands. According to clause 2,
a redistribution line pattern disposed between the first antenna module and the second antenna module; and
a third redistribution via pattern vertically passing through the ground layer, at least a portion of the upper insulating layer, the first lower antenna patch, and the first upper antenna patch and connected to the redistribution line pattern;
It further includes,
The first redistribution via pattern is,
Passing through at least a portion of the ground layer and the upper insulating layer in a vertical direction and connected to the first lower antenna patch,
The second redistribution via pattern is,
A semiconductor package extending in a vertical direction from the redistribution line pattern and connected to the second lower antenna patch. According to clause 3,
The side of the third redistribution via pattern is,
A semiconductor package, characterized in that the first lower antenna patch and the first upper antenna patch are spaced apart in the horizontal direction. According to clause 3,
The side surface of the first redistribution via pattern and the side surface of the third redistribution via pattern are,
A semiconductor package, characterized in that it is spaced apart from the ground layer in a horizontal direction. According to clause 3,
The third antenna module includes a PIFA antenna,
The semiconductor package is,
a fourth redistribution via pattern vertically passing through the ground layer and at least a portion of the upper insulating layer and connected to the third antenna module;
A semiconductor package further comprising: According to claim 1,
a ground pattern extending inside the lower insulating layer and connected to the ground layer and the ground wall;
A semiconductor package further comprising: According to clause 2,
a redistribution line pattern disposed between the first antenna module and the second antenna module; and
a third redistribution via pattern disposed outside the first antenna module, passing through at least a portion of the ground layer and the upper insulating layer, and connected to the redistribution line pattern;
It further includes,
The first redistribution via pattern is,
Passing through at least a portion of the ground layer and the upper insulating layer in a vertical direction and connected to the first lower antenna patch,
The second redistribution via pattern is,
A semiconductor package extending in a vertical direction from the redistribution line pattern and connected to the second lower antenna patch. According to clause 2,
a first redistribution line pattern disposed between the first antenna module and the second antenna module;
a second redistribution line pattern extending from an upper part of the first redistribution line pattern and connected to the second upper antenna patch;
a third redistribution line pattern disposed outside the first antenna module, passing through at least a portion of the ground layer and the upper insulating layer, and connected to the first redistribution line pattern; and
a fourth redistribution via pattern disposed outside the first antenna module, passing through at least a portion of the ground layer and the upper insulating layer, and connected to the second redistribution line pattern;
The first redistribution via pattern is,
Passing through at least a portion of the ground layer and the upper insulating layer in a vertical direction and connected to the first lower antenna patch,
The second redistribution via pattern is,
A semiconductor package extending in a vertical direction from the first redistribution line pattern and connected to the second lower antenna patch. According to clause 2,
The cross-sectional areas of the first lower antenna patch and the first upper antenna patch are,
A semiconductor package, characterized in that the cross-sectional area is larger than that of the second lower antenna patch and the second upper antenna patch. According to clause 2,
The vertical separation distance between the first lower antenna patch and the first upper antenna patch is 100 micrometers to 200 micrometers,
A semiconductor package, characterized in that the vertical separation distance between the second lower antenna patch and the second upper antenna patch is 100 micrometers to 200 micrometers. According to clause 2,
A semiconductor package, wherein the vertical separation distance between the first upper antenna patch and the second lower antenna patch is 100 micrometers to 400 micrometers. According to claim 1,
The first antenna module and the second antenna module are provided in plural pieces,
The plurality of first antenna modules are,
It is arranged in the form of an M*N matrix consisting of M
The plurality of second antenna modules are,
A semiconductor package disposed on top of the first antenna module so as to overlap the first antenna module in a vertical direction. According to claim 1,
the lower insulating layer, the ground layer, the upper insulating layer, the ground wall, the first antenna module, the second antenna module, the third antenna module, the first redistribution via pattern, and the second redistribution The via pattern constitutes the antenna package,
a package substrate on which the antenna package is mounted;
a semiconductor chip mounted on the package substrate; and
a molding layer disposed on the package substrate and surrounding the antenna package and the semiconductor chip;
A semiconductor package further comprising: According to claim 14,
The molding layer is,
A semiconductor package covering the side and top surfaces of the antenna package. According to claim 14,
The molding layer is,
A semiconductor package, characterized in that at least a portion of the top and side surfaces of the antenna package are exposed. According to claim 16,
The first antenna module includes a first lower antenna patch disposed inside the upper insulating layer; And a first upper antenna patch disposed to be spaced apart from the first lower antenna patch in a vertical direction within the upper insulating layer,
The second antenna module includes a second lower antenna patch disposed on top of the first upper antenna patch inside the upper insulating layer; And a second upper antenna patch disposed to be vertically spaced apart from the second lower antenna patch inside the upper insulating layer,
The level of the upper surface of the molding layer is,
A semiconductor package, characterized in that it is higher than the level of the upper surface of the first upper antenna patch of the first antenna module and lower than the level of the lower surface of the second lower antenna patch of the second antenna module.

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