KR102577263B1 - Semiconductor device - Google Patents

Abstract

A semiconductor device according to an embodiment of the present invention includes a substrate, a plurality of semiconductor devices formed on the substrate, a plurality of metal lines electrically connected to at least one of the plurality of semiconductor devices, and a plurality of metal lines on the plurality of metal lines. It is disposed and includes a protective layer having an open area that exposes some of the plurality of metal lines to provide a plurality of pads, wherein a first pad of the plurality of pads extends from at least one of the plurality of metal lines. It has a first area and a second area disposed around the first area and separated from the first area.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The present invention relates to semiconductor devices.

Electronic products are becoming smaller in size while requiring high-capacity data processing. Accordingly, there is a need to increase the integration degree of semiconductor devices used in such electronic products. The semiconductor device may include a plurality of pads for receiving electrical signals from the outside, and at least one of the plurality of pads may function as a sensor pad to check the alignment state of the probe connected to the plurality of pads. there is.

One of the technical problems to be achieved by the technical idea of the present invention is to increase the integration of semiconductor devices by providing a pad that can provide both a function for checking the alignment state of the probe and a function as a general pad. there is.

A semiconductor device according to an embodiment of the present invention includes a substrate, a plurality of semiconductor devices formed on the substrate, a plurality of metal lines electrically connected to at least one of the plurality of semiconductor devices, and a plurality of metal lines on the plurality of metal lines. It is disposed on and includes a protective layer having an open area exposing a portion of the plurality of metal lines to provide a plurality of pads, wherein the first pad included in the plurality of pads is at least one of the plurality of metal lines. It has a first area connected to and a second area disposed around the first area and electrically separated from the first area.

A semiconductor device according to an embodiment of the present invention includes a substrate, a plurality of memories having a channel region extending in a direction perpendicular to the upper surface of the substrate, and a plurality of gate electrode layers stacked on the substrate adjacent to the channel region. A cell element, a plurality of circuit elements disposed around the plurality of memory cell elements, a plurality of metal lines electrically connected to at least some of the plurality of memory cell elements and the plurality of circuit elements, and the plurality of metal lines It is provided on the protective layer and includes a protective layer that exposes some of the plurality of metal lines to provide a plurality of pads, wherein the plurality of pads includes a first region connected to at least one of the plurality of metal lines and the first region connected to the first region. It includes a first pad disposed around one area and having a second area electrically separated from the first area.

A semiconductor device according to an embodiment of the present invention includes a cell region having a plurality of memory cell elements, a peripheral circuit region having a plurality of circuit elements that drive the plurality of memory cell elements, and the cell region and the peripheral circuit region. supplies an electric signal to the pad, and includes a plurality of pads having first and second pads having different shapes, wherein the first pad is used to supply an electric signal to at least one of the cell region and the peripheral circuit region. It has a first area provided as a normal pad and a second area provided as a sensor pad for detecting the alignment state of the probes connected to the plurality of pads.

According to a memory device according to the technical idea of the present invention, at least one of the plurality of pads included in the semiconductor device may include a sensing area that can check the probe alignment state and a contact area that can operate as a general pad. . Accordingly, since at least one of the plurality of pads may not be provided as a separate sensor pad, the degree of integration of the semiconductor device can be improved.

The various and beneficial advantages and effects of the present invention are not limited to the above-described content, and may be more easily understood through description of specific embodiments of the present invention.

1 is a diagram showing a schematic layout of a semiconductor device according to an embodiment of the present invention.
FIG. 2A is a partial enlarged view showing a pad area of a semiconductor device according to an embodiment of the present invention.
FIG. 2B is a cross-sectional view showing a cross section in the II′ direction of the semiconductor device shown in FIG. 2A.
3 and 4 are partial enlarged views showing the pad area of a semiconductor device according to an embodiment of the present invention.
5 and 6 are diagrams illustrating a circuit provided to check the probe alignment state in a semiconductor device according to an embodiment of the present invention.
FIG. 7 is a flowchart provided to explain a method for checking the probe alignment state in a semiconductor device according to an embodiment of the present invention.
8 to 10 are diagrams illustrating the operation of a circuit provided to check the alignment state of a probe in a semiconductor device according to an embodiment of the present invention.
11 and 12 are block diagrams showing an electronic device including a memory device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings.

Throughout the specification, when referring to one component, such as a film, region, or wafer (substrate), being positioned “on,” “connected to,” or “coupled to” another component, it refers to one of the components described above. It can be interpreted that an element may be directly “on,” “connected,” or “coupled” and in contact with another component, or that there may be other components interposed between them. On the other hand, when a component is referred to as being located "directly on," "directly connected to," or "directly coupled" to another component, it is interpreted that there are no intervening components. do. Identical symbols refer to identical elements. As used herein, the term “and/or” includes any one and all combinations of one or more of the listed items.

Although the terms first, second, etc. are used herein to describe various members, parts, regions, layers and/or parts, these members, parts, regions, layers and/or parts are limited by these terms. It is obvious that does not work. These terms are used only to distinguish one member, component, region, layer or section from another region, layer or section. Accordingly, a first member, component, region, layer or portion described below may refer to a second member, component, region, layer or portion without departing from the teachings of the present invention.

Additionally, relative terms such as “top” or “over” and “bottom” or “under” may be used herein to describe the relationship of some elements to other elements as illustrated in the drawings. Relative terms may be understood as intended to include other orientations of the device in addition to the orientation depicted in the drawings. For example, if an element is turned over in the figures, elements depicted as being on the upper side of other elements will have an orientation on the lower side of the other elements as described above. Therefore, the term "top" as an example may include both the "bottom" and "top" directions depending on the specific orientation of the drawing. If the component is oriented in another direction (rotated 90 degrees relative to the other direction), relative descriptions used herein may be interpreted accordingly.

The terms used herein are used to describe specific embodiments and are not intended to limit the invention. As used herein, the singular forms include the plural forms unless the context clearly indicates otherwise. Additionally, when used herein, “comprise” and/or “comprising” means specifying the presence of stated features, numbers, steps, operations, members, elements and/or groups thereof. and does not exclude the presence or addition of one or more other shapes, numbers, operations, members, elements and/or groups.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will now be described with reference to drawings that schematically show ideal embodiments of the present invention. In the drawings, variations of the depicted shape may be expected, for example, depending on manufacturing technology and/or tolerances. Accordingly, embodiments of the present invention should not be construed as being limited to the specific shape of the area shown in this specification, but should include, for example, changes in shape resulting from manufacturing. The following embodiments may be configured by combining one or more embodiments.

The content of the present invention described below may have various configurations, and only the necessary configurations are presented here as examples, and the content of the present invention is not limited thereto.

1 is a diagram showing a schematic layout of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1 , a semiconductor device 10 according to an embodiment of the present invention may be a memory device having cell regions 11 and 12 having memory cell elements capable of storing data. The cell areas 11 and 12 may be divided into one or multiple areas, and the row decoder 13 and the column decoder 14 may be placed adjacent to the cell areas 11 and 12. The column decoder 14 may provide read/write circuitry together with the page buffer 15. The control circuit 16 may control the overall operation of the semiconductor device 10 . The row decoder 13, column decoder 14, page buffer 15, and control circuit 16 excluding the cell areas 11 and 12 may be provided as peripheral circuit areas.

The cell regions 11 and 12 may include a plurality of memory cell elements. In one embodiment, the semiconductor device 10 according to an embodiment of the present invention may be a memory device with a horizontal or vertical structure, where the cell regions 11 and 12 have a channel region, a gate electrode layer, a gate insulating film, etc. A plurality of cell elements may be included. A plurality of memory cell elements included in the cell areas 11 and 12 include a word line (WL), a common source line (CSL), a string select line (SSL), and a ground selection line. It can be connected to the row decoder 13 through a ground select line (GSL), etc., and can be connected to the column decoder 14 through a bit line (Bit Line, BL).

The row decoder 13 receives address information from the outside, decodes the received address information (ADDR), and outputs the word line (WL), common source line (CSL), and string selection line (WL) connected to the cell areas (11, 12). At least some of the SSL) and ground selection lines (GSL) can be selected.

The column decoder 14 may select at least some of the bit lines BL connected to the cell areas 11 and 12 according to a command received from the control circuit 16. The column decoder 14 and the page buffer 15 read data stored in memory cell elements connected to at least some of the selected bit lines BL, or read data into the memory cell elements connected to at least some of the selected bit lines BL. can be recorded.

The control circuit 16 may control the operations of the row decoder 13, column decoder 14, and page buffer 15 in response to control signals transmitted from the outside. When reading data stored in the cell areas 11 and 12, the control circuit 16 operates the row decoder 13 to supply a voltage for a read operation to the word line WL where the data to be read is stored. You can control it. When a voltage for a read operation is supplied to a specific word line (WL), the control circuit 16 operates a column decoder (14) to read data stored in a memory cell element connected to the word line (WL) to which a voltage for a read operation is supplied. ) and the operation of the page buffer 15 can be controlled.

Meanwhile, when writing data to the cell areas 11 and 12, the control circuit 16 controls the operation of the row decoder 13 to supply a voltage for a write operation to the word line (WL) on which data is to be written. can do. When the voltage for a write operation is supplied to a specific word line (WL), the control circuit 13 uses the column decoder 14 to write data to the memory cell element connected to the word line (WL) to which the voltage for the write operation is supplied. and the operation of the page buffer 15 can be controlled.

Meanwhile, a plurality of pads 17 may be provided at the edge of the semiconductor device 10. The plurality of pads 17 may be an area where at least a portion of the plurality of metal lines provided in the semiconductor device 10 is exposed. Electrical signals required for operation may be supplied to memory cell elements included in the cell areas 11 and 12 and circuit elements included in the peripheral circuit area through the plurality of pads 17 .

In a test process performed after manufacturing the semiconductor device 10, electrical signals necessary for testing the semiconductor device 10 may be applied through a plurality of probes in contact with the plurality of pads 17. In order to accurately test the semiconductor device 10, a plurality of probes must be accurately aligned with each of the plurality of pads 17, and the semiconductor device 10 may provide a circuit that can check the alignment of the probes. In particular, the semiconductor device 10 according to an embodiment of the present invention can provide a function for checking the alignment state of a probe and a function as a general pad in one pad.

FIG. 2A is a partial enlarged view showing a pad area of a semiconductor device according to an embodiment of the present invention. Meanwhile, FIG. 2B is a cross-sectional view showing a cross section in the II′ direction of the semiconductor device shown in FIG. 2A.

FIG. 2A may be an enlarged view of area A of the semiconductor device 10 shown in FIG. 1. First, referring to FIG. 2A, region A of the semiconductor device 10 may include a plurality of pads 100, 200, and 300. The plurality of pads 100, 200, and 300 may include a first pad 100 that provides a function to check the alignment state of the probe, and second pads 200 and 300 other than the first pad 100. You can. The second pads 200 and 300 cannot provide a function for checking the alignment state of the probe, and may be provided as general pads that supply an electrical signal to at least one of a plurality of semiconductor devices.

Each of the plurality of pads 100, 200, and 300 may be provided with a portion of the metal line 410 included in the semiconductor device 10 exposed to the outside. Referring to FIG. 2B, the metal line 410 may be disposed on the upper part of the semiconductor substrate region 101 including the semiconductor device, and the first metal line 411 and the first metal line 411 located relatively lower. ) may include a second metal line 412 located above. A protective layer 420 having insulating properties may be provided on the metal line 410, and a portion of the metal line 410 may be formed through the open areas 421, 422, and 423 formed by removing a portion of the protective layer 420. A plurality of pads 100, 200, and 300 may be formed by being exposed to the outside. As shown in FIG. 2B, a portion of the protective layer 420 may be removed from the open area 421 and a portion of the metal line 410 may be exposed to the outside.

The first pad 100 includes a contact area 110 electrically connected to the metal line 410 and a sensing area 120 that is electrically separated from the contact area 110 and disposed around the contact area 110. can do. The sensing area 120 may be placed adjacent to the edge of the open area 421, and as shown in FIGS. 2A and 2B, at least a portion of the sensing area 120 is not exposed by the open area 421. It may be shielded by the protective layer 420.

The contact area 110 may include a first area 111 and a second area 112 . The first area 111 may have a relatively large area compared to the second area 112, and the sensing area 120 may be disposed adjacent to the edge of the first area 111. The second area 112 is an area extending from a corner of the first area 111, and the contact area 110 can be electrically connected to the metal line 410 by the second area 112. In the embodiment shown in FIG. 2A, the first area 111 is shown as having a rectangular shape, but it is not necessarily limited to this shape. The second area 112 may have a plurality of second areas 112 extending in different directions from opposite corners of the first area 111 .

Meanwhile, the second region 112 may be electrically connected to the first metal line 411 disposed relatively lower through a plurality of vias 150. The second area 112 may be connected to a switching circuit having at least one switch element through the first metal line 411, and the switching circuit may be connected to the first and second circuits. In one embodiment, the first circuit may be a circuit that detects the alignment state of the probe, and the second circuit may be a circuit that supplies an electrical signal to a semiconductor element included in the semiconductor device 10. Meanwhile, the switching circuit may also be electrically connected to the first region 111 through the metal line 410.

Accordingly, by the operation of the switching circuit, the first pad 100 is connected to the first circuit and functions as a sensor pad for checking the alignment state of the probe, or is connected to the second circuit to operate the semiconductor device 10 ) can operate as a general pad to supply electrical signals to semiconductor devices. The configuration and operation of the switching circuit and the first circuit capable of detecting the alignment state of the probe will be described later.

The second and third pads 200 and 300 are provided as general pads that supply electrical signals to semiconductor devices, and may have a shape that fills the open areas 422 and 423 from which the protective layer 420 has been removed. Common pads, such as the second and third pads 200 and 300, may be connected to the lower metal line through the via 250, or may be directly connected to the second metal line 412 at the edge of the open area 423. there is. The shape and number of the second and third pads 200 and 300 may vary depending on the semiconductor device 10 .

3 and 4 are partial enlarged views showing the pad area of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3, the first pad 100A may be implemented in a shape different from the embodiment shown in FIGS. 2A and 2B. In the first pad 100A, the contact area 110A may include a first area 111A and a second area 112A, and at least a portion of the first area 111A is in the open area 421. It may be shielded by the protective layer 420 without being exposed. The second area 112A may be provided as one area, and a sensing area 120A may be provided adjacent to a portion of a corner of the first area 111A.

Similar to the embodiment previously described with reference to FIGS. 2A and 2B, the contact area 110A is electrically connected to the second metal line 412 through the second area 112A, and the sensing area 120A is connected to the via ( It may be electrically connected to the first metal line 411 through 150). The contact area 110A and the sensing area 120A may be electrically connected to or separated from each other through a switching circuit having at least one switch element. Whether the contact area 110A and the sensing area 120A are connected/disconnected may be determined depending on whether the probe is accurately aligned with the pads 100, 200, and 300 in the test process.

In the embodiment shown in FIG. 4, the first pad 100B may have a different shape from the embodiment shown in FIGS. 2A, 2B, and 3. The contact area 110B in the first pad 100B may include a first area 111B and a second area 112B, and the entire first area 111B may be exposed by the open area 421. You can. The second area 112B may be provided as one area extending from one corner of the first area 111B, and the sensing area 120B may be provided as an area extending from the first area 111B without contacting the second area 112B. ) can be arranged to surround the edges of the. That is, unlike the embodiments of FIGS. 2A, 2B, and 3 in which the sensing area 120B is provided as a plurality of separate areas, in the embodiment shown in FIG. 4, the sensing area 120B is provided as one area. It can be.

Similar to the embodiment shown in FIGS. 2A, 2B, and 3, the sensing area 120B is connected to the lower first metal line 411 through the via 150, and the contact area 110B is connected to the second metal line 411. It may be connected to the upper second metal line 412 through the area 112B. A switching circuit is connected between the sensing area 120B and the contact area 110B, and according to the operation of the switching circuit, the first pad 100B operates as one of a sensor pad for checking the alignment of the probe and a general pad. can do.

5 and 6 are diagrams illustrating a circuit provided to check the probe alignment state in a semiconductor device according to an embodiment of the present invention.

First, referring to FIG. 5, a switching circuit 500 having a plurality of switch elements (SW1-SW4) may be connected between the contact area 110 and the sensing area 120. The configuration of the switching circuit 500 is not limited to that shown in FIG. 5, and various configurations can be used to establish the connection between the first pad 100 and the first and second circuits 510 and 520 depending on the alignment state of the probe. It can be implemented as a circuit of this type.

One end of the switching circuit 500 may be connected to the first and second circuits 510 and 520. The first circuit 510 may be a circuit for outputting a predetermined confirmation voltage when the probe is not accurately aligned. When the probe is accurately aligned, the second circuit 520 is connected to the first pad 100 and can transmit the electrical signal supplied to the first pad 100 to the semiconductor device.

In one embodiment, if the probe is not accurately aligned with the first pad 100, that is, when the probe contacts the sensing area 120 of the first pad 100, the first and second switches SW1 and SW2 may be turned on and the third and fourth switches SW3 and SW4 may be turned off. Accordingly, the first circuit 510 and the sensing area 120 of the first pad 100 may be electrically connected through the switching circuit 500.

When the probe is accurately aligned with the first pad 100, the second switch SW2 may be turned off and the remaining first, third, and fourth switches SW1, SW3, and SW4 may be turned on. Accordingly, the contact area 110 and the sensing area 120 can be connected to the second circuit 520, and the electrical signal supplied to the first pad 100 can be transmitted to the second circuit 520 and the semiconductor device. there is.

Next, referring to FIG. 6 , the first circuit 510 may include an input circuit 511, an inverter circuit 513, and an output circuit 515. The input circuit 511 may include resistors R1 and R2 and switch elements TR1 and TR2, and the inverter circuit 513 may include a plurality of inverters INV1 and INV2. The output circuit 515 may include a switch TR3 whose output terminal is electrically connected to the second pad 200.

To check the alignment of the probe, after the probe contacts the first pad 100, a ground voltage (VSS) may be supplied through the probe. Meanwhile, the switch circuit 500 turns on the first and second switches (SW1 and SW2) and turns off the third and fourth switches (SW3 and SW4) to set the ground voltage (VSS) to the first circuit ( 510).

When the ground voltage is transmitted to the first circuit 510, the inverter circuit 513 may output a low signal. Due to the output of the inverter circuit 513, the switch element TR3 included in the output circuit 515 is turned on and the power supply voltage VDD can be detected through the second pad 200. That is, when the ground voltage (VSS) is supplied to the first pad 100 and the power supply voltage (VDD) is detected at the second pad 200, it may be determined that the probe is not properly aligned.

Conversely, when the ground voltage (VSS) is supplied to the first pad 100 and the first and second switches (SW1 and SW2) are turned on, the power supply voltage (VDD) is not detected at the second pad 200. Otherwise, it can be determined that the probe is properly aligned. If it is determined that the probe is properly aligned, the switch circuit 500 turns on the first, third, and fourth switches (SW1, SW3, and SW4) excluding the second switch (SW2) to open the first pad (100). ) of the contact area 110 and the sensing area 120 may be electrically connected to each other. Thereafter, the electrical signal supplied from the probe in contact with the first pad 100 may be transmitted to the second circuit 520. Accordingly, after using the first pad 100 for the purpose of checking the probe alignment, it can be used for the purpose of supplying an electrical signal like any other general second pad 200.

FIG. 7 is a flowchart provided to explain a method for checking the probe alignment state in a semiconductor device according to an embodiment of the present invention.

First, in order to check the alignment of the probe, the probe of the test device may contact the pads 100, 200, and 300 of the semiconductor device 10 according to an embodiment of the present invention (S10). When the probe is contacted, the test device may supply a ground voltage (VSS) through the probe in contact with the first pad 100 having the sensing area 120 (S11). That is, the ground voltage (VSS) may be supplied to the first pad 100. At this time, the switching circuit 500 electrically connected to the first pad 100 turns on the first and second switches (SW1 and SW2) and turns off the third and fourth switches (SW3 and SW4). The first pad 100 can be operated in a sensing mode to check the probe alignment state.

When the ground voltage (VSS) is supplied to the first pad 100, the test device connects the second pad 200 to the sensing circuit connected to the sensing area 120 - the first circuit 510 in FIGS. 5 and 6. It is determined whether the power supply voltage (VDD) is detected (S12). As described above, when the probe contacts the sensing area 120, that is, when the probe is not properly aligned, the power supply voltage VDD may be detected at the second pad 200.

If the power supply voltage VDD is detected at the second pad 200 as a result of the determination in step S12, the test device may realign the position of the probe and then re-contact the probe with the pad of the semiconductor device 10. Afterwards, it is possible to determine whether the probe is properly aligned by going through the probe alignment status inspection process including steps S11 and S12 again.

If the power supply voltage VDD is not detected at the second pad 200 as a result of the determination in step S12, the test device determines that the probe is properly aligned and can proceed with the test of the semiconductor device 10 (S14). While testing the semiconductor device 10, the first, third, and fourth switches (SW1, SW3, SW4) excluding the second switch (SW2) in the switching circuit 500 connected to the first pad 100 is turned on so that the sensing area 120 and the contact area 110 can be electrically connected to each other. Accordingly, the entire area of the first pad 100 can function as a normal pad like the second and third pads 200 and 300.

8 to 10 are diagrams illustrating the operation of a circuit provided to check the alignment state of a probe in a semiconductor device according to an embodiment of the present invention.

First, referring to FIG. 8 , the first probe (P1) may contact the first pad 100 and the second probe (P2) may contact the second pad 200. The contact area 110 and the sensing area 120 of the first pad 100 may be connected to the switching circuit 500, and the switching circuit 500 may be connected to the first circuit 510 and the second circuit 520. You can. Meanwhile, the second pad 200 may be connected to the second circuit 520 and the third circuit 530. The first circuit 510 may be a sensing circuit that operates when checking the probe alignment state, and the second and third circuits 520 and 530 may be a sensing circuit that operates through the first and second pads 100 and 200, respectively. It may be a circuit for transmitting electrical signals to internal circuits and elements of the semiconductor device 10.

When the first and second probes (P1, P2) contact the first and second pads (100, 200), respectively, the switching circuit 500 turns on the first and second switches (SW1, SW2) The third and fourth switches (SW3 and SW4) can be turned off. Accordingly, the electrical signal supplied from the first probe P1 in contact with the first pad 100 may be transmitted only to the first circuit 510 and not to the second circuit 520. At this time, the electrical signal supplied from the first probe P1 can be transmitted to the first circuit 510 only when the first probe P1 contacts the sensing area 120. That is, when the first probe P1 touches the contact area 110, the electrical signal supplied from the first probe P1 is not transmitted anywhere.

The test device with the probes P1 and P2 in contact with the semiconductor device 10 may supply the ground voltage VSS through the first probe P1 in contact with the first pad 100 . When the first probe (P1) touches the sensing area 120 of the first pad 100, the ground voltage (VSS) is transmitted to the first circuit 510 and is transmitted to the second pad 200 by the output circuit 515. ), the power supply voltage (VDD) can be output. That is, when the ground voltage (VSS) is supplied through the first probe (P1) and the power voltage (VDD) is detected by the second probe (P2), the test device is applied to the sensing area 120 of the first probe (P1). It can be judged that they are in contact, that is, the probes (P1, P2) are not properly aligned.

Unlike the embodiment shown in FIG. 8, when the first probe (P1) contacts the contact area 110 of the first pad 100, even if the ground voltage (VSS) is supplied through the first probe (P1) The power supply voltage VDD may not be detected from the second probe P2. Referring to FIG. 9, when the ground voltage (VSS) is supplied through the first probe (P1) in contact with the contact area 110, the contact area 110 is not connected to the first circuit 510, so the ground voltage (VSS) cannot be delivered to the first circuit 510. Accordingly, the power supply voltage VDD is not detected from the second probe P2 in contact with the second pad 200, and the test device can determine that the probes P1 and P2 are properly aligned.

If it is determined that the probes (P1, P2) are properly aligned, the switching circuit 500 can turn on the first, third, and fourth switches (SW1, SW3, and SW4) except the second switch (SW2). There is. Referring to FIG. 10, the first, third, and fourth switches SW1, SW3, and SW4 are turned on so that the contact area 110 and the sensing area 120 are electrically connected to each other. Additionally, both the contact area 110 and the sensing area 120 may be connected to the second circuit 520 and may be electrically separated from the first circuit 510.

Therefore, the electrical signal supplied through the first probe (P1) can only be transmitted to the second circuit 520 even if the first probe (P1) touches either the contact area 110 or the sensing area 120. there is. The second circuit 520 may be a circuit for transmitting an electrical signal transmitted to the first pad 100 to elements within the semiconductor device 10 . Since the electrical signal supplied through the first probe P1 is transmitted to the element inside the semiconductor device 10 through the first pad 100 and the second circuit 520, the first pad 100 is connected to the other pads. Likewise, it can be provided as a normal pad. That is, the functions of a sensor pad for checking the probe alignment state and a normal pad for supplying a general signal can be implemented together in one first pad 100.

11 and 12 are block diagrams showing an electronic device including a memory device according to an embodiment of the present invention.

Referring to FIG. 11, the storage device 1000 according to an embodiment may include a controller 1010 that communicates with a host (HOST) and memories 1020-1, 1020-2, and 1020-3 that store data. You can. Each memory 1020-1, 1020-2, and 1020-3 may include memory devices according to various embodiments described above.

The host (HOST) that communicates with the controller 1010 may be various electronic devices equipped with the storage device 1000, for example, a smartphone, digital camera, desktop, laptop, media player, etc. The controller 1010 receives a data write or read request sent from the host (HOST) and stores the data in the memory (1020-1, 1020-2, 1020-3), or stores the data in the memory (1020-1, 1020-2, A command (CMD) to retrieve data from 1020-3) can be created.

As shown in FIG. 11, one or more memories 1020-1, 1020-2, and 1020-3 within the storage device 1000 may be connected in parallel to the controller 1010. By connecting a plurality of memories 1020-1, 1020-2, and 1020-3 in parallel to the controller 1010, a storage device 1000 with a large capacity, such as a solid state drive (SSD), can be implemented.

Next, referring to FIG. 12, the electronic device 2000 according to an embodiment may include a communication unit 2010, an input unit 2020, an output unit 2030, a memory 2040, and a processor 2050.

The communication unit 2010 may include a wired/wireless communication module, a wireless Internet module, a short-range communication module, a GPS module, a mobile communication module, etc. The wired/wireless communication module included in the communication unit 2010 can be connected to an external communication network according to various communication standards to transmit and receive data.

The input unit 2020 is a module provided for the user to control the operation of the electronic device 2000, and may include a mechanical switch, a touch screen, a voice recognition module, etc. Additionally, the input unit 2020 may include a mouse or finger mouse device that operates in a trackball or laser pointer manner, and may further include various sensor modules through which the user can input data.

The output unit 2030 outputs information processed by the electronic device 2000 in the form of audio or video, and the memory 2040 can store programs or data for processing and control of the processor 2050. . The memory 2040 may include one or more memory devices according to various embodiments, and the processor 2050 may store or retrieve data by transmitting instructions to the memory 2040 according to necessary operations.

The memory 2040 may be built into the electronic device 2000 or may communicate with the processor 2050 through a separate interface. When communicating with the processor 2050 through a separate interface, the processor 2050 can store or retrieve data from the memory 2040 through various interface standards such as SD, SDHC, SDXC, MICRO SD, USB, etc. .

The processor 2050 can control the operation of each part included in the electronic device 2000. The processor 2050 may perform control and processing related to voice calls, video calls, data communications, etc., or may perform control and processing for multimedia playback and management. Additionally, the processor 2050 can process input received from the user through the input unit 2020 and output the result through the output unit 2030. Additionally, as described above, the processor 2050 may store in or retrieve data necessary for controlling the operation of the electronic device 2000 in the memory 2040.

The present invention is not limited by the above-described embodiments and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various forms of substitution, modification, and change may be made by those skilled in the art without departing from the technical spirit of the present invention as set forth in the claims, and this also falls within the scope of the present invention. something to do.

10: memory device
100, 200, 300: Pad
110: contact area
120: Sensing area

Claims (20)

Board;
a plurality of semiconductor devices formed on the substrate;
a plurality of metal lines electrically connected to at least one of the plurality of semiconductor devices; and
a protective layer disposed on the plurality of metal lines and having an open area exposing a portion of the plurality of metal lines to provide a plurality of pads;
a switching circuit connected to a first pad among the plurality of pads; and
It includes first and second circuits connected to the switching circuit,
The first pad has a first area extending from at least one of the plurality of metal lines, and a second area disposed around the first area and separated from the first area,
The semiconductor device is characterized in that the output terminal of the first circuit is connected to a second pad among the plurality of pads, which is different from the first pad.
delete delete delete delete delete delete delete delete delete delete delete According to paragraph 1,
The semiconductor device is characterized in that the first circuit outputs a confirmation voltage that can check the alignment state of the probe contacting each of the first and second pads to the second pad.
According to paragraph 1,
The switching circuit is a semiconductor device characterized in that when a probe touches the first pad, the voltage supplied to the first pad is transmitted to the first circuit.
According to clause 14,
The switching circuit is configured to transfer the voltage supplied to the first pad to the second circuit if a predetermined reference voltage is not detected from the second pad when the voltage supplied to the first pad is transmitted to the first circuit. A semiconductor device characterized in that it transmits
Board;
a plurality of memory cell elements having a channel region extending in a direction perpendicular to the upper surface of the substrate and a plurality of gate electrode layers stacked on the substrate adjacent to the channel region;
a plurality of circuit elements disposed around the plurality of memory cell elements;
a plurality of metal lines electrically connected to at least some of the plurality of memory cell elements and the plurality of circuit elements; and
a protective layer provided on the plurality of metal lines and exposing a portion of the plurality of metal lines to provide a plurality of pads; Includes,
The plurality of pads include a first pad having a first area connected to at least one of the plurality of metal lines and a second area disposed around the first area and electrically separated from the first area. A semiconductor device characterized in that.
According to clause 16,
The plurality of pads include a second pad different from the first pad, and the second pad has a shape different from the first pad.
According to clause 16,
The plurality of metal lines include a first metal line and a second metal line disposed above the first metal line,
A semiconductor device, wherein the plurality of pads are disposed between the second metal lines.
According to clause 18,
The first region is electrically connected to the second metal line.
a cell region having a plurality of memory cell elements;
a peripheral circuit area having a plurality of circuit elements that drive the plurality of memory cell elements; and
a plurality of pads that supply electrical signals to the cell region and the peripheral circuit region and have first and second pads having different shapes; Includes,
The first pad includes a first area provided as a normal pad for supplying an electrical signal to at least one of the cell area and the peripheral circuit area, and a sensor pad for detecting the alignment state of the probes connected to the plurality of pads. A semiconductor device characterized by having a second region provided as.

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