KR102574597B1 - Light emitting display device - Google Patents

Abstract

The present application provides a light emitting display device capable of improving light extraction efficiency of light emitted from a light emitting device. The light emitting display device according to the present application includes a light emitting device having a light emitting layer between a first electrode and a second electrode, and a light emitting device. and a non-flattening layer having a plurality of grooves provided between the light emitting element and the wavelength conversion layer, and a shortest distance between a bottom surface of the grooves and the wavelength conversion layer may be 0.1 micrometer or more.

Description

Light emitting display device {LIGHT EMITTING DISPLAY DEVICE}

The present application relates to a light emitting display device.

A light emitting display device has a high response speed, low power consumption, and unlike a liquid crystal display device, since it is self-emitting and does not require a separate light source, it has no problem with a viewing angle, and thus is attracting attention as a next-generation flat panel display device.

A light emitting display device displays an image by emitting light from a light emitting device including a light emitting layer interposed between two electrodes. At this time, the light generated according to the light emission of the light emitting element is emitted to the outside through the electrode and the substrate.

However, in the light emitting display device, light extraction efficiency decreases as some of the light emitted from the light emitting layer is not emitted to the outside due to total reflection at an interface between the light emitting layer and the electrode or at an interface between the substrate and the air layer. Accordingly, the light emitting display device has problems in that luminance is lowered and power consumption is increased due to low light extraction efficiency.

A technical problem of the present application is to provide a light emitting display device capable of improving light extraction efficiency of light emitted from a light emitting device.

In order to achieve the object as described above, the present invention is a light emitting element having a light emitting layer between a first electrode and a second electrode, a wavelength conversion layer overlapping the light emitting element; and a non-planarization layer having a plurality of grooves provided between the light emitting element and the wavelength conversion layer, wherein a shortest distance between a bottom surface of the grooves and the wavelength conversion layer is 0.1 micrometer or more.

At this time, the shortest distance between the bottom surface of the grooves and the wavelength conversion layer is 3 micrometers or less, and a circuit region having a thin film transistor connected to the first electrode of the light emitting device and supporting the wavelength conversion layer while covering the circuit region and a second insulating layer covering the first insulating layer and the wavelength conversion layer, wherein the non-planarization layer is provided on the second insulating layer overlapping the wavelength conversion layer.

The second insulating layer provided between the bottom surfaces of the grooves and the wavelength conversion layer has a thickness of 0.1 to 3 micrometers, and includes a barrier layer covering the wavelength conversion layer; and a second insulating layer covering the barrier layer, wherein the non-planarization layer is provided on the second insulating layer overlapping the wavelength conversion layer, and the barrier layer is formed on bottom surfaces of the grooves and the wavelength conversion layer. has a thickness corresponding to the shortest distance between them.

In addition, the barrier layer has a thickness of 0.1 to 3 micrometers, and includes a circuit region having a thin film transistor connected to the first electrode of the light emitting device; and a first insulating layer covering the circuit region and supporting the wavelength conversion layer, wherein the barrier layer further covers the first insulating layer on the circuit region.

At this time, the barrier layer is made of the same material as the first insulating layer, and the non-flattening layer further includes a barrier defining each of the plurality of grooves, the barrier comprising: a bottom portion adjacent to the wavelength conversion layer; It includes a top part spaced apart from the bottom part by a set height and a side part between the bottom part and the top part.

In addition, a cross-sectional area of the barrier parallel to the wavelength conversion layer increases as it approaches the wavelength conversion layer, and the side surface portion has a curved shape including an inflection point.

At this time, each of the first electrode, the light emitting layer, and the second electrode has a shape following the shape of the non-flattening layer, and the side surface portion includes an inflection portion including an inflection point, and a first inflection portion between the inflection portion and the bottom portion. It includes a curved part and a second curved part between the inflection part and the top part, and the thickness of the light emitting element covering the inflection part is smaller than the thickness of the light emitting element covering each of the first curved part and the second curved part, wherein the Based on the height of the barrier, a height ratio of each of the first curved portion, the inflection portion, and the second curved portion is 1:3:1.

At this time, the barrier has an aspect ratio of a height to a size of a bottom portion of 0.4 to 0.7, and bottom portions of adjacent barriers are spaced apart from each other.

Further, the bottom portion is spaced apart from 0.3 to 10 micrometers, the aspect ratio of the height to the size of the bottom portion of the barrier is 0.5 to 1.0, and the aspect ratio of the height to the half-height width of the barrier is 0.4 to 0.8.

In addition, the aspect ratio of the half-height to the aspect ratio of the barrier is 0.7 to 1.0, and the slope, which is the angle between the tangent line of the bottom of the barrier and the horizontal plane, is 40 to 80 degrees.

According to the means for solving the above problems, the present application can improve the light extraction efficiency of the light emitted from the light emitting device through the non-flattening layer.

In addition, the present application can form the non-flattening layer without exposing the wavelength conversion layer overlapping with the non-flattening layer, thereby preventing the reliability and lifetime of the light emitting device from deterioration due to the exposure of the wavelength conversion layer.

In addition to the effects of the present application mentioned above, other features and advantages of the present application will be described below, or will be clearly understood by those skilled in the art from such description and description.

1 is a circuit diagram illustrating a pixel area of a light emitting display device according to an example of the present application.
2 is a cross-sectional view illustrating a pixel area according to an example of the present application.
FIG. 3 is an enlarged view of part A shown in FIG. 2 .
FIG. 4 is a plan view for explaining a planar structure of the non-flattening layer shown in FIG. 2 .
FIG. 5 is an enlarged view of portion A shown in FIG. 2 .
FIG. 6 is a plan view for explaining light emission luminance in the non-flattening layer shown in FIG. 2 .
7 is a cross-sectional view illustrating a pixel area according to an example of the present application.
FIG. 8 is a cross-sectional view for explaining the cross-sectional structure of the non-flattening layer in portion B shown in FIG. 7 .
FIG. 9 is an enlarged view of part B shown in FIG. 7 .
10 is a cross-sectional view showing a pixel area according to a second embodiment of the present invention.
11 is an enlarged view of part B shown in FIG. 10;
12 illustrates the relationship between current efficiency enhancement (%) or enhancement of current efficiency (%) according to the barrier aspect ratio of each light emitting display device having various values of the barrier aspect ratio of the non-planarization layer. graph shown.
13 is a graph showing the luminance efficiency according to the relationship between the half-height aspect ratio and the aspect ratio according to the half-height width aspect ratio of the barrier of the non-flattening layer.

Advantages and features of the present application, and methods of achieving them, will become clear with reference to examples described below in detail in conjunction with the accompanying drawings. However, the present application is not limited to the examples disclosed below and will be implemented in a variety of different forms, and only the examples of the present application make the disclosure of the present application complete, and common in the technical field to which the invention of the present application belongs. It is provided to completely inform those who have knowledge of the scope of the invention, and the invention of this application is only defined by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining an example of the present application are exemplary, the present application is not limited to the matters shown. Like reference numbers designate like elements throughout the specification. In addition, in describing examples of the present application, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present application, the detailed description will be omitted.

When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'but' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described as 'into the ground', 'into the top of the ground', 'into the bottom of the ground', 'next to the inside', etc., 'right' Or, unless 'directly' is used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal precedence relationship is described with 'to after', 'after to', 'to after', 'to before', etc. It can also include non-continuous cases unless is used.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present application.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, "at least one of the first, second, and third items" means not only the first, second, and third items, but also two of the first, second, and third items. It may mean a combination of all items that can be presented from one or more.

Each feature of the various examples of the present application can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each example can be implemented independently of each other or can be implemented together in a related relationship. .

Hereinafter, preferred examples of the light emitting display device according to the present application will be described in detail with reference to the accompanying drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings.

- No. 1 Example -

1 is a circuit diagram showing a pixel area of a light emitting display device according to a first embodiment of the present application.

Referring to FIG. 1 , a pixel area of the light emitting display device according to the first exemplary embodiment of the present application includes a pixel circuit PC and a light emitting device ED.

The pixel circuit (PC) is provided in a circuit area within a pixel area defined by a gate line (GL) and a data line (DL), and is connected to an adjacent gate line (GL) and data line (DL) and a first driving power source (VDD). ) is connected to The pixel circuit PC controls light emission of the light emitting device ED according to the data voltage Vdata from the data line DL in response to the gate-on signal GS from the gate line GL. The pixel circuit PC according to an example includes a switching thin film transistor ST, a driving thin film transistor DT, and a capacitor Cst.

The switching thin film transistor ST includes a gate electrode connected to the gate line GL, a first source/drain electrode connected to the data line DL, and a second source/drain electrode connected to the gate electrode of the driving thin film transistor DT. includes The switching thin film transistor (ST) is turned on according to the gate-on signal (GS) supplied to the gate line (GL) and drives the data voltage (Vdata) supplied to the data line (DL) to the gate of the driving thin film transistor (DT). supplied to the electrode.

The driving thin film transistor DT includes a gate electrode connected to the second source/drain electrode of the switching thin film transistor ST, a drain electrode connected to the first driving power supply VDD, and a source electrode connected to the light emitting device ED. do. The driving thin film transistor (DT) is turned on according to the gate-source voltage based on the data voltage (Vdata) supplied from the switching thin film transistor (ST), and the first driving power supply (VDD) to the light emitting element (ED) Controls the supplied data signal.

The capacitor Cst is connected between the gate electrode and the source electrode of the driving thin film transistor DT, stores a voltage corresponding to the data voltage Vdata supplied to the gate electrode of the driving thin film transistor DT, and converts the voltage to the stored voltage. The driving thin film transistor (DT) is turned on. At this time, the capacitor Cst maintains the turn-on state of the driving thin film transistor DT until the data voltage Vdata is supplied through the switching thin film transistor ST in the next frame.

The light emitting element ED is provided in a light emitting area within the pixel area and emits light according to a data signal supplied from the pixel circuit PC.

As an example, the light emitting device ED includes a first electrode connected to the source electrode of the driving thin film transistor DT, a second electrode connected to the second driving power source VSS, and a light emitting layer provided between the first electrode and the second electrode. can include Here, the light emitting layer may include any one of an organic light emitting layer, an inorganic light emitting layer, and a quantum dot light emitting layer, or may include a laminated or mixed structure of an organic light emitting layer (or an inorganic light emitting layer) and a quantum dot light emitting layer.

As such, the pixel area according to the first embodiment of the present application controls the data signal supplied to the light emitting element ED according to the gate-source voltage of the driving thin film transistor DT according to the data voltage Vdata to By emitting (ED), a predetermined image is displayed.

2 is a cross-sectional view showing a pixel area according to a first embodiment of the present application.

Referring to FIG. 2 , the pixel area according to the first embodiment of the present application includes a circuit area CA and a light emitting area (or opening area) EA provided on a substrate 100 .

The substrate 100 is mainly made of a glass material, but may be made of a transparent plastic material that can be bent or bent, for example, a polyimide material. When a plastic material is used as a material of the substrate 100, considering that a high-temperature deposition process is performed on the substrate 100, polyimide having excellent heat resistance that can withstand high temperatures may be used. The entire front surface of the substrate 100 may be covered by one or more buffer layers 110 .

The buffer layer 110 serves to block diffusion of materials contained in the substrate 100 into the transistor layer during a high-temperature process during the manufacturing process of the thin film transistor. In addition, the buffer layer 110 may also play a role in preventing external moisture or moisture from penetrating toward the light emitting device. As such, the buffer layer 110 may be made of silicon oxide or silicon nitride. Optionally, the buffer layer 110 may be omitted in some cases.

The circuit area CA includes a transistor layer, a first insulating layer 130 and a second insulating layer 170 .

The transistor layer includes a driving thin film transistor (DT).

The driving thin film transistor DT according to an example includes an active layer 111, a gate insulating layer 113, a gate electrode 115, a protective layer 117, a drain electrode 119d, and a source electrode 119s. .

The active layer 111 includes a channel region 111c, a drain region 111d, and a source region 111s formed in the driving thin film transistor region of the circuit region CA defined on the substrate 100 or the buffer layer 110. include The active layer 111 includes a drain region 111d and a source region 111s that are conductive by an etching gas during the etching process of the gate insulating layer 113 and a non-conductive channel region 111c. In this case, the drain region 111d and the source region 111s may be spaced parallel to each other with the channel region 111c interposed therebetween.

The active layer 111 according to an example may be formed of a semiconductor material made of any one of amorphous silicon, polycrystalline silicon, oxide, and organic material, but is not limited thereto. For example, the active layer 111 according to the present application is made of an oxide such as Zinc Oxide, Tin Oxide, Ga-In-Zn Oxide, In-Zn Oxide, or In-Sn Oxide, or the oxide includes Al, Ni, It can consist of oxides doped with ions of Cu, Ta, Mo, Zr, V, Hf or Ti materials.

The gate insulating layer 113 is formed on the channel region 111c of the active layer 111 . The gate insulating film 113 is not formed on the entire surface of the substrate 100 including the active layer 111 or the buffer layer 110, but only on the channel region 111c of the active layer 111 in an island shape. is formed with

The gate electrode 115 is formed on the gate insulating layer 113 to overlap the channel region 111c of the active layer 111 . The gate electrode 115 serves as a mask to prevent the channel region 111c of the active layer 111 from being conductive by an etching gas during a patterning process of the gate insulating film 113 using an etching process. The gate electrode 115 may be made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or any of them. It may be made of an alloy, and may be made of a single layer or a multi-layer of two or more layers of the metal or alloy.

The protective layer 117 is formed on the gate electrode 115 and the drain region 111d and the source region 111s of the active layer 111 . That is, the protective layer 117 is formed on the entire surface of the substrate 100 or the buffer layer 110 to cover the gate electrode 115 and the drain region 111d and source region 111s of the active layer 111. cover The protective layer 117 may be made of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx) or an organic material such as benzocyclobutene or photo acryl. Optionally, the protective layer 117 may be expressed in terms of an interlayer insulating film.

The drain electrode 119d is electrically connected to the drain region 111d of the active layer 111 through a first contact hole provided in the protective layer 117 overlapping with the drain region 111d of the active layer 111. .

The source electrode 119s is electrically connected to the source region 111s of the active layer 111 through a second contact hole provided in the protective layer 117 overlapping the source region 111s of the active layer 111. .

Each of the drain electrode 119d and the source electrode 111s is made of the same metal material, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), It may be made of nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof, and may be made of a single layer or a multi-layer of two or more layers of the metal or alloy.

Additionally, the circuit area further includes a switching thin film transistor and a capacitor.

Since the switching thin film transistor is provided on the circuit area CA to have the same structure as the driving thin film transistor, a description thereof will be omitted.

The capacitor is provided in an overlapping region between the gate electrode 115 and the source electrode 119s of the driving thin film transistor DT, which overlap each other with the protective layer 117 interposed therebetween.

Additionally, the transistor provided in the circuit area CA may have a characteristic that the threshold voltage is shifted by light. To prevent this, the light emitting display device according to the present application is provided under the active layer 111 to block light. A layer (101) may be further included.

The light blocking layer 101 is provided between the substrate 100 and the active layer 111 to block light incident toward the active layer 111 through the substrate 100, thereby minimizing the change in the threshold voltage of the transistor due to external light. prevent. The light blocking layer 101 is covered by the buffer layer 110 . Optionally, the light blocking layer 101 may be electrically connected to the source electrode of a transistor to serve as a lower gate electrode of the corresponding transistor. In this case, the change in threshold voltage of the transistor according to the bias voltage as well as the characteristic change due to light may be reduced. minimize or prevent

The first insulating layer 130 is provided on the substrate 100 to cover the transistor layer. That is, the first insulating layer 130 covers the drain electrode 119d, the source electrode 119s, and the passivation layer 117 of the driving thin film transistor DT. The first insulating layer 130 according to an example may be made of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx). Optionally, the first insulating layer 130 may be expressed in terms of a passivation layer.

The second insulating layer 170 is provided on the substrate 100 to cover the first insulating layer 130 . The second insulating layer 170 is formed to have a relatively thick thickness and serves to provide a flat surface on the substrate 100 . The second insulating layer 170 according to an example may be made of an organic material such as photo acryl, benzocyclobutene, polyimide, or fluororesin.

The light emitting area EA includes a wavelength conversion layer 150, a non-planarization layer 180, and a light emitting element ED.

The wavelength conversion layer 150 is provided on the first insulating layer 130 overlapping the emission area EA. That is, the wavelength conversion layer 150 is provided between the first insulating layer 130 and the non-flattening layer 180 by being supported by the first insulating layer 130 and covered by the second insulating layer 170, thereby enabling the light emitting element ( ED) overlaps with

The wavelength conversion layer 150 according to an example includes a color filter that transmits only wavelengths of colors set in a pixel area among white light emitted from the light emitting device ED toward the substrate 100 . The wavelength conversion layer 150 according to an example may transmit only red, green, or blue wavelengths. For example, in the light emitting display device according to the present application, one unit pixel may be composed of adjacent first to third pixel areas. In this case, the wavelength conversion layer provided in the first pixel area includes a red color filter and a second pixel area. The wavelength conversion layer provided in the pixel region may include a green color filter, and the wavelength conversion layer provided in the third pixel region may each include a blue color filter. Additionally, in the light emitting display device according to the present application, one unit pixel may further include a white pixel area on which the wavelength conversion layer is not formed.

The wavelength conversion layer 150 according to another example may include quantum dots having a size that emits light of a color set in a pixel area by re-emitting light according to white light emitted from the light emitting device ED toward the substrate 100. . Here, the quantum dots may be selected from CdS, CdSe, CdTe, ZnS, ZnSe, GaAs, GaP, GaAs-P, Ga-Sb, InAs, InP, InSb, AlAs, AlP, or AlSb. For example, the wavelength conversion layer of the first pixel region comprises CdSe or InP quantum dots, the wavelength conversion layer of the second pixel region comprises CdZnSeS quantum dots, and the wavelength conversion layer of the third pixel region comprises ZnSe quantum dots, respectively. can include As such, a light emitting display device in which the wavelength conversion layer 150 includes quantum dots may have a high color gamut.

The wavelength conversion layer 150 according to another example may be formed of a color filter containing quantum dots.

The non-flattening layer 180 is provided on the second insulating layer 170 to have a curved (or concave-convex) shape to change the path of light emitted from the light emitting device ED, thereby increasing the light extraction efficiency of the pixel area. The non-planarization layer 180 according to the present application includes a plurality of grooves 181 provided between the light emitting device ED and the wavelength conversion layer 150 . That is, the non-planarization layer 180 may include a plurality of grooves 181 and barriers 183 .

Each of the plurality of grooves 181 is recessed from the front surface 170a of the second insulating layer 170 . At this time, based on the front surface 170a of the second insulating layer 170, each of the plurality of grooves 181 may have the same depth, but due to a process error during the patterning process of the non-flattening layer 180, a plurality of grooves 181 may be formed. Some of the grooves 181 may have different depths.

The bottom surface (or the lowermost surface) of each of the plurality of grooves 181 is spaced apart from the wavelength conversion layer 150 by a set distance. At this time, in order to prevent the front surface of the wavelength conversion layer 150 from being directly exposed to the groove 181 due to the depth of the groove 181, the wavelength conversion layer 150 is removed from the bottom surface of the groove 181. The shortest distance between them may be set to 0.1 micrometer (μm) or more. In this case, the second insulating layer 170 provided between the bottom surface of the grooves 181 and the wavelength conversion layer 150 has a thickness of 0.1 micrometer or more. Here, when the second insulating layer 170 between the bottom surface of the grooves 181 and the wavelength conversion layer 150 has a thickness of less than 0.1 micrometer, during the patterning process of the non-flattening layer 180, the wavelength conversion layer ( As a part of the front surface of the surface 150 is directly exposed to the groove 181, characteristics of the light emitting device ED formed on the non-flattening layer 180 may deteriorate.

The barrier 183 has a structure defining or surrounding each of the plurality of grooves 181 . The barrier 183 changes the propagation path of the light emitted from the light emitting device ED toward the substrate 100 to increase the light extraction efficiency of the light emitted from the light emitting device ED.

The light emitting device ED emits light toward the substrate 100 according to a bottom emission method. A light emitting device ED according to an example includes a first electrode E1, a light emitting layer EL, and a second electrode E2.

The first electrode E1 is formed on the non-planarization layer 180 on the light emitting area EA to be electrically connected to the source electrode 119s of the driving thin film transistor DT.

At this time, one end of the first electrode E1 adjacent to the circuit area CA extends onto the source electrode 119s of the driving thin film transistor DT and is formed through a contact hole provided in the first and second insulating layers 130 and 170. It is electrically connected to the source electrode 119s of the driving thin film transistor DT through (CH). Since the first electrode E1 directly contacts the non-planarization layer 180, it has a shape following the shape of the non-planarization layer 180.

The first electrode E1 may be an anode electrode of the light emitting device ED. The first electrode E1 according to an exemplary embodiment is indium tin oxide (ITO), which is a transparent conductive material such as TCO (Transparent Conductive Oxide), or IZO so that light emitted from the light emitting layer EL can be transmitted toward the substrate 100 . (Indium Zinc Oxide) or the like.

Since the light emitting layer EL is formed on the first electrode E1 and directly contacts the first electrode E1, it has a shape following the shape of the first electrode E1. As a result, the light emitting layer EL has It has a shape following the shape of the non-flattening layer 180 .

The light emitting layer EL according to an example includes two or more light emitting units for emitting white light. For example, the light emitting layer EL may include a first light emitting part and a second light emitting part for emitting white light by mixing the first light and the second light. Here, the first light emitting unit emits the first light and may include any one of a blue light emitting unit, a green light emitting unit, a red light emitting unit, a yellow light emitting unit, and a yellow-green light emitting unit. The second light emitting unit may include a blue light emitting part, a green light emitting part, a red light emitting part, a yellow light emitting part, and a light emitting part emitting light having a complementary color relationship with the first light among yellow-green light.

Since the second electrode E2 is formed on the light emitting layer EL and directly contacts the light emitting layer EL, the second electrode E2 has a shape following the shape of the light emitting layer EL. As a result, the second electrode E2 is not flattened. It has a shape following the shape of the layer 180 .

The second electrode E2 according to an example may be a cathode electrode of the light emitting device ED. The second electrode E2 according to an example may include a metal material having high reflectance to reflect incident light emitted from the light emitting layer EL toward the substrate 100 .

For example, the second electrode E2 may include a laminated structure of aluminum (Al) and titanium (Ti) (Ti/Al/Ti), a laminated structure of aluminum (Al) and ITO (ITO/Al/ITO), APC ( Ag/Pd/Cu) alloy, and a multilayer structure such as a laminated structure of APC alloy and ITO (ITO/APC/ITO), or silver (Ag), aluminum (Al), molybdenum (Mo), gold (Au) , Magnesium (Mg), calcium (Ca), or barium (Ba) may include a single layer structure made of any one material or two or more alloy materials selected.

As such, the light emitting element ED emits white light by light emission of the light emitting layer EL according to the data signal supplied to the first electrode E1. At this time, since the light emitting element ED has a shape following the shape of the non-flattening layer 180, white light incident at the interface between the first electrode E1 and the non-flattening layer 180 is incident at a total reflection threshold angle or less Light is extracted toward the substrate 100 as it is, and light incident at a total reflection critical angle or higher is extracted toward the substrate 100 after the light propagation path is changed by the groove 181 and the barrier 183 of the non-flattening layer 180. can Accordingly, the present application can increase the light extraction efficiency of each pixel area.

The light emitting display device according to the present application may further include a bank layer 190 and an encapsulation layer 200 .

The bank layer 190 defines the light emitting area EA and is provided on the edge of the first electrode E1 and the second insulating layer 170 . The bank layer 190 may be formed of an organic material such as benzocyclobutene (BCB)-based resin, acryl-based resin, or polyimide resin. Alternatively, the bank layer 190 may be formed of a photoresist containing a black pigment. In this case, the bank layer 190 serves as a light blocking member.

Each of the light emitting layer EL and the second electrode E2 of the light emitting device ED is formed on the bank layer 190 . That is, the light emitting layer EL is formed on the substrate 100 on which the first electrode E1 and the bank layer 190 are provided, and the second electrode E2 is formed to cover the light emitting layer EL.

The encapsulation layer 200 is formed on the substrate 100 to cover the second electrode E2, that is, the entire pixel area. The encapsulation layer 200 protects the thin film transistor and the light emitting device (ED) from external impact and prevents moisture from penetrating into the light emitting device.

Optionally, the encapsulation layer 200 may be changed to a filler that encloses the entire pixel area. In this case, the light emitting display device according to the present application includes the encapsulation substrate 300 attached to the substrate 100 via the filler. ) is further included. The encapsulation substrate 300 may be made of a metal material.

Additionally, the light emitting display device according to the present application may further include a polarizing film attached to the rear surface (or light extraction surface) of the substrate 100 . The polarizing film improves visibility and contrast ratio of the light emitting display device by changing external light reflected by a thin film transistor and/or lines provided in a pixel area into a circularly polarized light state.

As described above, in the light emitting display device according to the first exemplary embodiment of the present application, the path of light emitted from the light emitting element ED is changed by the non-flattening layer 180 provided in the light emitting area EA of the pixel area, thereby improving the light extraction efficiency. As a result, luminance may be improved and power consumption may be reduced. In addition, in the light emitting display device according to the first exemplary embodiment of the present application, the shortest distance between the non-flattening layer 180 and the wavelength conversion layer 150 is set to 0.1 micrometer or more, so that the wavelength conversion layer 150 forms a groove 181 ) is prevented from being directly exposed to, and as a result, deterioration in characteristics of the light emitting device ED caused by exposure of the wavelength conversion layer 150 can be prevented.

3 is an enlarged view of part A shown in FIG. 2, which is a view for explaining the cross-sectional structure of the non-flattening layer according to the first embodiment of the present application, and FIG. 4 is a view of the non-flattening layer shown in FIG. It is a plan view for explaining the planar structure.

2 to 4, the non-planarization layer 180 according to the first embodiment of the present application includes a plurality of grooves 181 and a barrier 183 defining each of the plurality of grooves 181. .

Each of the plurality of grooves 181 is recessed from the front surface 170a of the second insulating layer 170 at regular intervals, and may be expressed as a concave portion or a recessed portion.

Each of the plurality of grooves 181 may be arranged side by side along the first direction at regular intervals and arranged in a zigzag shape along the second direction. That is, each of the plurality of grooves 181 may be arranged in a lattice form having regular intervals, but adjacent grooves 181 may be alternately arranged along the second direction. Accordingly, the center of each of the three adjacent grooves 181 may form a triangular shape TS.

Each of the plurality of grooves 181 may have the same depth with respect to the front surface 170a of the second insulating layer 170, but some of the plurality of grooves 181 may be formed during the patterning process of the non-flattening layer 180. It may have a different depth due to process errors.

The bottom surface (or lowermost surface) 181a of each of the plurality of grooves 181 is spaced apart from the wavelength conversion layer 150 by a set distance. That is, the bottom surface 181a of the groove 181 faces the front surface 150a of the wavelength conversion layer 150 with the second insulating layer 170 interposed therebetween. At this time, in the second insulating layer 170 provided between the bottom surface of the groove 181 and the wavelength conversion layer 150, a part of the front surface of the wavelength conversion layer 150 is formed when the groove 181 is formed. ) has a thickness of 0.1 micrometer or more to prevent direct exposure to Here, when the groove 181 is formed, the second insulating layer 170 provided between the groove 181 and the wavelength conversion layer 150 becomes thicker, so that a portion of the front surface 150a of the wavelength conversion layer 150 becomes a groove. Although direct exposure to (181) can be effectively prevented, the material cost of the second insulating layer 170, the process time, and the thickness of the light emitting display device increase in terms of the manufacturing process. Accordingly, the material cost of the second insulating layer 170, the process time, and the light emission display are prevented from being directly exposed to the groove 181 due to the depth of the groove 181. In order to minimize each increase in the thickness of the device, the maximum thickness of the second insulating layer 170 provided between the bottom surface of the groove 181 and the wavelength conversion layer 150 is set to 3 micrometers or less. Therefore, among the plurality of grooves 181, the shortest distance L1 between the front surface 150a of the wavelength conversion layer 150 and the front surface 150a may be 0.1 micrometer, and among the plurality of grooves 181, the front surface of the wavelength conversion layer 150 may be shortest distance L1. The longest distance with (150a) may be 3 micrometers. As a result, the distance L1 between the bottom surface 181a of each of the plurality of grooves 181 and the front surface 150a of the wavelength conversion layer 150 may range from 0.1 to 3 micrometers.

When the shortest distance L1 between the grooves 181 and the wavelength conversion layer 150 is less than 0.1 micrometer, a portion of the front surface of the wavelength conversion layer 150 is removed during the patterning process of the non-planarization layer 180. It may be depressed or directly exposed to the groove 181. When the wavelength conversion layer 150 is exposed to the groove 181 without being covered by the second insulating layer 170, a dark spot defect may occur in a recessed portion of the wavelength conversion layer 150, Moisture due to outgassing of the wavelength conversion layer 150 diffuses into the light emitting device ED, and thus the characteristics, reliability, and lifespan of the light emitting device ED may deteriorate. There is a problem in that the first electrode E1 is deteriorated due to direct contact between the electrode E1 and the wavelength conversion layer 150, and the wavelength conversion layer 150 is damaged due to the degradation of the first electrode E1. Accordingly, when the wavelength conversion layer 150 is exposed in the groove 181 without being covered by the second insulating layer 170, the light emitting characteristic, reliability, and lifespan of the light emitting display device may deteriorate.

In the present application, when the non-planarization layer 180 is formed on the second insulating layer 170 overlapping the light emitting region EA, a portion of the front surface 150a of the wavelength conversion layer 150 is exposed in the groove 181. To prevent this, the second insulating layer 170 is formed of the 2-1st insulating layer 170-1 and the 2-2nd insulating layer 170-2. That is, in the present application, the second insulating layer 170 is continuously formed in a two-layer structure having different thicknesses using an insulating material, for example, the same organic material.

The 2-1st insulating layer 170-1 is formed to cover both the first insulating layer 130 and the wavelength conversion layer 150, and is an exposure prevention layer or a sacrificial layer preventing exposure of the wavelength conversion layer 150. serves as a layer. The 2-1 insulating layer 170-1 is formed to have a thickness of 0.1 to 3 micrometers, and the bottom surface 181a of each of the plurality of grooves 181 is formed on the front surface 150a of the wavelength conversion layer 150. The front surface 150a of the wavelength conversion layer 150 is prevented from being directly exposed to the groove 181 during the formation process of the non-flattening layer 180 by spacing the first surface 150a away from the surface by a range of 0.1 to 3 micrometers.

The 2-2nd insulating layer 170-2 is formed to a relatively thicker thickness than the 2-1st insulating layer 170-1 so as to cover all of the 2-1st insulating layer 170-1. The 2-2 insulating layer 170 - 2 forms a planarization layer on the 2-1 insulating layer 170 - 1 of the circuit area CA and the light emitting area EA of the substrate 100 . For example, the 2-2 insulating layer 170 - 2 has a thickness equal to or greater than the depth of the groove 181 or the height H of the barrier 183 .

The second insulating layer 170 is structurally composed of the 2-1 insulating layer 170-1 and the 2-2 insulating layer 170-1 to prevent exposure of the front surface 150a of the wavelength conversion layer 150. 2), but after the 2-1 insulating layer 170-1 is formed through the primary deposition process using an organic material and the primary curing process, the same organic material as the 2-1 insulating layer 170-1 is formed. The second-second insulating layer 170-2 is formed through a secondary deposition process using a material and a secondary curing process. Accordingly, the boundary between the 2-1st insulating layer 170-1 and the 2-2nd insulating layer 170-2 having a two-layer laminated structure formed on the circuit area CA of the substrate 100 They may not be structurally distinct.

The barrier 183 surrounds each of the plurality of grooves 181 to define each of the plurality of grooves 181 and may have a structure protruding on the wavelength conversion layer 150 in a convex shape. Accordingly, the barrier 183 may have a cross-sectional structure in the form of a convex lens or a micro lens. The barrier 183 increases the light extraction efficiency of the pixel area by changing the propagation path of the incident light emitted from the light emitting device ED toward the substrate.

The barrier 183 may have a hexagonal band shape in plan view. In this case, one groove 181 may be provided in the barrier 183 having a hexagonal band shape in plan view. Accordingly, the plurality of grooves 181 and the barrier 183 provided on the light emitting area EA may have a hexagonal honeycomb structure in plan view. However, in the present application, the barrier 183 defining one groove 181 may have various shapes such as a circular band, an elliptical band shape, or a polygonal band shape in plan view.

The barrier 183 has a cross-sectional area parallel to the wavelength conversion layer 150, and the cross-sectional area of the barrier 183 changes the traveling path of the incident light to increase the light extraction efficiency of the pixel area, the wavelength conversion layer ( 150), it can gradually increase.

The barrier 183 according to an example may include a bottom portion 183a, a top portion 183b, and a side portion 183c.

The bottom portion 183a may be defined as a bottom surface of the barrier 183 adjacent to the wavelength conversion layer 150 . That is, the bottom portion 183a is the contact area between the barrier 183 and the 2-1st insulating layer 170-1 of the second insulating layer 170 overlapping the wavelength conversion layer 150, or the 2-1st insulating layer 170-1. It may be defined as the bottom surface of the barrier 183 contacting the entire surface of the insulating layer 170-1.

The barrier 183 based on the height H of the barrier 183 and the bottom diameter within a range where the diameter (or width) D of the bottom portion 183a is relatively larger than that of the top portion 183b. It can be set according to the aspect ratio of Here, the aspect ratio of the barrier 183 may be defined as a value obtained by dividing the height (H) of the barrier 183 by the radius (D/2) of the bottom portion 183a.

Bottom surfaces 183a of adjacent barriers 183 may be connected to each other to form bottom surfaces 181a of the grooves 181 . In this case, the pitch P between adjacent barriers 183 may be set equal to the diameter (or width) D of the bottom portion 183a.

Optionally, the bottom surfaces 183a of adjacent barriers 183 may be spaced apart from each other, in which case the bottom surfaces 181a of the grooves 181 are exposed between the bottom surfaces 183a of adjacent barriers 183. 2-1 may be the insulating layer 170-1. The pitch P between adjacent barriers 183 is set larger than the diameter (or width) D of the bottom portion 183a, and the bottom portions 183a of the adjacent barriers 183 are spaced apart from each other with a gap therebetween. .

When a gap is formed between adjacent barriers 183 as described above, when forming the groove 181, even if misalignment occurs due to deformation of the exposure mask, the non-flattening layer 180 is formed without exposing the wavelength conversion layer 150. Since it is possible to form a process margin of the non-flattening layer 180 can be increased.

The top portion 183b is spaced apart from the bottom portion 183a by a set height. The top portion 183b may be defined as an apex of the barrier 183 having a convex shape. In this case, the top portion 183b may be located on the front surface 170a of the second insulating layer 170 or below the front surface 170a of the second insulating layer 170 .

The side surface portion 183c is provided between the bottom surface portion 183a and the top portion 183b.

The side portion 183c according to an example may be provided in a curved shape between the bottom portion 183a and the top portion 183b to increase the light extraction efficiency of the pixel area by changing the propagation path of incident light. In this case, the side portion 183c may have a curved shape including an inflection point IP in order to maximize the light extraction efficiency of the pixel area. In this case, the side surface portion 183c according to the present application includes an inflection portion IPP including an inflection point IP, a first curved portion CP1 between the inflection portion IPP and the bottom portion 183a, and an inflection portion. A second curved portion CP2 between (IPP) and the top portion 183b may be included.

The inflection part IPP includes a concave part provided between the inflection point IP and the first curved part CP1 and a convex part provided between the inflection point IP and the second curved part CP2. Accordingly, the propagation path of the light incident on the inflection part IPP may be changed at various angles by the concave part and the block part, respectively, and thus light extraction efficiency of the pixel area may be improved.

The first curved portion CP1 may be provided in a concave shape between the inflection portion PIP and the bottom portion 183a. The second curved portion CP2 may be provided in a convex shape between the inflection portion PIP and the top portion 183b.

Based on the height H of the barrier 183, the height h1 of the first curved portion CP1, the height h2 of the inflection portion IPP, and the height h3 of the second curved portion CP2 The ratio (h1:h2:h3) to ) may be set to 1:3:1, but is not limited thereto, and the height h1 of the first curved part CP1 and the height of the second curved part CP2 (h3) Each may be the same as or different from each other within a range lower than the height h2 of the inflection part IPP. In addition, based on the length of the side surface portion 183c, the curved length of the inflection part IPP is longer than the respective lengths of the first curved part CP1 and the second curved part CP2, and the first curved part CP1 and the length of each of the second curved portion CP2 may be set equal to or different from each other. At this time, the length of the second curved part CP2 may be set longer than the length of the first curved part CP1. The height or curve length of each of the first curved portion CP1, the inflection portion IPP, and the second curved portion CP2 is a barrier set to improve light extraction efficiency according to the light path change of the barrier 183. It can be set according to the aspect ratio of (183).

The inflection part (IPP), the first curved part (CP1), and the second curved part (CP2) of the side surface part 183c according to such an example have a symmetrical structure with respect to the top part 183b, so that the first of the present application The barrier 183 according to one embodiment may have a cross-sectional structure of a bell or Gaussian curve.

Optionally, the side portion 183c according to an example may have a concave or convex curved shape to have an arbitrary curvature between the bottom portion 183a and the top portion 183b.

5 is an enlarged view of part A shown in FIG. 2, which is a view for explaining the cross-sectional structure of the non-flattening layer and the light emitting device according to the first embodiment of the present application, and FIG. It is a plan view for explaining the light emission luminance in the carbonized layer.

Referring to FIGS. 2, 5, and 6 , the light emitting device ED according to the first embodiment of the present application includes a first electrode E1 sequentially stacked on a non-flattening layer 180, a light emitting layer EL, and A second electrode E2 is included. The light emitting device ED is formed to have a shape following the shape of the plurality of grooves 181 and the barrier 183 provided in the non-flattening layer 180, and thus the path of light emitted from the light emitting device ED. Light extraction efficiency may be increased as is changed toward the substrate by the non-planarization layer 180 .

The light emitting device ED according to the present application may have different thicknesses according to positions formed in the groove 181 and the barrier 183 . Specifically, in the process of forming the light emitting device ED using the deposition method, the deposition material of the light emitting device ED is deposited on the non-flattening layer 180, which is not a flat surface, while having straightness. Accordingly, the light emitting device ED is deposited on the non-flattening layer 180 to have a shape following the shape of the groove 181 and the barrier 183, thereby forming the concave portion 181 and the top portion 183b of the barrier 183. ), and the inflection part IPP may have different thicknesses T1 , T2 , and T3 . That is, each of the bottom surface 181a of the concave portion 181 and the top portion 183b of the barrier 183 has a greater curvature than the inflection portion IPP of the barrier 183 or the bottom portion 183a of the barrier 183. It has a small slope as a reference. Accordingly, the light emitting device ED has a first thickness T1 on the bottom surface 181a of the concave portion 181 and a first thickness T1 on the top portion 183b of the barrier 183 that is equal to or different from the first thickness T1. It may be formed to have a second thickness T2 and a third thickness T3 thinner than each of the first and second thicknesses T1 and T2 on the inflection portion IPP of the barrier 183 .

When the light emitting layer EL of the light emitting device ED is made of an organic light emitting layer, light emission of the light emitting layer EL mainly occurs in a region having a high current density. The light emitting device ED according to the present application has a relatively thin third Relatively strong main light emission occurs in the light emitting layer EL on the inflection part IPP of the barrier 183 having the thickness T3, and a concave having a first thickness T1 that is relatively thicker than the third thickness T3. In the light emitting layer EL on the bottom surface 181a of the portion 181, a first sub light emission weaker than the main light emission occurs, and a barrier 183 having a second thickness T2 relatively thicker than the third thickness T3 Even in the light emitting layer EL on the top portion 183b of the second sub light emission, which is weaker than the main light emission, occurs. At this time, depending on the shape of the non-flattening layer 180, the area where the main light emission occurs may be defined as the main light extraction area, and the area where the sub light emission occurs may be defined as the sub light extraction area. Accordingly, as shown in FIG. 6 , in the luminance of the non-flattening layer 180, the region overlapping the inflection portion (IPP) of the barrier 183 has a relatively high luminance, whereas the concave portion 181 has a relatively high luminance. An area overlapping the bottom surface 181a of has relatively low luminance.

Considering the thickness of the light emitting device ED formed along the shape of the non-flattening layer 180, the top portion 183b of the barrier 183, as a sub-emission region, may have high light extraction efficiency but low current density. there is. The bottom surface 181a of the concave portion 181, as a sub light emitting region, may have the lowest light extraction efficiency and the lowest current density. On the other hand, the inflection portion IPP of the barrier 183, as a main light emitting region, may have high light extraction efficiency and high current density. Accordingly, based on the amount of light emitted from the light emitting device ED per unit area, the amount of light emitted on the curved portion IPP of the barrier 183 is relatively the highest, and the amount of light emitted on the bottom surface 181a of the concave portion 181 is relatively large. The light emission amount on the top portion 183b of the barrier 183 may be equal to or greater than the light emission amount on the bottom surface 181a of the concave portion 181 .

Accordingly, in the side surface portion 183c of the barrier 183, the higher the ratio occupied by the inflection part IPP, the higher the light extraction efficiency. When the ratio occupied by the first curved part CP1 is low, The lower the power consumption, the lower the power consumption. Therefore, the barrier 183 according to the present application has a height h1 of the first curved portion CP1, a height h2 of the inflection portion IPP, and a second curved portion CP2 based on the height H. ) to the height h3 (h1:h2:h3) is set to 1:3:1, thereby increasing the light extraction efficiency.

Through the shape of the non-flattening layer 180, the light extraction efficiency is influenced by the aspect ratio of the barrier 183 based on the height H and the diameter D of the bottom portion 183a. Accordingly, the aspect ratio of the barrier 183 according to the present application is set in the range of 0.4 to 0.7 to increase light extraction efficiency.

When the aspect ratio of the barrier 183 is in the range of 0.4 to 0.7, the light extraction efficiency is higher than when the aspect ratio of the barrier 183 is less than 0.4 or greater than 0.7. That is, when the aspect ratio of the barrier 183 is less than 0.4, the height H of the barrier 183 is too low so that the light incident from the light emitting device ED cannot proceed toward the substrate and is trapped within the light emitting device ED. Extraction efficiency may be reduced. In addition, when the aspect ratio of the barrier 183 exceeds 0.7, the height H of the barrier 183 is too high, so that the light incident from the light emitting device ED cannot travel toward the substrate and is trapped within the barrier 183. Light extraction efficiency may decrease. In particular, when the aspect ratio of the barrier 183 exceeds 0.7, the rate of increase in current efficiency tends to decrease, whereas when the aspect ratio of the barrier 183 is in the range of 0.4 to 0.7, the current efficiency of the light emitting device ED. The rate of increase has a maximum value. Therefore, the aspect ratio of the barrier 183 is preferably set in the range of 0.4 to 0.7 to maximize the light extraction efficiency of the pixel area.

When the aspect ratio of the barrier 183 is in the range of 0.4 to 0.7, the diameter D of the bottom portion 183a is 4 to 12 micrometers based on the resolution of the mask for forming the non-flattening layer 180. range can be set. In this case, when the diameter D of the bottom portion 183a is 4 micrometers and the height H of the barrier 183 is 0.8 micrometers, the barrier 183 may have an aspect ratio of 0.4. Also, when the diameter D of the bottom portion 183a is 12 micrometers and the height H of the barrier 183 is 4.2 micrometers, the barrier 183 may have an aspect ratio of 0.7. Here, when the height (H) of the barrier 183 is less than 0.8 micrometer, the aspect ratio of the barrier 183 may decrease, and thus the rate of increase in current efficiency may decrease, and the light emitted from the light emitting device ED may be emitted from the barrier 183. The amount of multi-reflected light increases, and thus the amount of light extracted toward the substrate decreases. When the height (H) of the barrier 183 exceeds 4.2 micrometers, the aspect ratio of the barrier 183 increases, and thus the rate of increase in current efficiency may decrease.

Accordingly, in the present application, the diameter D of the bottom portion 183a is set to 4 to 12 micrometers so that the aspect ratio of the barrier 183 may range from 0.4 to 0.7, and the height H of the barrier 183 ) is set to 0.8 to 4.2 micrometers, it is possible to maximize the light extraction efficiency of the pixel area.

In addition, the half-height width F of the barrier 183 may be set to 1 to 2.5 micrometers. In this case, the half height width (F) of the barrier 183 may be defined as the width of the barrier 183 at the half height (H/2) of the barrier 183. When the half-height width F of the barrier 183 is less than 1 micrometer or greater than 2.5 micrometers, light extraction efficiency by the barrier 183 may decrease. That is, when the half-height width F of the barrier 183 is less than 1 micrometer, the light emitted from the light emitting device ED is more diffusely reflected from the barrier 183 than the amount of light extracted toward the substrate reflected by the barrier 183. As the amount of light trapped in the light emitting device ED increases, the light extraction efficiency may decrease.

In particular, among the lights emitted from the light emitting device ED, light having an incident angle smaller than the critical angle of total reflection may be emitted to the outside of the substrate through multiple reflections between side surfaces of the barrier 183 . On the other hand, when the half-height width F of the barrier 183 exceeds 2.5 micrometers, the amount of light emitted to the outside of the substrate decreases as the amount of reflected light between the side surfaces of the barrier 183 decreases.

In this example, the light emitting element ED increases the ratio occupied by the inflection part IPP, which is the main light emitting region due to the thinness of the light emitting element ED, among the regions of the barrier 183 formed on the non-flattening layer 180. The light extraction efficiency of light emitted from (ED) can be increased. In addition, in this example, by setting the aspect ratio of the barrier 183 in the range of 0.4 to 0.7, the current efficiency increase rate can be increased and power consumption can be reduced. Further, in this example, the light extraction efficiency of the light emitted from the light emitting device ED can be increased by setting the half-height width F of the barrier 183 to 1 to 2.5 micrometers. As a result, the present application can increase the light extraction efficiency of each pixel area.

7 is a cross-sectional view showing a pixel area according to the first embodiment of the present application, and FIG. 8 is a cross-sectional view for explaining the cross-sectional structure of the non-flattening layer in portion B shown in FIG. 7, which is the pixel area shown in FIG. A barrier layer is additionally formed in the region. Accordingly, in the following description, only the barrier layer and components related thereto will be described, and redundant descriptions of the same components will be omitted or simply described.

Referring to FIGS. 7 and 8 , the barrier layer 160 according to the present example is formed to cover the wavelength conversion layer 150 . That is, the barrier layer 160 is provided between the non-planarization layer 180 and the wavelength conversion layer 150 . In addition, the barrier layer 160 covers the first insulating layer 130 provided on each of the emission area EA and circuit area CA, as well as the front surface and each side surface of the wavelength conversion layer 150 . Accordingly, the barrier layer 160 overlapping the wavelength conversion layer 150 is provided between the bottom surface 181a of the grooves 181 and the wavelength conversion layer 150, and the bottom portion 183a of the barrier 183 It is provided between and the wavelength conversion layer 150 . In addition, the barrier layer 160 that does not overlap with the wavelength conversion layer 150 is provided between the first insulating layer 130 and the second insulating layer 170 . When the non-planarization layer 180 is formed, the barrier layer 160 serves as an etch stopper on the wavelength conversion layer 150 to prevent the wavelength conversion layer 150 from being directly exposed to the groove 181, Problems caused by exposure of the conversion layer 150 are fundamentally prevented.

The barrier layer 160 according to an example may have a thickness corresponding to the shortest distance L1 between the bottom surface 181a of the grooves 181 and the wavelength conversion layer 150 . That is, the barrier layer 160 may be formed to a thickness t1 of 0.1 to 3 micrometers to prevent the wavelength conversion layer 150 from being exposed to the groove 181 when the non-flattening layer 180 is formed. can

Here, when the barrier layer 160 has a thickness t1 of less than 0.1 micrometer, wavelength conversion particles included in the wavelength conversion layer 150 may penetrate the barrier layer 160 and damage the light emitting device ED. can In addition, the thicker the thickness t1 of the barrier layer 160 is, the more effective it is to prevent exposure of the wavelength conversion layer 150. However, in terms of the manufacturing process, the material cost of the barrier layer 160, the process time and light emission The thickness of the display device increases. Accordingly, when the non-planarization layer 180 is formed, the barrier layer 160 serves as an etch stopper on the wavelength conversion layer 150 while minimizing increases in material cost, process time, and thickness of the light emitting display device. It is preferably formed with a thickness (t1) of 0.1 to 3 micrometers. For example, when the wavelength conversion particles of the wavelength conversion layer 150 have a size of less than 0.1 micrometer, the barrier layer 160 may be formed to have a thickness t1 of at least 0.1 micrometer.

The barrier layer 160 according to an example may be made of a material that is not removed by a developing material (or an etching material) used during a patterning process of the second insulating layer 170 .

The barrier layer 160 according to another example may be made of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx). That is, the barrier layer 160 is made of the same material as the first insulating layer 130, and for example, the barrier layer 160 and the first insulating layer 130 may be made of SiO2.

After the process of forming the non-planarization layer 180, a process of forming a contact hole CH to expose a part of the source electrode 119s of the driving thin film transistor DT may be performed. Considering the process of forming the contact hole CH, when the barrier layer 160 is formed of the same material as the first insulating layer 130, the barrier layer 160 and the first insulating layer are formed through a single patterning process. A contact hole (CH) may be simultaneously formed in (130). Accordingly, in order to simplify the manufacturing process of the light emitting display device, the barrier layer 160 is preferably made of the same material as the first insulating layer 130 .

In the light emitting display device according to the present example, the path of light emitted from the light emitting element ED is changed by the non-flattening layer 180 provided in the light emitting area EA of the pixel area, thereby improving light extraction efficiency. Brightness can be improved and power consumption can be reduced.

In addition, in the light emitting display device according to the present example, the barrier layer 160 serving as an etch stop is formed between the non-flattening layer 180 and the wavelength conversion layer 150 so that the wavelength conversion layer 150 is formed in the groove 181. Direct exposure is prevented, and thus, deterioration in characteristics of the light emitting device ED caused by exposure of the wavelength conversion layer 150 may be prevented.

FIG. 9 is an enlarged view of part B shown in FIG. 7, in which the structure of grooves formed in the non-flattening layer is changed. Accordingly, only the grooves of the non-flattening layer and components related thereto will be described below, and redundant descriptions of other identical components will be omitted or simply described.

Referring to FIGS. 7 and 9 , the non-flattening layer 180 according to the present example includes a plurality of grooves 181 and a barrier 183 defining each of the plurality of grooves 181 . The non-flattening layer 180 according to this example is the same as the non-flattening layer shown in FIGS. 2 to 4 except for the bottom surface 181a of each of the plurality of grooves 181 .

First, the grooves 181 and the barrier 183 of the non-planarization layer 180 may be formed through a selective exposure process and a developing process of the second insulating layer 170 using a mask. At this time, when the exposure amount to the bottom surface 181 of the grooves 181 increases due to misalignment due to deformation of the exposure mask during the exposure process, the second insulating layer 170 corresponding to the bottom surface 181 of the grooves 181 ) is completely removed, the bottom portions 183a of adjacent barriers 183 may be spaced apart from each other to have a predetermined gap G. At this time, when the barrier layer 160 is not formed between the non-flattening layer 180 and the wavelength conversion layer 150 and a gap G is formed between the bottom portions 183a of adjacent barriers 183, the wavelength The conversion layer 150 is directly exposed to the groove 181 .

However, in this example, since the barrier layer 160 is formed between the non-flattening layer 180 and the wavelength conversion layer 150, a gap G is formed between the bottom portions 183a of adjacent barriers 183 In this case, the wavelength conversion layer 150 is not directly exposed to the groove 181 by the barrier layer 160 .

In addition, the gap G between the adjacent barriers 183 forms the bottom surface 181 of the grooves 181, and the light emitting element ED formed on the bottom surface 181 of the grooves 181 Since it corresponds to the sub light emitting area, the light extraction efficiency is not greatly affected. Accordingly, the light extraction efficiency of each pixel region has a similar tendency regardless of whether the gap G is formed between adjacent barriers 183 or not.

Therefore, in this example, the light extraction efficiency can be improved by forming the gap G between the adjacent barriers 183. In particular, even if misalignment occurs due to deformation of the exposure mask, exposure of the wavelength conversion layer 150 Since the non-planarization layer 180 can be formed without the process, the process margin of the non-planarization layer 180 can be increased.

The present application described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which this application belongs that various substitutions, modifications, and changes are possible without departing from the technical details of the present application. It will be clear to those who have knowledge of Therefore, the scope of the present application is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present application.

- No. 2 Example -

10 is a cross-sectional view showing a pixel area according to a second embodiment of the present invention.

Meanwhile, the light emitting display device 100 according to an exemplary embodiment of the present invention is divided into a top emission type and a bottom emission type according to the transmission direction of the emitted light. Hereinafter, in the present invention, the bottom emission type. I will explain the method with an example.

At this time, for convenience of explanation, each pixel area SP includes a light emitting area EA provided with a light emitting element ED and substantially implementing an image, and a driving thin film transistor positioned along the edge of the light emitting area EA ( DT) is defined to include the circuit area CA.

As shown, in the light emitting display device 100 according to the second embodiment of the present invention, the substrate 401 on which the driving thin film transistor DT and the light emitting element ED are formed is encapsulated by a protective film 402. (encapsulation).

Looking at this in more detail, the active layer 405 is located on the circuit area CA of each pixel area SP on the substrate 401. The active layer 405 is made of silicon, and the center thereof forms a channel. It consists of a region 405a and source and drain regions 405b and 405c doped with high-concentration impurities on both sides of the channel region 405a.

A gate insulating layer 406 is positioned above the active layer 405 .

A gate insulating film 406 is formed on the channel region 405a of the active layer 405 . The gate insulating film 406 is not formed on the entire surface of the substrate 401 including the active layer 405, but is formed in an island shape only on the channel region 405a of the active layer 405.

A gate electrode 407 corresponding to the channel region 405a of the active layer 405 and a gate wiring (not shown) extending in one direction are provided above the gate insulating layer 406 , although not shown in the drawings.

In addition, a protective layer 408 is positioned above the gate electrode 407 and the gate wiring (not shown). In this case, the protective layer 408 includes source and drain regions 405b located on both sides of the channel region 405a. , 405c) are provided with first and second active layer contact holes CH1 respectively exposing them.

Next, source and drain regions 405b are spaced apart from each other and exposed through the first and second active layer contact holes CH1 above the protective layer 408 including the first and second active layer contact holes CH1. Source and drain electrodes 410a and 410b contacting the 405c, respectively, are provided.

A first insulating layer 412 is positioned on the source and drain electrodes 410a and 410b and the protective layer 408 exposed between the two electrodes 410a and 410b.

At this time, the active layer 405 including the source and drain electrodes 410a and 410b and the source and drain regions 405b and 405c in contact with the electrodes 410a and 410b and a gate located on the active layer 405 The insulating film 406 and the gate electrode 407 form a driving thin film transistor (DT).

Meanwhile, although not shown in the drawing, a data line (not shown) intersecting with a gate line (not shown) to define each pixel area SP is positioned, and a switching thin film transistor (not shown) is connected to the driving thin film transistor DT. In the same structure, it is connected to the driving thin film transistor (DT).

In addition, the switching thin film transistor (not shown) and the driving thin film transistor (DT) are shown as an example of a top gate type in which the active layer 405 is formed of a polysilicon active layer or an oxide active layer in the drawing, and variations thereof For example, it may be provided as a bottom gate type made of pure and impurity amorphous silicon.

Also, the substrate 401 is mainly made of a glass material, but may be made of a transparent plastic material that can be bent or bent, for example, a polyimide material. In the case of using a plastic material as the material of the substrate 401, considering that a high-temperature deposition process is performed on the substrate 401, polyimide having excellent heat resistance that can withstand high temperatures may be used. The entire front surface of the substrate 401 may be covered by one or more buffer layers 403 .

In this case, the driving thin film transistor DT provided in the circuit area CA may have a characteristic that the threshold voltage is shifted by light. To prevent this, the light emitting display device 100 according to the present application has an active layer 405 ) may further include a light blocking layer 404 provided below.

The light blocking layer 404 is provided between the substrate 401 and the active layer 405 to block light incident toward the active layer 405 through the substrate 401, thereby minimizing or preventing a change in the threshold voltage of the transistor due to external light. do. This light blocking layer 404 is covered by a buffer layer 403 .

A wavelength conversion layer 414 is positioned above the first insulating layer 412 corresponding to the light emitting area EA of each pixel area SP.

That is, the wavelength conversion layer 414 is provided between the first insulating layer 412 and the non-flattening layer 420 by being supported by the first insulating layer 412 and covered by the second insulating layer 416, thereby enabling the light emitting element ( ED) overlaps with

The wavelength conversion layer 414 according to an example includes a color filter that transmits only wavelengths of colors set in the pixel region SP among white light emitted from the light emitting device ED toward the substrate 401 .

The wavelength conversion layer 414 according to an example may transmit only red, green, or blue wavelengths. For example, in the light emitting display device 100 according to the present application, one unit pixel may be composed of adjacent first to third pixel regions SP, and in this case, a wavelength conversion layer ( 414 may include a red color filter, the wavelength conversion layer 414 provided in the second pixel area may include a green color filter, and the wavelength conversion layer 414 provided in the third pixel area may include a blue color filter, respectively.

Additionally, in the light emitting display device 100 according to the present application, one unit pixel may further include a white pixel on which the wavelength conversion layer 414 is not formed.

The wavelength conversion layer 414 according to another example includes quantum dots having a size that emits light of a color set in each pixel region SP by re-emitting light according to white light emitted from the light emitting device ED toward the substrate 401 . can include Here, the quantum dots may be selected from CdS, CdSe, CdTe, ZnS, ZnSe, GaAs, GaP, GaAs-P, Ga-Sb, InAs, InP, InSb, AlAs, AlP, or AlSb.

For example, the wavelength conversion layer 414 of the first pixel region is CdSe or InP quantum dots, the wavelength conversion layer 414 of the second pixel region is CdZnSeS quantum dots, and the wavelength conversion layer 414 of the third pixel region ) may each include quantum dots of ZnSe. As such, the light emitting display device 100 in which the wavelength conversion layer 414 includes quantum dots may have a high color gamut.

The wavelength conversion layer 414 according to another example may be formed of a color filter containing quantum dots.

Above the wavelength shifting layer 414, a second insulating layer 416 having a drain contact hole CH2 exposing the drain electrode 410b along with the first insulating film 412 is sequentially positioned. A non-flattening layer 420 having a curved (or concavo-convex) shape is provided on the surface of the layer 416 to change the propagation path of light emitted from the light emitting device ED, thereby increasing the light extraction efficiency of the pixel region SP.

The non-planarization layer 420 according to the present application includes a plurality of grooves 418 provided between the light emitting device ED and the wavelength conversion layer 414 . That is, the non-planarization layer 420 may include a plurality of grooves 418 and barriers 419 .

Each of the plurality of grooves 418 is recessed from the front surface 416a of the second insulating layer 416 . At this time, based on the front surface 416a of the second insulating layer 416, each of the plurality of grooves 418 has the same depth as each other.

The bottom surface (or lowermost surface) of each of the plurality of grooves 418 is spaced apart from the wavelength conversion layer 414 by a set distance. At this time, in order to prevent the front surface of the wavelength conversion layer 414 from being directly exposed to the groove 418 due to the depth of the groove 418, the wavelength conversion layer 414 is formed from the bottom surface of the groove 418. The shortest distance between them may be set to 0.1 micrometer (μm) or more.

In this case, the second insulating layer 416 provided between the bottom surface of the grooves 418 and the wavelength conversion layer 414 has a thickness of 0.1 micrometer or more.

Here, when the second insulating layer 416 between the bottom surface of the grooves 418 and the wavelength conversion layer 414 has a thickness of less than 0.1 micrometer, during the patterning process of the non-flattening layer 420, the wavelength conversion layer ( As a part of the front surface of the surface 414 is directly exposed to the groove 418 , characteristics of the light emitting device ED formed on the non-flattening layer 420 may deteriorate.

The barrier 419 has a structure defining or surrounding each of the plurality of grooves 418 . The barrier 419 changes the propagation path of the light emitted from the light emitting device ED toward the substrate 401 to increase light extraction efficiency of the light emitted from the light emitting device ED.

The barrier 419 according to an example may include a bottom portion 419a (see FIG. 11), a top portion 419b (see FIG. 11), and a side portion 419c (see FIG. 11). In the non-flattening layer 420 according to the second embodiment, bottom portions 419a (see FIG. 11) of adjacent barriers 419 are spaced apart from each other with a gap G therebetween.

When the gap G is formed between the adjacent barriers 419 as described above, when the groove 418 is formed, even if misalignment occurs due to deformation of the exposure mask, the non-flattening layer ( 420), it is possible to increase the process margin of the non-planarization layer 420.

The light emitting display device 100 according to the second embodiment of the present invention proposes an optimal condition for the non-flattening layer 420 in which the gap G is formed between the barriers 419, and thus the light emitting device ED The light extraction efficiency of the light emitted from is further improved.

We will look into this in more detail later.

The upper part of the non-flattening layer 420 is connected to the drain electrode 410b of the driving thin film transistor DT, and for example, a material having a relatively high work function value forms the anode of the light emitting element E. An electrode EL1 is located.

The first electrode EL1 is a metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a metal and oxide such as ZnO:Al or SnO ₂ :Sb. and conductive polymers such as poly(3-methylthiophene), poly[3,4-(ethylene-1,2-dioxy)thiophene] (PEDT), polypyrrole, and polyaniline. In addition, it may be made of carbon nano tube (CNT), graphene, silver nano wire, or the like.

The first electrode EL1 is positioned for each pixel area SP, and a bank 421 is positioned between the first electrodes EL1 positioned for each pixel area SP. That is, the first electrode EL1 has a structure separated for each pixel region SP by using the bank 421 as a boundary for each pixel region SP.

Also, an organic light emitting layer EL is positioned above the first electrode EL1 including the bank 421. The organic light emitting layer EL may be composed of a single layer made of a light emitting material, and in order to increase light emitting efficiency, the organic light emitting layer EL may be formed of holes It may be composed of multiple layers of a hole injection layer, a hole transport layer, an emitting material layer, an electron transport layer, and an electron injection layer.

Also, a second electrode EL2 forming a cathode is positioned on the upper side of the organic light emitting layer EL.

The second electrode EL2 may be made of a material having a relatively low work function value. At this time, the second electrode EL2 has a double layer structure, and is composed of a single layer of an alloy composed of a first metal made of Ag or the like, which is a metal material having a low work function, and a second metal made of Mg, etc., in a certain ratio, or a plurality of layers thereof. can be configured.

In the light emitting display device 100, when a predetermined voltage is applied to the first electrode EL1 and the second electrode EL2 according to a selected signal, holes injected from the first electrode EL1 and the second electrode EL2 The electrons provided from are transported to the organic light emitting layer EL to form excitons, and when these excitons transition from an excited state to a ground state, light is generated and emitted in the form of visible light.

At this time, since the emitted light passes through the transparent first electrode EL1 and goes out, the light emitting display device 100 implements an arbitrary image.

Here, the first electrode EL1, the organic light emitting layer EL, and the second electrode EL2 sequentially positioned above the non-planarization layer 420 are all formed in the groove 418 and the barrier 419 of the non-planarization layer 420. ) as it is, and has a shape following the shape of the non-flattening layer 420.

In addition, a protective film 402 in the form of a thin film is formed on the driving thin film transistor DT and the light emitting element ED with an encapsulation layer 423 interposed therebetween, so that the light emitting display device 100 is encapsulated. (encapsulation).

An encapsulation layer 423 is formed on the substrate 401 to cover the second electrode E2, that is, the entire pixel area SP. The encapsulation layer 423 protects the driving thin film transistor DT and the light emitting device ED from external impact and prevents moisture from penetrating into the light emitting device ED.

In addition, in the light emitting display device 100 according to the second embodiment of the present invention, a polarizer (not shown) is positioned on the outer surface of the substrate 401 through which light is transmitted to prevent a decrease in contrast due to external light.

That is, the light emitting display device 100 adjusts the contrast by placing a polarizing plate (not shown) blocking external light incident from the outside in the transmission direction of the light emitted through the organic light emitting layer EL in the driving mode for realizing an image. will improve

As described above, in the light emitting display device 100 according to the second exemplary embodiment of the present invention, the light emitting element ED emits light by the non-flattening layer 420 provided in the light emitting area EA of the pixel area SP. The path of light is changed to improve light extraction efficiency, thereby improving luminance and reducing power consumption.

In addition, since the shortest distance between the non-flattening layer 420 and the wavelength conversion layer 414 is set to 0.1 micrometer or more, the wavelength conversion layer 414 is prevented from being directly exposed to the groove 418, thereby preventing the wavelength conversion layer 414 from being directly exposed to the groove 418. Deterioration in characteristics of the light emitting device ED caused by exposure of the conversion layer 414 may be prevented.

In particular, the light emitting display device 100 according to the second embodiment of the present invention proposes an optimal condition for the non-flattening layer 420 in which the gap G is formed between the barriers 419, so that the light emitting element ED ) to further improve the light extraction efficiency of the emitted light.

FIG. 11 is an enlarged view of part B shown in FIG. 10, which is a view for explaining the cross-sectional structure of the non-flattening layer according to the second embodiment of the present application.

12 shows the relationship between current efficiency enhancement (%) or enhancement of current efficiency (%) according to the barrier aspect ratio of each light emitting display device having different barrier aspect ratios of the non-planarization layer. 13 is a graph showing the luminance efficiency according to the relationship between the half-height aspect ratio and the half-height aspect ratio of the barrier of the non-flattening layer.

As shown in FIG. 11 , the non-planarization layer 420 includes a plurality of grooves 418 and a barrier 419 defining each of the plurality of grooves 418 .

Each of the plurality of grooves 418 is recessed from the front surface 416a of the second insulating layer 416 at regular intervals, and may be expressed as a concave portion or a recessed portion.

Each of the plurality of grooves 418 has the same depth with respect to the front surface 416a of the second insulating layer 416, and the bottom surface (or lowermost surface) 418a of each of the plurality of grooves 418 has a wavelength It is spaced apart from the conversion layer 414 by a set interval.

That is, bottom surfaces 418a of the grooves 418 face the front surface 414a of the wavelength conversion layer 414 with the second insulating layer 416 interposed therebetween. At this time, in the second insulating layer 416 provided between the bottom surface 418a of the grooves 418 and the wavelength conversion layer 414, a portion of the front surface of the wavelength conversion layer 414 is formed when the groove 418 is formed. To prevent direct exposure to (418), it has a thickness of 0.1 micrometers or more.

Here, when the grooves 418 are formed, the thickness of the second insulating layer 416 provided between the grooves 418 and the wavelength conversion layer 414 increases, so that a portion of the front surface 414a of the wavelength conversion layer 414 is formed. Although direct exposure to the groove 418 can be effectively prevented, the material cost of the second insulating layer 416, the process time, and the thickness of the light emitting display device increase in terms of a manufacturing process.

Accordingly, the depth of the groove 418 prevents the front surface of the wavelength conversion layer 414 from being directly exposed to the groove 418, while reducing the material cost of the second insulating layer 416, the process time, and the light emitting display. In order to minimize each increase in the thickness of the device, the maximum thickness of the second insulating layer 416 provided between the bottom surface 418a of the grooves 418 and the wavelength conversion layer 414 is set to 3 micrometers or less.

Therefore, among the plurality of grooves 418, the shortest distance L1 between the front surface 414a of the wavelength conversion layer 414 and the front surface 414a may be 0.1 micrometer, and among the plurality of grooves 418, the front surface of the wavelength conversion layer 414 may be shortest distance L1. The longest distance to 414a may be 3 micrometers. As a result, the distance L1 between the bottom surface 418a of each of the plurality of grooves 418 and the front surface 414a of the wavelength conversion layer 414 may range from 0.1 to 3 micrometers.

When the shortest distance L1 between the grooves 418 and the wavelength conversion layer 414 is less than 0.1 micrometer, a portion of the front surface of the wavelength conversion layer 414 is removed during the patterning process of the non-planarization layer 420. It may be recessed or exposed directly to the groove 418.

When the wavelength conversion layer 414 is exposed to the groove 418 without being covered by the second insulating layer 416, a dark spot defect may occur in a recessed portion of the wavelength conversion layer 414, Moisture due to outgassing of the wavelength conversion layer 414 diffuses into the light emitting device ED, and thus the characteristics, reliability, and lifespan of the light emitting device ED may deteriorate. There is a problem in that the first electrode E1 is deteriorated due to direct contact between the electrode E1 and the wavelength conversion layer 414, and the wavelength conversion layer 414 is damaged due to the degradation of the first electrode E1.

Accordingly, when the wavelength conversion layer 414 is exposed in the groove 418 without being covered by the second insulating layer 416, the light emitting characteristic, reliability, and lifespan of the light emitting display device 100 may deteriorate.

Here, the light emitting display device 100 according to the second embodiment of the present invention considers the material cost and process time of the second insulating layer 416 in terms of the manufacturing process, and the wavelength conversion layer among the plurality of grooves 418. In order to secure the shortest distance L1 from the front surface 414a of 414, the second insulating layer 416 is formed as a 2-1 insulating layer 416-1 and a 2-2 insulating layer 416-2. form with

That is, according to the present invention, the second insulating layer 416 is continuously formed in a two-layer structure having different thicknesses using an insulating material, for example, the same organic material.

The 2-1 insulating layer 416-1 is formed to cover both the first insulating layer 412 and the wavelength conversion layer 414, and is an exposure prevention layer or a sacrificial layer preventing exposure of the wavelength conversion layer 414. plays the role of

The 2-1 insulating layer 416-1 is formed to have a thickness of 0.1 to 3 micrometers, and the bottom surface 418a of each of the plurality of grooves 418 is formed on the front surface 414a of the wavelength conversion layer 414. The front surface 414a of the wavelength conversion layer 414 is prevented from being directly exposed to the groove 418 during the formation process of the non-planarization layer 420 by spacing the surface 414a apart from 0.1 to 3 micrometers.

Also, the 2-2 insulating layer 416-2 is formed to have a relatively thicker thickness than the 2-1 insulating layer 416-1 so as to cover all of the 2-1 insulating layer 416-1. The 2-2 insulating layer 416 - 2 forms a planarization layer on the 2-1 insulating layer 416 - 1 of the circuit area CA and the light emitting area EA of the substrate 401 . For example, the 2-2 insulating layer 416 - 2 has a thickness equal to or greater than the depth of the groove 418 or the height H of the barrier 419 .

The second insulating layer 416 is structurally composed of the 2-1 insulating layer 416-1 and the 2-2 insulating layer 416-2 to prevent exposure of the front surface 414a of the wavelength conversion layer 414. 2), but after the 2-1 insulating layer 416-1 is formed through the primary deposition process using an organic material and the primary curing process, the same organic material as the 2-1 insulating layer 416-1 is formed. The second-second insulating layer 416-2 is formed through a secondary deposition process using a material and a secondary curing process.

Accordingly, the boundary between the 2-1st insulating layer 416-1 and the 2-2nd insulating layer 416-2 having a two-layer laminated structure formed on the circuit area CA of the substrate 401 They may not be structurally distinct.

And, the barrier 419 of the non-flattening layer 420 surrounds each of the plurality of grooves 418 to define each of the plurality of grooves 418, and protrudes in a convex form on the wavelength conversion layer 414. can have a structure.

Accordingly, the barrier 419 may have a cross-sectional structure in the form of a convex lens or a micro lens. The barrier 419 increases light extraction efficiency of the pixel region SP by changing a traveling path of light emitted from the light emitting device ED and incident toward the substrate 401 .

The barrier 419 may have a hexagonal band shape in plan view. In this case, one groove 418 may be provided in the barrier 419 having a hexagonal band shape in plan view. Accordingly, the plurality of grooves 418 and the barrier 419 provided on the light emitting area EA may have a hexagonal honeycomb structure in plan view. However, in the present application, the barrier 419 defining one groove 418 may have various shapes such as a circular band, an elliptical band shape, or a polygonal band shape in plan view.

The barrier 419 has a cross-sectional area parallel to the wavelength conversion layer 414, and the cross-sectional area of the barrier 419 changes the traveling path of the incident light to increase the light extraction efficiency of the pixel region SP. The adjacent layer 414 may gradually increase.

The barrier 419 according to an example may include a bottom portion 419a, a top portion 419b, and a side portion 419c.

The bottom portion 419a may be defined as a bottom surface of the barrier 419 adjacent to the wavelength conversion layer 414 . That is, the bottom portion 419a is the contact area between the barrier 419 and the 2-1st insulating layer 416-1 of the second insulating layer 416 overlapping the wavelength conversion layer 414, or the 2-1st insulating layer 419. It can be defined as the bottom surface of the barrier 419 contacting the front surface of the layer 416-1.

The bottom surfaces 419a of the adjacent barriers 419 are spaced apart from each other to form a gap G. In this case, the bottom surfaces 418a of the grooves 418 are positioned between the bottom surfaces 419a of the adjacent barriers 419. may be the 2-1st insulating layer 416-1 exposed to.

The pitch P between adjacent barriers 419 is set larger than the diameter (or width) D of the bottom portion 419a, and the bottom portions 419a of the adjacent barriers 419 have a gap G therebetween. are spaced apart from each other

When the gap G is formed between the adjacent barriers 419 as described above, when the groove 418 is formed, even if misalignment occurs due to deformation of the exposure mask, the non-flattening layer ( 420), it is possible to increase the process margin of the non-planarization layer 420.

The top portion 419b of the barrier 419 of the non-flattening layer 420 is spaced apart from the bottom portion 419a by a set height. The top portion 419b may be defined as an apex of the barrier 419 having a convex shape. In this case, the top portion 419b may be located on the front surface 416a of the second insulating layer 416 or below the front surface 416a of the second insulating layer 416 .

And, the side part 419c is provided between the bottom part 419a and the top part 419b.

The side surface portion 419c according to an example may be provided in a curved shape between the bottom portion 419a and the top portion 419b to increase the light extraction efficiency of the pixel area SP by changing the propagation path of incident light. there is. In this case, the side portion 419c may have a curved shape including an inflection point IP in order to maximize the light extraction efficiency of the pixel area SP.

In this case, the side surface portion 419c according to the present application includes an inflection portion IPP including an inflection point IP, a first curved portion CP1 between the inflection portion IPP and the bottom portion 419a, and an inflection portion. A second curved portion CP2 between (IPP) and the top portion 419b may be included.

The inflection part IPP includes a concave part provided between the inflection point IP and the first curved part CP1 and a convex part provided between the inflection point IP and the second curved part CP2. Accordingly, the propagation path of the light incident on the inflection part IPP may be changed at various angles by the concave part and the block part, respectively, and thus light extraction efficiency of the pixel area SP may be improved.

Also, the first curved portion CP1 may be provided in a concave shape between the inflection portion PIP and the bottom portion 419a. The second curved portion CP2 may be provided in a convex shape between the inflection portion PIP and the top portion 419b.

Here, in the side surface portion 419c of the barrier 419, the higher the ratio occupied by the inflection part IPP, the higher the light extraction efficiency, and the lower the ratio occupied by the first curved part CP1 is. The power consumption can be reduced.

Therefore, based on the height H of the barrier 183, the height h1 of the first curved portion CP1, the height h2 of the inflection portion IPP, and the height of the second curved portion CP2 ( The light extraction efficiency can be increased by setting the ratio (h1:h2:h3) to h3) to 1:3:1.

At this time, the length of the second curved part CP2 may be set longer than the length of the first curved part CP1. The height or curve length of each of the first curved portion CP1, the inflection portion IPP, and the second curved portion CP2 is a barrier set to improve light extraction efficiency according to the light path change of the barrier 419. It can be set according to the aspect ratio (A/R) of (419).

The inflection part (IPP), the first curved part (CP1), and the second curved part (CP2) of the side surface part 419c according to such an example have a symmetrical structure centered on the top part 419b, so that the first of the present invention The barrier 419 according to the second exemplary embodiment may have a cross-sectional structure of a bell or Gaussian curve.

Optionally, the side portion 419c according to an example may have a concave or convex curved shape to have an arbitrary curvature between the bottom portion 419a and the top portion 419b.

Here, since the light path change according to the shape of the barrier 419 of the non-flattening layer 420 is a major factor in improving the light extraction efficiency, the bottom edge of the barrier 419 of the non-flattening layer 420 is a variable determining the shape. (419a) diameter (D (Diameter)), height (H (Height)), aspect ratio (A/R (Aspect Ratio)), F (Full Width Half Max), half height width aspect ratio (F_A) /R), slope (S(Slope)), separation distance (G(Gap)) between the bottom portions 419a of adjacent barriers 419, half-height aspect ratio to aspect ratio (Rm(Ratio of MLA)), etc. there is.

Here, the aspect ratio (A/R) of the barrier 419 can be defined through (Equation 1) below.

(Equation 1)

A/R = H/(D/2)

That is, it can be defined as a value obtained by dividing the height (H) of the barrier 419 by the radius (D/2) of the bottom portion 419a.

In the light emitting display device 100 according to the second exemplary embodiment of the present invention, as the gap G is formed between adjacent barriers 419, the aspect ratio A/R of the barriers 419 is in the range of 0.5 to 1.0. It is characterized by setting to .

At this time, the gap (G) may be made of 0.3 to 10 micrometers.

That is, when the separation distance (G) between the bottom portions 419a of adjacent barriers 419 is 0.3 to 10 micrometers and the aspect ratio (A/R) of the barriers 419 is less than 0.5, the barriers 419 When the height H of is too low, the light incident from the light emitting device ED does not travel toward the substrate 401 and is trapped within the light emitting device ED, and light extraction efficiency may be reduced.

In addition, when the aspect ratio (A/R) of the barrier 419 exceeds 1.0, the height H of the barrier 419 is too high, so light incident from the light emitting device ED does not travel toward the substrate 401. However, light extraction efficiency may be reduced because the light is trapped in the barrier 419.

In particular, when the aspect ratio (A/R) of the barrier 419 exceeds 1.0, the rate of increase in current efficiency tends to decrease, while the aspect ratio (A/R) of the barrier 419 is in the range of 0.5 to 1.0. In this case, the current efficiency increase rate of the light emitting device ED has a maximum value.

Therefore, it is preferable that the aspect ratio (A/R) of the barrier 419 is set in the range of 0.5 to 1.0 to maximize the light extraction efficiency of the pixel region SP.

12 illustrates the relationship between current efficiency enhancement (%) or enhancement of current efficiency (%) according to the barrier aspect ratio of each light emitting display device having various values of the barrier aspect ratio of the non-planarization layer. is the graph shown.

At this time, it means that the higher the current efficiency increase rate, the better the luminous efficiency.

Referring to the graph, it can be seen that the current efficiency increase rate of the light emitting display device 100 in which the aspect ratio (A/R) of the barrier 419 of the non-flattening layer 420 is set in the range of 0.5 to 1.0 is as high as 35 cd/A or more. can

On the other hand, when only the aspect ratio (A/R) is applied as a variable defining the shape of the barrier 419 of the non-flattening layer 420, the aspect ratio (A/R) is the same and only the diameter (D) and height (H) are used. Even if the defined ratio is the same, when the values defined by the remaining variables, such as the width of the half-height (F) or the distance (G) between the barriers 419, are different, the The shape changes markedly.

Therefore, in the light emitting display device 100 according to the second embodiment of the present invention, the aspect ratio (F_A/R) corresponding to the half-height width (F) of the barrier 419 is set in the range of 0.4 to 0.8. The half-height aspect ratio (Rm) is further set in the range of 0.7 to 1.0, and the slope (S) is characterized in that it is set in the range of 40 to 80 degrees.

An aspect ratio (F_AR) corresponding to the half-height width (F) of the barrier 419 may be defined through (Equation 2) below.

(Equation 2)

F_AR = (H/2)/(F/2) = H/F

In this case, the half-height width (F) of the barrier 419 may be defined as the width of the barrier 419 at the half-height (H/2) of the barrier 419 .

When the aspect ratio (F_AR) corresponding to the half-height width (F) of the barrier 419 is less than 0.4, the height (H) of the barrier 419 becomes too low, and light incident from the light emitting device (ED) is emitted from the substrate. The light extraction efficiency may be lowered because it cannot proceed toward the 401 and is trapped in the light emitting device ED.

In addition, when the aspect ratio (F_AR) corresponding to the half-height width (F) of the barrier 419 exceeds 0.8, the height (H) of the barrier 419 is too high, so light incident from the light emitting device (ED) The light extraction efficiency may be reduced because the light cannot proceed toward the substrate 401 and is trapped in the barrier 419 .

In particular, when the aspect ratio (F_AR) corresponding to the half-height width (F) of the barrier 419 exceeds 0.8, the current efficiency increase rate tends to decrease, whereas the half-height width (F) of the barrier 419 has a tendency to decrease. When the corresponding aspect ratio F_AR is in the range of 0.4 to 0.8, the current efficiency increase rate of the light emitting device ED has a maximum value.

Accordingly, the aspect ratio F_AR corresponding to the half-height width F of the barrier 419 is preferably set in the range of 0.4 to 0.8 to maximize the light extraction efficiency of the pixel region SP.

In addition, the half-height aspect ratio (Rm) to the aspect ratio of the barrier 419 can be defined through (Equation 3) below.

(Equation 3)

Rm = (F_A/R)/(A/R) = D/2F

When the aspect ratio of the half-height to the aspect ratio of the barrier 419 (Rm) is less than 0.7, the height H of the barrier 419 is too low so that light incident from the light emitting device ED does not travel toward the substrate 401. However, the light extraction efficiency may decrease because the light emitting element ED is trapped in the light emitting device ED.

In addition, when the aspect ratio of the half-height to the aspect ratio of the barrier 419 (Rm) exceeds 1.0, the height (H) of the barrier 419 is too high, so light incident from the light emitting device (ED) is emitted from the substrate 401. The light extraction efficiency may be reduced because the light is not able to proceed toward the direction and is trapped within the barrier 419 .

In addition, when the half-height aspect ratio Rm to the aspect ratio of the barrier 419 exceeds 1.0, the rate of increase in current efficiency tends to decrease, whereas the half-height aspect ratio Rm to the aspect ratio of the barrier 419 is 0.7. to 1.0, the current efficiency increase rate of the light emitting device ED has a maximum value.

Therefore, the half-height aspect ratio Rm to the aspect ratio of the barrier 419 is preferably set in the range of 0.7 to 1.0 to maximize the light extraction efficiency of the pixel region SP.

13 is a graph showing the luminance efficiency according to the relationship between the half-height aspect ratio and the half-height aspect ratio of the barrier 419 according to the half-height width-aspect ratio of the barrier of the non-flattening layer. When the range is 1.0 and the aspect ratio (F_AR) of the half-height width (F) of the barrier 419 ranges from 0.4 to 0.8, it can be seen that the luminance efficiency for white is very high.

In addition, the slope S means the angle between the tangential line of the bottom portion 419a of the barrier 419 and the horizontal plane, and the maximum slope is the angle between the tangent line of the bottom portion 419a of the barrier 419 and the horizontal plane. means

When the slope (S) of the barrier 419 of the non-flattening layer 420 is less than 40 degrees, the light propagation angle in the effective light emitting area is not significantly different from that in the case where the barrier 419 is not formed, so the efficiency is improved. Almost none, and when the slope (S) of the barrier 419 exceeds 80 degrees, the light propagation angle may be formed greater than the total reflection angle of the substrate 401 and the air layer outside the substrate 401, so that the light emitting element (ED) ) can greatly increase the amount of light trapped inside.

Accordingly, the slope S of the barrier 419 is preferably set in the range of 40 degrees to 80 degrees in order to maximize the light extraction efficiency of the pixel region SP.

That is, in the light emitting display device 100 according to the second exemplary embodiment of the present invention, as the gap G is formed between adjacent barriers 419, the aspect ratio A/R of the barriers 419 is 0.5 to 1.0. The aspect ratio (F_AR) corresponding to the half-height width (F) of the barrier 419 is set in the range of 0.4 to 0.8, and the half-height aspect ratio (Rm) for the aspect ratio is set in the range of 0.7 to 1.0. In addition, by setting the slope (S) to have a range of 40 to 80 degrees, it has an optimal condition in which light extraction efficiency is maximized.

At this time, the gap (G) may be made of 0.3 to 10 micrometers.

In addition, the half-height width F of the barrier 419 may be set to 1 to 2.5 micrometers. When the half-height width F of the barrier 419 is less than 1 micrometer or greater than 2.5 micrometer, the light extraction efficiency of the barrier 419 may decrease.

That is, when the half-height width F of the barrier 419 is less than 1 micrometer, the amount of light emitted from the light emitting device ED is extracted toward the substrate 401 reflected by the barrier 419 is greater than that of the barrier 419. As the amount of light diffusely reflected from ) increases and the amount of light trapped in the light emitting device ED increases, the light extraction efficiency may decrease.

In particular, among the lights emitted from the light emitting device ED, light having an incident angle smaller than the critical angle of total reflection may be emitted to the outside of the substrate 401 through multiple reflections between the side surfaces 419c of the barrier 419 . On the other hand, when the half-height width F of the barrier 419 exceeds 2.5 micrometers, the amount of light emitted to the outside of the substrate 401 decreases as the amount of reflected light between the side surfaces 419c of the barrier 419 decreases. this will decrease

As described above, since the gap G is formed between adjacent barriers 419 in the light emitting display device 100 according to the second exemplary embodiment of the present invention, the aspect ratio A/R of the barriers 419 is 0.5. to 1.0, the aspect ratio (F_A/R) corresponding to the half-height width (F) of the barrier 419 is set to the range of 0.4 to 0.8, and the half-height aspect ratio (Rm) to the aspect ratio is 0.7 to 0.7. By setting it in the range of 1.0 and setting the slope (S) to have a range of 40 to 80 degrees, it has an optimal condition in which light extraction efficiency is maximized.

Meanwhile, in the above description, the second insulating layer 416 is formed of the 2-1 insulating layer 416-1 and the 2-2 insulating layer 416-2 above the wavelength conversion layer 414. Although described as an example, a barrier layer (not shown) may be provided above the wavelength conversion layer 414 instead of the 2-1 insulating layer 416-1.

This barrier layer (not shown) serves as an etch stopper on the wavelength conversion layer 414 when the non-planarization layer 420 is formed, thereby preventing the wavelength conversion layer 414 from being directly exposed to the groove 418. A problem caused by exposure of the wavelength conversion layer 414 is fundamentally prevented.

A barrier layer (not shown) according to an example may have a thickness corresponding to the shortest distance L1 between the bottom surface 418a of the grooves 418 and the wavelength conversion layer 414 . That is, the barrier layer (not shown) may be formed to a thickness of 0.1 to 3 micrometers in order to prevent the wavelength conversion layer 414 from being exposed to the groove 418 when the non-flattening layer 420 is formed. .

Such a barrier layer (not shown) may be made of a material that is not removed by a developing material (or an etching material) used during the patterning process of the second insulating layer 416 .

A barrier layer (not shown) according to another example may be made of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx). That is, the barrier layer 160 may be made of the same material as the first insulating layer 412 .

The present invention is not limited to the above embodiments, and can be practiced with various changes without departing from the spirit of the present invention.

100: substrate, 130: first insulating layer
150: wavelength conversion layer, 160: barrier layer
170: 2nd insulating layer, 170-1: 2-1st insulating layer
170-2: 2-2 insulating layer, 180: non-flattening layer
181: home, 183: barrier
190: bank, 200: encapsulation layer
300: encapsulation substrate

Claims (22)

a light emitting element having a light emitting layer between the first electrode and the second electrode;
a wavelength conversion layer overlapping the light emitting element; And a non-flattening layer having a plurality of grooves provided between the light emitting element and the wavelength conversion layer,
The shortest distance between the bottom surface of the grooves and the wavelength conversion layer is 0.1 micrometer or more,
a circuit region having a thin film transistor connected to the first electrode of the light emitting device; a first insulating layer covering the circuit area and supporting the wavelength conversion layer; and a second insulating layer covering the first insulating layer and the wavelength conversion layer;
The non-planarization layer is provided on the second insulating layer overlapping the wavelength conversion layer,
The second insulating layer directly contacts the first insulating layer and the wavelength conversion layer,
The second insulating layer has a two-layer structure and includes a 2-1 insulating layer and a 2-2 insulating layer formed separately from each other and made of the same material,
The 2-2 insulating layer provided with the non-flattening layer is thicker than the 2-1 insulating layer,
The 2-1 insulating layer directly contacts the top and side surfaces of the wavelength conversion layer and directly contacts the top surface of the first insulating layer,
The 2-2 insulating layer directly contacts the upper surface of the 2-1 insulating layer,
The first electrode is in direct contact with the upper surface of the non-planarization layer.
light-emitting display device.
According to claim 1,
The light emitting display device of claim 1 , wherein a shortest distance between bottom surfaces of the grooves and the wavelength conversion layer is 3 micrometers or less.
delete According to claim 1,
The light emitting display device of claim 1 , wherein the 2-1st insulating layer provided between bottom surfaces of the grooves and the wavelength conversion layer has a thickness of 0.1 to 3 micrometers.
a light emitting element having a light emitting layer between the first electrode and the second electrode;
a wavelength conversion layer overlapping the light emitting element; And a non-flattening layer having a plurality of grooves provided between the light emitting element and the wavelength conversion layer,
The shortest distance between the bottom surface of the grooves and the wavelength conversion layer is 0.1 micrometer or more,
a circuit region having a thin film transistor connected to the first electrode of the light emitting device; a first insulating layer covering the circuit area and supporting the wavelength conversion layer; a barrier layer covering the first insulating layer and the wavelength conversion layer; and a second insulating layer covering the barrier layer, wherein the non-planarization layer is provided on the second insulating layer overlapping the wavelength conversion layer;
The barrier layer has a thickness corresponding to the shortest distance between the bottom surface of the grooves and the wavelength conversion layer,
The barrier layer directly contacts the top and side surfaces of the wavelength conversion layer and directly contacts the top surface of the first insulating layer;
The second insulating layer directly contacts the upper surface of the barrier layer,
The second insulating layer is thicker than the barrier layer,
The first electrode is in direct contact with the upper surface of the non-planarization layer.
light-emitting display device.
According to claim 5,
Wherein the barrier layer has a thickness of 0.1 to 3 micrometers.
delete According to claim 5,
The barrier layer is made of the same material as the first insulating layer.
The method of any one of claims 1, 2, 4 to 6, and 8,
The non-planarization layer further includes a barrier defining each of the plurality of grooves;
The barrier is
a bottom portion adjacent to the wavelength conversion layer;
a top part spaced apart from the bottom part by a set height; and
A light emitting display device comprising a side portion between the bottom portion and the top portion.
According to claim 9,
The light emitting display device of claim 1 , wherein a cross-sectional area of the barrier parallel to the wavelength conversion layer increases as it approaches the wavelength conversion layer.
According to claim 9,
The side surface portion has a curved shape including an inflection point.
According to claim 11,
The light emitting display device, wherein each of the first electrode, the light emitting layer, and the second electrode has a shape following the shape of the non-flattening layer.
According to claim 12,
The side part,
an inflection part including the inflection point;
a first curved portion between the inflection portion and the bottom portion; and
And a second curved portion between the inflection portion and the top portion,
A thickness of the light emitting element covering the inflection part is smaller than a thickness of the light emitting element covering each of the first curved part and the second curved part.
delete According to claim 13,
The light emitting display device of claim 1 , wherein the barrier has an aspect ratio of a height to a size of a bottom portion of 0.4 to 0.7.
According to claim 13,
The light emitting display device of claim 1 , wherein adjacent bottom surfaces of the barriers are spaced apart from each other.
17. The method of claim 16,
The bottom part is spaced apart from 0.3 to 10 micrometers,
The light emitting display device of claim 1 , wherein an aspect ratio of a height to a radius of the bottom portion of the barrier is 0.5 to 1.0.
18. The method of claim 17,
The light emitting display device of claim 1 , wherein an aspect ratio of a height to a half-height width of the barrier is 0.4 to 0.8.
According to claim 18,
The light emitting display device of claim 1 , wherein an aspect ratio of a half-height to an aspect ratio of the barrier is 0.7 to 1.0.
According to claim 19,
The light emitting display device of claim 1 , wherein an inclination, which is an angle between a tangent line of an edge curved surface of the bottom portion of the barrier and a horizontal plane, is 40 degrees to 80 degrees.
delete delete