KR102571623B1 - 초기 리턴 예측을 갖는 분기 타겟 버퍼 - Google Patents

초기 리턴 예측을 갖는 분기 타겟 버퍼 Download PDF

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Publication number
KR102571623B1
KR102571623B1 KR1020217004753A KR20217004753A KR102571623B1 KR 102571623 B1 KR102571623 B1 KR 102571623B1 KR 1020217004753 A KR1020217004753 A KR 1020217004753A KR 20217004753 A KR20217004753 A KR 20217004753A KR 102571623 B1 KR102571623 B1 KR 102571623B1
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South Korea
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return
instruction
branch
btb
address
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Korean (ko)
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KR20210025677A (ko
Inventor
아파르나 티아가라잔
마리우스 에버스
아루나차람 아나말라이
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
KR1020217004753A 2018-07-24 2019-07-17 초기 리턴 예측을 갖는 분기 타겟 버퍼 Active KR102571623B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/043,293 2018-07-24
US16/043,293 US11055098B2 (en) 2018-07-24 2018-07-24 Branch target buffer with early return prediction
PCT/US2019/042176 WO2020023263A1 (en) 2018-07-24 2019-07-17 Branch target buffer with early return prediction

Publications (2)

Publication Number Publication Date
KR20210025677A KR20210025677A (ko) 2021-03-09
KR102571623B1 true KR102571623B1 (ko) 2023-08-29

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Family Applications (1)

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KR1020217004753A Active KR102571623B1 (ko) 2018-07-24 2019-07-17 초기 리턴 예측을 갖는 분기 타겟 버퍼

Country Status (6)

Country Link
US (1) US11055098B2 (https=)
EP (1) EP3827338A4 (https=)
JP (1) JP7269318B2 (https=)
KR (1) KR102571623B1 (https=)
CN (1) CN112470122B (https=)
WO (1) WO2020023263A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11663126B1 (en) * 2022-02-23 2023-05-30 International Business Machines Corporation Return address table branch predictor
CN116737240B (zh) * 2022-03-02 2024-08-06 腾讯科技（深圳）有限公司 分支预测方法、装置、处理器、介质及设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030120906A1 (en) 2001-12-21 2003-06-26 Jourdan Stephan J. Return address stack
US20050076193A1 (en) 2003-09-08 2005-04-07 Ip-First, Llc. Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
US20140143494A1 (en) 2012-11-19 2014-05-22 Florida State University Research Foundation, Inc. Systems and methods for improving processor efficiency through caching

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5604877A (en) * 1994-01-04 1997-02-18 Intel Corporation Method and apparatus for resolving return from subroutine instructions in a computer processor
US5964868A (en) * 1996-05-15 1999-10-12 Intel Corporation Method and apparatus for implementing a speculative return stack buffer
US5850543A (en) * 1996-10-30 1998-12-15 Texas Instruments Incorporated Microprocessor with speculative instruction pipelining storing a speculative register value within branch target buffer for use in speculatively executing instructions after a return
US6957327B1 (en) * 1998-12-31 2005-10-18 Stmicroelectronics, Inc. Block-based branch target buffer
US6609194B1 (en) * 1999-11-12 2003-08-19 Ip-First, Llc Apparatus for performing branch target address calculation based on branch type
US7200740B2 (en) * 2001-05-04 2007-04-03 Ip-First, Llc Apparatus and method for speculatively performing a return instruction in a microprocessor
US6973563B1 (en) 2002-01-04 2005-12-06 Advanced Micro Devices, Inc. Microprocessor including return prediction unit configured to determine whether a stored return address corresponds to more than one call instruction
US20040003213A1 (en) 2002-06-28 2004-01-01 Bockhaus John W. Method for reducing the latency of a branch target calculation by linking the branch target address cache with the call-return stack
US8341383B2 (en) * 2007-11-02 2012-12-25 Qualcomm Incorporated Method and a system for accelerating procedure return sequences
US7882338B2 (en) * 2008-02-20 2011-02-01 International Business Machines Corporation Method, system and computer program product for an implicit predicted return from a predicted subroutine
US7913068B2 (en) * 2008-02-21 2011-03-22 International Business Machines Corporation System and method for providing asynchronous dynamic millicode entry prediction
US20120079255A1 (en) 2010-09-25 2012-03-29 Combs Jonathan D Indirect branch prediction based on branch target buffer hysteresis
US10338928B2 (en) 2011-05-20 2019-07-02 Oracle International Corporation Utilizing a stack head register with a call return stack for each instruction fetch
WO2013101152A1 (en) * 2011-12-30 2013-07-04 Intel Corporation Embedded branch prediction unit
US20140250289A1 (en) * 2013-03-01 2014-09-04 Mips Technologies, Inc. Branch Target Buffer With Efficient Return Prediction Capability
US11099849B2 (en) 2016-09-01 2021-08-24 Oracle International Corporation Method for reducing fetch cycles for return-type instructions
US20190235873A1 (en) * 2018-01-30 2019-08-01 Samsung Electronics Co., Ltd. System and method of reducing computer processor power consumption using micro-btb verified edge feature
GB201802815D0 (en) * 2018-02-21 2018-04-04 Univ Edinburgh Branch target buffer arrangement for instruction prefetching
GB2577051B (en) * 2018-09-11 2021-03-03 Advanced Risc Mach Ltd Branch prediction using branch target buffer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030120906A1 (en) 2001-12-21 2003-06-26 Jourdan Stephan J. Return address stack
US20050076193A1 (en) 2003-09-08 2005-04-07 Ip-First, Llc. Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
US20140143494A1 (en) 2012-11-19 2014-05-22 Florida State University Research Foundation, Inc. Systems and methods for improving processor efficiency through caching

Also Published As

Publication number Publication date
US11055098B2 (en) 2021-07-06
CN112470122B (zh) 2022-05-10
JP7269318B2 (ja) 2023-05-08
JP2021532471A (ja) 2021-11-25
WO2020023263A1 (en) 2020-01-30
KR20210025677A (ko) 2021-03-09
EP3827338A4 (en) 2022-04-27
US20200034151A1 (en) 2020-01-30
EP3827338A1 (en) 2021-06-02
CN112470122A (zh) 2021-03-09

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