KR102569488B1 - Mixed construction apparatus and method of min* and min operator to reduce the number of slices used in implementation of LDPC codes decoder - Google Patents

Abstract

The present invention relates to a slice reduction apparatus and method for an LDPC decoder, and more particularly, to a slice reduction apparatus and method for an LDPC decoder capable of efficiently reducing the number of slice resources by combining a min* operation and a minimum sum operation. It's about how.
In addition, according to the present invention, an input unit for receiving an input signal having an order of n (n is a positive integer); a check node calculation module for calculating an individual output signal using a minstar calculation method and a minimum sum calculation method with respect to the input signal received by the input unit; and an output unit for outputting an output signal, which is a set of individual output signals calculated by the check node operation module, to efficiently reduce the number of slice resources by providing a slice saving apparatus and method for an LDPC decoder.

Description

Slice reduction apparatus and method of LDPC decoder {Mixed construction apparatus and method of min* and min operator to reduce the number of slices used in implementation of LDPC codes decoder}

The present invention relates to a slice reduction apparatus and method for an LDPC decoder, and more particularly, to a slice reduction apparatus and method for an LDPC decoder capable of efficiently reducing the number of slice resources by combining a min* operation and a minimum sum operation. It's about how.

In general, LDPC codes (Low Density Parity Check Codes) were first proposed by Gallager in 1962, and after Mackay and Neal rediscovered them in 1996, they have established themselves as the most advanced technology among channel coding technologies.

A feature of this code is that most of the elements of the parity check matrix are made of 0, and the number of non-zero elements is small compared to the code length, so that iterative decoding based on probability is possible.

The first proposed LDPC code defined a parity check matrix in a non-systematic form, and was designed to have uniformly low weight in its rows and columns.

Here, weight means the number of 1s included in a column or row in a matrix.

Since the density of non-zero elements on the parity check matrix H of the LDPC code is small, decoding complexity is low.

In addition, decoding performance is superior to existing codes, showing good performance approaching the theoretical limit of Shannon. However, the LDPC code was difficult to implement as a hardware technology at the time, so it did not attract the attention of many people for more than 30 years.

In the early 1980s, a method for iterative decoding using a graph was developed, and various algorithms that can actually decode LDPC codes using this method have been developed.

A great advantage of LDPC codes compared to other channel coding techniques is excellent performance at high code rates required for high-speed data transmission.

The decoding process of LDPC (Low-Density Parity Check) codes can be separated into bit node update and check node update parts, and errors are corrected while repeating these processes sequentially.

At this time, in the process of updating the check node, the sum-product algorithm (SPA: Sum-Product Algorithm) and the minimum-sum algorithm (MSA: Min-Sum Algorithm) are typically used. In the case of the sum-product algorithm, error correction capability is relatively excellent, but hardware resource Conversely, in the least sum algorithm, the error correction ability is slightly lowered, but the hardware resource consumption can be greatly reduced.

In the existing LDPC code implementation process, a tree-structured LDPC decoder has been designed using the sum-product algorithm and similar techniques rather than the minimum-sum algorithm to satisfy the Quality of Service (QoS) presented in the wireless mobile communication standard. It served as a limitation in reducing the number of slice resources.

On the other hand, in order to reduce the computational complexity in the process of implementing the LDPC code with an FPGA, the multiplication operation of the sum-product algorithm is generally replaced with the min star (min ^* ) operation. At this time, the min star (min ^* ) operation module contains A Look Up Table (LUT) is included to replace the tanh ^{- 1} operation of the operation.

Therefore, as the codeword length of the LDPC code increases and the input/output order of each check node calculation module increases, the number of slices consumed increases during implementation, which is evaluated as an inefficient part from the FPGA implementation point of view.

Therefore, in order to reduce the number of consumed slices, the MSA technique is generally used. In this way, the number of consumed slices can be reduced, but error correction capability is poor (about 0.5 dB difference).

Therefore, to overcome this problem, a scaled-MSA technique that multiplies the minimum value of two input values by a random value between 0 and 1 during the check node update operation process, and a normalized method that subtracts a random value between 0 and 1 from the minimum value -MSA techniques, etc. have been developed.

However, even if these techniques are used, the error correction capability is somewhat lower than that of SPA (or MSA) (about 0.1 to 0.2 dB difference), and the increase in slice consumption due to the addition of a multiplier or subtractor cannot be ignored.

[Document 1] R. G. Gallager, “Low-Density Parity-Check Codes”. IRE Transaction on Information theory, Jan, 1962. [Document 2] John R. Barry, “Low-Density Parity-check Codes”, Georgia Institute of Technology, Oct, 2001. [Document 3] Seongwoon Kim, Changsoo Park, Seonyeong Hwang, “Implementation of a DVB-S2 LDPC Code Decoder with High Throughput Performance”, Journal of the Korean Society of Communications Engineers ‘08-09 Vol 33 No. 9, Sep, 2008, p. 924-933 [Document 4] Junyoung Wi, Sungwon Kim and Jun Heo, “Design of DVB-S2 LDPC Decoders With Various Code Rates”, ICT-CSCC 2014, Jul. 2014

Therefore, in order to solve the above problem, the present invention properly mixes the min star (min ^* ) algorithm and the minimum sum algorithm in the tree structure of the check node update operation process to increase the number of slice resources despite a slight error correction performance degradation. It is an object of the present invention to provide an apparatus and method for reducing slices of an LDPC decoder capable of reducing slices.

An aspect of the present invention is an input signal having order n (n is a positive integer) an input unit that receives input; a check node calculation module for calculating an individual output signal using a minstar calculation method and a minimum sum calculation method with respect to the input signal received by the input unit; and an output signal that is a set of individual output signals calculated by the check node calculation module. It includes an output unit that outputs.

In addition, the check node calculation module according to one aspect of the present invention is a first operator generating an output signal by using a minstar calculation technique in a section in which the check node update calculation is performed in a tournament format with respect to the input signal received by the input unit. ; and a second operator calculating individual output signals by using a minimum sum technique in a section in which an operation is performed on the output signal of the first operator in an inverse-tournament format.

In addition, the first calculator according to one aspect of the present invention binds a plurality of input information into two pieces, performs independent calculations, and proceeds until two outputs remain.

In addition, the first operator of one aspect of the present invention is characterized in that it performs the minstar operation using Equations 2 and 3 below.

In addition, the second operator of one aspect of the present invention is characterized in that it performs the minimum sum operation using Equations 2 and 4 below.

On the other hand, another aspect of the present invention is (A) an input signal having an input unit of order n (n is a positive integer) Receiving an input; (B) calculating, by the check node calculation module, individual output signals using the minstar calculation method and the minimum sum calculation method; and (C) an output signal that is a set of the calculated individual output signals. It includes the step of outputting.

In addition, in the step (B) of another aspect of the present invention, (B-1) a minstar operation technique in a section in which the check node operation module performs a check node update operation in a tournament format with respect to the input signal received by the input unit. generating an output signal using and (B-2) calculating individual output signals by using a minimum sum technique in a section in which the check node calculation module performs calculations on output signals in an inverse-tournament format.

Further, in the step (B-1) of another aspect of the present invention, the check node calculation module binds a plurality of input information into two pieces and performs independent calculations, and proceeds until two outputs remain.

In addition, the check node calculation module in step (B-1) of another aspect of the present invention performs minstar calculation using Equations 2 and 3.

In addition, the check node calculation module in step (B-2) of another aspect of the present invention performs a minimum sum operation using Equations 2 and 4.

According to the present invention, it is possible to reduce the number of slices consumed while minimizing the degradation of error correction performance in hardware implementation of the LDPC code.

To this end, in the present invention, in the tree structure of the check node update operation process, a method of using a min star (min ^* ) operation module in some sections at the beginning and a minimum sum operation module in some sections in the second half is used.

And as a result of checking the error correction result when using this method and verifying using a synthesis tool, it was confirmed that the slice area consumed more efficiently can be reduced.

1 is a state diagram illustrating a decoding process of an LDPC code from a hardware implementation point of view.
2 is a tenor graph expressing a decoding process of an LDPC code from a hardware implementation point of view.
3 is a check node update computation tree structure in the case where the input/output order is 8 in the present invention.
Figure 4 shows the implemented LDPC code hardware implementation structure of the present invention.
5 shows a tree structure of the check node update operation module proposed in the present invention.
6 is a block diagram of a slice reduction device of an LDPC decoder according to an embodiment of the present invention.
7 is a flowchart of a slice reduction method of an LDPC decoder according to an embodiment of the present invention.
8 is a result of comparing the number of consumed slices as a result of FPGA synthesis according to the present invention.
Figure 9 means the LUT algorithm inside the check node calculation module applied in the implementation of the present invention.
10 means a BER performance curve according to the check node operation method proposed in the present invention.

In order to explain the present invention and the operational advantages of the present invention and the objects achieved by the practice of the present invention, the following describes a preferred embodiment of the present invention and references it.

First, the terms used in this application are used only to describe specific embodiments, and are not intended to limit the present invention, and singular expressions may include plural expressions unless the context clearly dictates otherwise. In addition, in this application, terms such as "comprise" or "have" are intended to designate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or more other It should be understood that the presence or addition of features, numbers, steps, operations, components, parts, or combinations thereof is not precluded.

In describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description will be omitted.

First, the general decoding process of the LDPC code proceeds in the following order.

(1) initialization

Initialization in a general decoding process of an LDPC code is expressed by Equation 1 below.

(Equation 1)

means a message transmitted to an adjacent check node k _i connected by an edge based on the n-th bit node, and u _n means the n-th LLR (Log Likelihood Ratio) value of an N-length codeword. Here, An edge means a line connecting each node.

(2) Inspection node update

Is the information value coming from d _c bit nodes connected to the k-th check node, Assuming that is an information value transmitted from the k-th check node to d _c adjacent bit nodes, it is expressed as in Equation 2 below.

(Equation 2)

And, here, the g( ) function is equal to Equation 3 below when based on the min star (min ^* ) operation, and equal to Equation 4 below when based on the minimum sum operation.

(Equation 3)

(Equation 4)

During the check node update operation process in the above process In fact, there are many constraints in hardware implementation. Therefore, this part is implemented using a look-up table (LUT) based on the values of a and b, which are input information.

(3) Bit node update

is the information value coming from d _v check nodes connected to the nth bit node, When is the information value transmitted from the n-th bit node to d _v adjacent check nodes, the bit node update process is expressed as follows.

(Equation 5)

That is, it is a process of adding information messages received from d _v -1 check nodes except for one check node to which an information message will be sent after updating the bit node and the channel LLR value.

(4) Hard decision process

When all parity check equations satisfy the hard decision conditional expression, it means that a valid codeword (valid_codeword) is restored, and then the decoding process is terminated.

In addition, a state diagram and a tanner graph expressing the decoding process of the above-described LDPC code from a hardware implementation point of view are shown in FIGS. 1 and 2 .

In FIG. 1, a variable called bc_cnt serves as a counter to control the process of updating the bit node (BN) and check node (CN), and iteratively performs a decoding process using this variable.

At this time, only addition and subtraction operations are used in the bit node update operation module part, but various operation techniques such as minstar (min*), minimum sum operation (min), scaled, and normalized can be applied to the check node operation module part.

Next, referring to FIG. 2, calculation is performed using various information input based on an arbitrary inspection node, and at this time, the output information is calculated using the remaining information except for the input information received from the direction to be output. In the drawing, the blue line is the input and the red line is the output.

3 shows a tree structure of a check node update operation process when the input degree of the check node operation module is 8.

Looking at this, from the introductory part to the middle part, two input values are tied together in a tournament format, and the min* operation is performed in parallel and at the same time. And from the subsequent process to the end, it is a process of generating output information in a reverse-tournament format, that is, corresponding to the number of input information. (In performing the check node update operation module process in a situation where the degree of input information is 8, at least 4 steps are consumed from the hardware implementation point of view)

이고, 출력 신호는 8개의 개별 출력 신호의 집합인

이다. Referring to this, the input signal is a set of eight individual input signals.

, and the output signal is a set of eight individual output signals.

am.

The FPGA hardware structure of the LDPC code implemented in the process of verifying the present invention is shown in FIG. 4, and the LDPC code used in the DVB-S2X broadcasting standard is implemented.

The codeword length implemented in this process is 64,800 bits, and the supportable code rates are 90/180 and 135/180, which can be supported integrally, and each operation module decodes 360 bits in turn during the iterative decoding process. It was designed as a partial parallelization structure so that

As can be seen in FIG. 3, as the input/output order increases based on an arbitrary check node update operation module, the number of min* operators used increases significantly.

In addition, as can be seen in FIG. 4, the number of slice resources consumed in proportion to the parallelization level increases significantly in the design of a parallel structure for improving throughput when implementing an error correction code in FPGA hardware.

Therefore, in order to solve the given problem, a decryption design structure as shown in FIG. 5 is proposed.

Meanwhile, referring to FIG. 4 , the bit node operation module 10, the first local memory 20, the check node operation module 30, the second local memory 40, the memory controller 50 and the main controller 60 includes

The bit node operation module 10 is a module in which bit nodes are grouped according to a parity check matrix rule based on the DVB-S2 standard. In the bit node operation module 10, a plurality of bit node operation modules 11, 12, 13, and 14 each performing bit operation are connected in parallel.

The first local memory 20 stores output values of the bit node calculation module 10 and provides the values to the check node calculation module 30 .

In the first local memory 20, a plurality of local memories 21, 22, 23, and 24 respectively corresponding to the plurality of bit node calculation modules 11, 12, 13, and 14 are connected in parallel.

The check node calculation module 30 is a module that groups check nodes according to parity check matrix rules based on the DVB-S2 standard.

In the check node calculation module 30, a plurality of check node calculation modules 31, 32, 33, and 34 are connected in parallel.

The second local memory 40 stores output values of the check node calculation module 30 and provides the values to the bit node calculation module 10 .

In the second local memory 40, a plurality of local memories 41, 42, 43, and 44 respectively corresponding to the plurality of check node calculation modules 31, 32, 33, and 34 are connected in parallel.

The memory control unit 50 informs addresses of memory to store the output values of the bit node operation module 10 and the check node operation module 30, and the bit node operation module 10 and the check node operation module 30 tells the memory address of the value to be provided as input.

Meanwhile, an unshown channel LLR memory is a memory in which channel LLR (Log Likelihood Ratio) values are stored, and channel LLR values to be used for bit node calculation are input to the corresponding bit node calculation module 10 .

The main controller 60 controls the overall operation of the components 10 to 50 to perform an iterative decoding operation.

That is, in FIG. 4 , the main controller 60 controls the input value of the bit node calculation module 10 by controlling the second local memory 40 and the channel LLR memory. The bit node operation is performed using the input value of the bit node operation module 10 , and the operation result value of the bit node operation module 10 is stored in the first local memory 20 . Then, the value stored in the first local memory 20 is used as an input value of the check node calculation module 30 to perform a check node calculation in the check node calculation module 30, and the check node calculation module 30 ) is stored in the second local memory 40.

When performing the decoding operation in the above, the main controller 60 selectively controls the components 10 to 50. For example, the bit node calculation module 10 and the check node calculation module 30 are controlled not to perform calculation operations while an input value is input to the bit node calculation module 10 .

In other words, the main controller 60 controls the input value of the bit node operation module 10 stored in the second local memory 40 and the channel LLR value stored in the channel LLR memory through the memory controller 50 to input to the bit node calculation module 10.

Based on the input value, each bit node calculation module 10 performs bit node calculation and then stores the resultant value of the operation in the first local memory 20 .

The values stored in the first local memory 20 are input to the check node calculation module 30 under the control of the memory controller 50 .

Based on the input value, each check node calculation module 30 performs a check node calculation and stores the result of the calculation in the second local memory 40 . This completes one iteration process. After that, the above-described process is continuously repeated to proceed with decoding.

5 shows a check node update operation tree structure when the maximum order is 16 in the DVB-S2X standard based LDPC code, which is actually implemented for the verification process of the present invention.

Looking at this, the minstar (min ^* ) technique was used in the section where the check node update operation was performed in a tournament format, and the least sum technique was used in the section where the operation was performed in an inverse-tournament format.

By using such a technique, the number of consumed slices can be greatly reduced because the LUT part included in the min ^* operation technique can be reduced by half.

6 is a block diagram of a slice reduction device of an LDPC decoder according to an embodiment of the present invention.

Referring to FIG. 6 , an apparatus for reducing a slice of an LDPC decoder according to an embodiment of the present invention includes an input unit 100 , a check node calculation module 200 and an output unit 300 .

The check node calculation module 200 is composed of a first calculator 210 and a second calculator 220 .

7 is a flowchart of a slice reduction method of an LDPC decoder according to an embodiment of the present invention.

의 입력신호를 입력받는다(S100). 6 and 7, the input unit 100 when the input order is n

The input signal of is received (S100).

The input signal is a set of n individual input signals, and can generally be expressed as a parity check matrix. n is a positive integer and may have any value less than or equal to the maximum order. Therefore, in the embodiments of the present invention, it is possible to process input signals of various orders at once through one decoding method without requiring separate decoding methods.

Then, the check node operation module 200 arranges the first operator 210 and the second operator 220 using a tree structure based on the input order of the input signal.

The check node calculation module 200 performs independent calculations by grouping a plurality of input information into two pieces due to the nature of the tree structure calculation process. In the section where is repeated, the min star (min ^* ) technique is used, and the operation proceeds until two outputs of the first operator 210 remain (S110). At this time, the first operator 210 performs an operation using Equation 3.

In addition, the check node calculation module 200 uses the least sum technique in the section where parallel calculation is repeated in the form of an inverse-tournament using the second calculator 220, and proceeds until the end of the check node update operation ( S120). At this time, the second operator 220 performs an operation using Equation 4.

를 출력한다(S130). 입력 신호의 차수에 따라 출력 신호의 개별 출력 신호의 개수도 결정된다. 즉, n차수의 입력 신호는 n개의 개별 입력 신호의 집합이고, 출력 신호 역시 n개의 개별 출력 신호의 집합이 된다. 복호화 방법에 따른 입력 및 출력 과정은 본실시예의 구현 환경에 따라 다양하게 구현될 수 있는 것으로, 여기서는 구체적인 설명을 생략한다.The output unit 300 is an output signal that is a set of calculated individual output signals.

Outputs (S130). The number of individual output signals of the output signal is also determined according to the order of the input signal. That is, an input signal of order n is a set of n individual input signals, and an output signal is also a set of n individual output signals. Input and output processes according to the decoding method can be implemented in various ways according to the implementation environment of the present embodiment, and detailed descriptions are omitted here.

Meanwhile, the check node calculation module 200 of the apparatus and method for slice reduction of the LDPC decoder according to the present embodiment is applied to the check node calculation module 130 of FIG. 4 .

On the other hand, the result of FPGA synthesis using the synthesis tool (Xilinx ISE tool, based on vertex 7) is shown in FIG.

Looking at this, the number of consumed slices when implemented using only the existing minstar (min ^* ) operation module is about 91529.25 slices, and the number of consumed slices when implemented using the proposed method is about 58793 slices. That is, it was confirmed that the number of consumed slices can be reduced by about 36% when using the proposed method.

In addition, it was confirmed that there was no significant performance degradation when looking at the error correction aspect of the simulation results. Originally, as the iterative min star (min ^* ) operation is performed, the difference between the two input information of the check node update operation module finally converges to a number closer to 0.

Accordingly, the LUT output value obtained based on the difference between the minimum value and the absolute value using the two input values of the calculation module also converges to 0. (Refer to the LUT algorithm implemented in FIG. 9) Therefore, through the min star (min ^* ) process applied to the first half of the check node update, it is probabilistically possible that the minimum value corresponding to all input values of the check node calculation module is obtained. It is high, and thereafter, even if the least sum operation technique is used, performance degradation does not occur. The BER performance curve results obtained through the simulation process are shown in FIG. 8 .

The blue curve in FIG. 10 means the SPA method using the min star (min ^* ) calculation module, and the red curve means the MSA method using the minimum sum calculation module.

And the green curve in the middle means the BER performance curve graph of the method of compounding by mixing the min star (min ^* ) operation and the minimum sum operation proposed in the present invention.

According to the present invention, it is possible to reduce the number of slices consumed while minimizing the degradation of error correction performance in hardware implementation of the LDPC code.

To this end, in the present invention, in the tree structure of the check node update operation process, a method of using a min star (min ^* ) operation module in some sections at the beginning and a minimum sum operation module in some sections in the second half is used.

And as a result of checking the error correction result when using this method and verifying using a synthesis tool, it was confirmed that the slice area consumed more efficiently can be reduced.

The above description is merely an example of the technical idea of the present invention, and various modifications and variations can be made to those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments described in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

10, 11, 12, 13, 14: bit node calculation module
20, 21, 22, 23, 24: first local memory
30, 31, 32, 33, 34: check node calculation module
40, 41, 42, 43, 44: second local memory
50, 51, 52: memory control unit
60: main control unit
100: input unit
200: check node calculation module
300: output unit

Claims (10)

Input signal of order n, where n is a positive integer an input unit that receives input;
a check node calculation module for calculating an individual output signal using a minstar calculation method and a minimum sum calculation method with respect to the input signal received by the input unit; and
An output signal that is a set of individual output signals calculated by the check node calculation module. Including an output unit that outputs,
The check node calculation module may include: a first operator generating an output signal by using a minstar calculation technique in a section in which a check node update calculation is performed in a tournament format; and
A second operator calculating an individual output signal using a least sum technique in a section in which an operation is performed in an inverse-tournament format is included;
The first operator,
Is the information value coming from d _c bit nodes connected to the k-th check node, Assuming that is an information value transmitted from the k-th check node to d _c adjacent bit nodes, the operation expressed by Equation 2 below is performed,
(Equation 2)

Here, the g( ) function is as shown in Equation 3 below based on the minstar operation, a and b are input signals,
(Equation 3)

The second operator,
Is the information value coming from d _c bit nodes connected to the k-th check node, Assuming that is an information value transmitted from the k-th check node to d _c adjacent bit nodes, the operation expressed as in Equation 2 is performed,
In the second operator, the g( ) function is as shown in Equation 4 below based on the minimum sum operation,
(Equation 4)

Here, a and b are input signals, a slice reduction device of an LDPC decoder. The method of claim 1,
for the input signals a and b The value of is a slice reduction device of the LDPC decoder using a lookup table. The method of claim 1,
The slice saving device of the LDPC decoder, wherein the first operator performs independent operations by grouping a plurality of input information into two pieces, and proceeds until two outputs remain. delete delete (A) An input signal whose degree is n (n is a positive integer) Receiving an input;
(B) calculating, by the check node calculation module, individual output signals using the minstar calculation method and the minimum sum calculation method; and
(C) The output unit is an output signal that is a set of the calculated individual output signals. Including the step of outputting,
The step (B) is
(B-1) generating an output signal by using a minstar calculation technique in a section in which the check node calculation module performs a check node update calculation in a tournament format; and
(B-2) calculating, by the check node calculation module, an individual output signal using a least sum technique in a section in which calculation is performed in an inverse-tournament format;
The check node calculation module in step (B-1) Is the information value coming from d _c bit nodes connected to the k-th check node, Assuming that is an information value transmitted from the k-th check node to d _c adjacent bit nodes, the operation expressed by Equation 2 below is performed,
(Equation 2)

Here, the g( ) function is as shown in Equation 3 below based on the minstar operation, a and b are input signals,
(Equation 3)

The check node calculation module in step (B-2) Is the information value coming from d _c bit nodes connected to the k-th check node, Assuming that is an information value transmitted from the k-th check node to d _c adjacent bit nodes, the operation expressed as in Equation 2 is performed,
In the step (B-2), the g( ) function is as shown in Equation 4 below based on the minimum sum operation,
(Equation 4)

Here, a and b are input signals, a slice reduction method of an LDPC decoder. The method of claim 6,
for the input signals a and b The value of is a slice reduction method of an LDPC decoder using a lookup table. The method of claim 6,
In the step (B-1), the check node calculation module bundles a plurality of input information into two pieces, performs independent calculations, and proceeds until two outputs remain. delete delete

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