KR102564615B1 - Display and driving method for the same - Google Patents

Abstract

The present embodiments include a plurality of pixels formed in an area where a plurality of gate lines and a plurality of data lines intersect, and each of the plurality of pixels is compensated by a commonly transmitted compensation signal, and then a data signal is generated by the gate signal. is sequentially received and stored, a display panel in which a plurality of pixels emit light in response to a commonly transmitted light emitting signal, a gate driver that transmits a gate signal to a plurality of gate lines, and a data signal transmitted to a plurality of data lines. It relates to a display device including a data driver and a method of driving the same.
According to the present embodiments, the display device and its driving method can save time required for a compensation period for compensating for a threshold voltage.

Description

Display device and its driving method {DISPLAY AND DRIVING METHOD FOR THE SAME}

The present embodiments relate to a display device and a driving method thereof.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, and liquid crystal display devices (LCD: Liquid Crystal Display Device), plasma display devices, organic light emitting display devices ( Various types of display devices such as organic light emitting display devices (OLEDs) are being utilized.

Among these display devices, since the organic light emitting display emits light in response to the flow of current driven by the driving transistor, there is a problem in that the amount of light emitted is different depending on the deviation of the threshold voltage of the driving transistor. . In order to solve this problem, the drive is performed by compensating for the threshold voltage, but the time for storing the data signal may not be sufficiently secured due to the time for compensating for the threshold voltage. In addition, the light emission section for emitting light may not be sufficient due to the compensation section and the section for transmitting the data signal. Due to this, a problem in that the image quality of the display device may be deteriorated may occur.

An object of the present embodiments is to provide a display device capable of saving time required for one frame and a driving method thereof.

Another object of the present embodiments is to reduce manufacturing cost and provide a display device having a high resolution and a driving method thereof.

In one aspect, the present embodiments include a plurality of pixels formed in an area where a plurality of gate lines and a plurality of data lines intersect, and the plurality of pixels are compensated by a compensation signal transmitted in common, and then output to the gate signal. a display panel that sequentially receives and stores data signals, and current flows through a plurality of pixels in response to a commonly transmitted light emitting signal so that the plurality of pixels emit light; a gate driver that transmits a gate signal to a plurality of gate lines; and , To provide a display device including a data driver for transferring data signals to a plurality of data lines.

From another aspect, the present embodiments include a plurality of gate lines, a plurality of data lines, and a plurality of pixels formed in an area where the plurality of gate lines and the plurality of data lines intersect, and the plurality of pixels are in a compensation period. To provide a display panel that receives compensation signals that are commonly transmitted to each other, sequentially receives and stores data signals in each programming section, and emits light by flowing current in response to light-emitting signals that are commonly transmitted to each of the light-emitting sections.

In another aspect, the present embodiments are a method for driving a display device displaying an image including a plurality of frames, including a compensation step of transmitting a compensation signal corresponding to the start of each of the plurality of frames, sequentially after the compensation signal is transmitted. A method of driving a display device including a programming step of transmitting a plurality of data signals corresponding to one frame, and a light emitting step of transmitting a light emitting signal to display an image corresponding to the plurality of data signals after the programming step. is to provide

According to the present embodiments, it is possible to provide a display device and a driving method thereof that do not require setting a compensation period for each gate line for compensating the threshold voltage of a transistor included in a pixel. For this reason, the display device and its driving method according to the present embodiments can save time required for a compensation period for compensating for the threshold voltage.

In addition, according to the present embodiments, since the time corresponding to one frame can be implemented in a short time, a data signal can be sufficiently written even in a high frequency environment, and a display device capable of using a high frequency and a driving method thereof can be provided.

In addition, according to the present embodiments, it is possible to provide a display device and a driving method thereof capable of implementing a long programming time as needed by adjusting a programming time for writing data signals into pixels. For this reason, according to the present embodiments, the display device and its driving method can increase the programming time to a certain extent even if the data signal is time-divided and outputted through the output terminal of one data driver using a mux, so that a high-resolution display panel can be used. there is.

1 is a structural diagram showing an example of a display device according to the present embodiment.
FIG. 2 is a circuit diagram illustrating an exemplary embodiment of a pixel employed in the display device illustrated in FIG. 1 .
FIG. 3 is a timing diagram illustrating operations of a display panel employing the pixels shown in FIG. 2 .
FIG. 4 is a circuit diagram illustrating a second embodiment of a pixel employed in the display device shown in FIG. 1 .
FIG. 5 is a timing diagram illustrating operations of a display panel employing the pixels shown in FIG. 4 .
FIG. 6 is a circuit diagram illustrating an embodiment of the mux shown in FIG. 1 .
FIG. 7 is a flowchart illustrating driving of the display device shown in FIG. 1 .
FIG. 8A is an example illustrating a process of transmitting signals in each step in the method of driving the display device shown in FIG. 7 .
FIG. 8B is a comparison example comparing the process of transmitting the signal shown in FIG. 8A.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention are described in detail below with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

Also, terms such as first, second, A, B, (a), and (b) may be used in describing the components of the present invention. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the corresponding component is not limited by the term. When an element is described as being “connected,” “coupled to,” or “connected” to another element, that element is or may be directly connected to that other element, but intervenes between each element. It will be understood that may be "interposed", or each component may be "connected", "coupled" or "connected" through other components.

1 is a structural diagram showing an example of a display device according to the present embodiment.

Referring to FIG. 1 , a display device 100 may include a display panel 110 , a gate driver 120 , a data driver 130 and a controller 150 .

The display panel 110 is formed in an area where a plurality of gate lines (S1, S2, ..., Sn-1, Sn) and a plurality of data lines (D1, D2, ..., Dm-1, Dm) intersect. A plurality of pixels 101 may be included. In addition, each of the plurality of pixels 101 receives and stores data signals sequentially through a gate signal after being compensated by a commonly transmitted compensation signal, and stores the plurality of pixels 101 in response to a commonly transmitted light emitting signal. can emit light. As a result, the compensation period in which the compensation signal is transmitted in common can be common for each gate line (S1, S2, ..., Sn-1, Sn), and thus the time required for the compensation period can be reduced.

The compensation signal may be transmitted through the plurality of gate lines S1, S2, ..., Sn-1, and Sn. However, it is not limited thereto. Here, each pixel 101 is illustrated as being connected to a gate line and a data line, but is not limited thereto, and the display panel 110 may further include an initialization signal line, a light emitting signal line, and a high potential voltage line. Each pixel 101 may be connected to an initialization signal line, a light emitting signal line, a high potential voltage line, etc. to receive an initialization signal, a light emitting signal, and a high potential voltage. Common transmission of compensation signals may mean that, when one compensation signal is generated by the control unit 150, the generated compensation signal is transmitted to a plurality of gate lines. When one compensation signal is transmitted to a plurality of gate lines (S1, S2, ..., Sn-1, Sn) in common, the compensation signal is transmitted to a plurality of gate lines (S1, S2, ..., Sn-1, Sn). ) can be delivered simultaneously. The common transfer of the light emitting signals may mean that the light emitting signals are simultaneously transferred to the pixels 101 . Here, simultaneous does not mean perfectly coincident in time, but may also include occurrence of a slight time difference.

When a method of transmitting a light emitting signal in common so that a plurality of pixels emit light at the same time is applied to a display device having a high resolution, a compensation period and data storage time may be long. In this case, since the light emission time is not sufficient, the quality of the display device may deteriorate. However, as in the present embodiment, if the compensation signal can be transmitted in common and the compensation section can be reduced in the section of one frame, the emission time can be secured by the time corresponding to the reduced compensation section, even if the resolution is high, and the image quality of the display device is deteriorated. problem can be solved.

The gate driver 120 may sequentially transmit gate signals to the plurality of gate lines S1, S2, ..., Sn-1, Sn. When gate signals are sequentially transferred to pixels through a plurality of gate lines (S1, S2, ..., Sn-1, Sn), they are transmitted through a plurality of data lines (D1, D2, ..., Dm-1, Dm). A data signal may be transmitted to the pixel 101. In addition, the gate driver 120 may transfer the compensation signal to the plurality of gate lines S1, S2, ..., Sn-1, Sn. In addition, the gate driver 120 may generate a light emitting signal and transfer it to the display panel 110 . In this case, the gate driver 120 may transmit the light emitting signal to the pixel 101 by connecting the light emitting signal line through which the light emitting signal is transmitted to the pixel 10 .

When a gate signal and a light emitting signal are generated by the gate driver 120 and transmitted to the display panel 110, the gate driver 120 includes a gate signal unit (not shown) for generating a gate signal and a light emitting signal unit for generating a light emitting signal. (not shown). At this time, if the light emitting signal is transmitted to each pixel in common, the structure of the gate driver 120 can be simplified because there is no need to make the light emitting signal unit that generates the light emitting signal corresponding to the pixels corresponding to each gate line. There are advantages to being In addition, if the gate driver 120 does not generate a light emitting signal, there is no need to make a light emitting signal part in the gate driver 120, so the gate driver 120 can be configured more simply. Here, the gate driver 120 is illustrated as being disposed on the left side of the display panel 110, but is not limited thereto.

The data driver 130 may transfer data signals to the plurality of data lines D1, D2, ..., Dm-1, Dm. The data signals transmitted through the plurality of data lines D1, D2, ..., Dm-1, and Dm may be transmitted to the pixels to which the gate signals are transmitted through the gate driver 120 and stored therein.

The control unit 150 transmits control signals including a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), and a clock (clk) to the gate driver 120 and the data driver 130 so that the gate driver 120 and data The driving unit 130 may be driven. Also, the control unit 150 may transmit a data signal to the data driving unit 130 . However, it is not limited thereto. In addition, when the gate driver 120 does not generate a light emitting signal, the controller 150 may generate and output a light emitting signal. However, it is not limited thereto. The light emitting signal transmitted from the control unit 150 may be transmitted to the pixel or may be transmitted to a separate switch without being transmitted to the pixel 101, and turn on/off of the switch may be controlled using the light emitting signal. The controller 150 may be a timing controller that controls the operation of the display device 100 . However, it is not limited thereto.

In one embodiment, in the display device 100, a multiplexer 140 including at least one multiplexer may be further connected between the plurality of output terminals of the data driver 130 and the data lines. Each of the plurality of muxes 141_1, 141_2, ..., 141_q-1, 141_q has an input terminal connected to one output terminal among a plurality of output terminals of the data driver 130, and each output terminal has a plurality of data lines D1 and D2. .., Dm-1, Dm) may be connected to at least two different data lines. A control signal for controlling the mux may be output from the controller 150 . However, it is not limited thereto.

FIG. 2 is a circuit diagram illustrating an exemplary embodiment of a pixel employed in the display device illustrated in FIG. 1 .

Referring to FIG. 2 , the pixel 101a may include a pixel circuit including an OLED, first to fourth transistors T1a to T4a, and two capacitors C1a and C2a and controlling a current flowing through the OLED. there is. Here, the first transistor T1a may be a driving transistor that drives current flowing through the OLED.

The first electrode of the first transistor T1a may be connected to the second electrode of the fourth transistor T4a, the second electrode may be connected to the anode of the OLED, and the gate electrode may be connected to the first node N1a. Also, the first transistor T1a may drive a current from the first electrode to the second electrode in response to a voltage difference between the second electrode and the gate electrode.

The second transistor T2a has a first electrode connected to the data line Dm, a second electrode connected to the first node N1a, and a gate electrode connected to the gate line Sn. The second transistor T2a transmits the data voltage Vdata corresponding to the data signal transmitted through the data line Dm to the first node N1a in response to the voltage of the gate signal transmitted through the gate line Sn. can be conveyed

In the third transistor T3a, the first electrode is connected to the initialization signal line IVL to which the initialization voltage VINI corresponding to the initialization signal is transmitted, the second electrode is connected to the second node N2a, and the gate electrode is initialized. It may be connected to an initialization control signal line INI_EN that controls transfer of an initialization signal transmitted through the signal line IVL.

In the fourth transistor T4a, the first electrode is connected to the high potential voltage line VL to which the high potential voltage ELVDD is transmitted, the second electrode is connected to the first electrode of the first transistor T1a, and the gate electrode emits light. It may be connected to the light emitting signal line EMa through which a signal is transmitted.

The first capacitor C1a is connected between the first node N1a and the second node N2a and can maintain a constant voltage between the gate electrode and the source electrode of the first transistor T1a.

The second capacitor C2a may be connected between the anode electrode and the cathode electrode of the OLED, and may be connected in series with the first capacitor C1a to reduce the time during which the voltage is charged in the first capacitor C1a. The position of the second capacitor C2a is not limited thereto and may be disposed at a position that can be connected in series with the first capacitor C1a.

The first electrode of each transistor described above may be a drain electrode and the second electrode may be a source electrode. However, it is not limited thereto. In addition, each transistor is shown as an N MOS transistor, but is not limited thereto and may be a P MOS transistor.

FIG. 3 is a timing diagram illustrating operations of a display panel employing the pixels shown in FIG. 2 .

Referring to FIG. 3 , in the first period T1a, the initialization control signal ini_en is transmitted to the gate electrode of the third transistor T3a through the initialization control signal line INI_EN, so that the third transistor T3a is turned on. It can be. Also, the second transistor T2a and the fourth transistor T4a may be maintained in an off state. When the third transistor T3a is turned on, the initialization voltage VINI corresponding to the initialization signal transmitted through the initialization signal line IVL can be transmitted to the second node N2a, so that the first capacitor C1a is initialized. It can be. The initialization voltage VINI may be a low voltage capable of preventing current from flowing through the OLED. The initialization voltage VINI may be commonly transmitted to a plurality of pixels of the display panel 110 . The first period T1a may be referred to as an initialization period.

In the second period T2a, the compensation signal samPa may be commonly transmitted through the gate line Sn. What is commonly transmitted may be that the compensation signal samPa can be simultaneously transmitted through the plurality of gate lines S1 , S2 , ... , Sn−1 , and Sn connected to the gate driver 120 . A compensation period in which the compensation signal is commonly transmitted and the compensation signal is transmitted may be separately set for each frame. Here, simultaneous does not mean the exact same in time, but may include the existence of a certain time difference. Also, the compensation signal samPa may be transmitted through the emission signal line EMa. The transfer time of the compensation signal samPa through the plurality of gate lines S1, S2, ..., Sn-1, and Sn and the emission signal line EMa may overlap with each other. In addition, the compensation signal transmitted through the light emitting signal line EMa in the second period T2a may be referred to as a first light emitting signal among light emitting signals.

The second transistor T2a and the fourth transistor T4a may be turned on by the compensation signal samPa transmitted through the gate line Sn and the emission signal line EMa. Also, the third transistor T3a may maintain an off state. When the second transistor T2a and the fourth transistor T4a are turned on, current flows from the high potential voltage ELVDD to the second node N2a, and the voltage of the second node N2a is applied to the first transistor T1a. It flows until the voltage corresponding to the difference between the gate voltage and the threshold voltage is reached, and the first capacitor C1a can store the threshold voltage. Due to this, the threshold voltage of the first transistor T1a may be compensated. The second period T2a may be referred to as a compensation period or a sampling period.

In the third period T3a, when the gate signal Sn is transmitted to the gate line Sn, the second transistor T2a may be turned on. Also, the third transistor T3a and the fourth transistor T4a may be maintained in an off state. At this time, the display panel 110 includes a plurality of gate lines S1, S2, ..., Sn-1, and Sn, and gate signals transmitted to each gate line may be sequentially transmitted. When the second transistor T2a is turned on by the gate signal sn transmitted to the gate line Sn, the data voltage Vdata corresponding to the data signal can be transferred to the first node N1a. A voltage corresponding to a difference between the data voltage Vdata and the threshold voltage of the first transistor T1a may be stored in the capacitor C1a. The third section T3a may be referred to as a programming section.

In the fourth period T4a, the fourth transistor T4a may be turned on by the light emitting signal ema transmitted through the light emitting signal line EMa. Also, the second transistor T2a and the third transistor T3a may maintain an off state. When the fourth transistor T4a is turned on, current flows from the first electrode to the second electrode of the first transistor T1a by the voltage stored in the first capacitor C1a, so that the current is driven in the OLED and light is emitted. will emit light. The fourth section T4a may be referred to as a light emission section. In addition, the light emitting signal transmitted through the light emitting signal line EMa in the fourth period T4a may be referred to as a second light emitting signal. Here, it is shown that the light emitting signal ema is transmitted through one light emitting signal line EMa, but this is for convenience of explanation. The light emitting signal is transmitted to each of the plurality of light emitting signal lines, and the light emitting signal is simultaneously transmitted. can Here, simultaneous does not mean only the same time, but may include the existence of a predetermined time difference. In addition, since one light emitting signal output from the gate driver can be transmitted to each light emitting signal line, the structure of the light emitting signal unit outputting the light signal from the gate driver can be reduced or omitted, thereby simplifying the structure of the gate driver. can In addition, light emitting signals transmitted in common may have sections overlapping with each other.

For this reason, instead of setting a compensation period or sampling period for each gate line of the display panel 110, a compensation period or sampling period is set so that a compensation signal is commonly transmitted to each gate line, and the set compensation period or sampling period In the display panel 110, the compensation signal may be transmitted simultaneously through the plurality of gate lines S1, S2, ..., Sn-1, and Sn and the emission signal line EMa. As a result, it is possible to shorten the compensation period or sampling period by 1H time in one frame compared to setting the compensation period or sampling period for each gate line.

FIG. 4 is a circuit diagram illustrating a second embodiment of a pixel employed in the display device shown in FIG. 1 .

Referring to FIG. 4 , the pixel 101b may include a pixel circuit including an OLED, first to third transistors T1b to T3b, and two capacitors C1b and C2b and controlling a current flowing through the OLED. there is. Here, the first transistor T1b may be a driving transistor that drives current flowing through the OLED. In addition, a fourth transistor T4b may be connected between the OLED and the low potential voltage ELVSS separately from the pixel 101b. The low potential voltage ELVSS may be ground. However, it is not limited thereto. Here, the fourth transistor T4b is illustrated as corresponding to one pixel, but is not limited thereto, and a plurality of pixels connected to different gate lines may share one fourth transistor T4b. . Also, a plurality of pixels of the display panel 110 may share one fourth transistor T4b. As a result, the number of transistors included in the pixel circuit can be reduced compared to the pixel circuit shown in FIG. 2 . Also, the fourth transistor T4b may be a separate switch described in FIG. 1 .

The first electrode of the first transistor T1b is connected to the high potential voltage line VL to which the high potential voltage ELVDD is delivered, the second electrode is connected to the anode of the OLED, and the gate electrode is connected to the first node N1b. can be connected Also, the first transistor T1b can drive a current from the first electrode to the second electrode in response to a voltage difference between the second electrode and the gate electrode.

The second transistor T2b has a first electrode connected to the data line Dm, a second electrode connected to the first node N1b, and a gate electrode connected to the gate line Sn. The second transistor T2b transmits the data voltage Vdata corresponding to the data signal transmitted through the data line Dm to the first node N1b in response to the voltage of the gate signal transmitted through the gate line Sn. can be conveyed

In the third transistor T3b, the first electrode is connected to the initialization signal line IVL to which the initialization voltage VINI corresponding to the initialization signal is transmitted, the second electrode is connected to the second node N2b, and the gate electrode is initialized. It may be connected to an initialization control signal line INI_EN that controls transfer of an initialization signal transmitted through the signal line IVL.

The fourth transistor T4b has a first electrode connected to the cathode electrode of the OLED, a second electrode connected to the low potential voltage ELVSS, and a gate electrode connected to the light emitting signal line EMb through which the light emitting signal is transmitted. Here, the fourth transistor T4b is not included in the pixel circuit, but is connected between the low potential voltage ELVSS connected to the plurality of OLEDs in common and the OLED, so that the cathode electrode of the plurality of OLEDs is one fourth transistor T4b. ) can be connected to

The first capacitor C1b is connected between the first node N1b and the second node N2b and can maintain a constant voltage between the gate electrode and the source electrode of the first transistor T1b.

The second capacitor C2b may be connected between the anode electrode and the cathode electrode of the OLED, and may be connected in series with the first capacitor C1b to reduce the time during which the voltage is charged in the first capacitor C1b. The position of the second capacitor C2b is not limited thereto and may be disposed at a position that can be connected in series with the first capacitor C1b.

The first electrode of each transistor described above may be a drain electrode and the second electrode may be a source electrode. However, it is not limited thereto. In addition, each transistor is shown as an N MOS transistor, but is not limited thereto and may be a P MOS transistor.

FIG. 5 is a timing diagram illustrating operations of a display panel employing the pixels shown in FIG. 4 .

Referring to FIG. 5, in the first period T1b, the initialization control signal ini_en is transferred to the gate electrode of the third transistor T3b through the initialization control signal line INI_EN so that the third transistor T3b is turned on. It can be. Also, the second transistor T2b and the fourth transistor T4b may be maintained in an off state. When the third transistor T3b is turned on, the initialization voltage VINI corresponding to the initialization signal transmitted through the initialization signal line IVL can be transmitted to the second node N2b, so that the first capacitor C1b is initialized. It can be. The initialization voltage VINI may be a low voltage capable of preventing current from flowing through the OLED. The initialization voltage VINI may be commonly transmitted to all of the plurality of pixels of the display panel 110 . The first period T1b may be referred to as an initialization period.

In the second period T2b, the compensation signal samPb may be transmitted through the gate line Sn. The compensation signal samPb may be transmitted simultaneously through the plurality of gate lines S1 , S2 , ... , Sn-1 , and Sn connected to the gate driver 120 . Here, simultaneous does not mean the exact same time, but may include the presence of a certain time difference. The second transistor T2b may be turned on by the compensation signal samPb transmitted through the gate line Sn. The compensation signal samPb transmitted through the gate line Sn may overlap a section transmitted to other pixels connected to other gate lines. The third transistor T3b and the fourth transistor T4b may remain off. When the second transistor T2b is turned on, current flows from the high potential voltage ELVDD to the second node N2b, and the voltage of the second node N2a is the difference between the gate voltage and the threshold voltage of the first transistor T1b. It flows until the voltage corresponding to the difference is reached, so that the first capacitor C1b can store the threshold voltage. Due to this, the threshold voltage of the first transistor T1b may be compensated. The second period T2b may be referred to as a compensation period or a sampling period.

In the third period T3b, when the gate signal Sn is transmitted to the gate line Sn, the second transistor T2b may be turned on. Also, the third transistor T3b and the fourth transistor T4b may be maintained in an off state. At this time, the display panel 110 includes a plurality of gate lines, and gate signals transmitted to each gate line may be sequentially transmitted. When the second transistor T2b is turned on by the gate signal sn transmitted to the gate line Sn, the data voltage Vdata corresponding to the data signal can be transferred to the first node N1b. A voltage corresponding to a difference between the data voltage Vdata and the threshold voltage of the first transistor T1b may be stored in the capacitor C1b. The third section T3b may be referred to as a programming section.

In the fourth period T4b, the fourth transistor T4b may be turned on by the light emitting signal emb transmitted through the light emitting signal line EMb. Also, the second transistor T2b and the third transistor T3b may be maintained in an off state. When the fourth transistor T4b is turned on, current flows from the first electrode to the second electrode of the first transistor T1b by the voltage stored in the first capacitor C1b, so that the current is driven in the OLED and light is emitted. will emit light. The fourth section T4b may be referred to as a light emission section.

For this reason, instead of setting a compensation section or sampling section for each gate line of the display panel 110, a compensation section or sampling section for common transmission of a compensation section is set, and in the set compensation section or sampling section, the display panel ( 110) through the plurality of gate lines (S1, S2, ..., Sn-1, Sn) can be transmitted simultaneously compensation signal. As a result, it is possible to shorten the compensation period or sampling period by 1H time in one frame compared to setting the compensation period or sampling period for each gate line.

FIG. 6 is a circuit diagram illustrating an embodiment of the mux shown in FIG. 1 .

Referring to FIG. 6 , the mux 141_q may selectively output a signal transmitted through one input terminal to two output terminals OUT1 and OUT2. However, it is not limited thereto, and a signal transmitted through one input terminal may be selectively output through three output terminals.

The mux 141_q includes a first transistor T61 connected between the first input terminal IN1 and the first output terminal OUT1 and a second transistor connected between the first input terminal IN1 and the second output terminal OUT2 ( T62) may be included. Further, the first transistor T61 and the second transistor T62 receive the control signal from the control unit 150 shown in FIG. 1 and are turned on/off to control the signal output from the first input terminal IN1. It may be transmitted to the first output terminal OUT1 or the signal output from the first input terminal IN1 may be transmitted to the second output terminal OUT2. Here, the first input terminal IN1 may be connected to one output terminal Ox of the data driver 130 shown in FIG. 1, and the first and second output terminals OUT1 and OUT2 are shown in FIG. It may be different data lines Dm-1 and Dm disposed on the display panel 110. For this reason, the control unit 150 shown in FIG. 1 controls the data driving unit 130 to output different data signals through one output terminal of the data driving unit 130 through time division, and the output data signals are muxed. By the operation of (141_q), it can be transmitted to different data lines (Dm-1, Dm). Therefore, the number of output terminals of the data driver 130 may be less than the number of data lines Dm-1 and Dm disposed on the display panel 110. As a result, the film that electrically connects the data driver 130 and the display panel 110 can be formed from two layers to one layer, thereby reducing manufacturing costs.

FIG. 7 is a flowchart illustrating driving of the display device shown in FIG. 1 .

Referring to FIG. 7 , the display device driving a display device displaying an image including a plurality of frames includes a compensation step of transmitting a compensation signal corresponding to the start of each of the plurality of frames (S710). ), a programming step of sequentially transmitting a plurality of data signals corresponding to one frame after the compensation signal is transmitted (S720), and, after the programming step (S720), displaying an image corresponding to a plurality of data signals A light emitting step (S730) of transmitting a light emitting signal may be included.

In the compensating step (S710), a compensating signal may be commonly transmitted to a plurality of gate lines in order to transmit the compensating signal corresponding to the start of each frame. Here, common may mean that when one compensation signal is generated in the controller 150 shown in FIG. 1, the generated one compensation signal is transmitted to a plurality of gate lines. When one compensation signal is transmitted to a plurality of gate lines, the compensation signal may be simultaneously transmitted to the plurality of gate lines. Here, simultaneous does not mean perfectly coincident in time, but may also include occurrence of a slight time difference.

In the programming step (S720), the data voltage corresponding to the data signal is stored in the frame corresponding to the image, and the data voltage is stored after the compensation signal is transmitted in the compensation step (S710), as shown in FIGS. 2 and 4 After the threshold voltage of the first transistor of the pixel is compensated, the data voltage may be stored. In the programming step S720, the stored data voltages corresponding to the data signals may be sequentially stored for each gate line. Here, the image may include a photo or a video that is continuously displayed on the display device for a predetermined time or more.

In the light emitting step (S730), when the storage of the data voltage corresponding to the data signal is completed in the programming step (S720), the current corresponding to the data voltage is driven to the OLED by the light emitting signal so that the OLED can emit light. there is.

In an embodiment, the driving method of the display device may further include an initialization step (S700) of transmitting an initialization signal for initializing a data signal corresponding to a frame previous to a frame displayed before the compensating step (S710). In the initialization step ( S700 ), the initialization signal may cause the initialization voltage corresponding to each initialization signal to be simultaneously transmitted to the pixels through the initialization signal line.

FIG. 8A is an embodiment illustrating a signal transfer process for each step in the method of driving the display device shown in FIG. 7 , and FIG. 8B is a comparative example compared to the signal transfer process shown in FIG. 8A . . 8A and 8B respectively display the n-th frame and the n+1-th frame in an image including a plurality of frames.

Referring to FIG. 8A , in each of the n-th frame (n frame) and the n+1-th frame (n+1 frame), after a programming period progresses for a predetermined time, an emission period proceeds and a compensation period may proceed. In the programming period, gate signals are sequentially transmitted through the gate lines of the display panel, and data voltages corresponding to the data signals are stored at different times for each gate line. And, after the programming period ends, the light emission period is executed, and the light emission signal is transmitted in common so that the light emission period starts at the same time. And, after the light emission section ends, the compensation section starts. In the compensation section, the compensation signal is transmitted in common, so that the compensation section starts at the same time. As a result, since the compensation period does not proceed for each gate line, a time margin Tm may be generated between the n-th frame (n frame) and the n+1-th frame (n+1 frame).

However, referring to FIG. 8B , after the programming section is executed in the n-th frame (n frame) and the n+1-th frame (n+1 frame), it is shown that the emission section proceeds. In FIG. 8B , when a data voltage corresponding to a data signal is stored, threshold voltage compensation of the driving transistor is simultaneously performed, and a light emitting signal is transmitted in common so that the light emitting period starts at the same time.

In the case of FIG. 8B, compensation and programming are performed on pixels connected to one gate line, and then compensation and programming are performed on pixels connected to the next gate line. Since programming is performed after compensating for pixels connected to a plurality of gate lines, the time required for compensation does not proceed separately for each gate line, so the compensation period is short, making up one frame by about 1H time compared to the case of FIG. 8B. time may be shortened.

Therefore, in the case of FIG. 8A, a time margin (Tm) of about 1H time can be generated than in FIG. It is possible to apply

The above description and accompanying drawings are merely illustrative of the technical idea of the present invention, and those skilled in the art can combine the configuration within the scope not departing from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed according to the claims below, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display device
101: pixel
110: display panel
120: gate driving unit
130: data driving unit
140: mux part
150: control unit

Claims (19)

It includes a plurality of pixels formed in an area where a plurality of gate lines and a plurality of data lines intersect, and each of the plurality of pixels is compensated by a commonly transmitted compensation signal and then sequentially transmits a data signal by the gate signal. a display panel that receives, stores, and emits light from the plurality of pixels by flowing a current through the plurality of pixels in response to a commonly transmitted light emission signal;
a gate driver transferring the gate signal to the plurality of gate lines; and
A data driver for transmitting the data signal to the plurality of data lines;
Each of the plurality of pixels has at least:
A first transistor including a first electrode to which a voltage corresponding to the high potential voltage is transmitted, a gate electrode connected to the first node, and a second electrode connected to the second node, to drive a current flowing in the organic light emitting device;
a first electrode connected to one of the plurality of data lines, a second electrode connected to the first node, and a gate electrode connected to one of the plurality of gate lines; a second transistor for transferring a data voltage to the first node in response to the voltage of the gate signal transmitted through a line;
An initialization control signal through the initialization control signal line, including a first electrode connected to an initialization signal line through which an initialization voltage is transmitted, a second electrode connected to the second node, and a gate electrode connected to an initialization control signal line a third transistor for controlling transfer of the initialization voltage through the initialization signal line; and
A capacitor connected between the first node and the second node,
In a state where the voltage of the gate signal is set to turn off the second transistor, the initialization voltage through the initialization signal line is transferred to the second node by the initialization control signal for turning on the third transistor. and one of the plurality of pixels is initialized. According to claim 1,
A time period during which the commonly transmitted compensation signal is applied to the plurality of gate lines overlaps. According to claim 2,
wherein each of the plurality of pixels is connected to a light emitting signal line, and the gate driver transfers the light emitting signal through the light emitting signal line. According to claim 3,
The light-emitting signal line is a display in which the light-emitting signal is transmitted to the plurality of pixels after the compensation signal overlapping with the compensation signal transmitted through the gate line and the gate signal are transmitted to the last gate line among the plurality of gate lines. Device. According to claim 1,
The display device of claim 1 , wherein the display panel further includes a switch that blocks the current flowing through the plurality of pixels, and wherein the switch performs a switching operation in response to the emission signal. delete According to claim 1,
At least one MUX is connected between a plurality of output terminals of the data driver and the data lines, an input terminal of the MUX is connected to one output terminal among the plurality of output terminals, and two output terminals of the MUX are connected to the plurality of data lines. A display device connected to two different data lines among them. a plurality of gate lines;
a plurality of data lines; and
a plurality of pixels formed in an area where the plurality of gate lines and the plurality of data lines intersect;
The plurality of pixels receive a compensation signal that is commonly transmitted to each of the compensation sections, receive and store data signals sequentially transmitted to each of the programming sections, and emit light as a current flows in response to a light emission signal that is commonly transmitted to each of the light emission sections. and
Each of the plurality of pixels has at least:
A first transistor including a first electrode to which a voltage corresponding to the high potential voltage is transmitted, a gate electrode connected to the first node, and a second electrode connected to the second node, to drive a current flowing in the organic light emitting device;
a first electrode connected to one of the plurality of data lines, a second electrode connected to the first node, and a gate electrode connected to one of the plurality of gate lines; a second transistor for transferring a data voltage to the first node in response to a voltage of a gate signal transmitted through a line;
An initialization control signal through the initialization control signal line, including a first electrode connected to an initialization signal line through which an initialization voltage is transmitted, a second electrode connected to the second node, and a gate electrode connected to an initialization control signal line a third transistor for controlling transfer of the initialization voltage through the initialization signal line; and
A capacitor connected between the first node and the second node,
In a state where the voltage of the gate signal is set to turn off the second transistor, the initialization voltage through the initialization signal line is transferred to the second node by the initialization control signal for turning on the third transistor. and one of the plurality of pixels is initialized. According to claim 8,
The display panel of claim 1 , wherein a time period during which the compensation signal, which is commonly transmitted, is applied to the plurality of gate lines overlaps. According to claim 8,
Each of the plurality of pixels is connected to a light emitting signal line, and the compensation signal is transmitted to the plurality of gate lines and the plurality of light emitting signal lines, and the compensation signal is transmitted to the plurality of gate lines and the plurality of light emitting signal lines. The transmitted time is an overlapping display panel. According to claim 10,
The light emitting signal line transmits a light emitting signal, the light emitting signal is divided into a first light emitting signal and a second light emitting signal, the first light emitting signal is a signal transmitted to the light emitting signal line in the compensation section, and the first light emitting signal is transmitted to the light emitting signal line. 2. The light emission signal is a signal transmitted to the plurality of pixels in the emission period after the gate signal is transmitted to the last gate line among the plurality of gate lines. According to claim 8,
The display panel further includes a switch that cuts off the current flowing through the plurality of pixels, wherein the switch performs a switching operation in response to the emission signal. delete A method of driving a display device displaying an image including a plurality of frames,
The driving method is
a compensation step of transmitting a compensation signal corresponding to the start of each of the plurality of frames;
a programming step of sequentially transmitting a plurality of data signals corresponding to one frame after the compensation signal is transmitted; and
After the programming step, a light emitting step of transmitting a light emitting signal for displaying an image corresponding to the plurality of data signals,
Each of the plurality of pixels for displaying the image has at least:
A first transistor including a first electrode to which a voltage corresponding to the high potential voltage is transmitted, a gate electrode connected to the first node, and a second electrode connected to the second node, to drive a current flowing in the organic light emitting device;
a first electrode connected to one of the plurality of data lines, a second electrode connected to the first node, and a gate electrode connected to one of the plurality of gate lines; a second transistor for transferring a data voltage to the first node in response to a voltage of a gate signal transmitted through a line;
An initialization control signal through the initialization control signal line, including a first electrode connected to an initialization signal line through which an initialization voltage is transmitted, a second electrode connected to the second node, and a gate electrode connected to an initialization control signal line a third transistor for controlling transfer of the initialization voltage through the initialization signal line; and
A capacitor connected between the first node and the second node,
In a state where the voltage of the gate signal is set to turn off the second transistor, the initialization voltage through the initialization signal line is transferred to the second node by the initialization control signal for turning on the third transistor. A method of driving a display device in which one pixel among the plurality of pixels is initialized. According to claim 14,
In the compensating step, a compensating signal is commonly transmitted to a plurality of gate lines of the display panel. According to claim 14,
In the compensating step, a compensating signal is commonly transmitted to a plurality of gate lines and a plurality of emission signal lines of the display panel. According to claim 14,
In the programming step, the gate signal is sequentially transmitted to the plurality of gate lines, and a voltage corresponding to the data signal transmitted through the data line corresponding to the gate signal is stored in the plurality of pixels. driving method. According to claim 14,
The light emitting step is a method of driving a display device in which a light emitting signal is transmitted to the light emitting signal line in common to the plurality of pixels included in the display panel in which a plurality of gate lines, a plurality of data lines, and a plurality of light emitting signal lines intersect. . According to claim 14,
and an initialization step of transmitting the initialization signal for initializing a data signal corresponding to a frame previous to a frame displayed before the compensating step.

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