KR102557776B1 - Generating circuit for power and display apparatus with integrated touch screen comprising the same - Google Patents

Abstract

The present invention provides a power generation circuit capable of preventing a decrease in sensing sensitivity due to noise components and a touch screen integrated display device including the same. The power generation circuit according to the present invention provides a gate high voltage and a pulse modulation clock signal and and a pulse modulation circuit generating a plurality of gate pulse modulated signals using a pulse modulation enable signal having a first period and a second period, wherein the pulse modulation circuit outputs a DC voltage during the first period, and the pulse modulation circuit outputs a DC voltage during the first period. A plurality of gate pulse modulation signals can be output during the 2-period.

Description

A power generation circuit and a touch screen integrated display device including the same

The present invention relates to a display device integrated with a touch screen.

A touch screen device is a type of input device that inputs information through screen contact of a liquid crystal display device without a separate input device in various electronic devices. Such touch screen devices are used as input devices for various products such as televisions, laptop computers, monitors, and portable electronic devices.

Recently, demand for an in-cell touch type liquid crystal display device in which elements constituting a touch panel are embedded inside the liquid crystal display panel is increasing in order to slim down the liquid crystal display device. Since the in-cell touch-type liquid crystal display device uses a common electrode as a touch electrode, the liquid crystal display panel is driven in a time-division manner into a display section and a touch sensing section.

An active matrix type liquid crystal display device includes a liquid crystal cell provided in each of a plurality of pixels, and the liquid crystal cell includes a pixel electrode to which a data voltage is supplied, a common electrode to which a common voltage is supplied, and a liquid crystal layer provided between the pixel electrode and the common electrode. includes In such a liquid crystal display device, the voltage charged in the liquid crystal cell is affected by the kick-back voltage (or feed through voltage) generated due to the parasitic capacitance of the thin film transistor, and due to this kick-back voltage As the voltage applied to the pixel electrode of the liquid crystal cell fluctuates, flicker, afterimage, and color deviation occur in an image displayed on the liquid crystal display panel. This kick-back voltage can be reduced by a gate pulse modulation method that reduces the level of the gate high voltage at the falling edge of the gate pulse. That is, the gate pulse modulation method modulates the falling period of the gate high voltage with the gate pulse modulation voltage in order to lower the voltage difference between the gate high voltage and the gate low voltage of the gate pulse, thereby reducing the deterioration of image quality due to the kick-back voltage.

When such a gate pulse modulation method is applied to an in-cell touch type liquid crystal display device, deterioration in picture quality due to kick-back voltage can be improved. However, in the in-cell touch-type liquid crystal display device, the gate pulse modulation voltage is generated regardless of the display period and the touch sensing period, so that it acts as a noise component of the touch driving pulse in the touch sensing period. There is a problem in that the sensitivity is lowered.

The contents of the background art described above are technical information that the inventor of the present application possessed for derivation of the present invention or acquired in the process of derivation of the present invention, and must be known art disclosed to the general public prior to filing the present invention. can't

The present invention has been made to solve the above problems, and a technical problem is to provide a power generation circuit capable of preventing a decrease in sensing sensitivity due to noise components and a touch screen integrated display device including the same.

A power generation circuit according to the present invention includes a pulse modulation circuit for generating a plurality of gate pulse modulated signals using a gate high voltage, a pulse modulated clock signal, and a pulse modulated enable signal having a first period and a second period, The pulse modulation circuit may output a DC voltage during the first period and output a plurality of gate pulse modulation signals during the second period.

A touch screen integrated display device according to the present invention has a pulse modulation circuit for generating a plurality of gate pulse modulation signals using a gate high voltage, a pulse modulation clock signal, and a pulse modulation enable signal having a first period and a second period. A display panel having a power generation circuit, a gate line, a data line, and a touch electrode, supplying a touch driving signal to the touch electrode in a first period, sensing a change in capacitance through the touch electrode to generate touch data, and generating touch data in a second period A touch driving circuit supplying a common voltage to electrodes may be included, and the pulse modulation circuit may output a DC voltage during a first period and output a plurality of gate pulse modulation signals during a second period.

According to the present invention, by disabling the power generation circuit during the touch sensing period or by controlling the DC voltage to be output from the power generation circuit, it is possible to prevent a noise component caused by an alternating current gate pulse modulation signal from being introduced into a touch driving signal. This can improve the sensing sensitivity.

According to the present invention, a touch driving signal supplied to a touch electrode, a data load free signal supplied to all data lines, and a gate load free signal supplied to all gate lines have the same phase, thereby reducing the load of the touch electrodes. Touch sensitivity may be further improved.

In addition to the effects of the present invention mentioned above, other features and advantages of the present invention will be described below, or will be clearly understood by those skilled in the art from such description and description.

1 is a diagram for explaining a display device integrated with a touch screen according to an example of the present invention.
FIG. 2 is a diagram for explaining the timing control circuit shown in FIG. 1 .
FIG. 3 is a waveform diagram illustrating a touch synchronization signal output from the timing control circuit shown in FIG. 2 , an example of a pulse modulation enable signal, and an example of a pulse modulation clock signal.
FIG. 4 is a waveform diagram illustrating a touch synchronization signal output from the timing control circuit shown in FIG. 2 , a pulse modulation enable signal of another example, and a pulse modulation clock signal of another example.
FIG. 5 is a diagram for explaining a power generating circuit shown in FIG. 1 .
FIG. 6 is a waveform diagram showing input/output waveforms of the power generation circuit according to the first example shown in FIG. 5 .
FIG. 7 is a waveform diagram showing input/output waveforms of the power generation circuit according to the second example shown in FIG. 5 .
FIG. 8 is a diagram for explaining the touch driving circuit shown in FIG. 1 .
FIG. 9 is a diagram for explaining the data driving circuit shown in FIG. 1 .
FIG. 10 is a diagram for explaining the gate driving circuit shown in FIG. 1 .
11 is a waveform diagram showing driving waveforms of a display device integrated with a touch screen according to an example of the present invention.
12 is a waveform diagram showing driving waveforms of a display device integrated with a touch screen according to another example of the present invention.
13A and 13B are simulation waveform diagrams illustrating whether or not noise is generated in a touch driving signal according to gate pulse modulation in a comparison example and an example of the present invention.

The meaning of terms described in this specification should be understood as follows.

Singular expressions should be understood to include plural expressions unless the context clearly defines otherwise, and terms such as “first” and “second” are used to distinguish one component from another, The scope of rights should not be limited by these terms. It should be understood that terms such as "comprise" or "having" do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. The term “at least one” should be understood to include all possible combinations from one or more related items. For example, "at least one of the first item, the second item, and the third item" means not only the first item, the second item, or the third item, respectively, but also two of the first item, the second item, and the third item. It means a combination of all items that can be presented from one or more. The term "on" means not only the case where a certain component is formed directly on top of another component, but also the case where a third component is interposed between these components.

Hereinafter, a preferred example of a power generation circuit according to the present invention and a touch screen integrated display device including the same will be described in detail with reference to the accompanying drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

1 is a diagram for explaining a display device integrated with a touch screen according to an example of the present invention.

Referring to FIG. 1 , a touch screen integrated display device according to an example of the present invention includes a display panel 100, a timing control circuit 200, a power generation circuit 300, a touch driving circuit 400, and a data driving circuit ( 500), and a gate driving circuit 600.

The display panel 100 may be a liquid crystal display panel including an in-cell touch type touch electrode TE using a self-capacitance method. The display panel 100 may operate in a display mode and a touch sensing mode under the control of the timing control circuit 200 . For example, the display panel 100 displays an image using light emitted from a backlight unit (not shown) during the display mode, and during the touch sensing mode, the display panel 100 for touch sensing according to the change in capacitance of the touch electrodes TE. Serves as a touch panel.

The display panel 100 according to an example includes a plurality of data lines DL1 to DLn, a plurality of gate lines GL1 to GLm, a plurality of sub-pixels SP, a plurality of touch routing lines TL1 to TLk, and It includes a plurality of touch electrodes TE.

The plurality of data lines DL1 to DLn and the plurality of gate lines GL1 to GLm may be provided to cross each other on a substrate (not shown) to define a plurality of sub-pixel areas.

The plurality of data lines (DL1 to DLn) are provided parallel to a second horizontal axis direction (Y) intersecting the first horizontal axis direction (X) while having regular intervals along the first horizontal axis direction (X), or It may be provided in a zigzag shape along the second horizontal axis direction (Y). The plurality of data lines DL1 to DLn receive the data load free signal LFS1 through the data driving circuit 500 in a touch sensing mode and receive data signals from the data driving circuit 500 in a display mode.

The plurality of gate lines GL1 to GLm are provided at regular intervals along the second horizontal axis direction Y while parallel to the first horizontal axis direction X to cross the plurality of data lines DL1 to DLn. The plurality of gate lines GL1 to GLm receive a gate pulse, that is, the gate pulse modulation signal VGHM, from the gate driving circuit 600 during the scan period in the display mode, and operate the gate driving circuit during the rest of the display period except for the scan period. The gate low voltage (VGL) is received from 600. Also, the plurality of gate lines GL1 to GLm receive the gate load free signal LFS2 through the gate driving circuit 600 in the touch sensing mode.

Each of the plurality of subpixels SP includes a thin film transistor (not shown), a pixel electrode (not shown), and a storage capacitor (not shown).

The thin film transistor includes a gate electrode, a semiconductor layer, and source/drain electrodes, and may have a bottom gate structure in which the gate electrode is positioned below the semiconductor layer, or the gate electrode is positioned on the semiconductor layer. It may also consist of a top gate structure. A gate electrode and a source electrode of the thin film transistor are respectively connected to a gate line GL and a data line defining a corresponding subpixel. This thin film transistor is covered by a protective layer (or planarization layer) not shown.

The pixel electrode is provided on the passivation layer in the sub-pixel area and is connected to the drain electrode of the thin film transistor through a via hole provided in the passivation layer. The pixel electrode may include a transparent conductive material such as indium tin oxide (ITO).

Although not shown, the pixel electrode according to an example may include at least one slit therein. In this case, a fringe field may be formed between the pixel electrode and the touch electrode TE through the slit. ) is formed, and the liquid crystal can be driven in a fringe field switching mode by this fringe field.

Although not shown, a pixel electrode according to another example may include a plurality of pixel finger patterns having regular intervals. In this case, although not shown, the sub-pixel SP may further include a plurality of common finger patterns spaced apart from each of the plurality of pixel finger patterns and provided parallel to each other and connected to the touch electrode TE. A horizontal electric field is formed between the plurality of common finger patterns and the plurality of pixel finger patterns, and the liquid crystal may be driven in an in-plane switching mode by the horizontal electric field.

The storage capacitor may be formed between the thin film transistor and the touch electrode TE or may be formed between the pixel electrode and the touch electrode TE. The storage capacitor charges the data signal during the scan period and maintains an electric field formed between the pixel electrode and the touch electrode TE using the charged voltage during the display time.

Each of the plurality of touch routing lines TL1 to TLk is provided in the same form as the data line DL in each sub-pixel area on the passivation layer, and is individually connected to each of the plurality of touch electrodes TE. Each of the plurality of touch routing lines TL1 to TLk receives a common voltage Vcom from the touch driving circuit 400 in a display mode and receives a touch driving signal TDS from the touch driving circuit 400 in a touch sensing mode. receive

Each of the plurality of touch electrodes TE serves as a sensing electrode for sensing a user's touch or serves as a common electrode for driving liquid crystal by forming an electric field together with a pixel electrode. That is, each of the plurality of touch electrodes TE is used as a sensing electrode in a touch sensing mode and used as a common electrode in a display mode. Since each of the plurality of touch electrodes TE is also used as a common electrode for driving the liquid crystal, it may include a transparent conductive material such as indium tin oxide (ITO).

Since each of the plurality of touch electrodes TE is used as a self-capacitance sensing electrode in the touch sensing mode, it must have a minimum size for touch sensing. Accordingly, each of the plurality of touch electrodes TE may have a size corresponding to one or more subpixels SP.

The timing control circuit 200 generates a touch synchronization signal Tsync consisting of a first period (or display period) and a second period (or touch sensing period) based on the timing synchronization signal TSS. Additionally, the timing control circuit 200 time-divides each frame of the display panel 100 into at least one subframe based on the timing synchronization signal TSS, and drives each subframe in a display mode and a touch sensing mode. The touch synchronization signal Tsync is generated to increase the touch sensing cycle, thereby improving touch sensing sensitivity.

The timing control circuit 200 controls pixel data (R/G/ B) and provided to the data driving circuit 500.

The timing control circuit 200 generates a data control signal DCS and a gate control signal GCS based on the timing synchronization signal TSS in a display mode according to the touch synchronization signal Tsync, thereby driving the data driving circuit 500 and the gate driving circuit 600 each control the driving timing.

The timing control circuit 200 generates a pulse modulation enable signal DPM having a first period and a second period based on the touch synchronization signal Tsync, provides the pulse modulation enable signal DPM to the power generation circuit 300, and provides the timing synchronization signal The pulse modulation clock signal FLK is generated based on the main clock signal of TSS and the touch synchronization signal Tsync and provided to the power generation circuit 300 . Here, the pulse modulation enable signal DPM may be defined as a control signal for enabling or disabling the operation of the power generation circuit 300, and the pulse modulation clock signal FLK is It may be defined as a control signal for modulating a falling edge of a gate pulse supplied to a gate line.

The timing control circuit 200 according to the first example continuously generates a pulse modulated clock signal FLK having a voltage swing width between a high logic state and a low logic state while generating a touch synchronization signal Tsync. generate a low voltage level VL pulse modulation enable signal DPM during a first period of the touch sync signal Tsync, and generate a high voltage level VH pulse modulation enable signal DPM during a second period of the touch sync signal Tsync can create At this time, the timing control circuit 200 according to an example generates a pulse modulation enable signal DPM having the same first period and second period as those of the touch synchronization signal Tsync.

The timing control circuit 200 according to the second example continuously generates the pulse modulation enable signal DPM of the high voltage level VH and generates a DC voltage level pulse modulation clock during the first period of the touch synchronization signal Tsync. A pulse modulation clock signal FLK having a voltage swing width between a high logic state and a low logic state is continuously generated during the second period of the touch synchronization signal Tsync. Here, the DC voltage level of the pulse modulation clock signal FLK may have a voltage level corresponding to a high logic state or a low logic state.

The power generation circuit 300 generates a gate high voltage and uses the gate high voltage and the pulse modulation enable signal DPM and the pulse modulation clock signal FLK supplied from the timing control circuit 200 to generate a plurality of gates. A pulse modulated signal VGHM is generated and provided to the gate driving circuit 600 .

In order to prevent the plurality of gate pulse modulation signals VGHM from acting as noise components of the touch driving signal TDS during the touch sensing period, the power generating circuit 300 generates a first signal of the pulse modulation enable signal DPM. During the period, that is, the touch sensing period corresponding to the first period of the touch synchronization signal Tsync, the plurality of gate pulse modulation signals VGHM are not output. Further, the power generation circuit 300 generates a gate high voltage using a pulse modulation clock signal FLK based on a gate pulse modulation method for lowering a voltage difference between a gate high voltage and a gate low voltage of a gate pulse. A plurality of gate pulse modulated signals (VGHM) are generated and output by modulating the polling period of the voltage. In this case, each of the plurality of gate pulse modulation signals VGHM is maintained at the voltage level of the gate high voltage during the voltage holding period and linearly decreases from the voltage level of the gate high voltage during the voltage modulation period. In this case, each of the plurality of gate pulse modulation signals VGHM may linearly decrease from a voltage level of the gate high voltage to a preset gate high modulation voltage level or to a voltage level of the gate high voltage during the voltage modulation period.

The power generation circuit 300 according to the first example generates a pulse modulation enable signal DPM of a low voltage level supplied from the timing control circuit 200 according to the first example during the first period of the touch synchronization signal Tsync. DC voltage is output to the gate driving circuit 600, and a plurality of gate pulse modulation signals VGHM are generated during the second period of the touch sync signal Tsync according to the pulse modulation enable signal DPM of the high voltage level. output to the gate driving circuit 600.

The power generation circuit 300 according to another example generates DC voltage during the first period of the touch sync signal Tsync according to the DC voltage level pulse modulation clock signal FLK supplied from the timing control circuit 200 according to the second example. The gate driving circuit 600 outputs a voltage to the gate driving circuit 600 and generates a plurality of gate pulse modulated signals VGHM during the second period of the touch sync signal Tsync according to the pulse modulated clock signal FLK. output as

The power generating circuit 300 additionally generates a gate low voltage VGL that is relatively lower than the gate high voltage, and provides it to the gate driving circuit 600 .

The power generation circuit 300 generates a gate high voltage, a gate low voltage (VGL) and a plurality of gate pulse modulation signals (VGHM) using an external input power source (Vin), respectively, and supplies power to the display device It may be a power management integrated circuit mounted on a board (not shown).

The touch driving circuit 400 is connected to the plurality of touch electrodes TE in a one-to-one manner through a plurality of touch routing lines TL1 to TLk provided on the display panel 100 .

The touch driving circuit 400 includes a plurality of touch routing lines TL1 to TLk during the touch sensing mode of the display panel 100 according to the first period of the touch sync signal Tsync supplied from the host control circuit 800. After supplying the touch driving signal TDS to each of the plurality of touch electrodes TE through each of the plurality of touch routing lines TL1 to TLk, the capacitance change of the corresponding touch electrode TE is sensed through each of the plurality of touch routing lines TL1 to TLk. Touch row data Tdata is generated, and the generated touch row data Tdata is provided to the host control circuit 800 .

During the display mode of the display panel 100 according to the second period of the touch synchronization signal Tsync supplied from the host control circuit 800, the touch driving circuit 400 provides a plurality of touch routing lines TL1 to TLk, respectively. A common voltage (Vcom) is supplied to each of the plurality of touch electrodes (TE) through.

The host control circuit 800 is a micro controller unit (MCU) or an application processor, and the driving timing of the touch driving circuit 400 is based on the touch sync signal Tsync provided from the timing control circuit 200. to control In addition, the host control circuit 800 receives the touch row data Tdata supplied from the touch driving circuit 400, and generates touch coordinate information from the touch row data Tdata through the execution of a preset touch position calculation algorithm. and the application corresponding to the touch coordinate information is executed. Here, the touch position calculation algorithm may be executed in the touch driving circuit 400. In this case, the host control circuit 800 receives touch coordinate information supplied from the touch driving circuit 400 and corresponds to the received touch coordinate information. application can be executed.

The data driving circuit 500 operates in a display mode or a touch sensing mode in response to the data control signal DCS and the touch synchronization signal Tsync supplied from the timing control circuit 200 . For example, during the touch sensing mode of the display panel 100 according to the first period of the touch synchronization signal Tsync, the data driving circuit 500 generates a data load free signal to each of the plurality of data lines DL1 to DLn. (LFS1) is supplied simultaneously. Further, the data driving circuit 500 receives pixel data (R) supplied from the timing control circuit 200 in units of one horizontal period during the display mode of the display panel 100 according to the second period of the touch synchronization signal Tsync. /G/B) is converted into an analog type data signal and simultaneously supplied to a plurality of data lines DL1 to DLn.

The gate driving circuit 600 operates in a display mode or a touch sensing mode in response to a gate control signal GCS and a touch synchronization signal Tsync supplied from the timing control circuit 200 . The gate driving circuit 600 according to an example may include a plurality of gate driving integrated circuits attached to a non-display area on one side of the display panel 100 so as to be connected to one end of each of the plurality of gate lines GL1 to GLm. there is. The gate driving circuit 600 according to another example may be embedded (or integrated) in a non-display area on one side of the display panel 100 together with a manufacturing process of a thin film transistor provided in a sub-pixel.

During the touch sensing mode of the display panel 100 according to the first period of the touch synchronization signal Tsync, the gate driving circuit 600 operates a plurality of gate lines GL1 to GLm in response to the touch synchronization signal Tsync, respectively. A gate load free signal (LFS2) is simultaneously supplied to

The gate driving circuit 600 is powered by the gate control signal GCS supplied from the timing control circuit 200 during the display mode of the display panel 100 according to the second period of the touch synchronization signal Tsync. Gate pulses are sequentially supplied to the plurality of gate lines GL1 to GLm using the plurality of gate pulse modulation signals VGHM supplied from the generation circuit 300 . More specifically, the gate driving circuit 600 transmits a gate pulse, that is, a gate pulse modulation signal VGHM, to a plurality of gate lines GL1 during a scan period in response to the gate control signal GCS supplied from the timing control circuit 200. to GLm), and then maintaining each of the plurality of gate lines (GL1 to GLm) at the gate low voltage (VGL) supplied from the power generation circuit 300 during the rest of the display period except for the scan period, thereby maintaining the display panel ( 100), the thin film transistors connected to each of the plurality of gate lines GL1 to GLm are turned on in units of one horizontal period.

Additionally, the touch screen integrated display device according to an example of the present invention further includes a touch power driving circuit 700 .

The touch power driving circuit 700 generates and outputs a common voltage Vcom, a touch driving signal TDS, a data load free signal LFS1, and a gate load free signal LFS2, respectively. The touch power driving circuit 700 according to an example may include a common voltage generator, a touch driving signal generator, a first load-free signal generator, and a second load-free signal generator.

The common voltage generator generates a common voltage Vcom that is commonly supplied to the plurality of touch electrodes TE in the display mode of the display panel 100 and provides it to the touch driving circuit 400 . Optionally, the common voltage generator may be built into the power generation circuit 300 .

In the touch sensing mode of the display panel 100, the touch driving signal generating unit generates touch driving signals TDS that are individually or group supplied to the plurality of touch electrodes TE and provides them to the touch driving circuit 400. . Here, the touch driving signal TDS includes a plurality of driving pulses swinging with a voltage swing width between a first voltage and a second voltage symmetrical with respect to the common voltage Vcom.

The first load free signal generating unit generates a data load free signal LFS1 supplied to all data lines DL1 to DLn in the touch sensing mode of the display panel 100 and provides the generated data load free signal LFS1 to the data driving circuit 500 . Here, the data load free signal LFS1 may include a plurality of driving pulses having the same phase synchronized with the touch driving signal TDS supplied to the touch electrodes TE and swinging with the same voltage swing width. Since the data load free signal LFS1 has the same phase as the touch driving signal TDS, the load of the touch electrodes TE according to the parasitic capacitance between the touch electrode TE and the data lines GL1 to GLm ), it is possible to improve the touch sensitivity.

The second load free signal generation unit generates a gate load free signal LFS2 supplied to all gate lines GL1 to GLm in the touch sensing mode of the display panel 100 and provides it to the gate driving circuit 600 . Here, the gate load free signal LFS2 may include a plurality of driving pulses having the same phase as the touch driving signal TDS and swinging with the same voltage swing width. In this case, each of the plurality of driving pulses may swing between the third voltage and the fourth voltage based on the gate low voltage VGL. Also, the difference voltage between the gate low voltage VGL and the third voltage is equal to the difference voltage between the first voltage of the touch driving signal TDS and the common voltage Vcom, and the gate low voltage VGL and the fourth voltage The difference voltage between the voltages is set equal to the difference voltage between the second voltage of the touch driving signal TDS and the common voltage Vcom. Accordingly, the gate load free signal LFS2 has the same phase as the touch driving signal TDS and the same voltage swing width, but has a voltage swing width based on the gate low voltage VGL. During the touch sensing mode, the thin film transistor connected to the gate line is not turned on by the gate load free signal LFS2. Since the gate load free signal LFS2 has the same phase as the touch driving signal TDS, the load of the touch electrodes TE according to the parasitic capacitance between the touch electrode TE and the gate lines GL1 to GLm ), it is possible to improve the touch sensitivity.

FIG. 2 is a diagram for explaining the timing control circuit shown in FIG. 1, and FIG. 3 is a touch sync signal output from the timing control circuit shown in FIG. 2, an example of a pulse modulation enable signal, and an example of a pulse modulation clock signal. FIG. 4 is a waveform diagram showing a touch synchronization signal output from the timing control circuit shown in FIG. 2 , a pulse modulation enable signal of another example, and a pulse modulation clock signal of another example.

1 to 4, the timing control circuit 200 according to an example of the present invention includes a first signal generator 210, a second signal generator 230, a third signal generator 250, A control signal generator 270 and a pixel data generator 290 are included.

The first signal generator 210 generates and outputs a touch synchronization signal Tsync for operating the display panel 100 in a display mode and a touch sensing mode based on the timing synchronization signal TSS. Here, the timing synchronization signal TSS may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock signal MCLK, and a data enable signal DE.

The first signal generator 210 according to an example time-divisions the vertical sync signal Vsync to provide a touch sensing period (or first period) (TP) and a display period (or second period) (DP). A synchronization signal Tsync may be generated. Here, the touch sensing period TP of the touch sync signal Tsync may have a low logic state L to drive the display panel 100 in the touch sensing mode, and the display period of the touch sync signal Tsync ( DP) may have a high logic state (H) to drive the display panel 100 as a display module.

The first signal generator 210 according to an example time-divides each frame of the display panel 100 into at least one subframe based on the vertical synchronization signal Vsync, and divides each subframe into a display mode and a touch sensing mode. The touch sensing cycle is increased by generating a touch synchronization signal (Tsync) for driving, and through this, the touch sensing sensitivity is improved. In this case, the touch synchronization signal Tsync during one frame of the display panel 100 may include two or more touch sensing periods TP and two or more display periods DP.

The second signal generator 230 generates and outputs a pulse modulation enable signal DPM based on the touch synchronization signal Tsync output from the first signal generator 210 .

The second signal generator 230 according to the first example disables the operation of the power generation circuit 300 during the touch sensing period TP of the touch sync signal Tsync and displays the touch sync signal Tsync during the display period ( A plurality of gate pulses output from the power generation circuit 300 in the touch sensing mode of the display panel 100 by generating a pulse modulation enable signal DPM for enabling the operation of the power generation circuit 300 during DP). The modulation signal VGHM is prevented from acting as a noise component of the touch driving signal TDS, thereby improving sensing sensitivity. To this end, the second signal generating unit 230 according to the first example, as shown in FIG. 3 , has the same first period and display period DP as the touch sensing period TP of the touch synchronization signal Tsync. It is possible to generate and output a pulse modulation enable signal (DPM) having the same second period as . That is, the second signal generator 230 according to the first example generates a pulse modulation enable signal DPM having a low voltage level VL during the touch sensing period TP of the touch sync signal Tsync, During the display period DP of the touch synchronization signal Tsync, the pulse modulation enable signal DPM having a high voltage level VH may be generated.

The second signal generator 230 according to the second example performs pulse modulation to enable the operation of the power generation circuit 300 during the touch sensing period TP and the display period DP of the touch synchronization signal Tsync. An enable signal DPM may be generated. That is, as shown in FIG. 4 , the second signal generator 230 according to the second example has a high voltage level VH during the touch sensing period TP and the display period DP of the touch synchronization signal Tsync. ), the pulse modulation enable signal DPM can be continuously generated.

The third signal generator 250 generates a pulse modulated clock signal FLK based on the main clock signal MCLK or the main clock signal MCLK and the touch synchronization signal Tsync of the timing synchronization signal TSS. print out

As shown in FIG. 3 , the third signal generator 250 according to the first example generates a touch sync signal based on the main clock signal MCLK and the touch sync signal Tsync of the timing sync signal TSS. A pulse modulated clock signal FLK having a voltage swing width between a high logic state (H) and a low logic state (L) is continuously generated in synchronization with (Tsync). Accordingly, the pulse modulation clock signal FLK is continuously generated in synchronization with the touch synchronization signal Tsync regardless of the touch sensing period TP and the display period DP of the touch synchronization signal Tsync. Here, the rising/falling time of the pulse modulation clock signal FLK may not coincide with the rising/falling time of the touch synchronization signal Tsync.

As shown in FIG. 4 , the third signal generator 250 according to the second example generates a touch sync signal based on the main clock signal MCLK and the touch sync signal Tsync of the timing sync signal TSS. The pulse modulation clock signal FLK maintained at the DC voltage level during the touch sensing period TP of the touch sync signal Tsync is generated while being synchronized with Tsync, and during the display period DP of the touch sync signal Tsync. A pulse modulated clock signal FLK having a voltage swing between a high logic state (H) and a low logic state (L) is continuously generated. That is, the third signal generator 250 according to the second example outputs a DC voltage during the touch sensing period TP and generates the pulse modulation clock signal FLK during the display period DP of the touch synchronization signal Tsync. output continuously. Here, the rising/falling time of the pulse modulation clock signal FLK during the display period DP may not coincide with the rising/falling time of the touch synchronization signal Tsync.

The control signal generating unit 270 generates a data control signal DCS and a gate control signal GCS based on the timing synchronization signal TSS in the display mode according to the touch synchronization signal Tsync to generate the data driving circuit 500 ) and the driving timing of each gate driving circuit 600 is controlled. Here, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, and a polarity control signal. Also, the gate control signal GCS may include a gate start pulse, a plurality of gate shift clocks, and a gate output enable signal.

The pixel data generation unit 290 receives image data Idata supplied from a display driving system during the display mode of the display panel 100 according to the touch synchronization signal Tsync, and transmits the image data Idata to the display panel ( 100) are arranged into pixel data (R/G/B) and provided to the data driving circuit 500.

FIG. 5 is a diagram for explaining the power generation circuit shown in FIG. 1, FIG. 6 is a waveform diagram showing input/output waveforms of the power generation circuit according to the first example shown in FIG. 5, and FIG. 7 is a diagram shown in FIG. It is a waveform diagram showing input/output waveforms of the power generation circuit according to the second example.

Referring to FIGS. 5 to 7 , a power generation circuit 300 according to the present invention includes a gate voltage generation circuit 310 and a pulse modulation circuit 330 .

The gate voltage generating circuit 310 generates and outputs a gate high voltage (VGH) and a gate low voltage (VGL) using the input power source (Vin). Here, the gate high voltage has a gate-on voltage level (Von) for turning on the thin film transistor connected to the gate line. Also, the gate low voltage VGL may have a gate off voltage level Voff for turning off the thin film transistor connected to the gate line.

The pulse modulation circuit 330 uses the gate high voltage VGH supplied from the gate voltage generator circuit 310, the pulse modulated clock signal FLK supplied from the timing control circuit 200, and a first period and a second period. A plurality of gate pulse modulated signals VGHM are generated and output using the pulse modulated enable signal DPM. That is, the pulse modulation circuit 330 outputs a DC voltage during the first period TP of the touch synchronization signal Tsync according to the pulse modulation enable signal DPM and the pulse modulation clock signal FLK, and During the second period DP of the signal Tsync, a plurality of gate pulse modulation signals VGHM are generated and output.

As shown in FIG. 6 , the pulse modulation circuit 330 according to the first example includes a pulse modulation enable signal DPM of a low voltage level VL supplied from the timing control circuit 200 according to the first example. A DC voltage is output during the first period TP of the touch synchronization signal Tsync, and during the second period DP of the touch synchronization signal Tsync according to the high voltage pulse modulation enable signal DPM. A plurality of gate pulse modulation signals (VGHM) are generated and output. That is, the pulse modulation circuit 330 according to the first example is disabled according to the pulse modulation enable signal DPM of the low voltage level VL during the first period TP of the touch synchronization signal Tsync to generate a DC voltage (V0), more specifically, outputs the ground voltage (GND). On the other hand, the pulse modulation circuit 330 according to the first example is enabled according to the pulse modulation enable signal DPM of the high voltage level VH during the second period DP of the touch sync signal Tsync to generate pulses. The gate high voltage VGH is modulated according to the modulation clock signal FLK to generate a plurality of gate pulse modulation signals VGHM in which a polling period is modulated.

As shown in FIG. 7 , the pulse modulation circuit 330 according to the second example generates a pulse modulation enable signal DPM of a high voltage level VH supplied from the timing control circuit 200 according to the second example. is enabled according to the function to output a DC voltage during the first period TP of the touch synchronization signal Tsync, and generate a plurality of gate pulse modulation signals VGHM during the second period DP of the touch synchronization signal Tsync. and output That is, the pulse modulation circuit 330 according to the second example is enabled according to the pulse modulation enable signal DPM of the high voltage level VH, and pulses during the first period TP of the touch synchronization signal Tsync. The gate high voltage VGH is output according to the modulation clock signal FLK, and the gate high voltage VGH is modulated according to the pulse modulation clock signal FLK during the second period DP of the touch synchronization signal Tsync. A plurality of gated pulse modulated signals (VGHM) in which the polling interval is modulated are generated.

In the pulse modulation circuit 330 according to the first and second examples, each of the plurality of gate pulse modulation signals VGHM has a voltage maintaining period P1 maintained at the voltage level of the gate high voltage VGH and a gate high voltage ( A voltage modulation period P2 that linearly decreases in the voltage level of VGH) may be included. Here, the delay period P3 between the polling time of the pulse modulated clock signal FLK and the polling time of each of the plurality of gate pulse modulated signals VGHM may be set by the capacitance value of the capacitor element CE. Further, each of the plurality of gate pulse modulation signals VGHM may linearly decrease from a voltage level of the gate high voltage VGH to a voltage level of a preset gate middle voltage VGH_m or gate low voltage VGL. At this time, the slope of the voltage in the voltage modulation period P2 may be set by the resistance value of the resistance element RE.

As described above, the power generation circuit 330 according to the present invention does not output the plurality of gate pulse modulation signals VGHM during the touch sensing period TP, so that the plurality of gate pulse modulation signals VGHM generate the touch driving signal TDS. ) is prevented from acting as a noise component, and through this, sensing sensitivity in the touch sensing period TP is improved.

FIG. 8 is a diagram for explaining the touch driving circuit shown in FIG. 1 .

Referring to FIGS. 1 and 8 , a touch driving circuit 400 according to the present invention includes a first switching unit 410 , a touch sensing unit 430 , and a touch data processing unit 450 .

The first switching unit 410 generates a touch driving signal TDS or a common voltage Vcom for each of the plurality of touch routing lines TL1 to TLk based on the touch synchronization signal Tsync supplied from the timing control circuit 200. ) is supplied or each of the plurality of touch routing lines TL1 to TLk is connected to the touch sensing unit 430 . The first switching unit 410 according to an example includes a plurality of first switching elements 412 that are switched according to the touch synchronization signal Tsync.

Each of the plurality of first switching elements 412 transmits the touch driving signal TDS supplied from the touch power driving circuit 700 during a touch sensing period according to the touch synchronization signal Tsync in a low logic state to a plurality of touch routing After supplying the touch electrode TE through each of the lines TL1 to TLk, each of the plurality of touch routing lines TL1 to TLk is connected to the touch sensing unit 430 . Further, each of the plurality of first switching elements 412 transmits the common voltage Vcom supplied from the touch power driving circuit 700 to a plurality of touch routing lines during a display period according to the touch synchronization signal Tsync of a high logic state. By supplying each of (TL1 to TLk), the plurality of touch electrodes TE serve as a common electrode.

The touch sensing unit 430 is connected to a plurality of touch routing lines TL1 to TLk through the first switching unit 410 during a touch sensing period according to the touch synchronization signal Tsync in a low logic state, and the plurality of touches Touch raw data Tdata based on the capacitance change of each of the plurality of touch electrodes TE is generated through each of the routing lines TL1 to TLk and provided to the host control circuit 800 . In this case, the touch sensing unit 430 may perform individual touch sensing on the plurality of touch electrodes TE or group touch sensing on the plurality of touch electrodes TE. The touch sensing unit 430 according to an example includes a plurality of sensing units SU.

Each of the plurality of sensing units SU may include a touch sensing circuit (not shown) and an analog-to-digital converter (not shown).

The touch sensing circuit generates a touch signal by amplifying capacitance variation of the touch electrode TE through each touch routing line TL1 to TLk. The touch sensing circuit according to an example may be an integrator (not shown) including a comparator that compares a signal received from each of the touch routing lines TL1 to TLk with a reference voltage and outputs the result. An integrator according to an example may include an operational amplifier (not shown) including an inverting terminal, a non-inverting terminal, and an output terminal, and a feedback capacitor (not shown) connected between the inverting terminal and the output terminal of the operational amplifier. Here, inverting terminals of the integrator are connected to the touch electrodes TE through corresponding touch routing lines TL1 to TLk. A non-inverting terminal of the integrator receives the touch driving signal TDS as a reference voltage.

The analog-to-digital converter converts an analog output signal output from the touch sensing circuit into a digital signal to generate touch row data Tdata.

The touch data processing unit 450 temporarily stores the touch raw data Tdata supplied from the touch sensing unit 430 in an internal memory (not shown), and responds to a touch report signal to store the touch raw data Tdata stored in the internal memory. ) to the host control circuit 800.

In the touch driving circuit 400 according to this example, since the gate pulse modulation signal VGHM is not output from the power generation circuit 300 during the touch sensing period, a noise component based on the gate pulse modulation signal VGHM is introduced. Sensing sensitivity may be improved as touch sensing is performed without the touch screen.

FIG. 9 is a diagram for explaining the data driving circuit shown in FIG. 1 .

Referring to FIGS. 1 and 9 , a data driving circuit 500 according to the present invention includes a second switching unit 510 and a data signal supplying unit 530 .

The second switching unit 510 connects each of the plurality of data lines DL1 to DLn to the data signal supply unit 530 based on the touch synchronization signal Tsync supplied from the timing control circuit 200, or A data load free signal LFS1 is supplied to each of the data lines DL1 to DLn. The second switching unit 510 according to an example includes a plurality of second switching elements 512 that are switched according to the touch synchronization signal Tsync.

Each of the plurality of second switching elements 512 transmits the data load free signal LFS1 supplied from the touch power driving circuit 700 to all data lines during a touch sensing period according to the touch synchronization signal Tsync in a low logic state. (DL1 to DLn). Further, each of the plurality of second switching elements 512 connects each of the plurality of data lines DL1 to DLn to the data signal supply unit 530 during a display period according to the touch synchronization signal Tsync in a high logic state. The data signal Vdata output from the data signal supply unit 530 is supplied to the corresponding data lines DL1 to DLn.

The data signal supply unit 530 receives the pixel data (R/G/B) and the data control signal (DCS) of each sub-pixel supplied from the timing controller 300, and receives the data control signal (DCS) for each pixel. The data R/G/B is converted into an analog data signal Vdata and supplied to corresponding data lines DL1 to DLn through the second switching unit 510 . The data signal supply unit 530 according to an example includes a receiver (not shown) that receives pixel data R/G/B and a data control signal DCS of each sub-pixel, and a shift register unit that sequentially outputs a sampling signal. (not shown), a latch unit (not shown) that latches pixel data (R/G/B) of each sub-pixel according to a sampling signal, and grayscale voltage generation that generates a plurality of grayscale voltages by subdividing a plurality of reference gamma voltages. (not shown) converts the pixel data (R/G/B) of each sub-pixel output from the latch unit into an analog data signal (Vdata) using a plurality of grayscale voltages, and converts the digital-to-analog conversion unit (not shown). time), and an output buffer unit (not shown) outputting the data signal Vdata to the second switching unit 510 .

Additionally, the data driving circuit 500 according to the present invention may include the touch driving circuit 400 . That is, one data driving integrated circuit may be an integrated integrated circuit including the touch driving circuit 400 . In this case, one integrated circuit may include one data driving unit and a pair of touch driving units interposed between the data driving units for easy connection with the display panel 100 .

As described above, the data driving circuit 500 according to the present invention supplies the data load free signal LFS1 having the same phase as the touch driving signal TDS to all the data lines DL1 to DLn during the touch sensing period, thereby generating touch electrodes. The load of the touch electrodes TE according to the parasitic capacitance between TE and the data lines GL1 to GLm is reduced, and through this, touch sensitivity may be improved.

FIG. 10 is a diagram for explaining the gate driving circuit shown in FIG. 1 .

Referring to FIGS. 1 and 10 , a gate driving circuit 600 according to an example of the present invention includes a gate driving unit 610 and a third switching unit 630 .

The gate driver 610 receives the gate control signal GCS supplied from the timing controller 300, generates a gate pulse according to the gate control signal GCS, and supplies it to the third switching unit 630. The gate driver 610 according to an example may include a shift register including a plurality of stages ST1 to STm that are dependently connected to each other.

The plurality of stages ST1 to STm generate gate signals that are sequentially shifted using the gate start pulse GSP and gate shift clock GSC of the gate control signal GCS, and are supplied from the power generation circuit 300. A gate pulse is generated according to the gate signal using the gate pulse modulation signal VGHM and the gate low voltage VGL, and the gate pulse generated according to the gate output enable signal GOE of the gate control signal GCS output to the third switching unit 630. The plurality of stages (ST1 to STm) may have the same configuration except for sequentially outputting gate pulses using the gate pulse modulation signal (VGHM) in a gate driver of a general display device, and perform the same function. Therefore, a detailed description thereof will be omitted.

The third switching unit 630 connects the plurality of gate lines GL1 to GLm to the gate driver 610 or the gate load free signal input line ( 650). To this end, the third switching unit 430 includes a plurality of third switch elements 632 that are switched according to the touch synchronization signal TSS.

Each of the plurality of third switching elements 632 transmits the gate load free signal LFS2 supplied from the touch power driving circuit 700 to all gate lines during a touch sensing period according to the touch synchronization signal Tsync in a low logic state. (GL1 to GLm). Further, each of the plurality of third switching elements 632 connects each of the plurality of gate lines GL1 to GLm to the gate driver 610 during a display period according to the touch synchronization signal Tsync in a high logic state, thereby generating a gate Gate pulses output from the driver 610 are sequentially supplied to the plurality of gate lines GL1 to GLm.

As described above, the gate driving circuit 600 according to the present invention supplies the gate load free signal LFS2 having the same phase as the touch driving signal TDS to all gate lines GL1 to GLm during the touch sensing period, thereby generating a touch electrode. A load of the touch electrodes TE according to the parasitic capacitance between TE and the gate lines GL1 to GLm is reduced, and through this, touch sensitivity may be improved. In addition, the gate driving circuit 600 according to the present invention generates a gate pulse whose polling time is modulated using the gate pulse modulation signal VGHM and supplies it to the gate lines GL1 to GLm, thereby generating a gate high voltage and a gate high voltage of the gate pulse. Deterioration in picture quality due to a kick-back voltage according to a difference voltage between gate low voltages may be minimized.

11 is a waveform diagram showing driving waveforms of a display device integrated with a touch screen according to an example of the present invention.

Referring to FIGS. 1 and 11, a driving method of a display device integrated with a touch screen according to an example of the present invention will be described.

The display device integrated with a touch screen according to an example of the present invention may operate in a touch sensing mode according to a first interval of the touch synchronization signal Tsync and a display mode according to a second interval of the touch synchronization signal Tsync.

First, in the touch sensing mode, touch sensing for a user touch is performed in a state in which the operation of the power generating circuit 300 is disabled. A more detailed description of this is as follows.

The timing control circuit 200 generates a touch synchronization signal Tsync of a low logic state L corresponding to the touch sensing mode and a pulse modulation enable signal DPM of a low voltage level VL. The power generation circuit 300 is disabled according to the pulse modulation enable signal DPM of the low voltage level VL and outputs a DC voltage V0 instead of the plurality of gate pulse modulation signals VGHM. The touch power driving circuit 700 generates and outputs a touch driving signal TDS, a data load free signal LFS1, and a gate load free signal LFS2. The touch driving circuit 400 supplies the touch driving signal TDS to each of the plurality of touch electrodes TE in response to the touch synchronization signal Tsync in the low logic state L. At the same time, the data driving circuit 500 transmits a data load free signal LFS1 synchronized with the touch driving signal TDS to all data lines DL1 to DL1 in response to the touch synchronization signal Tsync in the low logic state L. DLn). In addition, the gate driving circuit 500 transmits a gate load free signal LFS2 synchronized with the touch driving signal TDS to all gate lines GL1 to GLm in response to the touch synchronization signal Tsync in the low logic state L. ) to supply Next, the touch driving circuit 400 senses the capacitance change of the corresponding touch electrode TE to generate touch raw data Tdata, and sends the generated touch raw data Tdata to the host control circuit 800. to provide. Accordingly, the host control circuit 800 receives the touch row data Tdata supplied from the touch driving circuit 400, and obtains touch coordinate information from the touch row data Tdata through the execution of a preset touch position calculation algorithm. Create and run the application corresponding to the touch coordinate information.

Next, in the display mode, an image is displayed on the display panel 100 by enabling the operation of the power generating circuit 300 . A more detailed description of this is as follows.

The timing control circuit 200 generates a touch sync signal Tsync of a high logic state (H) corresponding to a display mode and a pulse modulation enable signal DPM of a high voltage level (VH), and generates a touch sync signal ( The pulse modulation clock signal FLK having a voltage swing width between a high logic state (H) and a low logic state (L) is continuously generated while being synchronized with Tsync. The power generating circuit 300 is enabled according to the pulse modulation enable signal DPM of the high voltage level VH and modulates the gate high voltage VGH according to the pulse modulation clock signal FLK so that the polling period is modulated. outputs a plurality of gate pulse modulated signals VGHM. The gate driving circuit 500 generates a gate pulse based on a plurality of gate pulse modulation signals VGHM and a gate control signal GCS, and gates the gate in response to the touch synchronization signal Tsync of a high logic state H. Pulses are sequentially supplied to the plurality of gate lines GL1 to GLm. The touch power driving circuit 700 generates and outputs a common voltage Vcom. The touch driving circuit 400 supplies a common voltage Vcom to each of the plurality of touch electrodes TE in response to the touch synchronization signal Tsync in the high logic state H. At the same time, the data driving circuit 500 converts the pixel data R/G/B into an analog data signal Vdata in units of one horizontal period in response to the data control signal DCS, and enters a high logic state. In response to the touch synchronization signal Tsync of (H), the data signal Vdata for one horizontal line is simultaneously supplied to the plurality of data lines DL1 to DLn. Accordingly, an image corresponding to the data signal supplied to each of the plurality of subpixels (SP) is displayed on the display panel 100 .

As such, in the touch screen integrated display device according to an example of the present invention, the power generation circuit 300 is disabled during the touch sensing mode so that the noise component caused by the gate pulse modulation signal (VGHM) in the form of an alternating current is generated by the touch driving signal (TDS). ), the sensing sensitivity can be improved, and in particular, the touch driving signal TDS supplied to the touch electrode TE and the data load free signal LFS1 supplied to all data lines DL1 to DLn and Since the gate load free signals LFS2 supplied to all the gate lines GL1 to GLm have the same phase as each other, the load of the touch electrodes TE is reduced and touch sensitivity can be further improved.

12 is a waveform diagram showing driving waveforms of a display device integrated with a touch screen according to another example of the present invention.

Referring to FIGS. 1 and 12, a driving method of a touch screen integrated display device according to another example of the present invention will be described.

A display device integrated with a touch screen according to another example of the present invention may operate in a touch sensing mode according to a first interval of the touch synchronization signal Tsync and a display mode according to a second interval of the touch synchronization signal Tsync.

First, in the touch sensing mode, touch sensing for a user's touch is performed while controlling the DC voltage to be output from the power generating circuit 300 . A more detailed description of this is as follows.

The timing control circuit 200 generates a touch sync signal Tsync of a low logic state (L) corresponding to the touch sensing mode and a pulse modulation enable signal DPM of a high voltage level (VH), A pulse modulated clock signal FLK having (H) is continuously generated. The power generation circuit 300 is enabled according to the pulse modulation enable signal DPM of the high voltage level (VH) and generates the gate high voltage (VGH) according to the pulse modulation clock signal FLK of the high logic state (H). The gate pulse modulation signal VGHM maintained at a voltage level of VGHM is continuously output. The touch power driving circuit 700 generates and outputs a touch driving signal TDS, a data load free signal LFS1, and a gate load free signal LFS2. The touch driving circuit 400 supplies the touch driving signal TDS to each of the plurality of touch electrodes TE in response to the touch synchronization signal Tsync in the low logic state L. At the same time, the data driving circuit 500 transmits a data load free signal LFS1 synchronized with the touch driving signal TDS to all data lines DL1 to DL1 in response to the touch synchronization signal Tsync in the low logic state L. DLn). In addition, the gate driving circuit 500 transmits a gate load free signal LFS2 synchronized with the touch driving signal TDS to all gate lines GL1 to GLm in response to the touch synchronization signal Tsync in the low logic state L. ) to supply Next, the touch driving circuit 400 senses the capacitance change of the corresponding touch electrode TE to generate touch raw data Tdata, and sends the generated touch raw data Tdata to the host control circuit 800. to provide. Accordingly, the host control circuit 800 receives the touch row data Tdata supplied from the touch driving circuit 400, and obtains touch coordinate information from the touch row data Tdata through the execution of a preset touch position calculation algorithm. Create and run the application corresponding to the touch coordinate information.

Next, since the display mode displays an image on the display panel 100 in the same operation as the display mode of FIG. 11, a redundant description thereof will be omitted.

Such a touch screen integrated display device according to another example of the present invention maintains the gate pulse modulation signal (VGHM) output from the power generation circuit 300 at the voltage level of the gate high voltage (VGH) during the touch sensing mode, thereby alternating current. Sensing sensitivity may be improved by preventing noise components caused by the gate pulse modulation signal VGHM of the form from being introduced into the touch driving signal TDS. In particular, the touch driving signal TDS supplied to the touch electrode TE and The data load free signal LFS1 supplied to all data lines DL1 to DLn and the gate load free signal LFS2 supplied to all gate lines GL1 to GLm have the same phase, so that the touch electrodes TE ) is reduced, so touch sensitivity can be further improved.

13A and 13B are simulation waveform diagrams illustrating whether or not noise is generated in a touch driving signal according to gate pulse modulation in a comparison example and an example of the present invention.

First, referring to FIG. 13A , in the comparative example, the waveform of the touch driving signal TDS is measured while generating a plurality of gate pulse modulation signals VGHM by enabling the power generation circuit during the touch sensing period. As a result, in the comparative example, it can be confirmed that noise is generated in the touch driving signal TDS, as shown in parts A and B of FIG. 13A.

On the other hand, referring to FIG. 13B , in the example of the present invention, the waveform of the touch driving signal TDS is measured while disabling the power generation circuit or controlling the DC voltage to be output from the power generation circuit during the touch sensing period. As a result, in the example of the present invention, it can be confirmed that no noise is generated in the touch driving signal TDS.

As can be seen from the simulation waveform, the present invention disables the power generation circuit during the touch sensing period or controls the DC voltage to be output from the power generation circuit, thereby eliminating noise caused by the alternating current gate pulse modulation signal (VGHM). Components may be prevented from entering the touch driving signal TDS, thereby improving sensing sensitivity.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention belongs that various substitutions, modifications, and changes are possible without departing from the technical details of the present invention. It will be clear to those who have knowledge of Therefore, the scope of the present invention is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and equivalent concepts should be construed as being included in the scope of the present invention.

100: display panel 200: timing control circuit
210: first signal generator 230: second signal generator
250: third signal generator 270: control signal generator
300: power generation circuit 310: gate voltage generation circuit
330: pulse modulation circuit 400: touch drive circuit
500: data driving circuit 600: gate driving circuit
700: touch power driving circuit 800: host control circuit

Claims (10)

a gate voltage generating circuit generating a gate high voltage; and
A pulse modulation circuit generating a plurality of gated pulse modulated signals using the gate high voltage, a pulse modulated clock signal, and a pulse modulated enable signal having a first period and a second period;
The pulse modulation circuit,
During the first period corresponding to the touch sensing period, a DC voltage is generated and output to the gate driving circuit, and during the second period corresponding to the display period, a plurality of gate pulse modulation signals are generated and output to the gate driving circuit. power generation circuit. According to claim 1,
wherein each of the plurality of gate pulse modulation signals is maintained at a voltage level of the gate high voltage during a voltage holding period and linearly decreased at a voltage level of the gate high voltage during a voltage modulation period. According to claim 2,
The pulse modulation enable signal has a low voltage level during the first period and a high voltage level during the second period;
The pulse modulation circuit,
outputting the DC voltage in response to the pulse modulation enable signal and the pulse modulation clock signal of the low voltage level during the first period;
and outputting the plurality of gate pulse modulation signals in response to the pulse modulation enable signal and the pulse modulation clock signal of the high voltage level during the second period. According to claim 2,
The pulse modulation enable signal is maintained at a high voltage level during the first period and the second period,
The pulse modulation clock signal is maintained at a DC voltage level during the first period,
The pulse modulation circuit,
outputting the DC voltage in response to the pulse modulation enable signal of the high voltage level and the pulse modulation clock signal of the DC voltage level during the first period;
and outputting the plurality of gate pulse modulation signals in response to the pulse modulation enable signal and the pulse modulation clock signal of the high voltage level during the second period. According to claim 1,
The DC voltage has a voltage level of any one of a ground voltage and the gate high voltage. a power generation circuit according to any one of claims 1 to 5;
a display panel having gate lines, data lines, and touch electrodes;
a touch driving circuit supplying a touch driving signal to the touch electrodes in the first period, generating touch data by sensing capacitance change through the touch electrodes, and supplying a common voltage to the touch electrodes in the second period;
a data driving circuit supplying a data signal to the data line in the second period;
a gate driving circuit supplying gate pulses to the gate line in the second period using the plurality of gate pulse modulation signals supplied from the power generating circuit; and
A touch screen integrated display device comprising a timing control circuit for generating each of the pulse modulation enable signal and the pulse modulation clock signal. According to claim 6,
The timing control circuit generates a touch sync signal having a touch sensing period and a display period, and has a first period corresponding to the touch sensing period and a second period corresponding to the display period based on the touch synchronization signal. A display device integrated with a touch screen that generates a pulse modulation enable signal and provides it to the power generation circuit. According to claim 7,
The common voltage, the touch driving signal having a voltage swing width between a first voltage and a second voltage based on the common voltage, a data load free signal having the same phase as the touch driving signal, and the same phase as the touch driving signal a touch power driving circuit for generating each gate load free signal having a phase;
The data driving circuit supplies the data load free signal to the data line in the first period;
Wherein the gate driving circuit supplies the gate load free signal to the gate line in the first period. According to claim 8,
Wherein each of the data load free signal and the gate load free signal has the same voltage swing width while being in phase with the touch driving signal. According to claim 8,
The gate driving circuit,
a gate driver configured to generate the gate pulses based on the plurality of gate pulse modulation signals supplied from the power generation circuit and the gate control signal supplied from the timing control circuit; and
And a switching unit supplying the gate load free signal supplied from the touch power driving circuit to the gate line during the first period, and supplying the gate pulse supplied from the gate driver to the gate line during the second period. , touch screen all-in-one display device.

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