KR102551726B1 - Memory system - Google Patents

Abstract

An embodiment of the present invention relates to a memory system, and is a technology related to an accelerator of a large-capacity memory device. This embodiment of the present invention includes a plurality of memories for storing data and a pulled memory controller for reading data stored in the plurality of memories, performing a map operation, and storing result data of the map operation in the plurality of memories.

Description

Memory system {Memory system}

The present invention relates to a memory system and relates to an accelerator for a large-capacity memory device.

Recently, the spread of mobile communication terminals such as smart phones and tablet PCs has become popular. In addition, the use of social network services (SNS), machine to machine (M2M), sensor networks, and the like is increasing. Accordingly, the amount of data, the speed of generation and the variety thereof are increasing exponentially. In order to process big data, memory speed is also important, but memory devices and memory modules with large storage capacity are required.

Accordingly, the memory system includes a plurality of integrated memories to increase data storage capacity while overcoming physical limitations of the memory. For example, the server architecture of a cloud data center is being changed to a structure for efficiently executing a big-data application.

In order to efficiently process big data, pooled memory in which multiple memories are integrated is used. The pooled memory can provide a large capacity and a high bandwidth, and can be usefully used in an in-memory database.

An embodiment of the present invention provides a memory system that includes an accelerator inside a pulled memory to reduce energy consumption and improve performance of the system.

A memory system according to an embodiment of the present invention includes a plurality of memories for storing data; and a pulled memory controller that reads data stored in a plurality of memories, performs a map operation, and stores result data of the map operation in the plurality of memories.

Also, a memory system according to another embodiment of the present invention may include a fabric network connected to a processor; and a pulled memory that relays packets with the processor through a fabric network and delivers data stored in the memory to the processor upon request of the processor, wherein the pulled memory reads the data stored in the memory to off-load map operation, It includes a pulled memory controller that stores result data of an operation in a memory.

Embodiments of the present invention provide an effect of improving system performance and saving energy required for data operation.

1 is a diagram for explaining the concept of a memory system according to an embodiment of the present invention;
2 is a diagram showing the configuration of a memory system according to an embodiment of the present invention;
3 is a diagram showing a detailed configuration of the pulled memory controller of FIG. 2;
4 to 6 are diagrams for explaining the operation of a memory system according to an embodiment of the present invention;
7 is a diagram showing performance improvement of a memory system according to an embodiment of the present invention;

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing an embodiment of the present invention, when a part is said to be "connected" to another part, this is not only when it is "directly connected" but also when it is "electrically connected" with another element interposed therebetween. Also includes In addition, when a part "includes" or "includes" a certain component, this means that it may further include or include other components, not excluding other components unless otherwise specified. . In addition, even if some components are described in the singular form in the description of the entire specification, the present invention is not limited thereto, and it will be appreciated that the corresponding components may consist of a plurality of pieces.

Data center applications require more hardware resources as the size of data grows. Server architecture is evolving in the direction of using hardware resources more efficiently.

For example, many machine learning applications including deep learning are being executed in a cloud data center. Most of the applications such as deep learning and machine learning above have low temporal locality, so they require a graphic processing unit (GPU) or a field programmable gate array (FPGA) rather than a central processing unit (CPU). It is common to perform calculations through a hardware accelerator.

Here, temporal locality means that once accessed data is accessed again within a relatively close time. That is, the above applications use cold data that has not been accessed for a while rather than frequently accessed hot data.

A process of off-loading a job from a processor (eg, a central processing unit) to an accelerator is as follows. First, data is moved from the local memory of the processor to the local memory of the accelerator. Later, when the accelerator finishes its operation, it must move the resulting data back to the processor.

If the cost of moving data is greater than the cost of calculating data, implementing an architecture to move data as little as possible can reduce the overall cost. To this end, a memory-driven computing concept has recently been proposed.

1 is a diagram for explaining the concept of a memory system according to an embodiment of the present invention;

The embodiment of FIG. 1 represents a change in architecture from a System On Chip (SoC), that is, a processor-oriented computing (computing device) structure to a memory-oriented computing structure. In the processor-centric computing structure, one system-on-chip is connected to one memory in a one-to-one manner.

Memory-driven computing uses unified memory in which several systems-on-chips are connected through a fabric network. When data is exchanged between system-on-chips (SoCs), data is exchanged with a memory bandwidth.

In addition, a single unified memory connected through a fabric network does not require memory copy as in the past to send and receive data. For commercialization of memory-driven computing as described above, memory semantic interconnection must support high bandwidth, low latency, and coherency.

In the technical field to which an embodiment of the present invention belongs, research on interconnection of a transaction-based memory system is being actively conducted.

Regarding the accelerator, studies on the position of the accelerator according to the characteristics of the workload, such as Near Data Processing (NDP) or Processing In Memory (PIM), are also widely conducted. Here, processing-in-memory refers to a memory in which processor logic is closely coupled to memory cells in order to increase data processing speed and data transmission speed.

An embodiment of the present invention relates to a pooled memory architecture in which a plurality of memories are integrated and an in-memory database usage suitable therefor. Hereinafter, characteristics of a Map-Reduce Application according to an embodiment of the present invention will be described, and a process of processing a map operation in an accelerator (described later) in a pooled memory will be described. I'm going to do it.

2 is a diagram showing the configuration of a memory system according to an embodiment of the present invention.

The memory system 10 according to an embodiment of the present invention is based on the above-described memory-driven computing structure. The memory system 10 includes a plurality of processors (eg, central processing unit, CPU) 20 , a fabric network 30 , a plurality of channels 40 , and a plurality of pulled memories 100 .

Here, the plurality of processors 20 are connected to the fabric network 30 through the node CND. Also, the plurality of processors 20 are connected to the plurality of pulled memories 100 through the fabric network 30 . Also, the pulled memory 100 is connected to the fabric network 30 through a plurality of channels 40 . That is, each of the plurality of pulled memories 100 may be connected to the fabric network 30 through N channels 40 .

Each of the plurality of pooled memories 100 includes a plurality of memories 120 and a pooled memory controller (PMC) 110 for controlling the plurality of memories 120 . The pulled memory controller 110 is connected to each memory 120 through a bus BUS.

Each memory 120 may be directly connected to the fabric network 30 . However, a plurality of memories 120 may be included in one unified pulled memory 100 so that the pulled memory 100 may be connected to the fabric network 30 .

When the pulled memory 100 includes a plurality of memories 120 , the pulled memory controller 110 manages each memory 120 between the fabric network 30 and the plurality of memories 120 .

Here, the pulled memory controller 110 performs memory interleaving to increase throughput or address remapping to increase reliability, availability, and serviceability. support etc.

An in-memory database is a database management system that stores a database in main memory rather than storage for fast access.

Current server systems have physical limitations in increasing the capacity of memory. Accordingly, the application cannot increase the size of the database beyond the memory capacity of each server. When the size of the database increases, the database is inevitably divided into several servers to store the database, and in the process of combining multiple servers, there is a part where performance deteriorates. Since the pulled memory 100 provides a large capacity and a high bandwidth, it can be usefully used in an in-memory DB.

FIG. 3 is a diagram showing a detailed configuration of the pulled memory controller 110 of FIG. 2 .

The pulled memory controller 110 includes an interface 111 and an accelerator 112 . Here, interface 111 relays packets between fabric network 30 and accelerator 112 and memory 120 . The interface 111 is connected to the accelerator 112 through a plurality of channels CN.

In an embodiment of the present invention, the interface 111 may include a switch for relaying packets between the fabric network 30 and the accelerator 112 and memory 120 . In the embodiment of the present invention, it has been described as an example that the interface 111 includes a switch, but the embodiment of the present invention is not limited thereto, and means for relaying packets is not limited thereto.

And, the accelerator 112 performs arithmetic processing of data applied through the interface 111 . For example, the accelerator 112 performs a map operation on data applied from the memory 120 through the interface 111, and stores data about the result of the map operation in the memory 120 through the interface 111. .

In the embodiment of the present invention, it has been described that one accelerator 112 is included in the pulled memory controller 110 as an example. However, embodiments of the present invention are not limited thereto, and a plurality of accelerators 112 may be included in the pulled memory controller 110 .

The Map-Reduce application is a software framework designed for the purpose of processing large amounts of data in distributed parallel computing. Various applications use this map-reduce library. In map-reduce applications, map operation extracts intermediate information in the form of (key, value), and reduce operation collects them and outputs the desired final result.

For example, assuming that you are looking for "the highest annual global temperature" through a map-reduce application, the map operation reads a text file, extracts year and temperature information, and outputs a list in the form of (year, temperature). . Then, the reduce operation collects these results, sorts them in order of temperature, and outputs the desired final result. Here, it should be noted that the data used for the map operation is generally large, whereas the data resulting from the map operation is relatively small.

The embodiment of the present invention processes large amounts of data, such as map operations of map-reduce applications, but off-loads operations with little data reuse to the accelerator 112 in the pulled memory controller 110. ) can do. Here, off-loading refers to a series of processes of receiving and interpreting a request from the processor 20, performing an operation, and then outputting the operation result. When data is processed in the pulled memory 100, energy for transferring data to the node CND of the processor 20 can be saved and performance can be further improved.

The accelerator 112 according to an embodiment of the present invention may be included in the pulled memory controller 110 or located in the memory 120 . In terms of proximity data processing, processing data within each memory 120 is more efficient than processing data inside the pulled memory controller 110 .

The pulled memory controller 110 performs memory interleaving to provide high bandwidth. In this case, data is divided into several memories 120 and stored. In this case, data required by the accelerator 112 can also be divided into several memories 120, so in the embodiment of the present invention, the physical location of the accelerator 112 is placed in the pulled memory controller 110 as an example. Let's explain.

From now on, how much benefit of off-loading the map operation of the map-reduce application to the accelerator 112 will be seen in terms of performance and energy of the memory system 10 as a whole.

If an operation processed by the accelerator 112 is simple, such as a map operation of a map-reduce application, an operation time in the accelerator 112 is influenced by a bandwidth for reading data from memory. Accordingly, the computation time of the accelerator 112 may be reduced by increasing the bandwidth of the accelerator 112 .

As shown in FIG. 3 , node CNDs of a series of processors 20 are connected to the pulled memory 100 via a fabric network 30 . It is assumed that each node CND has one link L1 for each processor 20 and the accelerator 112 inside the pulled memory controller 110 has four links L2. That is, a wider bandwidth is allocated to the link L2 of the accelerator 112 than to the link L1 of the processor 20 . Then, when the map operation is off-loaded to the accelerator 112, the operation can be performed four times faster than the processing in the processor 20.

When the processor 20 performs both the map operation and the reduce operation, it is assumed that the time required for the map operation is 99% of the total execution time. In addition, it is assumed that several applications are executed in one processor 20, and the execution time of a map-reduce application among them occupies 10% of the execution time of all applications. In the case of offloading the map operation to the accelerator 112, the map operation time is reduced by 1/4, and thus the overall system performance can be improved by 81%.

4 to 6 are diagrams for explaining the operation of the memory system 10 according to an embodiment of the present invention.

First, as shown in path (1) of FIG. 4 , the processor 20 transfers a map operation request packet to the pulled memory 100 . That is, the map operation request packet transmitted from the processor 20 is transferred to the accelerator 112 through the interface 111 of the pulled memory controller 110 through the fabric network 30 . Here, the map operation request packet may include information about an address where data to be used for map operation is stored, a data size, and an address where map operation result data is stored.

Next, the pulled memory controller 110 transfers the map operation response packet to the processor 20 through the fabric network 30 as shown in path (2) of FIG. 4 . That is, the pulled memory controller 110 transmits a signal indicating that the accelerator 112 successfully received the map operation request packet to the processor 20 .

Subsequently, as shown in path (3) of FIG. 5 , the pulled memory controller 110 reads data necessary for map operation from each memory 120 and transfers it to the accelerator 112 . Here, data required by the accelerator 112 may be divided into several memories 120, and in this case, the accelerator 112 reads data from the plurality of memories 120. Then, the accelerator 112 performs a map operation based on the data read from the memory 120 .

Subsequently, as shown in path (4) of FIG. 5 , the pulled memory controller 110 reads map operation result data calculated in the accelerator 112 and transfers the data to each memory 120 to store the data. Data calculated by the accelerator 112 may be divided and stored in a plurality of memories 120 .

Next, as in the path (5) of FIG. 6, the pulled memory controller 110 transfers the interrupt packet to the processor 20 side. That is, the pulled memory controller 110 transfers an interrupt packet indicating that the map operation of the accelerator 112 is finished to the processor 20 through the fabric network 30 .

Thereafter, the pulled memory controller 110 reads the map operation result data stored in the memory 120 as shown in path (6) of FIG. forward to

7 is a diagram illustrating performance improvement of a memory system according to an exemplary embodiment of the present invention. 7 is a result graph showing how much the performance of the entire system increases as the number of channel CNs of the accelerator 112 increases when the accelerator 112 performs a map operation.

It can be seen that performance also increases as the number of channel CNs of the accelerator 112 increases. However, since the amount of performance increase is gradually smaller than the cost of increasing the number of channel CNs, setting the number of channel CNs of the accelerator 112 to 2 to 4 will be described as an example in the embodiment of the present invention.

It is assumed that 1 pJ (energy consumption)/bit is consumed per link L1 to move data through the node CND of the processor 20. In order to process data in the processor 20, the bus BUS of the memory 120 in FIG. 3, the channel 40 of the fabric network 30, and the node CND of the processor 20, that is, a total of three links, pJ/bit is consumed. However, if the map operation is off-loaded to the accelerator 112, since the data only passes through the bus BUS of the memory 120, the energy consumed to move the data can be reduced to 1/3, or 1 pJ/bit. To calculate how much energy is saved in the overall system, the static power of each piece of hardware must be taken into account.

As described above, the pulled memory 100 according to an embodiment of the present invention can provide large capacity and high bandwidth, and can be usefully used in an in-memory database or the like. By adding the accelerator 112 inside the pulled memory controller 110 and off-loading the map operation of the map-reduce application in the accelerator 112, the performance of the entire system can be improved and energy can be saved.

Those skilled in the art to which the present invention pertains should understand that the embodiments described above are illustrative in all respects and not limiting, since the present invention can be embodied in other specific forms without changing the technical spirit or essential characteristics thereof. only do The scope of the present invention is indicated by the claims to be described later rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and equivalent concepts should be construed as being included in the scope of the present invention. .

Claims (20)

A plurality of memories for storing data; and
a pulled memory controller that reads the data stored in the plurality of memories, performs a map operation, and stores result data of the map operation in the plurality of memories;
The pooled memory controller
an interface for relaying packets between a processor and the plurality of memories through a fabric network; and
An accelerator for performing the map operation on the data transmitted from the plurality of memories through the interface and storing result data of the map operation in the plurality of memories through the interface;
The accelerator is connected to the interface through a plurality of channels,
The number of links of the plurality of channels is greater than the number of links of the processor,
wherein the interface transmits the read data to the accelerator, receives the result data calculated by the accelerator, and transmits the received result data to the plurality of memories. delete delete delete The method of claim 1 , wherein the pulled memory controller
A memory system receiving a map operation request packet from the processor through the interface. 6. The method of claim 5, wherein the map operation request packet
A memory system comprising information on at least one of an address where data to be used for the map operation is stored, a size of the data, and an address where result data of the map operation is stored. The method of claim 1 , wherein the pulled memory controller
A memory system configured to transmit a map operation response packet to the processor through the interface. The method of claim 1 , wherein the pulled memory controller
A memory system that reads data necessary for the map operation from the plurality of memories and transmits the data to the accelerator. The method of claim 1 , wherein the pulled memory controller
A memory system configured to read result data of the map operation calculated in the accelerator and store the result data in the plurality of memories. The method of claim 1 , wherein the pulled memory controller
When the map operation is finished, the memory system transmits an interrupt packet to the processor through the interface. The method of claim 1 , wherein the pulled memory controller
A memory system for reading result data of the map operation stored in the plurality of memories and transmitting the data to the processor through the interface. The method of claim 1 , wherein the pulled memory controller
A memory system performing interleaving on the plurality of memories. The method of claim 1 , wherein the pulled memory controller
A memory system performing address remapping on the plurality of memories. The method of claim 1 , wherein the pulled memory controller
A memory system using a map-reduce application during the map operation. a fabric network associated with the processor; and
A pulled memory that relays packets with the processor through the fabric network and transmits data stored in the memory to the processor when requested by the processor;
The pooled memory is
a pulled memory controller that reads data stored in the memory, offloads a map operation, and stores result data of the map operation in the memory;
The pooled memory controller
an interface relaying the packet between the processor and the pulled memory controller through the fabric network; and
an accelerator for off-loading the map operation on the data transmitted from the memory through the interface and storing result data of the map operation in the memory through the interface;
the accelerator
connected through the interface and a plurality of channels,
The number of links of the plurality of channels is greater than the number of links of the processor,
performing the map operation and off-loading the map operation by reading the data received from the memory through the interface to generate the result data;
wherein the interface transmits the read data to the accelerator, receives result data calculated by the accelerator, and transmits the received result data to the memory. delete 16. The method of claim 15, wherein the pulled memory controller
A memory system configured to receive a map operation request packet from the processor through the interface and transmit a map operation response packet to the processor through the interface. 16. The method of claim 15, wherein the pulled memory controller
A memory system configured to read data necessary for the map operation from the memory, transfer the data to the accelerator, and store result data of the map operation calculated in the accelerator in the memory. 16. The method of claim 15, wherein the pulled memory controller
When the map operation is finished, an interrupt packet is transmitted to the processor through the interface, and result data of the map operation stored in the memory is read and transmitted to the processor through the interface. 16. The method of claim 15, wherein the pulled memory controller
A memory system performing at least one of an interleaving operation and an address remapping operation on the memory.

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