KR102541644B1 - On-chip transformer device - Google Patents

Abstract

The present invention relates to a technology of patterning a transformer together in an on-chip circuit patterning process, and relates to a technology of patterning a transformer formed by patterning a circuit on a semiconductor chip on the on-chip together with other on-chip patterning processes. According to the present invention, the primary closed loop member and the secondary closed loop member are sequentially alternately patterned on an on-chip in a state in which the coil-type primary closed-loop member and the coil-type secondary closed-loop member are electrically insulated from each other. Accordingly, the process yield is improved, thereby improving the reliability of semiconductor chip products.

Description

On-chip transformer device {On-chip transformer device}

The present invention relates to a technique of patterning a transformer together in an on-chip circuit patterning process.

More particularly, the present invention relates to a technique of patterning a transformer on an on-chip formed by patterning a circuit on a semiconductor chip along with other on-chip patterning processes.

First, a transformer refers to a stationary device that transfers electric energy between two or more circuits through an inductive electric conductor.

Looking at the operating principle of the transformer, first, the changing current in the primary side circuit creates a changing magnetic field. The changing magnetic field by that primary then induces a changing voltage in the secondary side circuit.

That is, energy, which is an induced electromotive force, is transferred to the secondary side through the changing current (AC) of the primary side. As a result, by connecting a load to the secondary side, the load uses the energy transferred as above.

And, [Fig. 1] is an exemplary view showing positions where a plurality of transformers employed in a general semiconductor chip are joined.

An on-chip is formed by patterning an integrated circuit (IC) on a semiconductor chip through, for example, an etching process. As shown in FIG. 1, after bonding elements such as a transformer on the integrated circuit, the semiconductor chip is completed through a packaging process. will do

At this time, in order to bond the transformer on the on-chip, in the process of forming the patterning on the on-chip, contact leads to be connected to the transformer must be patterned in advance.

That is, in the conventional on-chip manufacturing process, circuit patterning and contact lead patterning are performed on the on-chip, and then a transformer element previously made externally is bonded to the position shown in [Fig. 1].

In this way, when a semiconductor chip is completed by bonding external elements (eg, transformers) on an existing on-chip, an essential process of bonding external elements to the on-chip occurs, and inefficiency in the process of reducing the defect rate during bonding occurs. there is a problem with

Accordingly, in the process of patterning the integrated circuit on the semiconductor chip, the transformer is also patterned together to increase process efficiency and solve problems such as defective bonding to increase product reliability, thereby realizing a technology that can solve the problems of the prior art as described above. this is required

The present invention has been proposed in view of the above, and an object of the present invention is to reduce the number of manufacturing processes of a semiconductor chip, reduce defects in the existing bonding process, and improve product reliability by patterning a transformer together when forming an on-chip. It is to provide an on-chip transformer device that can be increased.

In order to achieve the above object, the present invention provides an on-chip transformer device patterned in a coil shape on an on-chip, comprising: a primary closed loop member 10 patterned to be a closed loop in a coil shape on an on-chip; A secondary closed loop member 20 patterned to be a closed loop in the form of a coil on the chip in the form of sequentially alternating with the form of a coil of the primary close loop member in a state of being electrically insulated from the primary close loop member; including It consists of

Here, the primary closed loop member 10 includes a first primary group 110 in which a plurality of first primary members form a plurality of lines in a first horizontal direction on one side of the on-chip and are spaced apart from each other by a predetermined distance. ; a second primary group 120 in which a plurality of second primary members form a plurality of lines in a first horizontal direction on the other side of the on-chip facing the first primary group and are spaced apart from each other by a predetermined distance; A plurality of lower primary members connecting the lower end of the first primary member and the lower end of the second primary member are provided so that the first primary group and the second primary group are interconnected to form one closed loop. a lower primary group 130 forming a plurality of lines under the first primary group and the second primary group; A plurality of upper primary members connecting the upper end of the first primary member and the upper end of the second primary member so that one closed loop connecting the first primary group and the second primary group is formed in conjunction with the lower primary group An upper primary group 140 forming a plurality of lines above the first primary group and the second primary group may be provided.

Further, in the secondary closed loop member 20, a plurality of first primary members electrically insulated from the plurality of first primary members and a plurality of first secondary members sequentially alternating with each other are disposed in a first horizontal direction. a first secondary group 210; On the other side of the on-chip facing the first secondary group, a plurality of second secondary members electrically insulated from the plurality of second primary members and sequentially alternating with the plurality of second primary members are connected in the first horizontal direction. a second secondary group 220 disposed as; A plurality of lower tiers sequentially alternating with a plurality of lower primary members while connecting the lower end of the first secondary member and the lower end of the second secondary member so that the first secondary group and the second secondary group are interconnected to form one closed loop. a lower secondary group 230 having a secondary member and forming a plurality of lines under the first secondary group and the second secondary group; Connect the upper end of the first secondary member and the upper end of the second secondary member so that a closed loop connecting the first secondary group and the second secondary group is formed in conjunction with the lower secondary group, but alternately with a plurality of upper primary members, respectively. upper secondary groups 240 forming a plurality of lines above the first secondary group and the second secondary group; may be provided.

In addition, the primary closed loop member 10 is disposed above the first primary member located at the outermost side of one side of the first primary group and energizes the first primary member closest to the lower part thereof. primary input/output terminal A member 150; A primary input/output terminal B disposed above the second primary member corresponding to the outermost part of the second primary group in the diagonal line of the primary input/output terminal A member to energize the second primary member closest to the lower portion of the primary input/output terminal B A member 160; may be further provided.

At this time, the secondary closed loop member 20 is located on the outermost side of one side of the first secondary group, but is disposed on the upper part of the first secondary member corresponding to the outer side of the primary input/output terminal A member and is closest to its lower part. a secondary input/output terminal A member 250 that energizes the first secondary member; It is located on the upper part of the second secondary member corresponding to the outermost part of the second secondary group in the diagonal line of the secondary input/output terminal A member, but is disposed on the upper part of the second secondary member corresponding to the outer side of the primary input/output terminal B member and has its lower part It may further include a secondary input/output terminal B member 260 that energizes the second secondary member closest to the .

Meanwhile, the upper primary group 140 is an upper primary member disposed between the primary input/output terminal A member and the primary input/output terminal B member, and faces the second primary member to which the primary input/output terminal B member is connected. A coiled upper part having one end connected to the first primary member at a location and having the other end connected to the second primary member most adjacent to the second primary member to which the primary input/output terminal B member is connected. Primary a member 141; An upper primary member disposed between the primary input/output terminal A member and the primary input/output terminal B member, wherein one end of the coiled upper primary a member is connected to the first primary member most adjacent to the first primary member. A connection pattern in which one end thereof is connected and the other end thereof is connected to the second primary member closest to the second primary member to which the other end of the coiled upper primary a member is connected is connected to the primary input/output terminal B One or more coil-type upper primary n-members 142 to 144 are disposed while moving from the coil-type upper primary a-member one by one toward the primary input/output terminal A member in the member.

And, the upper secondary group 240 is an upper secondary member disposed between the secondary input/output terminal A member and the secondary input/output terminal B member, and is a first secondary group opposite to the second secondary member to which the secondary input/output terminal B member is connected. a coil-shaped upper secondary a-member 241 having one end connected to the member and the other end connected to the second secondary member closest to the second secondary member to which the secondary input/output terminal B member is connected; An upper secondary member disposed between the secondary input/output terminal A member and the secondary input/output terminal B member, one end of which is connected to the first secondary member most adjacent to the first secondary member to which one end of the coiled upper secondary a member is connected , The second secondary member to which the other end of the coiled upper secondary a member is connected and the connection pattern in which the other end of the coiled upper secondary member is connected to the second secondary member closest to the coil is directed from the secondary input/output terminal B member to the secondary input/output terminal A member. One or more coil-type upper secondary n-members 242 to 244 disposed while moving one by one from the mold-type upper secondary a-member may be provided.

On the other hand, the first primary member includes a plurality of layers formed with via holes for vertical conduction so as to mutually conduct a lower primary member corresponding to its vertically lower portion and an upper primary member corresponding to its vertical upper portion in the vertical direction. can be overlapped.

In addition, the first secondary member may be arranged such that a plurality of layers formed with via holes for vertical conduction are overlapped in the vertical direction so as to conduct electricity between the lower secondary member corresponding to its vertical lower part and the upper secondary member corresponding to its vertical upper part. there is.

In addition, in the second primary member, a plurality of layers formed with via holes for vertical conduction are overlapped in the vertical direction so as to conduct electricity between the lower primary member corresponding to the vertically lower part and the upper primary member corresponding to the upper primary member thereof. can be placed.

In addition, the second secondary member may be arranged such that a plurality of layers formed with via holes for conduction in the vertical direction are overlapped in the vertical direction so as to conduct electricity between the lower secondary member corresponding to the lower secondary member and the upper secondary member corresponding to the upper secondary member. there is.

In the present invention, in a state in which the coil-type primary closed-loop member and the coil-type secondary closed-loop member are electrically insulated from each other, the primary closed-loop member and the secondary closed-loop member are sequentially alternately patterned on an on-chip, thereby reducing weak points. An advantage is that energy can be transferred from the primary closed loop member to the secondary closed loop member even through current.

In addition, the present invention is patterned on-chip by sequentially alternating the primary closed loop member and the secondary closed loop member in a state in which the coil-shaped primary closed-loop member and the coil-shaped secondary closed-loop member are electrically insulated from each other. It also shows the advantage of improving the reliability of semiconductor chip products by improving the process yield.

1 is an exemplary view showing positions where a plurality of transformers employed in a general semiconductor chip are to be joined;
[Figure 2] is an exploded perspective view of a primary closed loop member, which is a component of the present invention, and an exemplary view showing a state in which current flows;
[Figure 3] is a view in which each component of [Figure 2] is brought close to each other in the vertical direction;
4 is an exploded perspective view of a secondary closed loop member, which is a configuration of the present invention, and an exemplary view showing a state in which current flows;
[Figure 5] is a view in which each component of [Figure 4] is brought close to each other in the vertical direction;
[Figure 6] is a view combining [Figure 2] and [Figure 4] by crossing each other;
[Fig. 7] is a view in which each component of [Fig. 6] is placed close to each other in the vertical direction.

Hereinafter, the present invention will be described in detail with reference to the drawings.

[Fig. 2] is an exploded perspective view of a primary closed loop member, which is a component of the present invention, and is an exemplary view showing a state in which current flows, and [Fig. 3] is a view in which each component of [Fig. 2] is vertically adjacent to each other. [Fig. 4] is an exploded perspective view of the secondary closed loop member, which is a component of the present invention, and is an exemplary view showing a state in which current flows, and [Fig. 5] is a diagram in which each component of [Fig. [Fig. 6] is a drawing in which [Fig. 2] and [Fig. 4] are intersected and combined, and [Fig. 7] is a drawing in which each component of [Fig. 6] is placed close to each other in the vertical direction.

2 to 7, the present invention is an on-chip transformer device 1 patterned in a coil shape on an on-chip, comprising a primary closed-loop member 10 and a secondary closed-loop member ( 20) may be configured.

When patterning the integrated circuit on the chip, the primary closed loop member 10 is patterned together with the integrated circuit, but is patterned to be a closed loop in the form of a coil as shown in FIGS. 2 and 3 .

When patterning the integrated circuit on the on-chip, the secondary closed loop member 20 is patterned together with the integrated circuit, but is patterned to be a closed loop in the form of a coil as shown in FIGS. 4 and 5.

As a result, the on-chip transformer device 1 according to the present invention is patterned in the form of a dual closed loop maintaining an electrically insulated state from each other as shown in FIGS. 2 to 7 in the process of patterning the integrated circuit on the semiconductor chip. .

To this end, the primary closed loop member 10 and the secondary closed loop member 20 maintain an electrically insulated state from each other as shown in [FIG. 6] and [FIG. 7] while sequentially alternating on-chip Patterning is performed together with the patterning of the integrated circuit.

Here, the meaning that the primary closed loop member 10 and the secondary closed loop member 20 sequentially alternate each other means that the primary closed loop member 10 according to [FIG. 2] and [FIG. 3] As the secondary closed loop member 20 according to [Figs. 4] and [Fig. 5] is inserted into the space between [Figs. 6] and [Fig. 7], as a result, each component is sequentially alternated. will be.

In other words, the meaning that the primary closed loop member 10 and the secondary closed loop member 20 sequentially alternate each other means that the secondary closed loop member 20 according to [FIG. 4] and [FIG. 5] As the primary closed loop member 10 according to [Figs. 2] and [Fig. 3] is inserted in the space between [Figs. 6] and [Fig. 7], as a result, each component is sequentially alternated. that it becomes

To this end, the primary closed loop member 10 includes a first primary group 110, a second primary group 120, a lower primary group 130, An upper primary group 140 , a primary input/output terminal A member 150 , and a primary input/output terminal B member 160 may be provided.

In the first primary group 110, a plurality of first primary members 111, 112, 113, 114, and 115 are arranged in a first horizontal direction as shown in [FIG. 2] and [FIG. 3] at one side of the on-chip. A plurality of lines may be formed but spaced apart from each other by a predetermined distance.

Here, the first horizontal direction denotes a direction in which the plurality of first primary members 111, 112, 113, 114, and 115 are spaced apart from each other by a predetermined distance and lined up in a row, as shown in FIG. 2.

Further, the first primary members 111, 112, 113, 114, and 115 have lower primary members 131, 132, 133, and 134 corresponding to their vertical lower portions as shown in [FIG. 2] and [FIG. 3]. , 135) and the upper primary members 141, 142, 143, and 144 corresponding to their vertical upper portions may be overlapped in a vertical direction so as to mutually conduct a plurality of layers having via holes for vertical conduction.

At this time, the plurality of first primary members 111, 112, 113, 114, and 115 include upper primary members 141, 142, 143, and 144 and primary input/output as shown in [FIG. 2] and [FIG. 3]. It is also configured to be mutually energized with the terminal A member 150.

Here, 'a plurality of layers' means that, for example, one first primary member 111 may form a plurality of layers 111a, 111b, and 111c and overlap each other in the vertical direction as shown in FIG. 2. it means.

In addition, 'a plurality of layers' means that, for example, another first primary member 112 may form a plurality of layers 112a, 112b, and 112c and overlap each other in the vertical direction as shown in [FIG. 2]. means that

In addition, 'a plurality of layers' means that, for example, another first primary member 113 may form a plurality of layers 113a, 113b, and 113c, overlapping each other in the vertical direction as shown in [FIG. 2]. means there is

The second primary group 120 includes a plurality of second primary members 121, 122, and 123 as shown in [FIG. 2] and [FIG. 3] on the other side of the on-chip facing the first primary group 110. , 124, 125) form a plurality of lines in the first horizontal direction, but may be spaced apart from each other by a predetermined distance.

Here, the first horizontal direction denotes a direction in which the plurality of second primary members 121, 122, 123, 124, and 125 are spaced apart from each other by a predetermined distance and lined up in a row, as shown in FIG. 2.

Further, the second primary members 121, 122, 123, 124, and 125 have lower primary members 131, 132, 133, 134, and 135 corresponding to their vertical lower parts and upper parts corresponding to their vertical upper parts. A plurality of layers having via holes for up-and-down conduction to conduct electricity through the primary members 141 , 142 , 143 , and 144 may be overlapped in the up-and-down direction.

At this time, the plurality of second primary members 121, 122, 123, 124, and 125 correspond to the upper primary members 141, 142, 143, and 144 and the primary input/output as shown in [FIG. 2] and [FIG. 3]. It is also configured to be mutually energized with the terminal B member 160.

Here, 'a plurality of layers' means that, for example, one second primary member 121 may form a plurality of layers 121a, 121b, and 121c and overlap each other in the vertical direction as shown in FIG. 2. it means.

In addition, 'a plurality of layers' means that, for example, another second primary member 122 may form a plurality of layers 122a, 122b, and 122c and overlap each other in the vertical direction as shown in FIG. 2. means that

In addition, 'a plurality of layers' means that, for example, another second primary member 123 may form a plurality of layers 123a, 123b, and 123c and overlap each other in the vertical direction as shown in [FIG. 2]. means there is

In the lower primary group 130, the first primary group 110 and the second primary group 120 are interconnected to form one closed loop, as shown in [FIGS. 2] and [FIG. 3]. By providing a plurality of lower primary members 131, 132, 133, 134, 135 connecting the lower ends of the primary members 111 to 115 and the lower ends of the second primary members 121 to 125, the first primary 2 and 3 below the group 110 and the second primary group 120, a plurality of lower primary members corresponding to the plurality of lower primary members 131, 132, 133, 134, and 135 are formed. form a line

The upper primary group 140 interlocks with the lower primary group 130 so that one closed loop connecting the first primary group 110 and the second primary group 120 is formed [Fig. 2] and [ As shown in FIG. 3, a plurality of upper primary members 141 to 144 connecting the upper ends of the first primary members 111 to 115 and the upper ends of the second primary members 121 to 125 are provided, so that the first 2 and 3 above the primary group 110 and the second primary group 120, a plurality of upper primary members 141, 142, 143, 144 and primary input/output terminals It forms a plurality of lines corresponding to the A member 150.

Meanwhile, the upper primary group 140 includes a plurality of upper primary members 141 to 140 as shown in [FIG. 2] and [FIG. 3] so that the primary closed loop member 10 can be implemented as a coil-shaped closed loop. 144) was composed of a coiled upper primary a member 141 and one or more coiled upper primary n members 142 to 144.

The coiled upper primary a member 141 is disposed between the primary input/output terminal A member 150 and the primary input/output terminal B member 160 as shown in [FIG. 2] and [FIG. 3]. 141, one end thereof is connected to the first primary member 111 at a position opposite to the second primary member 121 to which the primary input/output terminal B member 160 is connected, and the primary input/output terminal The other end thereof is connected to the second primary member 122 closest to the second primary member 121 to which the B member 160 is connected.

The coil-type upper primary n-members 142 to 144 are upper fry disposed between the primary input/output terminal A member 150 and the primary input/output terminal B member 160 as shown in [FIG. 2] and [FIG. 3]. As the head members 142 to 144, one end of the coiled upper primary a-member 141 is connected to the first primary member 111 to which one end is connected and the first primary member 112 closest to the other. and a connection pattern having its other end connected to the second primary member 123 most adjacent to the second primary member 122 to which the other end of the coiled upper primary a-member 141 is connected. While moving from the head input/output terminal B member 160 to the primary input/output terminal A member 150 one by one from the coil-type upper primary a member 141, a plurality of ( 142, 143, 144) may be arranged.

As shown in FIGS. 2 and 3, the primary input/output terminal A member 150 is disposed above the first primary member 115 located at the outermost part of one side of the first primary group 110. and energizes the first primary member 115 closest to its lower part.

As shown in FIGS. 2 and 3, the primary input/output terminal B member 160 corresponds to the outermost part of the second primary group 120 on the diagonal of the primary input/output terminal A member 150. It is disposed above the primary member 121 and energizes the second primary member 121 closest to its lower part.

On the other hand, as shown in [Figs. 6] and [Fig. 7], the secondary closed loop member 20 forming a dual closed loop with the primary closed loop member 10 is also shown in [Figs. 4] and [5]. Similarly, the first secondary group 210, the second secondary group 220, the lower secondary group 230, the upper secondary group 240, the secondary input/output terminal A member 250, and the secondary input/output terminal B member 260 are provided. can do.

As shown in [FIG. 4] to [FIG. 7], the first secondary group 210 includes a plurality of first primary members 111 to 115 electrically insulated from the plurality of first primary members 111 to 115 and A plurality of first secondary members 211, 212, 213, 214, and 215 sequentially alternating may be arranged in a first horizontal direction as shown in [FIGS. 4] and [FIG. 5].

Here, the first horizontal direction refers to a direction in which the plurality of first secondary members 211, 212, 213, 214, and 215 are spaced apart from each other by a predetermined distance and lined up in a row, as shown in [FIG. 4] and [FIG. 6]. indicate

Also, the first secondary members 211, 212, 213, 214, and 215 have lower secondary members 231, 232, 233, 234, and 235 corresponding to their vertical lower parts as shown in [FIG. 4] and [FIG. 5]. ) and the upper secondary members 241, 242, 243, and 244 corresponding to their vertical upper portions, a plurality of layers formed with via holes for vertical conduction may be overlapped in the vertical direction.

At this time, the plurality of first secondary members 211, 212, 213, 214, and 215 are the upper secondary members 241, 242, 243, and 244 and the secondary input/output terminal A member as shown in [FIG. 4] and [FIG. 5]. (250) is also configured to be mutually energized.

Here, 'a plurality of layers' means that, for example, one first secondary member 211 can be disposed overlapping in the vertical direction by forming a plurality of layers 211a, 211b, and 211c as shown in [FIG. 4]. do.

In addition, 'a plurality of layers' means that, for example, another first secondary member 212 may form a plurality of layers 212a, 212b, and 212c and overlap each other in the vertical direction as shown in [FIG. 4]. it means.

In addition, 'a plurality of layers' means that, for example, another first secondary member 213 may form a plurality of layers 213a, 213b, and 213c and overlap each other in the vertical direction as shown in [FIG. 4]. means that

The second secondary group 220 is electrically insulated from the plurality of second primary members 121 to 125 on the other side of the on-chip facing the first secondary group 210 [Fig. 4] and [Fig. 5]. ], the plurality of second primary members 121 to 125 and the plurality of second secondary members 221, 222, 223, 224, and 225 sequentially alternating with each other may be disposed in the first horizontal direction.

Here, the first horizontal direction indicates a direction in which the plurality of second secondary members 221, 222, 223, 224, and 225 are spaced apart from each other by a predetermined distance and lined up in a line, as shown in FIG. 4.

Further, the second secondary members 221, 222, 223, 224, and 225 have lower secondary members 231, 232, 233, 234, and 235 corresponding to their vertical lower parts and upper secondary members corresponding to their vertically upper parts. It is preferable that a plurality of layers having via holes for up and down conduction are overlapped in the up and down direction so as to conduct electricity through (241, 242, 243, and 244).

At this time, the plurality of second secondary members 221, 222, 223, 224, and 225 are the upper secondary members 241, 242, 243, and 244 and the secondary input/output terminal B member as shown in [FIG. 4] and [FIG. 5]. (260) is also configured to be mutually energized.

Here, 'a plurality of layers' means that, for example, one second secondary member 221 can be disposed overlapping in the vertical direction by forming a plurality of layers 221a, 221b, and 221c as shown in [FIG. 4]. do.

In addition, 'a plurality of layers' means that, for example, another second secondary member 222 may form a plurality of layers 222a, 222b, and 222c and overlap each other in the vertical direction as shown in [FIG. 4]. it means.

In addition, 'a plurality of layers' means that, for example, another second secondary member 223 may form a plurality of layers 223a, 223b, and 223c and overlap each other in the vertical direction as shown in FIG. 4. means that

As shown in [FIG. 4] to [FIG. 7], the lower secondary group 230 includes a first secondary member ( 211 to 215 and the lower ends of the second secondary members 221 to 225, but sequentially alternating with the plurality of lower primary members 131, 132, 133, 134, and 135 (231). , 232, 233, 234, 235), a plurality of lower secondary members 231 are provided below the first secondary group 210 and the second secondary group 220 as shown in [FIGS. 4] and [FIG. 5]. , 232, 233, 234, 235) form a plurality of lines.

The upper secondary group 240 interlocks with the lower secondary group 230 to form a closed loop connecting the first secondary group 210 and the second secondary group 220 in [FIG. 4] to [FIG. 7]. A plurality of upper secondary members connecting the upper ends of the first secondary members 211 to 215 and the upper ends of the second secondary members 221 to 225 but sequentially alternating with the plurality of upper primary members 141 to 144 ( 214 to 244), a plurality of upper secondary members 241, 242, 243, 244) and a plurality of lines corresponding to the secondary input/output terminal A member 250.

On the other hand, the upper secondary group 240 includes a plurality of upper secondary members 241 to 244 as shown in [FIG. 4] and [FIG. 5] so that the secondary closed loop member 20 can be implemented as a closed loop in the form of a coil. was composed of a coil-type upper secondary a-member 241 and one or more coil-type upper secondary n-members 242 to 244.

The coiled upper secondary member a 241 is an upper secondary member 241 disposed between the secondary input/output terminal A member 250 and the secondary input/output terminal B member 260 as shown in FIGS. 4 and 5. , One end thereof is connected to the first secondary member 211 at a position opposite to the second secondary member 221 to which the secondary input/output terminal B member 260 is connected, and the secondary input/output terminal B member 260 is connected. Its other end is connected to the second secondary member 222 closest to the second secondary member 221 .

The coiled upper secondary n-members 242 to 244 are upper secondary members 242 disposed between the secondary input/output terminal A member 250 and the secondary input/output terminal B member 260 as shown in [FIG. 4] and [FIG. 5]. 244), one end of the coiled upper secondary member a is connected to the first secondary member 212 closest to the first secondary member 211 to which one end is connected, and one end thereof is connected to the coiled upper secondary member a. The second secondary member 222 to which the other end of the member 241 is connected and the connection pattern in which the other end of the member 241 is connected to the second secondary member 223 closest to it is connected to the secondary input/output terminal B member 260. A plurality of 242, 243, and 244 may be disposed as shown in [FIG. 4] and [FIG. 5] while moving one cell from the coil-type upper secondary a-member 241 toward the terminal A-member 250.

As shown in FIGS. 4 and 5, the secondary input/output terminal A member 250 is located at the outermost part of one side of the first secondary group 210, but corresponds to the outer side of the primary input/output terminal A member 150. It is disposed above the first secondary member 215 and energizes the first secondary member 215 closest to its lower part.

The secondary input/output terminal B member 260 is a second secondary member corresponding to the outermost part of the second secondary group 220 on the diagonal of the secondary input/output terminal A member 250 as shown in [FIG. 4] and [FIG. 5] ( 221) but is disposed on the upper part of the second secondary member 221 corresponding to the outer side of the primary input/output terminal B member 160 to conduct electricity to the second secondary member 221 closest to its lower part. .

1: on-chip transformer device according to the present invention
10: absence of primary closed loop
20: absence of secondary closed loop
110: first primary group
111 to 115: first primary member
120: second primary group
121 to 125: second primary member
130: lower primary group
131 to 135: lower primary member
140: upper primary group
141: coil type upper primary a member (upper primary member)
142 to 144: coil type upper primary n member (upper primary member)
150: primary input/output terminal A member
160: primary input/output terminal B member
210: first secondary group
211 to 215: first secondary member
220: second secondary group
221 to 225: second secondary member
230: lower secondary group
231 to 235: lower secondary member
240: upper secondary group
241: coil type upper secondary a member (upper secondary member)
242 to 244: coil type upper secondary n member (upper secondary member)
250: Secondary input/output terminal A member
260: Secondary input/output terminal B member

Claims (4)

As an on-chip transformer device patterned in the form of a coil on-chip,
a primary closed loop member 10 patterned on the on-chip to form a closed loop in a coil form;
A secondary closed loop patterned to be a closed loop in a coil form on the on-chip in a form electrically insulated from the primary closed loop member 10 and sequentially alternating with the coil form of the primary closed loop member 10, respectively. loop member 20;
It is composed of,
The primary closed loop member 10,
a first primary group 110 in which a plurality of first primary members form a plurality of lines in a first horizontal direction on one side of the on-chip and are spaced apart from each other by a predetermined distance;
On the other side of the on-chip facing the first primary group 110, a plurality of second primary members form a plurality of lines in the first horizontal direction and are spaced apart from each other by a predetermined distance; 120);
A lower portion connecting the lower end of the first primary member and the lower end of the second primary member so that the first primary group 110 and the second primary group 120 are interconnected to form one closed loop. a lower primary group 130 having a plurality of primary members and forming a plurality of lines below the first primary group 110 and the second primary group 120;
The upper end of the first primary member and the second primary group 130 interlock with each other so that a closed loop connecting the first primary group 110 and the second primary group 120 is formed. 2 Upper primary groups forming a plurality of lines above the first primary group 110 and the second primary group 120 by providing a plurality of upper primary members connecting the upper ends of the primary members ( 140);
to provide,
The secondary closed loop member 20,
a first secondary group 210 in which a plurality of first secondary members electrically insulated from the plurality of first primary members and sequentially alternating with each other are arranged in the first horizontal direction;
a plurality of second secondary members electrically insulated from the plurality of second primary members on the other side of the on-chip facing the first secondary group 210 and sequentially alternating with the plurality of second primary members, respectively; a second secondary group (220) in which members are disposed in the first horizontal direction;
The lower portion of the first secondary member and the lower portion of the second secondary member are connected so that the first secondary group 210 and the second secondary group 220 are interconnected to form one closed loop, and a plurality of lower fryers are connected. lower secondary groups 230 forming a plurality of lines below the first secondary group 210 and the second secondary group 220 by having a plurality of lower secondary members sequentially alternating with the head member;
The upper end of the first secondary member and the second secondary member are interlocked with the lower secondary group 230 to form a closed loop connecting the first secondary group 210 and the second secondary group 220. By providing a plurality of upper secondary members that connect the upper ends and sequentially alternate with the plurality of upper primary members, a plurality of lines are formed at the upper portions of the first secondary group 210 and the second secondary group 220. upper secondary group 240;
An on-chip transformer device comprising:
delete The method of claim 1,
The primary closed loop member 10,
A primary input/output terminal A member 150 disposed above the first primary member located at the outermost side of one side of the first primary group 110 and energizing the first primary member closest to its lower portion. );
The second primary member disposed above the second primary member corresponding to the outermost part of the second primary group 120 on the diagonal of the primary input/output terminal A member 150 and closest to the lower portion of the second primary member a primary input/output terminal B member 160 to conduct electricity to;
more provided,
The secondary closed loop member 20,
A first secondary located on the outermost side of one side of the first secondary group 210 but disposed above a first secondary member corresponding to the outside of the primary input/output terminal A member 150 and closest to its lower portion. a secondary input/output terminal A member 250 that energizes the member;
Located on the upper part of the second secondary member corresponding to the outermost part of the second secondary group 220 on the diagonal of the secondary input/output terminal A member 250, but corresponding to the outer side of the primary input/output terminal B member 160 a secondary input/output terminal B member 260 disposed above the second secondary member and energizing the second secondary member closest to its lower portion;
It further provides,
The upper primary group 140,
The upper primary member disposed between the primary input/output terminal A member 150 and the primary input/output terminal B member 160, the second primary member to which the primary input/output terminal B member 160 is connected One end thereof is connected to the first primary member at a position opposite to the first primary member, and the other end thereof is connected to the second primary member most adjacent to the second primary member to which the primary input/output terminal B member 160 is connected. A coil-type upper primary a-member 141 to which is connected;
The first upper primary member disposed between the primary input/output terminal A member 150 and the primary input/output terminal B member 160, to which one end of the coiled upper primary a member 141 is connected. A second primary having one end connected to the first primary member most adjacent to the primary member and most adjacent to the second primary member to which the other end of the coiled upper primary a-member 141 is connected. The connection pattern to which its other end is connected to the member is moved from the primary input/output terminal B member 160 toward the primary input/output terminal A member 150 from the coiled upper primary a member 141 by one space. At least one coil-type upper primary n member (142 to 144) disposed while doing;
to provide,
The upper secondary group 240,
The upper secondary member disposed between the secondary input/output terminal A member 250 and the secondary input/output terminal B member 260 at a position facing the second secondary member to which the secondary input/output terminal B member 260 is connected. A coil-type upper secondary member a having one end connected to the first secondary member and the other end connected to the second secondary member closest to the second secondary member to which the secondary input/output terminal B member 260 is connected. (241);
As the upper secondary member disposed between the secondary input/output terminal A member 250 and the secondary input/output terminal B member 260, one end of the coiled upper secondary a member 241 is connected to the first secondary member closest to the first secondary member. One end thereof is connected to an adjacent first secondary member, and the other end thereof is connected to a second secondary member most adjacent to a second secondary member to which the other end of the coiled upper secondary a-member 241 is connected. One or more coil-type upper secondary n members ( 242 to 244);
An on-chip transformer device comprising:
The method of claim 3,
The first primary member includes a plurality of layers formed with via holes for vertical conduction so as to mutually conduct the lower primary member corresponding to its vertically lower portion and the upper primary member corresponding to its vertical upper portion in the vertical direction. are placed overlapping with
In the first secondary member, a plurality of layers formed with via holes for vertical conduction are disposed overlapping each other in a vertical direction so as to conduct electricity between the lower secondary member corresponding to a vertical lower part of the first secondary member and the upper secondary member corresponding to a vertical upper part of the first secondary member. ,
The second primary member has a plurality of layers formed with via holes for vertical conduction so as to conduct electricity between the lower primary member corresponding to its vertically lower portion and the upper primary member corresponding to its vertical upper portion in the vertical direction. placed overlapping,
In the second secondary member, a plurality of layers formed with via holes for conduction in the vertical direction are overlapped in the vertical direction so as to conduct electricity between the lower secondary member corresponding to the vertical lower part and the upper secondary member corresponding to the upper secondary member. An on-chip transformer device, characterized in that.

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