KR102537974B1 - Electroluminescent Display - Google Patents

Abstract

The present invention provides an electroluminescent display device including a display panel, a data driver, a power supply, and a compensation circuit. The data driver drives the display panel. The power supply unit supplies a high potential voltage and a low potential voltage to the display panel. The compensation circuit unit receives feedback of the high potential voltage supplied to the display panel and controls the gamma voltage based on the feedback high potential voltage.

Description

Electroluminescent display device {Electroluminescent display}

The present invention relates to an electroluminescent display device.

As information technology develops, the market for display devices, which are communication media between users and information, is growing. Accordingly, the use of display devices such as an electroluminescent display, a liquid crystal display (LCD), and a plasma display panel (PDP) is increasing.

An electroluminescent display device, which is a part of the display devices described above, includes a display panel including a plurality of sub-pixels arranged in a matrix form or the like, and a driving unit for driving the display panel. The driver includes a scan driver for supplying scan signals (or gate signals) to the display panel and a data driver for supplying data signals to the display panel.

When a scan signal and a data signal are supplied to sub-pixels arranged in a matrix form, light is emitted from the selected sub-pixels, thereby displaying an image. Although electroluminescent display devices are currently being used in various fields of display devices, a compensation method capable of maintaining high display quality even on a large screen and high resolution is required.

The present invention to solve the problems of the background art described above is to improve the display quality by eliminating the difference in luminance on the display panel according to the fluctuation of the high potential voltage.

As a means for solving the above problems, the present invention provides an electroluminescent display device including a display panel, a data driver, a power supply unit, and a compensation circuit unit. The data driver drives the display panel. The power supply unit supplies a high potential voltage and a low potential voltage to the display panel. The compensation circuit unit receives feedback of the high potential voltage supplied to the display panel and controls the gamma voltage based on the feedback high potential voltage.

The compensation circuit unit may add or subtract the feedback high potential voltage to the gamma reference voltage or generate the gamma reference voltage using the feedback high potential voltage.

The data driver may include a gamma voltage generator that provides a gamma voltage, and the compensation circuit may output compensation voltages to be added to or subtracted from the low gamma reference voltage and the high gamma reference voltage based on the feedback high potential voltage.

The compensation circuit unit performs addition compensation by adding the compensation voltage to the gamma reference voltage when the feedbacked high potential voltage increases compared to the previous one, and performs subtraction compensation by subtracting the compensation voltage from the gamma reference voltage when the feedbacked high potential voltage is decreased compared to the previous one. can

The data driver may include a reference voltage generator for supplying a gamma reference voltage to the gamma voltage generator, and the reference voltage generator may generate the gamma reference voltage with a feedbacked high potential voltage supplied from the compensation circuit unit.

The data driver may include a compensation circuit, and the compensation circuit may add or subtract a feedback high potential voltage from the gamma reference voltage in response to an externally supplied selection signal or generate a gamma reference voltage using the feedback high potential voltage.

It includes a first circuit board on which the power supply unit is located, a second circuit board connected to the first circuit board, and a third circuit board on which the data driver unit is located, and the feedback high potential voltage is compensated through the first power supply feedback line. Applied to the circuit unit, the first power feedback line may be positioned on the display panel and the third circuit board, or may be positioned on the display panel, the second circuit board, and the third circuit board.

In another aspect, the present invention provides an electroluminescent display device including a display panel, a data driver, a power supply, and a compensation circuit. The data driver drives the display panel. The power supply unit supplies a high potential voltage and a low potential voltage to the display panel. The compensation circuit unit receives feedback from the high potential voltage supplied to the display panel and controls the high potential voltage to be supplied to the display panel based on the feedbacked high potential voltage.

The compensation circuit unit has a comparator having a non-inverting terminal connected to the first power line on one side connected to the output terminal of the power supply unit and an output terminal connected to the first power line on the other side connected to the display panel, and one end connected to the first power line on the other side connected to the display panel. A compensation capacitor, a first compensation resistor having one end connected to the other end of the compensation capacitor and the other end connected to the inverting terminal of the comparator, and a second compensation resistor having one end connected to the inverting terminal of the comparator and the other end connected to the output terminal of the comparator can do.

The comparator may be built inside the power supply unit, and the compensation capacitor, the first compensation resistor, and the second compensation resistor may be disposed outside the power supply unit.

The present invention has an effect of improving display quality by not only compensating the high potential voltage variation in real time, but also solving the problem of the difference in luminance between the top and bottom of the display panel. In addition, the present invention has an effect of solving the problem of color coordinates being distorted (color coordinate movement) during compensation as well as improving the response time (Response Time) performance value degradation phenomenon.

1 is a schematic block diagram of an organic light emitting display device according to a first embodiment of the present invention.
2 is a schematic configuration diagram of a sub-pixel shown in FIG. 1;
3 is an exemplary configuration diagram of an organic light emitting display device according to a comparative example;
4 and 5 are reference drawings for description related to voltage drop occurring in Comparative Example.
6 and 7 are diagrams showing arrangement examples of a first power line for high potential voltage feedback according to a first embodiment of the present invention.
8 and 9 are exemplary diagrams of main devices to which the first embodiment of the present invention can be applied.
10 is an exemplary view showing the internal configuration of the data driver shown in FIG. 9;
11 to 13 are exemplary diagrams showing an internal configuration of a data driver according to a first embodiment of the present invention.
14 is an exemplary configuration diagram of a voltage compensating circuit based on high potential voltage feedback according to a second embodiment of the present invention.
15 and 16 are diagrams showing an arrangement example of a voltage compensating circuit unit according to a second embodiment of the present invention.
17 is a diagram for explaining the operation of a voltage compensating circuit unit;
18 is a diagram for explaining an effect according to voltage compensation;

Hereinafter, specific details for the implementation of the present invention will be described with reference to the accompanying drawings.

The electroluminescent display device described below is applicable not only to organic light emitting display devices implemented based on organic light emitting diodes, but also to inorganic light emitting display devices implemented based on inorganic light emitting diodes. However, an organic light emitting display device will be described below as an example.

<First Embodiment>

1 is a schematic block diagram of an organic light emitting display device according to a first embodiment of the present invention, and FIG. 2 is a schematic configuration diagram of a subpixel shown in FIG. 1 .

As shown in FIG. 1 , the organic light emitting display device according to the first embodiment of the present invention includes a display panel 150, a timing controller 110, a data driver 120, a scan driver 140, and a power supply unit. (180).

The timing controller 110 supplies a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a data enable signal (Data Enable, DE), a clock signal (CLK), and a digital data signal (DDATA) from the outside. can receive The timing controller 110 uses signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a clock signal (CLK) to operate the data driver 120 and the scan driver. Operation timing of (140) can be controlled.

Since the timing controller 110 can determine the frame period by counting the data enable signal DE of one horizontal period, the vertical sync signal Vsync and the horizontal sync signal Hsync supplied from the outside can be omitted. The control signals generated by the timing controller 110 include a gate timing control signal (GDC) for controlling the operation timing of the scan driver 140 and a data timing control signal (DDC) for controlling the operation timing of the data driver 120. ), etc. are included. The timing controller 110 is mounted on a control board in the form of an integrated circuit (IC).

The data driver 120 converts the digital data signal DDATA supplied from the timing controller 110 into an analog data voltage ADATA in response to the data timing control signal DDC supplied from the timing controller 110. convert The data driver 120 outputs the converted data voltage ADATA through the data lines DL1 to DLn of the display panel 150 . The data driver 120 is mounted on a circuit board in the form of an IC or mounted on a non-display area of the display panel 150 .

The scan driver 140 generates a scan signal (or gate signal) capable of operating the transistors of the subpixels (SP) included in the display panel 150 in response to the gate timing control signal (GDC) supplied from the timing controller 110 . are generated sequentially. The scan driver 140 outputs scan signals through the scan lines SL1 to SLm of the display panel 150 . The scan driver 140 is mounted on a circuit board in the form of an IC or formed on the non-display area of the display panel 150 in the form of a gate in panel.

The power supply unit 180 outputs a high potential voltage ELVDD and a low potential voltage ELVSS. The high potential voltage ELVDD and the low potential voltage ELVSS output from the power supply unit 180 are supplied to the display panel 150 . The high potential voltage ELVDD is supplied through the first power line of the display panel 150 and the low potential voltage ELVSS is supplied through the second power line of the display panel 150 . The power supply 180 is mounted on a circuit board in the form of an IC or mounted on a control board.

The display panel 150 displays an image corresponding to the scan signal output from the scan driver 140 and the data voltage ADATA output from the data driver 120 . The display panel 150 is implemented as a top-emission method, a bottom-emission method, or a dual-emission method according to the structure of the sub-pixels SP. The display panel 150 is positioned between the lower substrate and the upper substrate and includes subpixels SP that emit light in response to a scan signal and a data voltage ADATA.

The subpixels SP include a red subpixel, a green subpixel, and a blue subpixel, or include a white subpixel, a red subpixel, a green subpixel, and a blue subpixel. The subpixels SP may have one or more different light emitting areas according to light emitting characteristics. The sub-pixels SP may convert white light generated from the organic light emitting diode into red, green, and blue light based on the color filter layer, but are not limited thereto.

As shown in FIG. 2, one sub-pixel operates in response to the data voltage ADATA supplied through the switching transistor TFT connected to the scan line SL1 and data line DL1 and the switching transistor TFT. A pixel circuit (PC) is included. The pixel circuit PC includes a driving transistor, a capacitor, an organic light emitting diode, and the like. The pixel circuit PC may include a compensation circuit for compensating for deterioration of at least one of the driving transistor and the organic light emitting diode. Since the compensation circuit has been proposed in various forms, a detailed description thereof will be omitted.

FIG. 3 is an exemplary configuration diagram of an organic light emitting display device according to a comparative example, and FIGS. 4 and 5 are reference views for description related to a voltage drop occurring in the comparative example.

As shown in FIG. 3 , the organic light emitting display device according to the comparative example may be divided into a module side and an application side (AP side). The application side (AP side) includes a power supply unit 180 and a first circuit board 111 . The power supply unit 180 is mounted on the first circuit board 111 . The module side includes a display panel 150 , a data driver 120 , a second circuit board 112 and a third circuit board 113 . The data driver 120 is mounted on the third circuit board 113 .

The first circuit board 111 , the second circuit board 112 , the third circuit board 113 and the display panel 150 are electrically connected. The first power line ELVDDL is positioned on the first circuit board 111 , the second circuit board 112 , the third circuit board 113 , and the display panel 150 . Meanwhile, second power lines are also located on the first circuit board 111, the second circuit board 112, the third circuit board 113, and the display panel 150, but they are not shown and omitted. The first power line ELVDDL is branched into two lines on the second circuit board 112 and the third circuit board 113 as an example, but is not limited thereto.

As shown in FIGS. 3 to 5, the high potential voltage is output from the power supply 180 disposed on the application side (AP side) and transmitted to the module side through the first power line ELVDDL. . That is, the first power line ELVDDL takes a long path (the length of the lead wire is long) to the first circuit board 111, the second circuit board 112, the third circuit board 113, and the display panel 150. will have

For this reason, on the side of the driving transistor DT, which needs to receive a high-potential voltage and generate a driving current within the sub-pixel SP, a voltage drop (IR Drop) due to an increase in resistance (Rdrop) according to the length of the wire, etc. will be affected Since the high potential voltage is applied from the side where the data driver 120 is disposed, high luminance is displayed at a location close to the data driver 120 on the display panel 150 , but low luminance is displayed at a location far away from the data driver 120 .

On the other hand, in the prior art, a number of algorithm-based compensation methods have been proposed in order to resolve fluctuations such as voltage drop occurring in a structure such as the comparative example. However, it has been reported that the conventionally proposed algorithm-based compensation method is difficult to compensate in real time due to time delay due to current calculation or gain application, and also causes problems such as color coordinates being distorted (color coordinate shift). The present invention proposes the following method to solve this problem.

6 and 7 are diagrams illustrating arrangement examples of a first power line for high potential voltage feedback according to a first embodiment of the present invention.

As shown in FIGS. 6 and 7 , the organic light emitting display device according to the first embodiment of the present invention can be divided into a module side and an application side (AP side). The application side (AP side) includes a power supply unit 180 and a first circuit board 111 . The power supply unit 180 is mounted on the first circuit board 111 . The module side includes a display panel 150 , a data driver 120 , a second circuit board 112 and a third circuit board 113 . The data driver 120 is mounted on the third circuit board 113 .

The first circuit board 111 , the second circuit board 112 , the third circuit board 113 and the display panel 150 are electrically connected. The first power line ELVDDL is positioned on the first circuit board 111 , the second circuit board 112 , the third circuit board 113 , and the display panel 150 . Meanwhile, second power lines are also located on the first circuit board 111, the second circuit board 112, the third circuit board 113, and the display panel 150, but they are not shown and omitted. The first power line ELVDDL is branched into two lines on the second circuit board 112 and the third circuit board 113 as an example, but is not limited thereto.

As shown in FIGS. 6 and 7 , in the first embodiment of the present invention, as in the comparative example, a high potential voltage is output from the power supply unit 180 disposed on the application side (AP side) and the first power line ELVDDL ) to the module side. That is, in the first embodiment of the present invention and in the same manner as in the comparative example, the first power line ELVDDL is connected to the first circuit board 111, the second circuit board 112, the third circuit board 113, and the display panel 150. ) as an example to have a long path. However, this is only one example, and the present invention is applicable even when the power supply unit 180 is mounted on the module side, which will be explained in the following description.

The first embodiment of the present invention includes a first power feedback line ELVDDL_FBL capable of feeding back (feedback) the high potential voltage applied to the display panel 150 to the data driver 120 . The first power feedback line ELVDDL_FBL is disposed on the third circuit board 113 and the display panel 150 as shown in FIG. 6 or is disposed on the second circuit board 112, the third circuit board 113 and It may be disposed on the display panel 150 .

In FIG. 6 , the first power feedback line (ELVDDL_FBL) is branched to one side and the other side with respect to the data driver 120 and is then connected to the data driver 120 as an example, but is not limited thereto. In addition, in FIG. 7 , the first power feedback line ELVDDL_FBL is branched as shown in FIG. 6 , but after the length is extended adjacent to the branch point of the first power supply line ELVDDL on the second circuit board 112, the data driver 120 ), but is not limited thereto.

The organic light emitting display device according to the first embodiment of the present invention feeds back the high potential voltage applied to the display panel to the data driver 120, and compensates the voltage variation on the display panel side based on the feedback high potential voltage. . Therefore, the data driver and related devices to which the first embodiment can be applied will be described. However, the data driver and related devices to which the first embodiment can be applied are not limited to the following description.

8 and 9 are exemplary diagrams of main devices to which the first embodiment of the present invention can be applied, FIG. 10 is an exemplary diagram showing the internal configuration of the data driver shown in FIG. 9, and FIGS. 11 to 13 are These diagrams show the internal configuration of the data driver according to the first embodiment of the present invention.

As shown in FIGS. 8 and 9 , the data driver 120 is based on the reference voltage output from the first reference voltage terminal RV1 and the nth reference voltage terminal RVn of the reference voltage generator 130. and a gamma voltage generator 125 that generates gamma voltage. The data driver 120 converts the digital data signal DDATA supplied from the timing controller 110 into an analog data voltage ADATA based on the gamma voltage and outputs it.

The reference voltage generator 130 generates and outputs a reference voltage based on a voltage supplied from the outside. The reference voltage generator 130 may be included inside the data driver 120 as shown in FIG. 8 or may be included outside the data driver 120 as shown in FIG. 9 .

9 and 10, the data driver 120 includes a shift register 121, a latch 123, a gamma voltage generator 125, a DA converter 127, and an output buffer 129. ), etc.

The data timing control signal (DDC) output from the timing controller 110 includes a source start pulse (Source, Start Pulse, SSP), a source sampling clock (SSC), a source output enable signal (Source Output Enable, SOE) ), etc. are included. The source start pulse SSP controls the data sampling start time of the data driver 120 . The source sampling clock SSC is a clock signal that controls a data sampling operation in the data driver 120 based on a rising or falling edge. The source output enable signal SOE controls the output of the data driver 120 .

The shift register unit 121 outputs a sampling signal (SAM) in response to the source start pulse (SSP) and the source sampling clock (SSC) output from the timing controller 110 . The latch unit 123 sequentially samples the digital data signal DDATA in response to a sampling signal (SAM) output from the shift register unit 121 and sequentially samples the digital data signal DDATA in response to the source output enable signal SOE. Outputs digital data signals (DDATA) for one line at the same time. The latch unit 123 may be composed of at least two, but only one has been shown and described for convenience of description.

The DA converter 127 converts the digital data signal DDATA for one line into an analog data signal ADATA in response to the first to nth gamma gradation voltages GMA1 to GMAn output from the gamma voltage generator 125. convert to The output buffer unit 129 amplifies (or amplifies and compensates for) the analog data signal ADATA output from the DA converter 127 and outputs it to each data line.

Referring to FIGS. 11 to 13 together with FIG. 10 , the data driver 120 receives feedback of the high potential voltage applied to the display panel through the first power feedback line ELVDDL_FBL. The data driver 120 includes components 161 and 163 capable of performing voltage compensation based on the feedbacked high potential voltage ELVDD_FB. The first embodiment of the present invention has a structure in which voltage compensation for voltage fluctuations is performed inside the data driver 120 .

11 to 13 are three types of device configuration examples for achieving the first embodiment of the present invention, and these are described in detail as follows. However, the resistor string unit 120 included inside the gamma voltage generator 125 and divides the voltage based on the reference voltage, and the gamma voltage (GMA; V0 to V255) based on the divided voltages. Since the generating unit 124 is a general component included in the data driving unit 120, only main features excluding them will be described in detail.

The first example shown in FIG. 11 is a compensation method that reflects the variation of the high potential voltage to the gamma reference voltage (GMA Ref.). To this end, the data driver 120 includes a voltage up/down compensation circuit unit 161 that outputs a compensation voltage to be added or subtracted from the gamma reference voltage (GMA Ref.) based on the high potential voltage fed back through the first power feedback line ELVDDL_FBL. includes

According to the first example, the first reference voltage terminal RV1 of the reference voltage generator 130 is the low gamma voltage terminal BRV1 (or low grayscale gamma voltage terminal) of the gamma voltage generator 125 , and the nth reference voltage terminal RVn is connected to the high gamma voltage terminal BRVn (or high grayscale gamma voltage terminal) of the gamma voltage generator 125 . As an example, the voltage increase/decrease compensation circuit unit 161 is positioned as a separate block. However, the voltage increase/decrease compensation circuit unit 161 is configured to indirectly increase/decrease the voltage for the reference voltages output from the first reference voltage terminal RV1 and the nth reference voltage terminal RVn of the reference voltage generator 130. It may be configured as a circuit and may be included in the reference voltage generator 130 .

For example, when the feedbacked high potential voltage is increased compared to the previous one, the voltage up/down compensation circuit unit 161 performs compensation (additional compensation) by adding the compensation voltage to the gamma reference voltage (GMA Ref.). In contrast, when the feedbacked high potential voltage is reduced compared to the previous one, the voltage up/down compensation circuit unit 161 performs compensation (subtraction compensation) by subtracting the compensation voltage from the gamma reference voltage (GMA Ref.).

As the voltage up/down compensation circuit unit 161 is added, the low gamma voltage terminal BRV1 and the high gamma voltage terminal BRVn of the gamma voltage generator 125 receive the reference voltage output from the reference voltage generator 130 as it is. Instead of being supplied, a reference voltage for which addition compensation or subtraction compensation is made is supplied. That is, the reference voltage generating unit 130 outputs the reference voltage in a normal manner. However, the reference voltage output from the reference voltage generation unit 130 is indirectly changed by the voltage adjustment circuit unit 161 .

For example, to the low gamma voltage terminal BRV1, the first reference voltage VREG1_REF1 ± the compensation voltage ELVDD_FB_BIN[c] composed of the feedbacked high potential voltage (c is a specific compensation voltage value of 0 to N shown in FIG. 11). Compensation voltage value) is supplied to the high gamma voltage terminal (BRVn), and the compensation voltage (ELVDD_FB_BIN[c] consisting of the nth reference voltage (VREG1_REF1023) ± the feedback high potential voltage (ELVDD_FB_BIN[c], c is 0 shown in FIG. 11) is supplied to the high gamma voltage terminal (BRVn). A specific compensation voltage value among compensation voltage values of ~N) is supplied. To this end, the voltage up/down compensation circuit unit 161 may change the analog high potential voltage ELVDD_FB supplied through the first power feedback line ELVDDL_FBL into a digital high potential voltage and then output the output, but is not limited thereto. don't

The second example shown in FIG. 12 is a compensation method that generates a gamma reference voltage (GMA Ref.) by reflecting the variation of the high potential voltage. To this end, the data driver 120 controls voltage for controlling generation of the gamma reference voltage (GMA Ref.) of the reference voltage generator 130 based on the high potential voltage fed back through the first power feedback line ELVDDL_FBL. Compensation circuit unit 163 is included.

According to the second example, the first reference voltage terminal RV1 of the reference voltage generator 130 is connected to the low gamma voltage terminal BRV1 (or low gradation voltage terminal) of the gamma voltage generator 125, The n reference voltage terminal RVn is connected to the high gamma voltage terminal BRVn (or high grayscale voltage terminal) of the gamma voltage generator 125 . As an example, the voltage control compensation circuit unit 163 is positioned as a separate block. However, the voltage control compensating circuit unit 163 is a separate circuit to directly increase or decrease the voltage for the reference voltage to be output from the first reference voltage terminal RV1 and the nth reference voltage terminal RVn of the reference voltage generator 130. It may be configured as, of course, may be included in the reference voltage generator 130.

As the voltage control compensating circuit unit 163 is added, the gamma voltage generator 125 receives a reference voltage generated as a result of the high potential voltage variation directly reflected from the reference voltage generator 130 . That is, the reference voltage output from the reference voltage generation unit 130 is not prepared based on an externally applied voltage, but based on a feedback high potential voltage (the feedback high potential voltage becomes a voltage source).

For example, the first reference voltage (VREG1_REF1 = ELVDD_FB + α) output from the reference voltage generator 130 is supplied to the low gamma voltage terminal BRV1, and the high gamma voltage terminal BRVn is supplied by the reference voltage generator 130. The nth reference voltage (VREG1023_REF1023 = ELVDD_FB + β) output from is supplied. However, since the first reference voltage and the n-th reference voltage are generated based on the first variation (ELVDD_FB ± α) and the second variation (ELVDD_FB ± β) of the feedback high potential voltage, the voltage variation of the display panel has already been compensated or compensated for. It corresponds to the offset reference voltage.

The third example shown in FIG. 13 has a structure including both the voltage increase/decrease compensation circuit unit 161 for performing the first example described above and the voltage control compensation circuit unit 163 for performing the second example.

According to the third example, the reference voltage is changed based on the voltage up/down compensation circuit unit 161 to reflect the variation of the high potential voltage, or based on the voltage control compensation circuit unit 163, the reference voltage is fed back to the high potential instead of the external voltage. It is possible to compensate or cancel the fluctuation of the high potential voltage by generating it based on the voltage.

The voltage adjustment circuit unit 161 and the voltage control compensation circuit unit 163 may perform a selective operation in response to the selection signal CN_110 supplied from the timing control unit. For example, when the selection signal CN_110 is applied at a logic high level, only the voltage control compensation circuit unit 161 may operate without the voltage control compensation circuit unit 163 operating. Conversely, when the selection signal CN_110 is applied as logic low, only the voltage control compensation circuit 163 may operate without the voltage increase/decrease compensation circuit unit 161 operating.

However, this is just one example, and if there is no need to actively vary operating conditions according to device characteristics, the selection signal line for transmitting the selection signal CN_110 may be fixed by connecting it to a specific voltage source.

As described above, the first embodiment of the present invention indirectly reflects the variation of the high potential voltage in the form of adding or subtracting to the reference voltage (first example) or directly reflects the variation of the high potential voltage. Create (second example) or implement a data driver to select and reflect one of both (first example and second example) described above (third example).

As described above, the first embodiment of the present invention changes the gamma voltage in various ways to compensate for voltage fluctuations such as a voltage drop of a high potential voltage based on a feedback line and a circuit rather than an algorithm. As a result, the first embodiment of the present invention can perform real-time compensation without a time delay (because there is no process such as current calculation or gain application) occurring in the algorithm method. In addition, the first embodiment of the present invention can compensate faster than the algorithm method, so it can solve the problem of color coordinates being distorted (color coordinate shift) during compensation as well as improving the phenomenon of response time performance value degradation. In addition, the first embodiment of the present invention can compensate for the fluctuation of the high potential voltage in real time and also solve the problem of the difference between the upper and lower luminance on the display panel, thereby improving the display quality.

<Second Embodiment>

14 is an exemplary configuration diagram of a voltage compensating circuit based on high potential voltage feedback according to the second embodiment of the present invention, and FIGS. 15 and 16 are arrangement examples of the voltage compensating circuit according to the second embodiment of the present invention. , FIG. 17 is a diagram for explaining the operation of the voltage compensation circuit unit, and FIG. 18 is a diagram for explaining the effect of voltage compensation.

As shown in FIG. 14, the second embodiment (FIG. 14 (b)) of the present invention is applied through the first power line (ELVDD) of the sub-pixel (SP) compared to the comparative example (FIG. 14 (a)). A voltage compensating circuit unit 160 is included to improve the effects of voltage fluctuations of the high potential voltage. In FIG. 14, "OLED" is an organic light emitting diode, "DT" is a driving transistor, and "Vdata" is a data voltage for operating the driving transistor.

In the organic light emitting display device according to the second embodiment of the present invention, the high potential voltage applied to the display panel is fed back to the voltage compensating circuit unit 160, and the variation on the display panel side is based on the feedback high potential voltage (ELVDD_FB). (An example of ELVDD drop due to Rdrop, which is a resistance component as a voltage drop, etc.) can be compensated for.

To this end, the voltage compensation circuit unit 160 includes a comparator CP, a first compensation resistor R1, a second compensation resistor R2, and a compensation capacitor Cc. Therefore, the first power feedback line and the voltage compensation circuit for applying the second embodiment will be described. However, the arrangement method of lines and circuits for applying the second embodiment is not limited to the following description.

In the first example shown in FIG. 15 , all components included in the voltage compensating circuit unit 160 are disposed on the second circuit board 112 . The first power line ELVDDL1 connected to the output terminal of the power supply unit 180 is connected to the non-inverting terminal (+) of the comparator CP, and the second circuit board 112, the third circuit board 113 and the display panel The first power line ELVDDL1 connected to 150 is connected to the output terminal of the comparator CP. That is, "ELVDDL1" is a power supply line to which a high potential voltage before compensation is delivered, and "ELVDD2" is a power supply line to which a high potential voltage is delivered after compensation.

One end of the first power feedback line ELVDDL_FBL is connected to the first power line ELVDDL of the display panel 150 and the other end is connected to one end of the compensation capacitor Cc. The first compensation resistor R1 has one end connected to the other end of the compensation capacitor Cc and the other end connected to the inverting terminal (-) of the comparator CP. The second compensating resistor R2 has one end connected to the inverting terminal (-) of the comparator CP and the other end connected to the output terminal of the comparator CP.

In the second example shown in FIG. 16, the high potential voltage applied to the display panel is fed back to the voltage compensating circuit unit 160 in the same manner as the configuration of the first example, and display is based on the feedback high potential voltage ELVDD_FB. Compensates for voltage fluctuations on the panel side. However, in the second example, the passive elements R1, R2, and Cc of the voltage compensating circuit unit 160 are disposed on the second circuit board 112, and the comparator CP is embedded inside the power supply unit 180. There is a difference compared to the first example. That is, the voltage compensation circuit unit 160 is divided into a first voltage compensation circuit unit 160a built into the power supply unit 180 and a second voltage compensation circuit unit 160b disposed outside the power supply unit 180. "ELVDDS" means a voltage source that generates a high potential voltage.

As the voltage compensating circuit unit 160 has the configuration shown in FIGS. 15 and 16 , it can compensate for a variation (eg, voltage drop, etc.) on the display panel side based on the feedbacked high potential voltage ELVDD_FB. The voltage compensating circuit unit 160 compares the high potential voltage before compensation applied to the non-inverting terminal (+) of the comparator CP with the feedbacked high potential voltage applied to the inverting terminal (-) of the comparator CP and outputs Through this, the high potential voltage is controlled to be output while maintaining a constant and uniform level.

As shown in FIG. 17, in the second embodiment of the present invention, the voltage drop (Vdrop) of the high potential voltage (ELVDD_FB) fed back according to the images (Black, White, Gray) displayed on the display panel appears in a different aspect. It can be seen that the voltage-compensated high potential voltage (EVDD') is output so as to cancel it even if it is. And for voltage compensation in this way, it can be designed as N = R2/R1. The voltage compensation scheme like the second embodiment is based on the following equation.

ELVDD' = ELVDD - R2/R1 ELVDD_FB

ELVDD' is the compensated high potential voltage applied to the display panel, ELVDD is the high potential voltage before compensation output from the voltage source, R1 is the resistance value of the first compensation resistor, R2 is the resistance value of the second compensation resistor, , ELVDD_FB is the high potential voltage fed back from the display panel.

Applying the voltage compensating circuit according to the second embodiment of the present invention as shown in FIG. 18(b) also solves the problem of the upper and lower luminance difference appearing on the display panel 150 before application as shown in FIG. 18(a). Therefore, the second embodiment of the present invention can compensate for the fluctuation of the high potential voltage in real time and also solve the problem of the difference between the upper and lower luminance on the display panel, thereby improving the display quality.

As described above, the present invention has an effect of improving display quality by not only compensating for the fluctuation of the high potential voltage in real time, but also solving the problem of the difference in luminance between the top and bottom of the display panel. In addition, the present invention has an effect of solving the problem of color coordinates being distorted (color coordinate movement) during compensation as well as improving the response time (Response Time) performance value deterioration phenomenon.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the technical configuration of the present invention described above can be changed into other specific forms by those skilled in the art without changing the technical spirit or essential features of the present invention. It will be appreciated that this can be implemented. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

150: display panel 120: data driving unit
161: voltage up/down compensation circuit part 163: voltage control compensation circuit part
160: voltage compensation circuit part ELVDDL: first power line
ELVDDL_FBL: 1st power feedback line

Claims (10)

display panel;
a data driver driving the display panel;
a power supply unit supplying a high potential voltage and a low potential voltage to the display panel; and
a compensation circuit unit receiving feedback from the high potential voltage supplied to the display panel and controlling a gamma voltage based on the feedbacked high potential voltage;
the data driver
a gamma voltage generator providing the gamma voltage;
The compensation circuit unit outputs a compensation voltage to be added or subtracted from the gamma reference voltage based on the feedback high potential voltage, and when the feedbacked high potential voltage increases compared to the previous one, performs addition compensation for adding the compensation voltage to the gamma reference voltage. , The electroluminescent display performs subtraction compensation in which a compensation voltage is subtracted from the gamma reference voltage when the feedback high potential voltage decreases compared to the previous one. delete delete delete According to claim 1,
the data driver
a reference voltage generator supplying the gamma reference voltage to the gamma voltage generator;
wherein the reference voltage generation unit generates the gamma reference voltage with the feedbacked high potential voltage supplied from the compensation circuit unit. display panel;
a data driver driving the display panel;
a power supply unit supplying a high potential voltage and a low potential voltage to the display panel; and
a compensation circuit unit receiving feedback from the high potential voltage supplied to the display panel and controlling a gamma voltage based on the feedbacked high potential voltage;
The data driver includes the compensation circuit,
The compensation circuit unit increases or subtracts the feedback high potential voltage from the gamma reference voltage in response to a selection signal supplied from the outside or generates the gamma reference voltage with the feedback high potential voltage. display panel;
a data driver driving the display panel;
a power supply unit supplying a high potential voltage and a low potential voltage to the display panel;
a compensation circuit unit receiving feedback from the high potential voltage supplied to the display panel and controlling a gamma voltage based on the feedbacked high potential voltage;
a first circuit board on which the power supply unit is located;
a second circuit board connected to the first circuit board; and
A third circuit board on which the data driver is located; includes,
The feedbacked high potential voltage is applied to the compensation circuit part through a first power feedback line,
The first power feedback line is positioned on the display panel and the third circuit board, or is positioned on the display panel, the second circuit board, and the third circuit board. display panel;
a data driver driving the display panel;
a power supply unit supplying a high potential voltage and a low potential voltage to the display panel; and
a compensation circuit unit receiving feedback from the high potential voltage supplied to the display panel and controlling the high potential voltage to be supplied to the display panel based on the feedbacked high potential voltage;
The compensation circuit part
A non-inverting terminal is connected to the first power line on one side connected to the output terminal of the power supply unit.
a comparator connected to and having an output terminal connected to a first power line on the other side connected to the display panel;
a compensation capacitor having one end connected to the first power line on the other side connected to the display panel;
A first compensation resistor having one end connected to the other end of the compensation capacitor and the other end connected to the inverting terminal of the comparator;
and a second compensation resistor having one end connected to the inverting terminal of the comparator and the other end connected to the output terminal of the comparator. delete According to claim 8,
The comparator is built into the power supply unit,
wherein the compensation capacitor, the first compensation resistor and the second compensation resistor are disposed outside the power supply unit.

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