KR102532090B1 - Z-inversion type display device - Google Patents

Abstract

The present invention relates to a display device that performs gate pulse modulation (GPM) according to an overlap area between a gate electrode and a source electrode in a Z-inversion method. In the display device of the Z-inversion method according to an embodiment of the present invention, in a display device in which pixels are formed according to the Z-inversion method, each pixel area defined by a gate line and a data line disposed crossing each other is provided. A pixel transistor including a pixel electrode, a gate electrode connected to the gate line, and a source/drain electrode connected to the pixel electrode, wherein the gate electrode and the source/drain electrode form a first overlapping region, the gate A dummy gate electrode formed on the same layer as the electrode and a dummy source/drain electrode formed on the same layer as the source/drain electrodes, wherein the dummy gate electrode and the dummy source/drain electrode form a second overlapping region. and a display driver modulating a gate pulse supplied to the gate line based on an output current of the dummy transistor that varies according to a width of the second overlap region.

Description

Z-inversion method display device {Z-INVERSION TYPE DISPLAY DEVICE}

The present invention relates to a display device that performs gate pulse modulation (GPM) according to an overlap area between a gate electrode and a source electrode in a Z-inversion method.

Recently, in driving a liquid crystal display (LCD), in order to prevent deterioration of liquid crystal in the liquid crystal display (LCD) and to improve display quality, an inversion type driving method is used. there is.

Existing inversion methods are classified into a frame inversion system, a line inversion system, a column inversion system, a dot inversion system, and the like.

Among the inversion methods, the frame inversion, line inversion, and column inversion methods have an advantage of low power consumption, but have a problem of image quality deterioration such as crosstalk or a difference in upper and lower luminance.

In addition, the dot inversion method can reduce the above-described picture quality degradation problem and provide excellent picture quality, but has a problem in that power consumption is too high.

In order to improve such an existing inversion method, a Z-inversion system has been proposed.

The Z-inversion method is a method of supplying data voltages to data lines in which transistors TFTs and pixel electrodes are alternately arranged left and right, in a column inversion method.

In other words, the Z-inversion method is an improved structure of the column inversion method. Basically, the circuit is driven according to the column inversion method, but the direction of the transistor (TFT) in the liquid crystal panel is reversed for each line, so that the dot It is a method of displaying the screen similar to the inversion method.

1 is a diagram showing the structure of a pixel electrode according to the conventional Z-inversion method, and FIG. 2 is a diagram showing the structure of a conventional gate electrode and a source electrode according to the Z-inversion method shown in FIG. 1 .

Referring to FIG. 1 , among a plurality of pixel electrodes PXL included in the display panel, pixel electrodes located in odd rows are connected to transistors formed in the left direction. Also, pixel electrodes located in even rows are connected to transistors formed in the right direction.

Accordingly, the channels of transistors positioned in odd-numbered rows are formed in the left direction, and the channels of transistors positioned in even-numbered rows are formed in the right direction.

Referring to FIG. 2(a) , in a normal state, drain electrodes (electrodes connected to pixel electrodes, not shown) of transistors provided in odd-numbered rows are positioned to the left of the source electrode S.

Also, in a normal state, drain electrodes of transistors provided in even-numbered rows are positioned to the right of the source electrode S.

On the other hand, the area where the source electrode S and the gate electrode G overlap form capacitance Cgs, which is provided in even and odd rows in a normal state, as shown in FIG. 2(a). The Cgs of the connected transistors are equal to each other.

Meanwhile, some errors may occur in the position of the source/drain electrodes due to process errors, etc. In this case, the area where the source electrode S and the gate electrode G overlap is different from the normal state.

Referring to (b) of FIG. 2 , when the source/drain electrodes are shifted by 1.8 μm in the left direction with respect to the gate electrode G, the area where the source electrode S and the gate electrode G overlap is in odd rows. increases and decreases in even-numbered rows.

In other words, compared to the normal state, Cgs of transistors included in odd-numbered rows increases and Cgs of transistors included in even-numbered rows decreases, so that Cgs of transistors included in even-numbered rows and odd-numbered rows are different from each other.

The voltage charged in the pixel (hereinafter referred to as charging voltage) is lowered by Cgs when the transistor is turned off, and the degree to which the charging voltage is lowered (kickback voltage) is determined according to the size of Cgs. Accordingly, as shown in (b) of FIG. 2 , when Cgs is different for each pixel electrode, the charging voltage of each pixel is different.

Since such an imbalance of kickback voltages causes flickering and horizontal line defects in the display device, a method for resolving the imbalance of kickback voltages has been studied.

FIG. 3 is a view showing a state in which a Cgs compensation pattern is added to the gate electrode shown in FIG. 2 .

Referring to FIG. 3 , a compensation pattern C may be formed on the gate electrode G to solve the imbalance of the kickback voltage described above. Accordingly, as shown in (b) of FIG. 3 , even when the source/drain electrodes are partially displaced from the gate electrode G, Cgs of the transistor can be maintained at the same level as the normal state.

However, according to the method using the compensation pattern as described above, there is a problem in that the aperture ratio of the pixel electrode is lowered by the compensation pattern (C) formed on the gate electrode (G).

Accordingly, there is a demand for a method capable of resolving the imbalance of the kickback voltage without lowering the aperture ratio.

An object of the present invention is to provide a Z-inversion type display device that performs a gate pulse modulation (GPM) operation according to an overlapping area between a gate electrode and a source electrode in the Z-inversion type.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention not mentioned above can be understood by the following description and will be more clearly understood by the examples of the present invention. It will also be readily apparent that the objects and advantages of the present invention may be realized by means of the instrumentalities and combinations indicated in the claims.

In order to achieve this object, a Z-inversion display device according to an embodiment of the present invention is a display device in which pixels are formed according to the Z-inversion method, and is defined by crossing gate lines and data lines. a pixel electrode provided in each pixel area, a gate electrode connected to the gate line, and a source/drain electrode connected to the pixel electrode, wherein the gate electrode and the source/drain electrode form a first overlapping area. A pixel transistor comprising: a dummy gate electrode formed on the same layer as the gate electrode, and dummy source/drain electrodes formed on the same layer as the source/drain electrodes, wherein the dummy gate electrode and the dummy source/drain electrodes are and a dummy transistor forming a second overlap region and a display driver modulating a gate pulse supplied to the gate line based on an output current of the dummy transistor that varies according to a width of the second overlap region. .

In addition, a display device of a Z-inversion method according to an embodiment of the present invention is a display device in which pixels are formed according to the Z-inversion method, and a pixel is defined by a plurality of gate lines and data lines that are intersecting. a display panel having pixel electrodes in respective regions; a data driver supplying data voltages to the pixel electrodes through the plurality of data lines; a gate driver supplying gate pulses to the pixel electrodes through the plurality of gate lines; a gate modulator configured to detect a current flowing in a dummy transistor formed on the same layer as a pixel transistor provided in a pixel area and to generate a gate pulse modulated signal based on the detected current, wherein the gate driver generates the gate pulse modulated signal It is characterized in that the gate pulse is modulated and supplied according to.

According to the present invention, a gate pulse modulation (GPM) operation is performed according to the overlapping area between the gate electrode and the source electrode in the Z-inversion method, so that a separate compensation pattern can be eliminated, thereby securing a design margin of the transistor. In addition, there is an effect of increasing the aperture ratio of the pixel.

In addition, the present invention modulates the gate pulse applied to the pixel electrode disposed in one row based on the gate pulse applied to the pixel electrode disposed in one row, thereby performing kickback of the pixel electrode disposed in each row. The voltage difference can be minimized, and accordingly, flickering of the display device and defects in horizontal lines can be prevented.

In addition, the present invention modulates the gate pulse by measuring the output current of the dummy transistor or modulates the gate pulse by receiving overlay information from the user, thereby providing constant gate pulse modulation (GPM) from the product design stage to the consumer use stage. There is an effect that can perform an action.

1 is a diagram showing the structure of a basic pixel electrode according to a Z-inversion method;
FIG. 2 is a diagram showing structures of a gate electrode and a source electrode according to the Z-inversion method shown in FIG. 1;
3 is a view showing a state in which a compensation pattern is added to the gate electrode shown in FIG. 2;
4 is a diagram illustrating a Z-inversion type display device according to an embodiment of the present invention.
FIG. 5 is a view for explaining the display panel shown in FIG. 4;
FIG. 6 is a diagram illustrating pixel transistors of pixel electrodes arranged in odd-numbered rows among the pixel electrodes shown in FIG. 5;
FIG. 7 is a diagram illustrating pixel transistors of pixel electrodes arranged in even-numbered rows among the pixel electrodes shown in FIG. 5;
8 is a diagram illustrating a dummy transistor including a second overlap region;
9 is a diagram showing an equivalent circuit of the dummy transistor shown in FIG. 8;
10 is a graph showing the relationship between output current and gate-source voltage of a dummy transistor.
11 is a diagram showing how the amplitude of a section in which a gate pulse is modulated is modulated low;
12 is a diagram showing how the width of a section in which a gate pulse is modulated is widely modulated;

The above objects, features and advantages will be described later in detail with reference to the accompanying drawings, and accordingly, those skilled in the art to which the present invention belongs will be able to easily implement the technical spirit of the present invention. In describing the present invention, if it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to indicate the same or similar components.

The present invention relates to a display device that performs gate pulse modulation (GPM) according to an overlap area between a gate electrode and a source electrode in a Z-inversion method.

In this specification, the present invention is described on the assumption that it is implemented in a liquid crystal display (LCD), but is not limited thereto, and may be implemented in any display device to which a Z-inversion method can be applied.

Hereinafter, referring to FIGS. 4 to 12 , a Z-inversion type display device according to an exemplary embodiment of the present invention will be described in detail.

FIG. 4 is a view showing a Z-inversion type display device according to an embodiment of the present invention, and FIG. 5 is a view for explaining the display panel shown in FIG. 4 .

FIG. 6 is a diagram illustrating pixel transistors of pixel electrodes disposed in odd rows among the pixel electrodes shown in FIG. 5 , and FIG. 7 illustrates pixel transistors of pixel electrodes disposed in even rows among the pixel electrodes shown in FIG. 5 . it is a drawing

FIG. 8 is a diagram illustrating a dummy transistor including a second overlap region, and FIG. 9 is a diagram illustrating an equivalent circuit of the dummy transistor illustrated in FIG. 8 .

10 is a graph illustrating a relationship between output current and gate-source voltage of a dummy transistor.

FIG. 11 is a diagram showing how the amplitude of a gate pulse modulated section is modulated low, and FIG. 12 is a diagram showing how the width of a gate pulse modulated section is modulated wide.

Referring to FIG. 4 , a Z-inversion type display device according to an embodiment of the present invention includes a display panel 10, display driving units 20, 30, and 40, a timing controller TC, and a main processor MP. can include Meanwhile, the display driver 20 , 30 , and 40 may include a data driver 20 , a gate driver 30 , and a gate modulator 40 . The Z-inversion display device shown in FIG. 4 is according to an embodiment, and its components are not limited to the embodiment shown in FIG. 4, and some components are added, changed, or deleted as necessary. It can be.

The display panel 10 may include a lower substrate, an upper substrate, and a liquid crystal layer interposed between the lower substrate and the upper substrate. A data line and a gate line, which will be described later, may be formed on a lower substrate of the display panel 10 .

The display panel 10 may be divided into a display area AA where an image is displayed and a non-display area NA where an image is not displayed.

First, referring to FIGS. 4 to 7 , the pixel electrode P and a method of driving the same will be described in detail.

Referring to FIG. 5 , the pixel electrode P may be provided in a pixel area defined by gate lines G1 to Gn and data lines D1 to Dm intersecting in the display area AA.

The pixel area is defined as an area where a plurality of gate lines G1 to Gn and a plurality of data lines D1 to Dm intersect, and may be formed in a matrix form within the display panel 10 .

Each pixel electrode P is provided in each pixel area, and is connected to one data line and one gate line to receive a data voltage and a gate pulse.

To this end, each pixel electrode P may be connected to a pixel transistor 50 provided at a point where the plurality of data lines D1 to Dm and the plurality of gate lines G1 to Gn cross each other in the pixel area. Here, the pixel transistors 50 may be alternately arranged on the left and right sides of the data lines D1 to Dm according to the Z-inversion method.

Accordingly, as shown in FIG. 5 , the pixel electrodes P positioned in odd rows are connected to the pixel transistors 50 formed in the left direction, and the pixel electrodes P positioned in even rows may be connected to a transistor formed in the right direction.

Meanwhile, the data driver 20 may supply data voltages to the pixel electrodes P through a plurality of data lines D1 to Dm, and the gate driver 30 may supply data voltages to the pixel electrodes P through a plurality of gate lines G1 to Gn. A gate pulse may be supplied to the electrode P.

When the pixel transistors 50 are turned on by the gate pulses applied to the gate lines G1 to Gn, the pixel electrodes P arranged in odd-numbered rows receive data voltages from the data lines D1 to Dm adjacent to the left. The pixel electrodes P disposed in the even rows may receive data voltages from the data lines D1 to Dm adjacent to the right.

The pixel electrode P may form an electric field according to a potential difference between the data voltage supplied through the pixel transistor 50 and the common voltage Vcom applied from a common electrode (not shown). Liquid crystal molecules provided in the liquid crystal layer of the display panel 10 can control the transmission amount of light by a corresponding electric field, and accordingly, a specific image can be displayed on the display panel 10 .

Referring to FIG. 4 , the above-described driving method of the pixel electrode P will be described in more detail. The main processor MP may transmit a plurality of timing signals together with digital video data RGB of an input image, for example, vertical A synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a main clock MCLK, and the like may be provided to the timing controller TC.

The timing controller TC may synchronize operation timings of the data driver 20 and the gate driver 30 . To this end, the timing controller TC may provide gate timing control signals such as a gate start pulse GSP, a gate shift clock GSC, and a gate output enable signal GOE to the gate driver 30 . In addition, the timing controller TC may provide data timing control signals such as a source sampling clock SSC, a polarity control signal POL, and a source output enable signal SOE to the data driver 20 .

Based on the aforementioned gate/data timing control signal, the gate driver 30 may sequentially supply gate pulses to the plurality of gate lines G1 to Gn, and the data driver 20 may sequentially supply a plurality of gate pulses to the plurality of data lines D1 to Dm. ) can be sequentially supplied with data voltages.

Next, the structure of each electrode constituting the pixel transistor 50 will be described in detail with reference to FIGS. 5 to 7 .

As described above, the plurality of pixel electrodes P shown in FIG. 5 may be divided into odd-numbered row pixel electrodes P and even-numbered row pixel electrodes P. Accordingly, the pixel transistors 50 may also be divided into odd-numbered row pixel transistors 50a and even-numbered row pixel transistors 50b.

The pixel transistor 50 may include a gate electrode G connected to the gate lines G1 to Gn and a source/drain electrode S/D connected to the pixel electrode P. Also, the pixel transistor 50 may further include a semiconductor layer (not shown) forming a channel between the source electrode and the drain electrode.

Referring to FIG. 6 , the channels of the pixel transistors 50a in odd-numbered rows may be formed in a left direction. Accordingly, in an example, in the pixel transistors 50a of odd-numbered rows, the drain electrode (an electrode connected to the pixel electrode P, not shown) may be positioned to the left of the source electrode.

Also, referring to FIG. 7 , the channels of the pixel transistors 50b in even-numbered rows may be formed in a rightward direction. Accordingly, in one example, the drain electrode of the pixel transistors 50b in even-numbered rows may be positioned to the right of the source electrode.

Positions of the source electrode and the drain electrode may be reversed. However, hereinafter, it will be described that the source/drain electrodes S/D of the pixel transistors 50a arranged in odd-numbered rows consist of a source electrode and a drain electrode positioned to the left of the source electrode. In addition, it will be described that the source/drain electrodes S/D of the pixel transistors 50b arranged in even rows are composed of a source electrode and a drain electrode positioned to the right of the source electrode.

Referring back to FIGS. 6 and 7 , the gate electrode G and the source/drain electrodes S/D may form a first overlap region.

The first overlap region may be defined as a region in which capacitance Cgs is formed between the gate electrode G and the source/drain electrodes S/D when the gate pulse applied to the gate electrode G falls. . Accordingly, in the structure described above, a region in which the source electrode and the gate electrode G overlap may be defined as the first overlap region.

The first overlapping area may be set to a preset width in a manufacturing process of the pixel transistor 50 . Also, in the normal state, the first overlap area may be designed to have the same width in odd-numbered rows and even-numbered rows.

However, in the process of forming the source/drain electrodes S/D, some errors may occur in the position of the source/drain electrodes S/D, and accordingly, the width of the first overlapping area is equal to the preset area. It can vary.

More specifically, when the source/drain electrodes S/D move to the left with respect to the gate electrode G, as described with reference to FIG. 2 , the first overlap area in odd-numbered rows may increase from a normal state. , and in even-numbered rows, the first overlap area may decrease from the normal state.

Meanwhile, as described above, the capacitance Cgs is formed in the first overlap region, and the voltage charged in the pixel electrode P may be reduced by the kickback voltage due to the capacitance Cgs.

When the first overlap area is different from the normal state, the kickback voltages of the pixel electrodes P disposed in odd and even rows are not the same, and the difference in kickback voltage may cause flickering and horizontal line defects. there is.

Hereinafter, a method of compensating for the above-described difference in kickback voltage will be described in detail with reference to FIGS. 4, 5, and 8 to 12 .

The Z-inversion type display device of the present invention may further include a dummy transistor 60 .

Referring to FIG. 8 , the dummy transistor 60 includes dummy gate electrodes D-G formed on the same layer as the gate electrode G of the pixel transistor 50 and source/drain electrodes S/D of the pixel transistor 50 . D) may include dummy source/drain electrodes D-S/D formed on the same layer.

The dummy transistor 60 may be provided in an arbitrary area within the display panel 10, but is preferably provided in the non-display area NA of the display panel 10 to prevent image distortion.

The dummy gate electrodes D-G of the dummy transistor 60 may be formed on the same layer as the gate electrode G of the pixel transistor 50 described above in the substrate array on which the display panel 10 is formed.

In addition, the dummy source/drain electrodes D-S/D of the dummy transistor 60 are the same as those of the aforementioned source/drain electrodes S/D of the pixel transistor 50 in the substrate array on which the display panel 10 is formed. can be formed in layers.

In this case, the dummy gate electrodes D-G and the dummy source/drain electrodes D-S/D may form a second overlapping region.

The second overlap region may be defined as a region in which dummy capacitance Cdgs is formed between the dummy gate electrodes D-G and the dummy source/drain electrodes D-S/D. For example, the second overlap region may be defined as a region where the dummy source electrode and the dummy gate electrodes D-G overlap, or may be defined as a region where the dummy drain electrode and the dummy gate electrode D-G overlap. However, in the following description, a region where the dummy drain electrode and the dummy gate electrodes D-G overlap is assumed to be the second overlap region.

The second overlapping area may be set to a preset width in the manufacturing process of the dummy transistor 60 . Meanwhile, the dummy gate electrodes D-G and the dummy source/drain electrodes D-S/D may have various shapes according to design needs. However, as will be described later, in order to increase the coupling effect by the second overlap region, the width of the second overlap region may be larger than that of the first overlap region.

As described above, the dummy gate electrodes D-G and the dummy source/drain electrodes D-S/D are on the same layer as the gate electrode G and the source/drain electrodes S/D of the pixel transistor 50, respectively. can be formed Accordingly, when the source/drain electrodes S/D of the pixel transistor 50 are moved relative to the gate electrode G, the dummy source/drain electrodes D-S/D of the dummy transistor 60 are also moved to the dummy gate. It can move based on the electrodes D-G.

More specifically, the amount of change in the position of the source/drain electrodes S/D with respect to the gate electrode G may be the same as the amount of change in the position of the dummy source/drain electrodes D-S/D with respect to the dummy gate electrodes D-G. .

Referring to FIG. 2 as an example, when the location of the source/drain electrodes S/D is shifted 1.8 μm to the left with respect to the gate electrode G, the dummy source/drain electrodes D-S/D shown in FIG. 8 The position of may also be shifted 1.8 μm to the left with respect to the dummy gate electrodes D-G.

In other words, when the dummy transistor 60 is formed to correspond to the pixel transistors 50a of odd-numbered rows as shown in FIG. 8 , when the first overlap area of the pixel transistor 50 increases, the dummy transistor 60 ) may also increase. Conversely, when the first overlap area of the pixel transistor 50 decreases, the second overlap area of the dummy transistor 60 may also decrease.

The display driver 20 , 30 , 40 may modulate the gate pulse supplied to the gate lines G1 to Gn based on the output current Is of the dummy transistor 60 that varies according to the width of the second overlap region. there is.

The display drivers 20, 30, and 40 include a data driver 20, a gate driver 30, and a gate modulator 40, and hereinafter, a gate modulator 40 and a gate driver for modulation of gate pulses ( 30) will be mainly explained.

The gate modulator 40 may supply power to the dummy transistor 60 , and the dummy transistor 60 may output a variable current according to the width of the second overlap region.

Referring to FIGS. 8 and 9 , the dummy transistor 60 formed as shown in FIG. 8 can be represented as an equivalent circuit as shown in FIG. 9 .

The dummy transistor 60 may be turned on according to coupling occurring in the second overlapping region and output a current according to the width of the second overlapping region.

To turn on the dummy transistor 60, the gate modulator 40 may supply the reference voltage Vref to the dummy drain electrode when the dummy gate electrodes D-G are in a floating state.

As shown in FIG. 9 , the first node N1 may be connected to the dummy drain electrode, and the second node N2 may be connected to the dummy gate electrodes D-G. The gate modulator 40 may be connected to the first node N1 and the dummy source electrode.

The gate modulator 40 may supply the reference voltage Vref to the first node N1 when the dummy gate electrodes D-G are in a floating state, that is, when the second node N2 is in a floating state.

In this case, a voltage proportional to the width of the second overlapping region may be supplied to the dummy gate electrodes D-G according to coupling occurring in the second overlapping region.

Referring back to FIGS. 8 and 9 , the second overlap region shown in FIG. 8 may be represented by the dummy capacitance Cdgs shown in FIG. 9 . Accordingly, the size of the dummy capacitance Cdgs may be proportional to the width of the second overlap region.

The reference voltage Vref applied to the first node N1 may be coupled to the second node N2 according to the size of the dummy capacitance Cdgs. Since this voltage coupling occurs in proportion to the size of the dummy capacitance Cdgs, the reference voltage Vref applied to the first node N1 is proportional to the size of the dummy capacitance Cdgs to the second node N2. can be coupled.

For example, the voltage of the second node N2 in a floating state before the reference voltage Vref is applied to the first node N1 may be 0 [V]. When the reference voltage Vref of 5 [V] is applied to the first node N1, a voltage between 0 and 5 [V] may be coupled to the second node N2 according to the size of the dummy capacitance Cdgs. there is.

When a certain voltage is coupled to the second node N2, the corresponding voltage is applied to the dummy gate electrodes D-G, and current is applied to the source electrode of the dummy transistor 60 according to the gate-source voltage Vgs formed at this time. can be output. The gate modulator 40 may detect the output current Is output in this way.

Referring to FIG. 10 , the output current Is output from the source electrode may be proportional to the gate-source voltage Vgs. Assuming that the source voltage is constant, the gate-source voltage (Vgs) is proportional to the area of the second overlap region, and consequently, the output current (Is) output from the source electrode may be proportional to the area of the second overlap region. there is.

The gate modulator 40 may detect the output current Is and modulate the gate pulse supplied to the gate lines G1 to Gn according to the magnitude of the output current Is.

In one example, the gate modulator 40 compares the magnitude of the output current Is and the reference current Iref to detect the current change ΔI, and based on the detected current change ΔI The gate pulse can be modulated.

Referring back to FIGS. 8 and 10 , in the normal state, the second overlap area may be set to a preset width. In other words, in a normal state, the dummy capacitance Cdgs may be determined as a specific value.

When the second overlap region has a preset width, when the reference voltage Vref is applied to the dummy drain electrode, a reference gate-source voltage Vgs-ref may be formed between the dummy gate electrode D-G and the dummy source electrode. . In this case, the current flowing through the dummy source electrode may be the reference current Iref, and information about the reference current Iref may be previously stored in the gate modulator 40 .

Meanwhile, as described above, the source/drain electrodes S/D of the pixel transistor 50 may move based on the gate electrode G. Accordingly, the dummy source/drain electrodes D-S/D of the dummy transistor 60 may also move relative to the dummy gate electrodes D-G, and accordingly, the width of the second overlapping region may be different from the normal state.

By changing the width of the second overlap region, the output current Is of the dummy transistor 60 becomes different from the reference current Iref (Iref -> Is1), and the gate modulator 40 responds to the reference current Iref. It is possible to detect the current change amount (ΔI) of the output current (Is) for the output current (Is).

For example, as described with reference to FIG. 2 , when the source/drain electrodes S/D of the pixel transistor 50 are deviated by 1.8 μm in the left direction with respect to the gate electrode G, the dummy transistor 60 is formed. The source/drain electrodes D-S/D may also shift leftward by 1.8 um with respect to the dummy gate electrodes D-G, and accordingly, the area of the second overlapping region may increase.

When the width of the second overlap region increases, when the reference voltage Vref is applied to the dummy drain electrode (first node N1), the voltage supplied to the dummy gate electrodes D-G increases, and accordingly, the gate- The source voltage Vgs may increase (Vgs-ref -> Vgs1) from the reference gate-source voltage Vgs-ref.

As the gate-source voltage (Vgs) increases, the output current (Is) flowing to the dummy source electrode increases from the reference current (Iref), and the gate modulator 40 detects the increased output current (Is1) to make a reference A current variation ΔI with respect to the current Iref may be detected.

The gate modulator 40 may modulate at least one of the amplitude and timing of the gate pulse based on the output current Is of the dummy transistor 60 .

The gate modulator 40 may basically perform a gate pulse modulation operation. More specifically, even in a normal state, the first overlap area may have a preset area, and a signal applied to the pixel electrode P may be affected by a kickback voltage caused by the first overlap area.

In order to minimize the effect of the kickback voltage, the gate modulator 40 may basically perform an operation of modulating the gate high voltage on at least one of a rising edge and a falling edge of the gate pulse.

In addition, the gate modulator 40 may perform an additional gate pulse modulation operation based on the output current Is of the dummy transistor 60 .

In an example, the gate modulator 40 may generate a gate pulse modulation signal Sm for modulating an amplitude of a gate pulse modulation section based on the output current Is of the dummy transistor 60 . .

More specifically, the gate modulator 40 may generate a signal for adjusting an amplitude of the gate pulse at at least one of a rising edge and a falling edge of the gate pulse. The corresponding signal may include information about a gate modulation voltage (VGPM), which is a voltage value of a modulated gate pulse.

In another example, the gate modulator 40 may generate a gate pulse modulation signal Sm for modulating the width of a section in which the gate pulse is modulated based on the output current Is of the dummy transistor 60 .

More specifically, the gate modulator 40 may generate a signal for adjusting a width of a section in which the gate pulse is modulated on at least one of a rising edge and a falling edge of the gate pulse. The corresponding signal may include information about the modulation period (M) of the modulated gate pulse.

The gate modulator 40 may identify the gate modulation voltage (VGPM) and the modulation period (M) of the gate pulse by referring to a look-up table.

More specifically, the gate modulator 40 includes information about the output current Is of the dummy transistor 60 or the gate modulation voltage VGPM corresponding to the change amount ΔI of the output current and the modulation period M. It can be stored in advance in the form of a lookup table. The gate modulator 40 may identify information about the gate modulation voltage VGPM or the modulation period M corresponding to the output current Is of the dummy transistor 60 by referring to the lookup table.

The aforementioned gate modulation voltage VGPM may be set in inverse proportion to the current flowing through the dummy transistor 60 . Accordingly, the gate modulator 40 may generate the gate pulse modulation signal Sm for modulating the amplitude of the gate pulse modulation section low in proportion to the current flowing through the dummy transistor 60 .

Also, the modulation period M of the gate pulse may be set in proportion to the current flowing through the dummy transistor 60 . Accordingly, the gate modulator 40 may generate a gate pulse modulation signal Sm that widely modulates the width of a section in which the gate pulse is modulated in proportion to the current flowing through the dummy transistor 60 .

Hereinafter, a method of modulating a gate pulse applied to a pixel electrode P in one row of the display panel 10 will be described in detail with reference to FIGS. 11 and 12 .

The gate modulator 40 modulates the gate pulse applied to the pixel electrode P disposed in the other row based on the gate pulse applied to the pixel electrode P disposed in any one of the odd and even rows. can

In one example, the gate modulator 40 may modulate gate pulses applied to pixel electrodes P in even rows based on gate pulses applied to pixel electrodes P in odd rows.

Referring to FIG. 11 , the gate modulator 40 may basically generate a modulation signal Sm for a gate pulse applied to all pixel electrodes P. Gate pulses applied to all pixel electrodes P according to the modulation signal Sm have modulation sections of M1 and M2 at rising and falling edges, respectively, and the amplitude of the gate pulses in the modulation section can be controlled by VGPM1. .

Then, when the output current Is of the dummy transistor 60 or the change amount ΔI of the output current is detected, the gate modulator 40 outputs an even number based on the gate pulses applied to the pixel electrodes P of the odd rows. Amplitudes of gate pulses applied to the pixel electrodes P of a row may be controlled.

In this case, a lookup table as shown in Table 1 below may be previously stored in the gate modulator 40 .

Is △I ODD VGPM EVEN VGPM I1 I1-Iref VGPM1 VGPM2 I2 I2-Iref VGPM1 VGPM3 I3 I3-Iref VGPM1 VGPM4 I4 I4-Iref VGPM1 VGPM5

When the detected output current Is is I1, the gate modulator 40 may identify the gate modulation voltage VGPM for the pixel electrode P of an even row as VGPM2 by referring to [Table 1]. A gate pulse modulation signal Sm including information on the identified gate modulation voltage VGPM may be generated.

As shown in FIG. 11 , the amplitude of the gate pulses applied to the pixel electrodes P of even-numbered rows according to the corresponding gate pulse modulation signal Sm may have an amplitude of VGPM2 in the modulation period.

In another example, the gate modulator 40 may include a pixel electrode disposed in another row based on a gate pulse applied to the pixel electrode P disposed in one row in which the first overlap area is reduced among odd and even rows. The gate pulse applied to P) can be modulated.

As shown in FIG. 2 , when the source/drain electrodes S/D of the pixel transistor 50 move in the left direction, the first overlap area of the pixel transistors 50a disposed in odd-numbered rows may increase. , the first overlap area of the pixel transistors 50b disposed in even-numbered rows may decrease.

At this time, the gate modulator 40 modulates the gate pulses applied to the pixel electrodes P in odd rows based on the gate pulses applied to the pixel electrodes P in even rows in which the first overlap area is reduced. ) can be controlled.

In this case, a lookup table as shown in [Table 2] below may be previously stored in the gate modulator 40.

Is △I ODD M EVEN M I1 I1-Iref M3/M4 M1/M2 I2 I2-Iref M5/M6 M1/M2 I3 I3-Iref M7/M8 M1/M2 I4 I4-Iref M9/M10 M1/M2

When the detected output current Is is I2, the gate modulator 40 sets the modulation period M of the rising edge and the falling edge of the pixel electrode P of the odd-numbered row to M5, respectively, referring to [Table 2]. And it can be identified as M6, and a gate pulse modulation signal (Sm) including information about the identified modulation section can be generated.

According to the corresponding gate pulse modulation signal Sm, the modulation period M of the gate pulses applied to the pixel electrodes P of odd-numbered rows is controlled to M5 at the rising edge and M6 at the falling edge, as shown in FIG. can

As described above, when the gate pulse applied to the pixel electrode P disposed in another row is modulated based on the gate pulse applied to the pixel electrode P disposed in one row in which the first overlap area is reduced. , there is an effect of lowering the kickback voltage for the pixel electrodes P of all rows.

Meanwhile, information about the gate modulation voltage VGPM and the modulation period M may be included in the gate pulse modulation signal Sm and provided to the timing controller TC.

The timing controller TC may control the gate signal output from the gate driver 30 based on the gate pulse modulation signal Sm.

For example, the timing controller TC may provide a gate timing control signal and power according to the gate pulse modulation signal Sm to the gate driver 30 . Accordingly, the gate driver 30 may output a gate pulse having a specific gate modulation voltage (VGPM) in a specific modulation period (M).

Meanwhile, the gate modulator 40 may receive overlay information from a user and generate a gate pulse modulation signal Sm corresponding to the input overlay information.

In other words, the gate modulator 40 may receive overlay information from the user and modulate the gate pulse without performing the above-described operation of detecting the output current Is of the dummy transistor 60 .

In the gate modulator 40, information on the gate modulation voltage VGPM and the modulation period M corresponding to each piece of overlay information may be stored in advance in the form of a lookup table. Accordingly, the gate modulator 40 may identify the gate modulation voltage VGPM and the modulation period M corresponding to the overlay information, and generate a gate pulse modulation signal Sm including the identified information.

The overlay information may include arbitrary information related to the capacitance Cgs formed by the gate electrode G and the source/drain electrodes S/D of the pixel transistor 50 . For example, the overlay information may include the Δposition of the source/drain electrodes S/D of the pixel transistor 50, the area of the first overlapping region, and the like.

At this time, in one example, the gate modulator 40 refers to the look-up table as shown in [Table 3] below, based on the gate pulses applied to the pixel electrodes P of odd rows, the pixel electrodes P of even rows. The gate pulse applied to may be modulated.

△position Area ODD VGPM EVEN VGPM ODD M EVEN M 0.5um 80um2 VGPM1 VGPM2 M1/M2 M3/M4 1um 85um2 VGPM1 VGPM3 M1/M2 M5/M6 1.5um 90um2 VGPM1 VGPM4 M1/M2 M7/M8 2.0um 95um2 VGPM1 VGPM5 M1/M2 M9/M10

For example, during the process of forming the pixel transistor 50, the user may measure the amount of change in the position of the source/drain electrodes (S/D) as 1.5 μm and input the amount of change in the position to the gate modulator 40. there is.

In one example, a user may modulate an amplitude or a modulation period M of gate pulses applied to pixel electrodes P in even rows based on gate pulses applied to pixel electrodes P in odd rows. The gate modulator 40 identifies the gate modulation voltage (VGPM) and the modulation period (M) for the amount of change in position (1.5 μm) input from the user as VGPM4 and M7/M8, respectively, with reference to [Table 3]. can

Accordingly, the gate modulator 40 modulates the amplitude in the modulation period M of the gate pulse applied to the pixel electrodes P of even-numbered rows to VGPM4, or modulates the modulation period at the rising edge and falling edge of the gate pulse. (M) can be modulated with M7 and M8, respectively.

Since the control of the gate pulse according to the gate modulation voltage VGPM and the modulation period M has been described above with reference to FIGS. 11 and 12, further detailed descriptions will be omitted.

As described above, the present invention can remove a separate compensation pattern by performing a gate pulse modulation (GPM) operation according to the overlapping area between the gate electrode and the source electrode in the Z-inversion method, and accordingly, transistor design It is possible to secure a margin and increase the aperture ratio of pixels.

In addition, the present invention modulates the gate pulse applied to the pixel electrode disposed in one row based on the gate pulse applied to the pixel electrode disposed in one row, thereby performing kickback of the pixel electrode disposed in each row. The voltage difference can be minimized, and thus flickering and horizontal line defects of the display device can be prevented.

In addition, the present invention modulates the gate pulse by measuring the output current of the dummy transistor or modulates the gate pulse by receiving overlay information from the user, thereby providing constant gate pulse modulation (GPM) from the product design stage to the consumer use stage. action can be performed.

The above-described present invention, since various substitutions, modifications, and changes are possible to those skilled in the art without departing from the technical spirit of the present invention, the above-described embodiments and accompanying drawings is not limited by

Claims (20)

In a display device in which pixels are formed according to the Z-inversion method,
pixel electrodes respectively provided in pixel regions defined by intersecting gate lines and data lines;
a pixel transistor including a gate electrode connected to the gate line and a source/drain electrode connected to the pixel electrode, wherein the gate electrode and the source/drain electrode form a first overlapping region;
a dummy gate electrode formed on the same layer as the gate electrode and dummy source/drain electrodes formed on the same layer as the source/drain electrodes, wherein the dummy gate electrode and the dummy source/drain electrodes form a second overlapping region; a dummy transistor forming a; and
a display driver modulating a gate pulse supplied to the gate line based on an output current of the dummy transistor that varies according to a width of the second overlap region;
The display driver in another row is based on a gate pulse applied to pixel electrodes disposed in either odd or even rows based on the amount of change in the output current of the dummy transistor, which varies according to the width of the second overlap region. Modulating at least one of a modulation voltage and a modulation period of a gate pulse applied to a pixel electrode disposed on
Z-inversion type display device.
According to claim 1,
Pixel electrodes arranged in odd-numbered rows receive data voltages from left adjacent data lines, and pixel electrodes arranged in even-numbered rows receive the data voltages from right adjacent data lines.
According to claim 1,
The Z-inversion type display device of
According to claim 1,
wherein the display driver supplies a reference voltage to a dummy drain electrode when the dummy gate electrode is in a floating state, and detects the output current flowing through the dummy source electrode.
According to claim 4,
A Z-inversion type display device wherein a voltage proportional to an area of the second overlapping area is supplied to the dummy gate electrode according to coupling occurring in the second overlapping area.
According to claim 1,
An output current of the dummy transistor is proportional to an area of the second overlap region.
According to claim 1,
The Z-inversion type display device according to claim 1 , wherein the display driver compares the magnitude of the output current with the magnitude of the reference current, detects a current change amount, and modulates the gate pulse based on the detected current change amount.
According to claim 1,
wherein the display driver modulates at least one of an amplitude and a timing of the gate pulse based on the output current of the dummy transistor.
delete According to claim 1,
The display driver modulates a gate pulse applied to a pixel electrode disposed in another row based on a gate pulse applied to a pixel electrode disposed in one row in which the first overlap area is decreased among odd and even rows, and modulates a Z- Inversion type display device.
According to claim 1,
The display driver of the Z-inversion method modulates the amplitude of the section in which the gate pulse is modulated.
According to claim 1,
The display driver of the Z-inversion method modulates a width of a section in which the gate pulse is modulated.
According to claim 1,
The pixel transistor is provided within the pixel area, and the dummy transistor is provided outside a display area including the pixel area.
In a display device in which pixels are formed according to the Z-inversion method,
A pixel electrode is provided in each pixel area defined by a plurality of gate lines and data lines that are intersecting, and a gate electrode connected to the gate line and a gate electrode connected to the pixel electrode form a first overlapping area with the gate electrode. A display panel including a pixel transistor including source/drain electrodes, and a dummy transistor including a dummy gate electrode in a floating state and a dummy source/drain electrode connected to a reference voltage source and forming a second overlapping region with the dummy gate electrode. ;
a data driver supplying a data voltage to the pixel electrode through the plurality of data lines;
a gate driver supplying a gate pulse to the pixel electrode through the plurality of gate lines; and
a gate modulator configured to detect a current flowing through the dummy transistor formed on the same layer as the pixel transistor provided in the pixel region, and to generate a gate pulse modulation signal based on the detected current;
The gate modulator in another row is based on a gate pulse applied to pixel electrodes disposed in any one of odd and even rows based on the amount of change in the output current of the dummy transistor, which varies according to the width of the second overlap region. modulates at least one of a modulation voltage and a modulation period of a gate pulse applied to a pixel electrode disposed on;
The gate driver modulates and supplies the gate pulse according to the gate pulse modulation signal.
delete According to claim 14,
The dummy transistor is turned on according to the coupling generated in the second overlap region to output current through the dummy source/drain electrodes.
According to claim 14,
The gate modulator generates a gate pulse modulation signal that modulates an amplitude of a section in which the gate pulse is modulated to be low in proportion to a current flowing through the dummy transistor.
According to claim 14,
wherein the gate modulator generates a gate pulse modulation signal that widely modulates a width of a section in which the gate pulse is modulated in proportion to a current flowing through the dummy transistor.
According to claim 14,
The Z-inversion type display device of claim 1 , wherein the gate modulator receives overlay information from a user and generates the gate pulse modulation signal corresponding to the input overlay information.
According to claim 19,
The overlay information includes a position change amount of a source/drain electrode of a pixel transistor and an area of a first overlapping region formed by a gate electrode of a pixel transistor and the source/drain electrode.

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