KR102531380B1 - 3D cross point memory device including interlevel connection structures and manufacturing method thereof - Google Patents

Abstract

First electrically conductive lines, first pillar structures, second electrically conductive lines, second pillar structures, third electrically conductive lines, third pillar structures, fourth electrically conductive lines, and fourth pillar Structures are formed over the substrate. Each pillar structure includes a memory element. Interconnection structures are formed on the first electrically conductive lines. The first electrically conductive lines can have thin segments located outside the area of the arrays of memory elements, and interconnection structures can be formed on the thin segments. Alternatively or additionally, the interconnection structures may include a vertical stack of first conductive via structures, conductive pad structures, and second conductive via structures in contact with respective first electrically conductive lines of the first electrically conductive lines. . Fifth electrically conductive lines may be formed on top surfaces of the second two-dimensional array of memory elements and on top surfaces of the interconnection structures.

Description

3D cross point memory device including interlevel connection structures and manufacturing method thereof

related application

This application claims the benefit of priority to U.S. Provisional Patent Application No. 16/410,326 and U.S. Provisional Patent Application No. 16/410,376, filed on May 13, 2019, the entire contents of which are incorporated herein by reference. do.

technology field

TECHNICAL FIELD [0002] The present invention relates generally to the field of semiconductor devices, and more particularly to three-dimensional cross-point memory devices including inter-level connection structures and methods of manufacturing the same.

A cross point array device is a device in which unit device elements are arranged as a two-dimensional array of a three-dimensional array and are accessed by selected pairs of access lines located at different levels. A cross point array device may be configured as a two dimensional array comprising two sets of access lines, or may be configured as a three dimensional array comprising three or more sets of access lines.

Each unit device element can be accessed by selection of an upper one of the access lines and a lower one of the access lines. Access lines are referred to as word lines or bit lines according to the configuration of peripheral devices connected to the access lines and according to the configuration of components within each unit device element. In the case of a three-dimensional cross point array device, the access lines at each odd-numbered level can be bit lines and the access lines at each even-numbered level can be word lines, or vice versa.

According to one embodiment of the present invention, there is provided a memory device, comprising: first electrically conductive lines, a two-dimensional array of first pillar structures, second electrically conductive lines, a two-dimensional array of second pillar structures A vertical stack comprising an array, third electrically conductive lines, a two-dimensional array of third pillar structures, fourth electrically conductive lines, a two-dimensional array of fourth pillar structures, and fifth electrically conductive lines - a first pillar structure each of the first pillar structures, the second pillar structures, the third pillar structures, and the fourth pillar structures include a respective memory element, and the two-dimensional array of first pillar structures comprises first electrically conductive lines having a first width. lying on top surfaces of the first parts; and interconnection structures providing electrically conductive paths between the fifth electrically conductive lines and the first electrically conductive lines, each of the interconnection structures having a second width smaller than the first width. in contact with the top surface of the second portion of the first electrically conductive line of the

According to another aspect of the present invention, a method of forming a memory device is provided, the method comprising forming first electrically conductive lines extending laterally along a first horizontal direction over a substrate - the first electrically conductive line. include first portions having a first width and second portions having a second width smaller than the first width; Over the two-dimensional array of first pillar structures, second electrically conductive lines, two-dimensional array of second pillar structures, third electrically conductive lines, two-dimensional array of third pillar structures, fourth electrically conductive lines, and Forming a vertical stack comprising a two-dimensional array of fourth pillar structures, each of the first pillar structures, the second pillar structures, the third pillar structures, and the fourth pillar structures including a respective memory element. Ham -; forming interconnection structures on top surfaces of the second portions of the first electrically conductive lines; and forming fifth electrically conductive lines on top surfaces of the two-dimensional array of fourth pillar structures and on top surfaces of the interconnection structures.

According to yet another aspect of the present invention, a memory device is provided, comprising: first electrically conductive lines, a two-dimensional array of first pillar structures, second electrically conductive lines, a two-dimensional array of second pillar structures A vertical stack comprising an array, third electrically conductive lines, a two-dimensional array of third pillar structures, fourth electrically conductive lines, a two-dimensional array of fourth pillar structures, and fifth electrically conductive lines - a first pillar structure s, the second pillar structures, the third pillar structures, and the fourth pillar structures each include a respective memory element; and interconnection structures providing electrically conductive pathways between the fifth electrically conductive lines and the first electrically conductive lines, each of the interconnection structures first contacting a respective first electrically conductive line of the first electrically conductive lines. a vertical stack of a first conductive via structure, a conductive pad structure in contact with a top surface of the first conductive via structure, and a second conductive via structure in contact with a respective fifth electrically conductive line of the conductive pad structure and the fifth electrically conductive lines; contains - contains

According to another aspect of the present invention, a method of forming a memory device is provided, the method comprising forming a vertical stack over a substrate, the vertical stack comprising first electrically conductive lines, a two-dimensional array of first pillar structures. , second electrically conductive lines, a two-dimensional array of second pillar structures, third electrically conductive lines, a two-dimensional array of third pillar structures, fourth electrically conductive lines, and a two-dimensional array of fourth pillar structures. wherein each of the first pillar structures, the second pillar structures, the third pillar structures, and the fourth pillar structures includes a respective memory element and is embedded within a respective dielectric material layer; forming interconnection structures through dielectric material layers embedding the first pillar structures, the second pillar structures, the third pillar structures, or the fourth pillar structures, each of the interconnection structures having a first electrically conductive a first conductive via structure in contact with a respective first electrically conductive line of the lines, a conductive pad structure in contact with a top surface of the first conductive via structure, and a respective fifth electrically conductive of the conductive pad structure and the fifth electrically conductive lines; a vertical stack of second conductive via structures in contact with the line; and forming fifth electrically conductive lines on the two-dimensional array of fourth pillar structures and interconnect structures.

1A shows a first layer stack including a first conductive material layer, a first selector layer, a first phase change memory layer, an optional first barrier layer, and a first hard mask layer, according to a first embodiment of the present invention. A vertical cross-section of the first exemplary structure after formation of
FIG. 1B is a vertical cross-sectional view of a first example structure along the vertical plane B-B′ of FIG. 1A.
FIG. 1C is a vertical cross-sectional view of a first example structure along vertical plane C-C′ of FIG. 1A.
1D is a plan view of the first example structure of FIGS. 1A-1C. The vertical plane A - A' is the plane of the vertical section of Figs. 1A to 1C. The vertical plane B - B' is the plane of the vertical section of Figs. 1A to 1C. The vertical plane C-C' is the plane of the vertical cross-section of Figs. 1A to 1C.
2A is a vertical cross-sectional view of a first exemplary structure after patterning a first hard mask layer into hard mask strips, in accordance with a first embodiment of the present invention.
FIG. 2B is a vertical cross-sectional view of the first example structure along the vertical plane B-B′ of FIG. 2A.
FIG. 2C is a vertical cross-sectional view of the first example structure along the vertical plane C-C′ of FIG. 2A.
2D is a plan view of the first example structure of FIGS. 2A-2C. The vertical plane A - A' is the plane of the vertical cross section of Figs. 2a to 2c. The vertical plane B - B' is the plane of the vertical section of Figs. 2a to 2c. The vertical plane C-C' is the plane of the vertical cross-section of Figs. 2a to 2c.
3A is a vertical cross-sectional view of a first example structure after covering first portions of hard mask strips with a layer of masking material and slimming second portions of hard mask strips, in accordance with a first embodiment of the present invention.
FIG. 3B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B′ of FIG. 3A.
3C is a vertical cross-sectional view of the first example structure along the vertical plane C-C′ of FIG. 3A.
3D is a plan view of the first exemplary structure of FIGS. 3A-3C. The vertical plane A - A' is the plane of the vertical cross-section of Figs. 3A to 3C. The vertical plane B - B' is the plane of the vertical section of Figs. 3a to 3c. The vertical plane C-C' is the plane of the vertical cross-section of Figs. 3a to 3c.
4A is a vertical cross-sectional view of a first exemplary structure after formation of first stacked rail structures laterally spaced by first trenches, in accordance with a first embodiment of the present invention.
FIG. 4B is a vertical cross-sectional view of the first example structure along the vertical plane B-B′ of FIG. 4A.
4C is a vertical cross-sectional view of the first example structure along the vertical plane C-C' of FIG. 4A.
4D is a plan view of the first exemplary structure of FIGS. 4A-4C. The vertical plane A - A' is the plane of the vertical cross-section of Figs. 4a to 4c. The vertical plane B - B' is the plane of the vertical section in Figs. 4a to 4c. The vertical plane C-C' is the plane of the vertical section of Figs. 4a to 4c.
5A is a vertical cross-sectional view of a first exemplary structure after formation of a two-dimensional rectangular array of first pillar structures, in accordance with a first embodiment of the present invention.
FIG. 5B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B′ of FIG. 5A.
5C is a vertical cross-sectional view of the first exemplary structure along the vertical plane C-C' of FIG. 5A.
5D is a plan view of the first exemplary structure of FIGS. 5A-5C. Vertical plane A - A' is the plane of the vertical cross-section of Figs. 5A to 5C. The vertical plane B - B' is the plane of the vertical cross-section of Figs. 5a to 5c. The vertical plane C-C' is the plane of the vertical cross-section of Figs. 5A to 5C.
6A is a vertical cross-sectional view of a first exemplary structure after formation of a first dielectric material layer, in accordance with a first embodiment of the present invention.
FIG. 6B is a vertical cross-sectional view of the first example structure along the vertical plane B-B′ of FIG. 6A.
6C is a vertical cross-sectional view of the first example structure along the vertical plane C-C' of FIG. 6A.
6D is a plan view of the first exemplary structure of FIGS. 6A-6C. The vertical plane A - A' is the plane of the vertical cross-section of Figs. 6A to 6C. The vertical plane B-B' is the plane of the vertical cross-section of Figs. 6a to 6c. The vertical plane C-C' is the plane of the vertical cross-section of Figs. 6A to 6C.
7A shows a second layer stack comprising a second conductive material layer, a second selector layer, a second phase change memory layer, an optional second barrier layer, and a second hard mask layer, according to a first embodiment of the present invention. A vertical cross-section of the first exemplary structure after formation of
FIG. 7B is a vertical cross-sectional view of the first example structure along the vertical plane B-B′ of FIG. 7A.
7C is a vertical cross-sectional view of the first example structure along the vertical plane C-C′ of FIG. 7A.
7D is a plan view of the first example structure of FIGS. 7A-7C. The vertical plane A - A' is the plane of the vertical cross-section of Figs. 7A to 7C. The vertical plane B-B' is the plane of the vertical section of Figs. 7a to 7c. The vertical plane C-C' is the plane of the vertical section of Figs. 7a to 7c.
8A is a vertical cross-sectional view of a first exemplary structure after formation of second electrically conductive lines, a two-dimensional rectangular array of second pillar structures, and a second dielectric material layer, in accordance with a first embodiment of the present invention.
FIG. 8B is a vertical cross-sectional view of the first example structure along the vertical plane B-B' of FIG. 8A.
8C is a vertical cross-sectional view of the first example structure along the vertical plane C-C′ of FIG. 8A.
8D is a plan view of the first example structure of FIGS. 8A-8C. The vertical plane A - A' is the plane of the vertical section of Figs. 8A to 8C. The vertical plane B - B' is the plane of the vertical section of Figs. 8A to 8C. The vertical plane C-C' is the plane of the vertical cross-section of Figs. 8A to 8C.
9A is a vertical cross-sectional view of a first exemplary structure after formation of first conductive via structures, in accordance with a first embodiment of the present invention.
FIG. 9B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B′ of FIG. 9A.
FIG. 9C is a vertical cross-sectional view of the first example structure along the vertical plane C-C′ of FIG. 9A.
9D is a plan view of the first example structure of FIGS. 9A-9C. Vertical plane A - A' is the plane of the vertical cross-section of Figs. 9A-9C. The vertical plane B-B' is the plane of the vertical cross-section of Figs. 9a to 9c. The vertical plane C-C' is the plane of the vertical cross-section of Figs. 9A-9C.
9E is a perspective view of a region including first conductive via structures within the first example structure of FIGS. 9A-9D.
Figure 9f is a schematic layout of the area of Figure 9e.
10A is a two-dimensional diagram of a third dielectric material layer, fourth electrically conductive lines, fourth pillar structure, a two-dimensional rectangular array of third electrically conductive lines, third pillar structures, according to a first embodiment of the present invention. A vertical cross-sectional view of the first example structure after formation of the array, the fourth layer of dielectric material, and the second conductive via structures.
FIG. 10B is a vertical cross-sectional view of the first example structure along the vertical plane B-B′ of FIG. 10A.
10C is a vertical cross-sectional view of the first example structure along the vertical plane C-C′ of FIG. 10A.
10D is a plan view of the first exemplary structure of FIGS. 10A-10C. Vertical plane A - A' is the plane of the vertical cross-section of Figs. 10A to 10C. The vertical plane B - B' is the plane of the vertical section in Figs. 10A to 10C. The vertical plane C - C' is the plane of the vertical section in Figs. 10A to 10C.
11A is a vertical cross-sectional view of a first exemplary structure after formation of fifth electrically conductive lines, according to a first embodiment of the present invention.
FIG. 11B is a vertical cross-sectional view of the first example structure along the vertical plane B-B′ of FIG. 11A.
11C is a vertical cross-sectional view of the first example structure along the vertical plane C-C′ of FIG. 11A.
11D is a plan view of the first exemplary structure of FIGS. 11A-11C. Vertical plane A - A' is the plane of the vertical cross-section of Figs. 11A to 11C. The vertical plane B - B' is the plane of the vertical section of Figs. 11A to 11C. The vertical plane C - C' is the plane of the vertical section of Figs. 11A to 11C.
12A shows a first layer stack including a first conductive material layer, a first selector layer, a first phase change memory layer, an optional first barrier layer, and a first hard mask layer, according to a second embodiment of the present invention. A vertical cross-section of the second example structure after formation of
FIG. 12B is a vertical cross-sectional view of a second example structure along the vertical plane B-B′ of FIG. 12A.
FIG. 12C is a vertical cross-sectional view of a second example structure along the vertical plane C-C′ of FIG. 12A.
12D is a plan view of the second exemplary structure of FIGS. 12A-12C. The vertical plane A - A' is the plane of the vertical cross-section of Figs. 12A to 12C. The vertical plane B-B' is the plane of the vertical cross-section of Figs. 12a to 12c. The vertical plane C-C' is the plane of the vertical cross-section of Figs. 12A to 12C.
13A is a vertical cross-sectional view of a second exemplary structure after formation of first stacked rail structures laterally spaced by first trenches, in accordance with a second embodiment of the present invention.
FIG. 13B is a vertical cross-section of a second example structure along the vertical plane B-B′ of FIG. 13A.
FIG. 13C is a vertical cross-sectional view of a second example structure along the vertical plane C-C′ of FIG. 13A.
13D is a plan view of the second exemplary structure of FIGS. 13A-13C. The vertical plane A - A' is the plane of the vertical cross-section of Figs. 13A to 13C. The vertical plane B-B' is the plane of the vertical cross-section of Figs. 13A to 13C. Vertical plane C-C' is the plane of the vertical cross-section of Figs. 13A-13C.
14A is a vertical cross-sectional view of a second exemplary structure after formation of a two-dimensional rectangular array of first pillar structures, in accordance with a second embodiment of the present invention.
FIG. 14B is a vertical cross-sectional view of a second example structure along the vertical plane B-B′ of FIG. 14A.
14C is a vertical cross-sectional view of a second example structure along the vertical plane C-C′ of FIG. 14A.
14D is a plan view of the second exemplary structure of FIGS. 14A-14C. Vertical plane A - A' is the plane of the vertical cross-section of Figs. 14A-14C. The vertical plane B-B' is the plane of the vertical cross-section of Figs. 14a to 14c. The vertical plane C-C' is the plane of the vertical cross-section of Figs. 14a to 14c.
15A is a vertical cross-sectional view of a second exemplary structure after formation of a first dielectric material layer, in accordance with a second embodiment of the present invention.
FIG. 15B is a vertical cross-section of a second example structure along the vertical plane B-B′ of FIG. 15A.
15C is a vertical cross-sectional view of a second example structure along the vertical plane C-C′ of FIG. 15A.
15D is a plan view of the second example structure of FIGS. 15A-15C. Vertical plane A - A' is the plane of the vertical cross-section of Figs. 15A-15C. The vertical plane B-B' is the plane of the vertical cross-section of Figs. 15A to 15C. The vertical plane C-C' is the plane of the vertical cross-section of Figs. 15A-15C.
16A is a second exemplary structure after formation of second electrically conductive lines, a two-dimensional array of second pillar structures, a second dielectric material layer, and first conductive via structures, in accordance with a second embodiment of the present invention; is a vertical section of
FIG. 16B is a vertical cross-sectional view of a second example structure along the vertical plane B-B′ of FIG. 16A.
16C is a vertical cross-sectional view of a second example structure along the vertical plane C-C′ of FIG. 16A.
16D is a plan view of the second exemplary structure of FIGS. 16A-16C. The vertical plane A - A' is the plane of the vertical cross-section of Figs. 16A to 16C. The vertical plane B-B' is the plane of the vertical cross-section of Figs. 16A to 16C. The vertical plane C-C' is the plane of the vertical section of Figs. 16A-16C.
17A illustrates formation of a layer stack including a third conductive material layer, a third selector layer, a third phase change memory layer, an optional third barrier layer, and a third hard mask layer, in accordance with a second embodiment of the present invention. Below is a vertical cross-section of the second exemplary structure.
FIG. 17B is a vertical cross-sectional view of a second example structure along the vertical plane B-B′ of FIG. 17A.
FIG. 17C is a vertical cross-sectional view of a second example structure along the vertical plane C-C′ of FIG. 17A.
17D is a plan view of the second exemplary structure of FIGS. 17A-17C. Vertical plane A - A' is the plane of the vertical cross-section of Figs. 17A-17C. The vertical plane B - B' is the plane of the vertical cross-section of Figs. 17A to 17C. Vertical plane C-C' is the plane of the vertical cross-section of Figs. 17A-17C.
18A is a vertical cross-sectional view of a second exemplary structure after patterning a third hard mask layer into hard mask strips and hard mask plates, in accordance with a second embodiment of the present invention.
FIG. 18B is a vertical cross-sectional view of a second example structure along the vertical plane B-B′ of FIG. 18A.
18C is a vertical cross-sectional view of a second example structure along the vertical plane C-C′ of FIG. 18A.
18D is a plan view of the second exemplary structure of FIGS. 18A-18C. Vertical plane A - A' is the plane of the vertical cross-section of Figs. 18A-18C. Vertical plane B - B' is the plane of the vertical cross-section of Figs. 18A-18C. Vertical plane C-C' is the plane of the vertical cross-section of FIGS. 18A-18C.
19A is a vertical cross-sectional view of a second exemplary structure after formation of first spacer material portions around hard mask strips and formation of second spacer material portions around hard mask plates, in accordance with a second embodiment of the present invention; am.
FIG. 19B is a vertical cross-sectional view of a second example structure along the vertical plane B-B′ of FIG. 19A.
19C is a vertical cross-sectional view of a second example structure along the vertical plane C-C′ of FIG. 19A.
19D is a plan view of the second exemplary structure of FIGS. 19A-19C. Vertical plane A - A' is the plane of the vertical cross-section of Figs. 19A-19C. The vertical plane B - B' is the plane of the vertical cross-section of Figs. 19A to 19C. Vertical plane C-C' is the plane of the vertical cross-section of FIGS. 19A-19C.
20A is a vertical cross-sectional view of a second exemplary structure after masking the second spacer material portions with a patterned photoresist layer and removing the second spacer material portions, in accordance with a second embodiment of the present invention.
FIG. 20B is a vertical cross-section of a second example structure along the vertical plane B-B′ of FIG. 20A.
FIG. 20C is a vertical cross-sectional view of a second example structure along vertical plane C-C′ of FIG. 20A.
20D is a plan view of the second example structure of FIGS. 20A-20C. Vertical plane A - A' is the plane of the vertical cross-section of Figs. 20A to 20C. The vertical plane B-B' is the plane of the vertical cross-section of Figs. 20A to 20C. The vertical plane C-C' is the plane of the vertical cross-section of Figs. 20A to 20C.
21A is a vertical cross-sectional view of a second example structure after removing the patterned photoresist layer, in accordance with a second embodiment of the present invention.
FIG. 21B is a vertical cross-sectional view of a second example structure along the vertical plane B-B′ of FIG. 21A.
FIG. 21C is a vertical cross-section of a second example structure along the vertical plane C-C′ of FIG. 21A.
21D is a plan view of the second exemplary structure of FIGS. 21A-21C. Vertical plane A - A' is the plane of the vertical cross-section of Figs. 21A to 21C. Vertical plane B - B' is the plane of the vertical cross-section of Figs. 21A to 21C. The vertical plane C-C' is the plane of the vertical cross-section of Figs. 21A to 21C.
22A is a vertical cross-sectional view of a second exemplary structure after formation of third electrically conductive lines and third stacked rail structures, in accordance with a second embodiment of the present invention.
FIG. 22B is a vertical cross-sectional view of a second exemplary structure along the vertical plane B-B′ of FIG. 22A.
22C is a vertical cross-sectional view of a second exemplary structure along the vertical plane C-C′ of FIG. 22A.
22D is a plan view of the second exemplary structure of FIGS. 22A-22C. The vertical plane A - A' is the plane of the vertical cross-section of Figs. 22A to 22C. The vertical plane B-B' is the plane of the vertical cross-section of Figs. 22A to 22C. Vertical plane C-C' is the plane of the vertical cross-section of FIGS. 22A-22C.
23A is a vertical cross-sectional view of a second exemplary structure after formation of a two-dimensional rectangular array of third pillar structures, in accordance with a second embodiment of the present invention.
FIG. 23B is a vertical cross-sectional view of a second exemplary structure along the vertical plane B-B′ of FIG. 23A.
23C is a vertical cross-sectional view of a second example structure along the vertical plane C-C' of FIG. 23A.
23D is a plan view of the second example structure of FIGS. 23A-23C. The vertical plane A - A' is the plane of the vertical cross-section of Figs. 23A to 23C. The vertical plane B - B' is the plane of the vertical cross-section of Figs. 23A to 23C. Vertical plane C-C' is the plane of the vertical cross-section of Figs. 23A-23C.
24A shows a second exemplary structure after formation of a third dielectric material layer, fourth electrically conductive lines, a two-dimensional array of fourth pillar structures, and a fourth dielectric material layer, according to a second embodiment of the present invention. is a vertical section of
FIG. 24B is a vertical cross-sectional view of a second example structure along the vertical plane B-B′ of FIG. 24A.
24C is a vertical cross-sectional view of a second example structure along the vertical plane C-C′ of FIG. 24A.
24D is a plan view of the second example structure of FIGS. 24A-24C. Vertical plane A - A' is the plane of the vertical cross-section of Figs. 24A-24C. The vertical plane B-B' is the plane of the vertical cross-section of Figs. 24A to 24C. Vertical plane C-C' is the plane of the vertical cross-section of FIGS. 24A-24C.
25A is a vertical cross-sectional view of a second exemplary structure after formation of second conductive via structures, in accordance with a second embodiment of the present invention.
FIG. 25B is a vertical cross-sectional view of a second example structure along the vertical plane B-B′ of FIG. 25A.
25C is a vertical cross-sectional view of a second example structure along the vertical plane C-C′ of FIG. 25A.
25D is a plan view of the second example structure of FIGS. 25A-25C. The vertical plane A - A' is the plane of the vertical cross-section of Figs. 25A to 25C. The vertical plane B - B' is the plane of the vertical cross-section of Figs. 25A to 25C. Vertical plane C-C' is the plane of the vertical cross-section of Figs. 25A-25C.
26A is a vertical cross-sectional view of a second exemplary structure after formation of fifth electrically conductive lines, in accordance with a second embodiment of the present invention.
FIG. 26B is a vertical cross-sectional view of a second example structure along the vertical plane B-B′ of FIG. 26A.
26C is a vertical cross-sectional view of a second example structure along the vertical plane C-C′ of FIG. 26A.
26D is a plan view of the second example structure of FIGS. 26A-26C. The vertical plane A - A' is the plane of the vertical cross-section of Figs. 26A to 26C. The vertical plane B-B' is the plane of the vertical cross-section of Figs. 26A to 26C. Vertical plane C-C' is the plane of the vertical cross-section of Figs. 26A-26C.

Since a unit device element within a three-dimensional cross point array device is accessed by a selected pair of access lines within vertical neighboring sets of access lines, activation of multiple bit lines located at different levels results in only one If a word line is activated, do not activate more than one unit device element. Likewise, activation of multiple word lines located at different levels does not activate more than one unit device element if only one bit line is activated. Therefore, the architecture of the three-dimensional cross point array device can be greatly simplified in case the bit lines of vertical neighboring pairs are connected together or in the case where the word lines of vertical neighboring pairs are connected together.

In physical hardware, interconnection between access lines spaced on two levels utilizes a vertical interconnection structure comprising two interconnection via structures spanning two device levels. However, the formation of such vertical interconnection structures is susceptible to electrical shorts, dielectric breakdown, and/or increased parasitic capacitance due to the fine pitch used to form the access lines. Typically, access lines are formed with a minimum lithographic pitch to increase device density. Thus, misalignment of interconnect via structures due to overlay deformations can cause various yield problems and reliability problems in a three-dimensional cross point array device.

In view of the above, embodiments of the present invention relate to three-dimensional cross point array memory devices including interlevel connection structures and methods of manufacturing the same, and various embodiments thereof are described below. Structures and methods of embodiments of the present invention provide reliable inter-level conductive paths spanning two device levels for a three-dimensional cross point array memory device.

The drawings are not drawn to scale. Multiple instances of an element may be redundant where a single instance of an element is shown unless the absence of overlapping of elements is explicitly stated or clearly indicated otherwise. Unless indicated otherwise, “contact” between elements refers to direct contact between elements providing an edge or surface shared by the elements. Ordinal numbers such as “first,” “second,” and “third” are only used to identify like elements, and different ordinal numbers may be used throughout the specification and claims of the invention. Like reference numerals designate like or similar elements. Unless otherwise indicated, elements having the same reference number are assumed to have the same material composition.

As used herein, “layer” refers to a portion of material that includes a region having a thickness. A layer may extend throughout the underlying or overlying structure, or may have an extent less than the extent of the underlying or overlying structure. A layer can also be a region of a continuous structure, homogeneous or heterogeneous, having a thickness less than the thickness of the continuous structure. For example, a layer may be positioned between any pair of horizontal planes on or between the top and bottom surfaces of the continuous structure. The layer may extend horizontally, vertically, and/or along a tapered surface. The substrate may be one layer, may include one or more layers therein, and/or may have one or more layers on, above, and/or below.

As used herein, “layer stack” refers to a stack of layers. As used herein, “line” or “line structure” refers to a layer having a predominant direction of extension, i.e., the direction in which the layer extends the most.

As used herein, “semiconductive material” refers to a material having an electrical conductivity in the range of 1.0×10 ⁻⁶ S/cm to 1.0×10 ⁵ S/cm. As used herein, “semiconductor material” refers to a material having an electrical conductivity, when no electrical dopant is present therein, in the range of 1.0×10 ⁻⁶ S/cm to 1.0×10 ⁵ S/cm, and Suitable doping with dopants can produce doped materials with electrical conductivities in the range of 1.0 S/cm to 1.0 x 10 ⁵ S/cm. As used herein, “electrical dopant” refers to a p-type dopant that adds a hole to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, “conductive material” refers to a material having an electrical conductivity greater than 1.0×10 ⁵ S/cm. As used herein, “insulator material” or “dielectric material” refers to a material having an electrical conductivity less than 1.0×10 ⁻⁶ S/cm. As used herein, “heavily doped semiconductor material” is a semiconductor material that is doped with an electrical dopant at a sufficiently high atomic concentration to be a conductive material, ie, to have an electrical conductivity greater than 1.0×10 ⁵ S/cm. refers to A “doped semiconductor material ^” may be a heavily doped semiconductor material, or an electrical ^dopant (ie, p -type dopant and/or n-type dopant). "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Accordingly, the semiconductor material may be semiconducting or conducting, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material may be semiconducting or conductive depending on the atomic concentration of electrical dopants therein. As used herein, “metallic material” refers to a conductive material that contains at least one metallic element therein. All measurements of electrical conductivity are made under standard conditions.

Referring to FIGS. 1A-1D , a first exemplary structure for forming a three-dimensional phase change memory device is shown, which includes a substrate 9 . Substrate 9 may include a semiconductor substrate, an insulating substrate, or a conductive substrate, and may have a thickness ranging from 60 micrometers to 1 mm, although smaller and larger thicknesses may also be used. In embodiments where substrate 9 comprises a semiconductor substrate, semiconductor devices 20 such as field effect transistors may be formed on the top surface of substrate 9 . In one embodiment, semiconductor device 20 may include peripheral circuitry configured to operate a three-dimensional array of memory elements that may be subsequently formed thereon. In one embodiment, base dielectric material layers 60 having metal interconnect structures 80 formed therein may be formed over the substrate 9 . For example, metallic interconnect structures 80 may include base level metallic line structures 82 and base level metallic via structures 84, which are connected to various nodes of semiconductor devices 20 below. can be connected to

A first material layer stack 12L, 14L, 16L, 17L, 175L, also referred to as a first layer stack or a first vertical stack, may be formed over the substrate 9 . As used herein, “material layer stack” refers to a layer stack comprising a plurality of material layers. The first material layer stack (12L, 14L, 16L, 17L, 175L) is configured to enhance memory elements, combinations of memory elements and selector elements, memory elements, selector elements, and possibilities of memory elements and/or selector elements. material layers to form a two-dimensional array of device components, which may be combinations of additional components for In general, the first material layer stack (12L, 14L, 16L, 17L, 175L) is any material stack that can be subsequently patterned into a two-dimensional array of pillar structures including memory elements and optional selector elements. can include The first material layer stack 12L, 14L, 16L, 17L, 175L includes phase change memory elements, magnetoresistive memory elements, ferromagnetic memory elements, resistive memory elements (eg, titanium oxide or nickel oxide memory elements). metallic oxide memory elements, such as memory elements) or any other type of memory elements that can be individually accessed in a cross point array configuration.

For example, the first material layer stack 12L, 14L, 16L, 17L, 175L may include a first conductive material layer 12L, a first selector layer 14L, a first phase change memory layer 16L, an optional second A first barrier layer 17L and a first hard mask layer 175L may be included. Each layer in the first material layer stack 12L, 14L, 16L, 17L, 175L is a blanket material layer, that is, a first horizontal direction hd1 and a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. ) can be formed as an unpatterned material layer extending laterally along .

The first conductive material layer 12L may include at least one conductive material layer, which may be at least one metallic material layer. For example, the first conductive material layer 12L may include, from bottom to top, a first metallic layer 122L (eg, a tungsten layer) and a first metallic nitride layer 124L (eg, a tungsten nitride layer or a titanium nitride layer). layers) of layer stacks. The thickness of the first metallic layer 122L may be in the range of 21 nm to 100 nm, such as 30 nm to 70 nm, although smaller and larger thicknesses may also be used. The thickness of the first metallic nitride layer 124L may be in the range of 1 nm to 10 nm, such as 1.5 nm to 5 nm, although smaller and larger thicknesses may also be used.

The first selector layer 14L may include a non-Ohmic material that provides electrical connection or electrical isolation depending on the magnitude and/or polarity of an externally applied voltage bias across it. In one embodiment, the first selector layer 14L includes at least one layer of critical switch material. At least one layer of threshold switch material may include an ovonic threshold switch (OTS) material or a diode threshold switch material (e.g., a p-n semiconductor diode, a p-i-n semiconductor diode, a Schottky diode, or a metal-insulator-metal diode). materials) that exhibit nonlinear electrical behavior, such as materials for a threshold switch. As used herein, an ovonic threshold switch (OTS) is a high-resistance state when not crystallized in a low-resistance state under a voltage above the threshold voltage and not subjected to a voltage above the threshold voltage across a layer of OTS material. It is a device that returns to As used herein, “ovonic threshold switch material” refers to a material that exhibits a non-linear resistivity curve under an applied external bias voltage that causes the resistivity of the material to decrease with the magnitude of the applied external bias voltage. In other words, the ovonic threshold switch material is non-ohmic and becomes more conductive under a higher external bias voltage than under a lower external bias voltage.

An ovonic threshold switch material (OTS material) can be amorphous (eg, amorphous) in a high-resistance state and can remain amorphous in a low-resistance state during application of a voltage above its threshold voltage across the OTS material. (eg, may remain in an amorphous state). The OTS material can revert back to its high-resistance state when the high voltage above its threshold voltage is removed. Throughout the resistive state changes, the ovonic threshold switch material may remain amorphous (eg, amorphous). In one embodiment, the ovonic threshold switch material may include a layer of chalcogenide material that exhibits hysteresis in both write and read states. The chalcogenide material may be a Ge-Se compound or a GeTe compound such as a Ge-Se-As compound semiconductor material doped with a dopant selected from As, N, and C. The ovonic threshold switch material layer may include a first ovonic threshold switch material layer 144L comprising any ovonic threshold switch material. In one embodiment, the first ovonic threshold switch material layer 144L may include and/or consist essentially of a GeSeAs compound, a GeSe compound, a SeAs compound, a GeTe compound, or a SiTe compound.

In one embodiment, the material of the first ovonic threshold switch material layer 144L is changed upon application of an external bias voltage that exceeds a threshold bias voltage magnitude (also referred to as threshold voltage). 144L) may be selected to reduce the resistivity by at least two orders of magnitude (ie, by more than a factor of 100). In one embodiment, the composition and thickness of the first ovonic threshold switch material layer 144L is such that the threshold bias voltage magnitude can be in the range of 1 V to 4 V, but smaller and higher voltages for the threshold bias voltage magnitude. may also be selected to be used. The thickness of the first ovonic threshold switch material layer 144L may be, for example, in the range of 5 nm to 50 nm, such as 10 nm to 30 nm, although smaller and larger thicknesses may also be used.

The first selector layer 14L comprises an optional first upper barrier material layer 146L overlying the first ovonic threshold switch material layer 144L and an optional first lower barrier material layer 146L overlying the first ovonic threshold switch material layer 144L. A barrier material layer 142L may be included. Optional first upper and/or lower barrier material layers 146L, 142L include a material that suppresses diffusion of the material of the first ovonic threshold switch material layer 144L. For example, the first upper and/or lower barrier material layers 146L and 142L may include amorphous carbon or diamond-like carbon (DLC). In one embodiment, the first upper barrier material layers 146L may include an upper amorphous carbon layer in contact with the top surface of the first ovonic threshold switch material layer 144L, and the first lower barrier material layer 142L ) may include a lower amorphous carbon layer in contact with the bottom surface of the first ovonic threshold switch material layer 144L. The thickness of the first upper barrier material layer 146L may be in the range of 4 nm to 40 nm, such as 8 nm to 21 nm, although smaller and larger thicknesses may also be used. The thickness of the first lower barrier material layer 142L may be in the range of 4 nm to 40 nm, such as 8 nm to 21 nm, although smaller and larger thicknesses may also be used.

The first phase change memory layer 16L may include a first phase change memory material layer 164L. The first phase change memory material layer 164L may include a phase change memory material. As used herein, “phase change memory material” refers to a material that has at least two different phases that provide different resistivities. At least two different phases can be provided, for example, by controlling the rate of cooling from a heated state to provide a higher high-resistivity amorphous state and a lower low-resistivity polycrystalline state. In this case, a higher high-resistivity state of the phase-change memory material can be achieved by faster quenching of the phase-change memory material after heating to an amorphous state, and a lower resistance of the phase-change memory material. -The resistivity state can be achieved by slower cooling of the phase change memory material after heating to an amorphous state.

Exemplary phase change memory materials include germanium antimony telluride compounds such as Ge2Sb2Te5 (GST), germanium antimony compounds, indium germanium telluride compounds, aluminum selenium telluride compounds, indium selenium telluride compounds, and aluminum indium selenium. Including, but not limited to, telluride compounds. These compounds (eg compound semiconductor material) may be doped (eg nitrogen doped GST) or undoped. Accordingly, the phase change memory material layer may include a germanium antimony telluride compound, a germanium antimony compound, an indium germanium telluride compound, an aluminum selenium telluride compound, an indium selenium telluride compound, or an aluminum indium selenium telluride compound, and/or may consist essentially of them. The thickness of the first phase change memory material layer 164L may be in the range of 1 nm to 60 nm, such as 3 nm to 40 nm and/or 10 nm to 25 nm, although smaller and larger thicknesses may also be used. there is.

The first phase change memory layer 16L may optionally include a first lower conductive liner layer 162L underlying the first phase change memory material layer 164L, and optionally, the first phase change memory material and a first top conductive liner layer 166L overlying layer 164L. Optional first lower conductive liner layer 162L and/or optional first upper conductive liner layer 166L, when present, include a conductive metallic material. In one embodiment, the first lower conductive liner layer 162L and/or the first upper conductive liner layer 166L may include a conductive metallic nitride, such as titanium nitride, tantalum nitride, or tungsten nitride. The thickness of each of the first lower conductive liner layer 162L and the first upper conductive liner layer 166L may be in the range of 1 nm to 10 nm, such as 1.5 nm to 5 nm, although smaller and larger thicknesses may also be used. can be used

An optional first barrier layer 17L, if present, includes a barrier material and may be formed on top of the first phase change memory layer 16L. The barrier material may be a material capable of preventing diffusion of the first phase change memory material and providing effective encapsulation thereof. In one embodiment, the barrier material can include and/or consist essentially of amorphous carbon. The thickness of the first barrier layer 17L may be in the range of 12 nm to 75 nm, such as 21 nm to 60 nm, although smaller and larger thicknesses may also be used.

The first hard mask layer 175L may include a hard mask material that may be used as a planarization stop structure in a subsequent planarization process. The first hard mask layer 175L may include a material selected from metal, dielectric material, or semiconductor material. For example, the first hard mask layer 175L may include silicon nitride, a dielectric metallic oxide, or a metal. In one embodiment, the first hard mask layer 175L may include silicon nitride. The thickness of the first hard mask layer 175L may be in the range of 3 nm to 30 nm, such as 6 nm to 15 nm, although smaller and larger thicknesses may also be used.

2A-2D, a first photoresist layer 177 may be applied over the first material layer stack 12L, 14L, 16L, 17L, 175L and lithographically patterned to form a line and space pattern. It can be. The first photoresist layer 177 may have a plurality of strip portions, which laterally extend along a first horizontal direction hd1 and a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. ) has a uniform pitch along. A uniform pitch may be in the range of 30 nm to 600 nm, for example. An anisotropic etch process may be performed to transfer the pattern of the first photoresist layer 177 through the first hard mask layer 175L. The first hard mask layer 175L may be patterned into first hard mask strips 175 . In one embodiment, the first photoresist layer 177 and/or the first hard mask strips 175 are patterned using any suitable double patterning method to obtain a finer pitch and/or strip width. can get angry The first hard mask strips 175 may laterally extend along the first horizontal direction hd1 and may have a uniform pitch along the second horizontal direction hd2. In one embodiment, the first hard mask strips 175 may have a uniform width along the second horizontal direction hd2, referred to herein as a first width w1. The first width w1 may be in the range of 15 nm to 300 nm, although smaller and larger dimensions may also be used. The first photoresist layer 177 may be subsequently removed, for example by ashing.

Referring to FIGS. 3A-3C , a layer of masking material 179 may be applied over the first exemplary structure and may be patterned to form end regions of a plurality of first hard mask strips 175 that are parallel to each other. there is. Masking material layer 179 may be, for example, a lithographically patterned photoresist layer. For example, first portions 1751 and third portions 1753 of each first hard mask strip 175 may be masked with masking material layer 179 while the first portion of the respective pair Second portions 1752 of each first hard mask strip 175 located between portion 1751 and third portions 1753 are not masked by masking material layer 179 .

An isotropic slimming process may be performed to etch back the physically exposed surface regions of the first hard mask strips 175 . For example, when the first hard mask strips 175 include silicon nitride or silicon oxide, a wet etch process using a mixture of hydrofluoric acid and glycerin or dilute hydrofluoric acid is used to The second portions 1752 of the fields 175 may be isotropically trimmed. The recess distance may be in the range of 2 nm to 150 nm. The second portions 1752 of the first hard mask strips 175 may have a second width w2 after the isotropic slimming process. The second width w2 may be in the range of 10 nm to 250 nm, such as 20 nm to 150 nm, although smaller and larger dimensions may also be used. The first hard mask strips 175 are patterned to include a neck region of a second portion 1752 having a second width w2 smaller than the first width w1. area. Masking material layer 179 may be removed, for example, by ashing.

Referring to FIGS. 4A to 4D , an anisotropic etch process may be performed using the first hard mask strips 175 as an etch mask. The anisotropic etch process includes an optional first barrier layer 17L, a first phase change memory layer 16L, a first selector layer 14L, and a first conductive layer that are not masked by the first hard mask strips 175. It may etch through portions of material layer 12L. The chemistry of the anisotropic etch process is carried out through portions of the selective first barrier layer 17L, the first phase change memory layer 16L, the first selector layer 14L, and the first conductive material layer 12L. It can be changed sequentially to etch sequentially. The anisotropic etch process may stop at or below the top surface of the base dielectric material layers 60 . The patterns of the hard mask strips 175 are selectively formed by an anisotropic etch process to form an optional first barrier layer 17L, a first phase change memory layer 16L, a first selector layer 14L, and a first conductive material layer 12L. ) is transcribed through the parts of First trenches 11 extending laterally along the first horizontal direction hd1 are formed by anisotropic etching. The first trenches 11 may have line trenches extending laterally along the first horizontal direction.

Remaining portions of the first material layer stack 12L, 14L, 16L, 17L, 175L include first stacked rail structures 150L and first electrically conductive lines 100, each of which has a first horizontal It extends laterally along the direction hd1. The first electrically conductive lines 100 include remaining patterned portions of the first metallic layer 122L. The first stacked rail structures 150L are laterally spaced apart by the first trenches 11 along the second horizontal direction hd2. As used herein, “rail” or “rail structure” refers to a structure that extends primarily along its length. As used herein, “stacked rails” or “stacked rail structure” refers to a stack of at least two rails extending laterally along the same longitudinal direction.

Each of the first stacked rail structures 150L includes, from bottom to top, the first selector rail 14', which is a patterned portion of the first selector layer 14L, and the first phase change memory layer 16L. The patterned portion of the first phase change memory rail 16' and the patterned portion of the first barrier layer 17L may include the first barrier rail 17'. As used herein, “strip” refers to a rail having a thickness less than its width. The first stacked rail structures 150L extend laterally along the first horizontal direction hd1, are laterally spaced apart from each other by first trenches 11, and are positioned over the substrate 9. .

In one embodiment, each first stacked rail structure 150L may include a first metallic nitride strip 124', which may be a patterned portion of the first metallic nitride layer 124L. In one embodiment, each first selector rail 14' includes a first lower barrier material strip 142', a first ovonic threshold switch material rail 144', and a first upper barrier material strip 146' ) may include a vertical stack of The first lower barrier material strip 142' is a patterned portion of the optional first lower barrier material layer 142L. The first ovonic threshold switch material rail 144' is a patterned portion of the first ovonic threshold switch material layer 144L. The first upper barrier material strip 146' is a patterned portion of the optional first upper barrier material layer 146L. In one embodiment, each first phase change memory rail 16' includes, from bottom to top, a first optional lower conductive liner strip 162', a first phase change memory material rail 164', and a first phase change memory material rail 164'. 1 optional upper conductive liner strip 166'. Each first lower conductive liner strip 162' is a patterned portion of the first lower conductive liner layer 162L, and each first phase change memory material rail 164' is a first phase change memory material layer. 164L, and each first top conductive liner strip 166' is a patterned portion of the first top conductive liner layer 166L. The first stacked rail structures 150L extend laterally along the first horizontal direction hd1 and are spaced laterally from each other by first trenches 11 over the base dielectric material layers 60 . do.

5A to 5D , another photoresist layer (not shown) may be applied over the first exemplary structure, an area including portions of first stacked rail structures 150L having a first width. It can be lithographically patterned into line and space patterns within fields. Each of the line and space patterns may extend laterally along the second horizontal direction hd2 and may be laterally spaced apart along the first horizontal direction hd1. The pitch of each line and space pattern may be in the range of 30 nm to 600 nm, although smaller and larger distances may also be used. The width of each line in the line and space pattern may be about half the pitch of the line and space pattern.

An anisotropic etch process may be performed to transfer the pattern of the photoresist layer through the hard mask strips 175 and the first stacked rail structures 150L. Each of the hard mask strips 175 may be patterned into hard mask segments 178 having a rectangular horizontal cross-sectional shape. The first stacked rail structures 150L are patterned into a two-dimensional rectangular array of first pillar structures 150 . Each of the first pillar structures 150 may have a rectangular horizontal cross-sectional shape. The first metallic nitride strips 124' may be patterned into first metallic nitride segments, or may function as an etch stop structure and remain as first metallic nitride strips 124'.

The chemistry of the anisotropic etch process can change the various materials of the hard mask strips 175, the first barrier rails 17', the first phase change memory rails 16', and the first selector rails 14'. through, and optionally through the first metallic nitride strips 124'. The anisotropic etch process may stop at or within the top surface of the first electrically conductive lines 100 or within the first metallic nitride strips 124'.

As used herein, “pillar” or “pillar structure” refers to a structure that extends along a vertical direction such that each sidewall of the structure is vertical or substantially vertical. As used herein, a sidewall is "substantially vertical" if the sidewall tapers, ie is tilted, with respect to the vertical direction by an inclination angle of less than 10 degrees. In the illustrative example, each first pillar structure 150 includes, from bottom to top, a first selector pillar 14, which is a patterned portion of a first selector rail 14', a phase change memory rail 16' ), and an optional first barrier segment 17 that is a patterned portion of the first barrier strip 17'.

Each first selector pillar is a selector element, that is, an element that provides non-linear voltage-current characteristics to function as a conductor under first voltage bias conditions and as an insulator under second voltage bias conditions. In one embodiment, each first selector pillar 14 comprises a first lower barrier material portion 142, which is a patterned portion of a first lower barrier material strip 142', a first ovonic threshold switch material rail ( A vertical stack of first ovonic threshold switch material portion 144, which is the patterned portion of 144'), and first upper barrier material portion 146, which is the patterned portion of first upper barrier material strip 146'. can include

In one embodiment, each first selector pillar 14 is a first ovonic threshold switch material portion 144, a top of the first ovonic threshold switch material portion 144 as a first upper barrier material portion 146. An upper amorphous carbon portion in contact with the surface, and a lower amorphous carbon portion in contact with the bottom surface of the first ovonic threshold switch material portion 144 as the first lower barrier material portion 142 .

Each of the first phase change pillars 16 may be a phase change memory element, that is, a structure that changes resistance according to a phase of an internal material. In one embodiment, each first phase change pillar 16 is an optional first lower conductive liner segment 162 that is a patterned portion of a first optional lower conductive liner strip 162', a first phase change memory material A first phase change memory material pillar 164, which is a patterned portion of a rail 164', and a first optional top conductive liner segment 166, which is a patterned portion of a first top conductive liner strip 166'. Can include vertical stacks. The photoresist layer may be removed, for example by ashing.

Alternatively, the two-dimensional array of first pillar structures 150 may include a first two-dimensional array of memory elements. A first two-dimensional array of memory elements may be formed on top surfaces of first and third portions of the first electrically conductive lines 100 having a first width w1 . Top surfaces of the second portions of the first electrically conductive lines 100 may be physically exposed.

Referring to FIGS. 6A-6D , a first dielectric material may be deposited over the example structure and planarized using the top surfaces of the first pillar structures 150 as stop surfaces. For example, (in case the first barrier segments 17 are not used) a first layer lying on a horizontal plane comprising the top surfaces of the optional first barrier segments 17 or the first phase change pillars 16. Excess portions of the first layer of dielectric material may be removed by a planarization process, which may use a recess etch process and/or a chemical mechanical planarization process. Hard mask segments 178 may be removed in parallel during the planarization process. The remaining continuous portion of the first dielectric material constitutes the first dielectric material layer 160 . The first dielectric material layer 160 may include undoped silicate glass, doped silicate glass, or spin-on glass. A dielectric liner (not shown) may optionally be deposited prior to deposition of the first dielectric material. The first dielectric material layer 160 can be formed around the first two-dimensional array of memory elements and can fill gaps between the memory elements of the first two-dimensional array. Peripheral contact via structures 182 may optionally be formed through first dielectric material layer 160 .

Referring to FIGS. 7A-7D , a second material layer stack (22L, 24L, 26L, 27L, 275L), also referred to as a second layer stack or a second vertical stack, comprises a first dielectric material layer 160 and a first It may be formed over a two-dimensional array of pillar structures 150 . For example, the second material layer stack 22L, 24L, 26L, 27L, 275L may include a second conductive material layer 22L, a second selector layer 24L, a second phase change memory layer 26L, and an optional second material layer 22L. A second barrier layer 27L and a second hard mask layer 275L may be included. Each layer in the second material layer stack 22L, 24L, 26L, 27L, 275L is a blanket material layer, that is, a second horizontal direction hd1 and a second horizontal direction hd2 perpendicular to the second horizontal direction hd1. ) can be formed as an unpatterned material layer extending laterally along .

The second conductive material layer 22L may include at least one conductive material layer, which may be at least one metallic material layer. For example, the second conductive material layer 22L may include, from bottom to top, a second metallic layer 222L (eg, a tungsten layer) and a second metallic nitride layer 224L (eg, a tungsten nitride layer or a titanium nitride layer). layers) of layer stacks. The thickness of the second metallic layer 222L may be in the range of 21 nm to 100 nm, such as 30 nm to 70 nm, although smaller and larger thicknesses may also be used. The thickness of the second metallic nitride layer 224L may be in the range of 1 nm to 10 nm, such as 1.5 nm to 5 nm, although smaller and larger thicknesses may also be used. In another embodiment, the second conductive material layer 22L is used for process feasibility and/or smaller variations in contact between portions of the second conductive material layer 22L and underlying and overlying memory material layers. , two separate metallic material layers formed during separate deposition and patterning steps, e.g., a first tungsten layer patterned into the underlying layers of first pillar structures 150, and the first tungsten layer and the first pillar structure. and a second tungsten layer deposited on the first tungsten layer after patterning them.

The second selector layer 24L includes a non-ohmic material that provides an electrically isolated electrical connection depending on the magnitude and/or polarity of an externally applied voltage bias across it. In one embodiment, the second selector layer 24L includes at least one threshold switch material layer, such as an ovonic threshold switch material layer. The ovonic threshold switch material layer may include a second ovonic threshold switch material layer 244L comprising any ovonic threshold switch material. In one embodiment, the second ovonic threshold switch material layer 244L may include and/or consist essentially of a GeSeAs compound, a GeSe compound, a SeAs compound, a GeTe compound, or a SiTe compound.

In one embodiment, the material of the second ovonic threshold switch material layer 244L upon application of an external bias voltage that exceeds a threshold bias voltage magnitude (also referred to as the threshold voltage), the second ovonic threshold switch material layer (244L) 244L) may be selected to reduce the resistivity of at least two orders of magnitude (ie, by more than a factor of 100). In one embodiment, the composition and thickness of the second ovonic threshold switch material layer 244L is such that the threshold bias voltage magnitude is within the range of 1 V to 4 V, but smaller and larger voltages for the threshold bias voltage magnitude are also possible. can be selected for use. The thickness of the second ovonic threshold switch material layer 244L may be, for example, in the range of 5 nm to 50 nm, such as 10 nm to 30 nm, although smaller and larger thicknesses may also be used.

The second selector layer 24L includes an optional second upper barrier material layer 246L overlying the second ovonic threshold switch material layer 244L and an optional second lower barrier material layer 246L overlying the second ovonic threshold switch material layer 244L. A barrier material layer 242L may be included. Optional second upper and/or lower barrier material layers 246L, 242L include a material that suppresses diffusion of the material of the second ovonic threshold switch material layer 244L. For example, the second upper and/or lower barrier material layers 246L and 242L may include amorphous carbon or diamond-like carbon (DLC). The thickness of the second upper barrier metallic nitride layer 246L may be in the range of 4 nm to 40 nm, such as 8 nm to 21 nm, although smaller and larger thicknesses may also be used. The thickness of the second lower barrier material layer 242L may be in the range of 4 nm to 40 nm, such as 8 nm to 21 nm, although smaller and larger thicknesses may also be used.

The second phase change memory layer 26L includes a second phase change memory material layer 264L. The second phase change memory material layer 264L includes phase change memory material. The thickness of the second phase change memory material layer 264L may be in the range of 1 nm to 60 nm, such as 3 nm to 40 nm and/or 10 nm to 25 nm, although smaller and larger thicknesses may also be used. there is.

The second phase change memory layer 26L may optionally include a second lower conductive liner layer 262L underlying the second phase change memory material layer 264L, and optionally, the second phase change memory material and a second top conductive liner layer 266L overlying layer 264L. The optional second lower conductive liner layer 262L and/or the optional second upper conductive liner layer 266L, when present, include a conductive metallic material. In one embodiment, the second lower conductive liner layer 262L and/or the second upper conductive liner layer 266L may include a conductive metallic nitride, such as titanium nitride, tantalum nitride, or tungsten nitride. The thickness of each of the second lower conductive liner layer 262L and the second upper conductive liner layer 266L may be in the range of 1 nm to 10 nm, such as 1.5 nm to 5 nm, although smaller and larger thicknesses may also be used. can be used

An optional second barrier layer 27L, if present, includes a barrier material and may be formed on top of the second phase change memory layer 26L. The barrier material is a material that can prevent diffusion of the second phase change memory material and can provide effective encapsulation thereof. In one embodiment, the barrier material can include and/or consist essentially of amorphous carbon. The thickness of the second barrier layer 27L may be in the range of 12 nm to 75 nm, such as 21 nm to 60 nm, although smaller and larger thicknesses may also be used.

The second hard mask layer 275L includes a hard mask material that can be used as a planarization stop structure in a subsequent planarization process. The second hard mask layer 275L may include a material selected from metal, dielectric material, or semiconductor material. For example, the second hard mask layer 275L may include silicon nitride, a dielectric metallic oxide, or a metal. In one embodiment, the second hard mask layer 275L may include silicon nitride. The thickness of the second hard mask layer 275L may be in the range of 3 nm to 30 nm, such as 6 nm to 15 nm, although smaller and larger thicknesses may also be used.

Referring to FIGS. 8A-8D , the processing steps described above with reference to FIGS. 2A-2D result in patterning the second hard mask layer 275L into hard mask strips extending laterally along the first horizontal direction. This can be done by changing the pattern of the photoresist layer so that it can be The processing steps described above with reference to FIGS. 4A to 4D are performed to form an optional second barrier layer 27L, a second phase change memory layer 26L, a second selector layer 24L, and a second conductive material layer ( 22L) to transfer the pattern of hard mask strips. Each patterned portion of the second metallic layer 222L constitutes a second electrically conductive line 200 . Each patterned portion of the second selector layer 24L constitutes a second selector rail. Each patterned portion of the second phase change memory layer 26L constitutes a second phase change memory rail. Each patterned portion of the second barrier layer constitutes a second barrier strip.

The processing steps described above with reference to FIGS. 5A-5D may be performed by rotating the lithography pattern such that a two-dimensional array of second pillar structures 250 is formed. Specifically, the photoresist layer may be patterned into a line and space pattern extending laterally along the second horizontal direction hd2. The pattern in the photoresist layer can be transferred through the second barrier strips, the second phase change memory rails, and the second selector rails. In the illustrative example, each second pillar structure 250 includes, from bottom to top, a second selector pillar 24 that is a patterned portion of a second selector rail, a second selector pillar 24 that is a patterned portion of a phase change memory rail. 2 phase change pillars 26, and an optional second barrier segment 27 that is a patterned portion of the second barrier strip.

Each second selector pillar 24 may be a selector element, that is, an element that provides nonlinear voltage-current characteristics to function as a conductor under second voltage bias conditions and as an insulator under second voltage bias conditions. In one embodiment, each second selector pillar 24 is a second lower barrier material portion 242, which is a patterned portion of a second lower barrier material strip, a patterned portion of a second ovonic threshold switch material rail. a second ovonic threshold switch material portion 244 that is phosphorus, and a second upper barrier material portion 246 that is a patterned portion of the second upper barrier material strip.

Each of the second phase-change pillars 26 may be a phase-change memory element, that is, a structure that changes resistance according to a phase of an internal material. In one embodiment, each second phase change pillar 26 is an optional second lower conductive liner segment 262 that is a patterned portion of a second optional lower conductive liner strip, a patterned second phase change memory material rail. a vertical stack of second phase-change memory material pillars 264, which are portions of the second phase change memory material, and second optional top conductive liner segments 266, which are patterned portions of the second top conductive liner strip. The photoresist layer may be removed, for example by ashing.

Alternatively, the two-dimensional array of second pillar structures 250 may include a second two-dimensional array of memory elements. A second two-dimensional array of memory elements may be formed on top surfaces of the second electrically conductive lines 200 . Top surfaces of the second portions of the second electrically conductive lines 200 may be physically exposed between the second pillar structures 250 of each row arranged along the first horizontal direction.

The processing steps described above with reference to FIGS. 6A-6D may be repeated to deposit a second dielectric material over the first exemplary structure. The second dielectric material can be planarized using the top surfaces of the second pillar structures 250 as stop surfaces. For example, a first layer lying on a horizontal plane including top surfaces of optional second barrier segments 27 or second phase change pillars 26 (in case the second barrier segments 27 are not used). 2 Excess portions of the dielectric material may be removed by a planarization process, which may use a recess etch process and/or a chemical mechanical planarization process. The remaining portions of the second hard mask strips 275 may be removed in parallel during the planarization process. The remaining continuous portion of the second dielectric material constitutes the second dielectric material layer 260 . The second dielectric material layer 260 may include undoped silicate glass, doped silicate glass, or spin-on glass. A dielectric liner (not shown) may optionally be deposited prior to deposition of the first dielectric material. A second dielectric material layer 260 is formed around the second two-dimensional array of memory elements and fills gaps between the memory elements of the second two-dimensional array.

9A-9F , the first via cavities are formed by a second dielectric material layer 260 directly over the top surfaces of the second portions of the first electrically conductive lines 100 having a second width w2. and through the first dielectric material layer 160 . The length L of the second portions may be in the range of 500 nm to 5,000 nm, although smaller and larger lengths L may also be used. In one embodiment, the first via cavities are such that each row of first via cavities extends along a second horizontal direction hd2 and rows of first via cavities extend laterally along a first horizontal direction hd1. It may be formed as a plurality of rows of first via cavities spaced apart from each other. In one embodiment, the first via cavities of each row may contact every N-th first electrically conductive line 100 , where N is a positive integer greater than one. Although embodiments in which N = 2 are illustrated herein, embodiments in which N is 3 or greater are explicitly illustrated.

At least one conductive material can be deposited within the first via cavities, and excess portions of the at least one conductive material can be removed from above a horizontal plane that includes the top surface of the first dielectric material layer 160 . The at least one conductive material may include, for example, a metallic nitride material such as TiN, TaN, or WN, and a metallic fill material such as W, Cu, Ru, Co, Mo, or alloys thereof. Each remaining portion of the at least one conductive material filling the first via cavities constitutes the first conductive via structure 180 . Each first conductive via structure 180 may contact a top surface of a second portion of a respective first electrically conductive line of the first electrically conductive lines 100, and the first electrically conductive lines 100 may be in contact with at least one sidewall of the respective first electrically conductive line. Each first conductive via structure 180 may have a top surface in a horizontal plane that includes the top surface of the second dielectric material layer 260 . The first conductive via structures 180 are formed through the second dielectric material layer 260 and the first dielectric material layer 160, and the second dielectric material layer 260 and the first dielectric material layer 160 can be in contact with the side walls of

Referring to FIGS. 10A to 10D, the above description with reference to FIGS. 2A to 2D, 4A to 4D, 5A to 5D, 6A to 6D, 7A to 7D, and 8A to 8D The processing steps include the third electrically conductive lines 300 extending laterally along the first horizontal direction hd1, the two-dimensional array of third pillar structures 350, the third dielectric material layer 360, the second to sequentially form fourth electrically conductive lines 400 extending laterally along two horizontal directions hd2, a two-dimensional array of fourth pillar structures 450, and a fourth dielectric material layer 460; can Each of the third pillar structures 350 and the fourth pillar structures 450 may have the same structure as the first pillar structures 150 and/or the second pillar structures 250 .

Second via cavities may be formed through the fourth dielectric material layer 460 and the third dielectric material layer 360 directly over the top surfaces of the first conductive via structures 180 . In one embodiment, the second via-cavities are such that each row of second via-cavities extends along the second horizontal direction hd2 and rows of second via-cavities extend laterally along the first horizontal direction hd1. It may be formed as a plurality of rows of second via cavities spaced apart from each other. In one embodiment, the second via cavities may have an areal overlay with the first conductive via structures 180 .

At least one conductive material can be deposited in the second via cavities, and excess portions of the at least one conductive material can be removed from above a horizontal plane that includes the top surface of the fourth dielectric material layer 460 . The at least one conductive material may include, for example, a metallic nitride material such as TiN, TaN, or WN, and a metallic fill material such as W, Cu, Ru, Co, Mo, or alloys thereof. Each remaining portion of the at least one conductive material filling the second via cavities constitutes the second conductive via structure 380 . Each second conductive via structure 380 may contact a top surface of a respective first conductive via structure 180 . Each second conductive via structure 380 may have a top surface in a horizontal plane that includes the top surface of the fourth dielectric material layer 460 . The second conductive via structures 380 may pass through the third and fourth dielectric material layers 360 and 460 and contact sidewalls of the third and fourth dielectric material layers 360 and 460 . .

Interconnection structures 180 and 380 are formed through dielectric material layers 160 , 260 , 360 and 460 . The interconnection structures 180 and 380 have upper ends of the second portions of respective first electrically conductive lines of the first electrically conductive lines 100 having a second width w2 smaller than the first width w1 formed on the surface.

Referring to FIGS. 11A-11D , a metallic layer may be deposited over the fourth dielectric material layer 460 and the two-dimensional array of fourth pillar structures 450 . The metallic layer can be patterned to form fifth electrically conductive lines 500 . The fifth electrically conductive lines 500 may have the same pattern as the first electrically conductive lines 100 . A fifth dielectric material layer 560 may be formed around the fifth electrically conductive lines 500 .

In one embodiment, fifth electrically conductive lines 500 and fifth dielectric material layer 560 may be formed by repeating the processing steps described above. The fifth electrically conductive lines 500 may extend laterally along the first horizontal direction hd1. Each fifth electrically conductive line 500 may include a first portion having a first width w1 and a second portion having a second width w2.

Referring collectively to FIGS. 1A to 11D , a memory device is provided, which is placed over a substrate 9 and includes first electrically conductive lines 100 , 2 of first pillar structures 150 . dimensional array, second electrically conductive lines 200, two-dimensional array of second pillar structures 250, third electrically conductive lines 300, two-dimensional array of third pillar structures 350, 4 electrically conductive lines 400, a two-dimensional array of fourth pillar structures 450, and a vertical stack comprising fifth electrically conductive lines 500 - first pillar structures 150, second pillars Structures 250 , third pillar structures 350 , and fourth pillar structures 460 each include a respective memory element (such as a phase change memory material pillar), and first pillar structures 150 overlying the top surfaces of the first portions of the first electrically conductive lines 100 having a first width w1; and interconnection structures (180, 380) providing electrically conductive paths between the fifth electrically conductive lines (500) and the first electrically conductive lines (100) - each of the interconnection structures (180, 380) and contacting the top surface of the second part of the respective first electrically conductive line of the first electrically conductive lines 100 having a second width w2 smaller than the first width w1.

In one embodiment, each of the interconnection structures 180 and 380 is in contact with a top surface of a second portion of a respective first electrically conductive line of the first electrically conductive lines 100 and the second pillar structures ( 250) a first conductive via structure 180 extending vertically to a horizontal plane that includes top surfaces of the two-dimensional array; and a second conductive via structure 380 overlying the first contact via structure 180 and contacting a bottom surface of a respective fifth electrical conductive line of the fifth electrical conductive lines 500 .

In one embodiment, the bottom surface of the second conductive via structure 380 contacts the top surface of the first conductive via structure 180 . In one embodiment, a two-dimensional array of first pillar structures 150 is formed in a first dielectric material layer 160 that laterally surrounds a lower portion of each of first conductive via structures 180; A two-dimensional array of second pillar structures 250 is formed in a second dielectric material layer 260 laterally surrounding an upper portion of each of the first conductive via structures 180 .

In one embodiment, the first electrically conductive lines 100, the third electrically conductive lines 300, and the fifth electrically conductive lines 500 extend laterally along the first horizontal direction hd1 and ; The second electrically conductive lines 200 and the fourth electrically conductive lines 400 extend laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

In one embodiment, a first portion of each of the first electrically conductive lines 100 underlies a respective row of first pillar structures 150 in the two-dimensional array of first pillar structures 150 and contact them; The second portion of each of the first electrically conductive lines 100 is laterally offset from the area containing the two-dimensional array of first pillar structures 150 .

In one embodiment, each of the first electrically conductive lines 100 has a respective first portion having a pair of first sidewalls spaced a first width w1 and a second sidewall spaced a second width w2. a respective second part having a pair of ; Each second sidewall of the pair of second sidewalls has a first width w1 and a second width w2 along a horizontal direction perpendicular to the first horizontal direction hd1, that is, along the second horizontal direction hd2. ) is laterally offset from one first sidewall of the pair of first sidewalls by half the difference between the first sidewalls. In one embodiment, each of the first electrically conductive lines 100 has a first width w1, is adjacent to a respective second portion, and extends from the substrate 9 to the second portion of the first pillar structures 150 . and a respective third portion in contact with the bottom surfaces of the two-dimensional array of additional first pillar structures 150 positioned at the same vertical distance as the dimensional array.

In one embodiment, each of the fifth electrically conductive lines 500 includes a respective first portion having a first width w1 and a respective second portion having a second width w2; Each of the interconnection structures 180 and 380 is in contact with a bottom surface of one of the second portions of the fifth electrically conductive lines 500 .

In one embodiment, each of the first pillar structures 150 , the second pillar structures 250 , the third pillar structures 350 , and the fourth pillar structures 450 is formed from its uppermost surface to its lowermost portion. and at least one vertical or tapered sidewall extending vertically into the surface. In one embodiment, first pillar structures 150, second pillar structures 250, third pillar structures 350, and fourth pillar structures 450 each have a memory material portion and a selector material portion. includes a serial connection of In one embodiment, the memory material portion includes a phase change material; The selector material portion includes an ovonic threshold switch material.

Referring to FIGS. 12A to 12D , the second exemplary structure according to the second embodiment of the present invention may be the same as the first exemplary structure of FIGS. 1A to 1D .

Referring to FIGS. 13A to 13D , the processing steps described above with reference to FIGS. 2A to 2D and 4A to 4D are performed to form first electrically conductive lines 100 laterally spaced apart by first trenches. ) and the first stacked rail structures 150L. Each of the first stacked rail structures 150L and the first electrically conductive lines 100 extends laterally along the first horizontal direction hd1. The first electrically conductive lines 100 include remaining patterned portions of the first metallic layer 122L. The first stacked rail structures 150L are laterally spaced apart by the first trenches 11 along the second horizontal direction hd2. Each of the first stacked rail structures 150L and the first electrically conductive lines 100 may have a uniform thickness throughout, which is referred to as a first width w1 in this specification.

Each of the first stacked rail structures 150L includes, from the bottom to the top, the first selector rail 14', which is a patterned portion of the first selector layer 14L, and the first phase change memory layer 16L. The patterned portion of the first phase change memory rail 16' and the patterned portion of the first barrier layer 17L may include the first barrier rail 17'. As used herein, “strip” refers to a rail having a thickness less than its width. The first stacked rail structures 150L extend laterally along the first horizontal direction hd1, are laterally spaced apart from each other by first trenches 11, and are positioned over the substrate 9 .

In one embodiment, each first stacked rail structure 150L may include a first metallic nitride strip 124' that is a patterned portion of a first metallic nitride layer 124L. In one embodiment, each first selector rail 14' includes a first lower barrier material strip 142', a first ovonic threshold switch material rail 144', and a first upper barrier material strip 146' ) may include a vertical stack of The first lower barrier material strip 142' is a patterned portion of the optional first lower barrier material layer 142L. The first ovonic threshold switch material rail 144' is a patterned portion of the first ovonic threshold switch material layer 144L. The first upper barrier material strip 146' is a patterned portion of the optional first upper barrier material layer 146L. In one embodiment, each first phase change memory rail 16' includes, from bottom to top, a first optional lower conductive liner strip 162', a first phase change memory material rail 164', and a first phase change memory material rail 164'. 1 optional upper conductive liner strip 166'. Each first lower conductive liner strip 162' is a patterned portion of the first lower conductive liner layer 162L, and each first phase change memory material rail 164' is a first phase change memory material layer. 164L, and each first top conductive liner strip 166' is a patterned portion of the first top conductive liner layer 166L. The first stacked rail structures 150L extend laterally along the first horizontal direction hd1 and are spaced laterally from each other by first trenches 11 over the base dielectric material layers 60 . do.

14A to 14D, another photoresist layer (not shown) is applied over the first exemplary structure, regions including portions of first stacked rail structures 150L having a first width. lithographically patterned into line and space patterns within Each of the line and space patterns may extend laterally along the second horizontal direction hd2 and may be laterally spaced apart along the first horizontal direction hd1. The pitch of each line and space pattern may be in the range of 30 nm to 600 nm, although smaller and larger distances may also be used. The width of each line in the line and space pattern may be about half the pitch of the line and space pattern.

An anisotropic etch process may be performed to transfer the pattern of the photoresist layer through the hard mask strips 175 and the first stacked rail structures 150L. Each of the hard mask strips 175 may be patterned into hard mask segments 178 having a rectangular horizontal cross-sectional shape. The first stacked rail structures 150L are patterned into a two-dimensional rectangular array of first pillar structures 150 . Each of the first pillar structures 150 may have a rectangular horizontal cross-sectional shape. The first metallic nitride strips 124' may be patterned into first metallic nitride segments, or may function as an etch stop structure and remain as first metallic nitride strips 124'.

The chemistry of the anisotropic etch process can change the various materials of the hard mask strips 175, the first barrier rails 17', the first phase change memory rails 16', and the first selector rails 14'. through, and optionally through the first metallic nitride strips 124'. The anisotropic etch process may stop at or within the top surface of the first electrically conductive lines 100 or within the first metallic nitride strips 124'. In the illustrative example, each first pillar structure 150 includes, from bottom to top, a first selector pillar 14, which is a patterned portion of a first selector rail 14', a phase change memory rail 16' ), and an optional first barrier segment 17 that is a patterned portion of the first barrier strip 17'.

Each first selector pillar is a selector element, that is, an element that provides non-linear voltage-current characteristics to function as a conductor under first voltage bias conditions and as an insulator under second voltage bias conditions. In one embodiment, each first selector pillar 14 comprises a first lower barrier material portion 142, which is a patterned portion of a first lower barrier material strip 142', a first ovonic threshold switch material rail ( A vertical stack of first ovonic threshold switch material portion 144, which is the patterned portion of 144'), and first upper barrier material portion 146, which is the patterned portion of first upper barrier material strip 146'. can include

In one embodiment, each first selector pillar 14 is a first ovonic threshold switch material portion 144, a top of the first ovonic threshold switch material portion 144 as a first upper barrier material portion 146. an upper amorphous carbon portion in contact with the surface, and a lower amorphous carbon portion in contact with the bottom surface of the first ovonic threshold switch material portion 144 as the first lower barrier material portion 142 .

Each of the first phase-change pillars 16 is a phase-change memory element, that is, a structure that changes resistance according to the phase of the material therein. In one embodiment, each first phase change pillar 16 is an optional first lower conductive liner segment 162 that is a patterned portion of a first optional lower conductive liner strip 162', a first phase change memory material A first phase change memory material pillar 164, which is a patterned portion of a rail 164', and a first optional top conductive liner segment 166, which is a patterned portion of a first top conductive liner strip 166'. Can include vertical stacks. The photoresist layer may be removed, for example by ashing.

Alternatively, the two-dimensional array of first pillar structures 150 may include a first two-dimensional array of memory elements. A first two-dimensional array of memory elements may be formed on top surfaces of the first and third portions of the first electrically conductive lines 100 having a first width w1 . Top surfaces of the second portions of the first electrically conductive lines 100 may be physically exposed. The first electrically conductive lines 100 may have a uniform width throughout, which may be the first width w1. The first electrically conductive lines 100 may be laterally spaced apart from each other by a first distance s1 along the second horizontal direction hd2. The first electrically conductive layers 100 have a uniform pitch, which may be a first pitch p1 equal to the sum of the first width w1 and the first spacing s1 along the second horizontal direction hd2. It can be formed as a periodic one-dimensional array.

Referring to FIGS. 15A-15D , a first dielectric material may be deposited over the example structure and planarized using the top surfaces of the first pillar structures 150 as stop surfaces. For example, (in case the first barrier segments 17 are not used) a first layer lying on a horizontal plane comprising the top surfaces of the optional first barrier segments 17 or the first phase change pillars 16. Excess portions of the first layer of dielectric material may be removed by a planarization process, which may use a recess etch process and/or a chemical mechanical planarization process. Hard mask segments 178 may be removed in parallel during the planarization process. The remaining continuous portion of the first dielectric material constitutes the first dielectric material layer 160 . The first dielectric material layer 160 may include undoped silicate glass, doped silicate glass, or spin-on glass. A dielectric liner (not shown) may optionally be deposited prior to deposition of the first dielectric material. The first dielectric material layer 160 is formed around the first two-dimensional array of memory elements and fills gaps between the memory elements of the first two-dimensional array.

Referring to FIGS. 16A-16D , the set of processing steps described above with reference to FIGS. 7A-7D and 8A-8D are performed to form second electrically conductive lines 200 , second pillar structures 250 ), and a second dielectric material layer 260 can be formed.

First via cavities may be formed through the second dielectric material layer 260 and the first dielectric material layer 160 directly over the top surfaces of the first electrically conductive lines 100 . In one embodiment, the first via cavities are such that each row of first via cavities extends along a second horizontal direction hd2 and rows of first via cavities extend laterally along a first horizontal direction hd1. It may be formed as a plurality of rows of first via cavities spaced apart from each other. In one embodiment, the first via cavities of each row may contact every N-th first electrically conductive line 100 , where N is a positive integer greater than one. Although embodiments in which N = 2 are illustrated herein, embodiments in which N is 3 or greater are explicitly illustrated.

At least one conductive material can be deposited in the first via cavities, and excess portions of the at least one conductive material can be removed from above a horizontal plane that includes the top surface of the second dielectric material layer 260 . The at least one conductive material may include, for example, a metallic nitride material such as TiN, TaN, or WN, and a metallic fill material such as W, Cu, Ru, Co, Mo, or alloys thereof. Each remaining portion of the at least one conductive material filling the first via cavities constitutes the first conductive via structure 180 . Each first conductive via structure 180 may contact a top surface of a second portion of a respective first electrically conductive line of the first electrically conductive lines 100, and the first electrically conductive lines 100 may be in contact with at least one sidewall of the respective first electrically conductive line. Each first conductive via structure 180 may have a top surface in a horizontal plane that includes the top surface of the second dielectric material layer 260 . The first conductive via structures 180 are formed through the second dielectric material layer 260 and the first dielectric material layer 160, and the first dielectric material layer 260 and the first dielectric material layer 160 can be in contact with the side walls of

Referring to FIGS. 17A-17D , a third material layer stack (32L, 34L, 36L, 37L, 375L), also referred to as a third layer stack or third vertical stack, includes a second dielectric material layer 260 and a second vertical stack. It is formed over the two-dimensional array of pillar structures 250 . For example, the third material layer stack 32L, 34L, 36L, 37L, and 375L includes a third conductive material layer 32L, a third selector layer 34L, a third phase change memory layer 36L, and an optional second layer. A third barrier layer 37L and a third hard mask layer 375L may be included. Each layer in the third material layer stack 32L, 34L, 36L, 37L, 375L is a blanket material layer, that is, a third horizontal direction hd1 and a third horizontal direction hd2 perpendicular to the third horizontal direction hd1. ) can be formed as an unpatterned material layer extending laterally along .

The third conductive material layer 32L includes at least one conductive material layer, which may be at least one metallic material layer. For example, the third conductive material layer 32L may include, from bottom to top, a third metallic layer 322L (eg, a tungsten layer) and a third metallic nitride layer 324L (eg, a tungsten nitride layer or a titanium nitride layer). layers) of layer stacks. The thickness of the third metallic layer 322L may be in the range of 31 nm to 100 nm, such as 30 nm to 70 nm, although smaller and larger thicknesses may also be used. The thickness of the third metallic nitride layer 324L may be in the range of 1 nm to 10 nm, such as 1.5 nm to 5 nm, although smaller and larger thicknesses may also be used. In another embodiment, the third conductive material layer 32L is used for process feasibility and/or smaller variations in contact between portions of the third conductive material layer 32L and the underlying and overlying memory material layers. , two separate metallic material layers formed during separate deposition and patterning steps, e.g., a first tungsten layer patterned into layers of underlying first pillar structures 150, and the first tungsten layer and underlying pillars. and a third tungsten layer deposited on the first tungsten layer after patterning the structures.

The third selector layer 34L includes a non-ohmic material that provides an electrically isolated electrical connection depending on the magnitude and/or polarity of an externally applied voltage bias across it. In one embodiment, the third selector layer 34L includes at least one threshold switch material layer, such as an ovonic threshold switch material layer. The ovonic threshold switch material layer may include a third ovonic threshold switch material layer 344L comprising any ovonic threshold switch material. In one embodiment, the third ovonic threshold switch material layer 344L may include and/or consist essentially of a GeSeAs compound, a GeSe compound, a SeAs compound, a GeTe compound, or a SiTe compound.

In one embodiment, the material of the third ovonic threshold switch material layer 344L is changed upon application of an external bias voltage that exceeds a threshold bias voltage magnitude (also referred to as threshold voltage). 344L) can be selected to reduce the resistivity by at least two orders of magnitude (ie, by more than a factor of 100). In one embodiment, the composition and thickness of the third ovonic threshold switch material layer 344L is such that the threshold bias voltage magnitude is within the range of 1 V to 4 V, but smaller and larger voltages for the threshold bias voltage magnitude are also possible. can be selected for use. The thickness of the third ovonic threshold switch material layer 344L may be, for example, in the range of 5 nm to 50 nm, such as 10 nm to 30 nm, although smaller and larger thicknesses may also be used.

The third selector layer 34L includes an optional third upper barrier material layer 346L overlying the third ovonic threshold switch material layer 344L and an optional third lower barrier material layer 346L underlying the third ovonic threshold switch material layer 344L. A barrier material layer 342L may be included. Optional third upper and/or lower barrier material layers 346L, 342L include a material that suppresses diffusion of the material of the third ovonic threshold switch material layer 344L. For example, the third upper and/or lower barrier material layers 346L and 342L may include amorphous carbon or diamond-like carbon (DLC). The thickness of the third upper barrier metallic nitride layers 346L may be in the range of 4 nm to 40 nm, such as 8 nm to 31 nm, although smaller and larger thicknesses may also be used. The thickness of the third lower barrier material layer 342L may be in the range of 4 nm to 40 nm, such as 8 nm to 31 nm, although smaller and larger thicknesses may also be used.

The third phase change memory layer 36L includes a third phase change memory material layer 364L. The third phase change memory material layer 364L includes phase change memory material. The thickness of the third phase change memory material layer 364L may be in the range of 1 nm to 60 nm, such as 3 nm to 40 nm and/or 10 nm to 35 nm, although smaller and larger thicknesses may also be used. there is.

The third phase change memory layer 36L may optionally include a third lower conductive liner layer 362L underlying the third phase change memory material layer 364L, and optionally, the third phase change memory material and a third top conductive liner layer 366L overlying layer 364L. Optional third lower conductive liner layer 362L and/or optional third upper conductive liner layer 366L, if present, include a conductive metallic material. In one embodiment, the third lower conductive liner layer 362L and/or the third upper conductive liner layer 366L may include a conductive metallic nitride, such as titanium nitride, tantalum nitride, or tungsten nitride. The thickness of each of the third lower conductive liner layer 362L and the third upper conductive liner layer 366L may be in the range of 1 nm to 10 nm, such as 1.5 nm to 5 nm, although smaller and larger thicknesses may also be used. can be used

An optional third barrier layer 37L, if present, includes a barrier material and may be formed on top of the third phase change memory layer 36L. The barrier material is a material capable of preventing diffusion of the third phase change memory material and providing effective encapsulation thereof. In one embodiment, the barrier material can include and/or consist essentially of amorphous carbon. The thickness of the third barrier layer 37L may be in the range of 12 nm to 75 nm, such as 31 nm to 60 nm, although smaller and larger thicknesses may also be used.

The third hard mask layer 375L includes a hard mask material that can be used as a planarization stop structure in a subsequent planarization process. The third hard mask layer 375L may include a material selected from a metal, a dielectric material, or a semiconductor material. For example, the third hard mask layer 375L may include silicon nitride, a dielectric metallic oxide, or a metal. In one embodiment, the third hard mask layer 375L may include silicon nitride. The thickness of the third hard mask layer 375L may be in the range of 3 nm to 30 nm, such as 6 nm to 15 nm, although smaller and larger thicknesses may also be used.

Referring to FIGS. 18A-18D , a photoresist layer may be applied over the third material layer stacks 32L, 34L, 36L, 37L, and 375L, regions of each two-dimensional array of second pillar structures 250. may be lithographically patterned to form line and space patterns over the first conductive via structures 180 and to form discrete plate patterns over the regions of the first conductive via structures 180 . The line and space pattern includes line patterns extending laterally along the first horizontal direction hd1. The line and space patterns may have a uniform pitch along a second horizontal direction hd2 perpendicular to the first horizontal direction. A uniform pitch may be in the range of 30 nm to 600 nm, for example. The discrete plate pattern includes discrete areas covering each area of the first conductive via structure 180 .

An anisotropic etch process is performed to transfer the pattern of the photoresist layer through the third hard mask layer 375L. The third hard mask layer 375L may be patterned into third hard mask strips 375 having line shapes and hard mask plates 373 having discrete shapes. As shown in FIG. 18D , each of the third hard mask strips 375 may have a uniform width and laterally extend along the first horizontal direction hd1, and may have a uniform width along the first horizontal direction hd1. It may be formed between adjacent pairs of rows of second pillar structures 250 extending in the lateral direction. The third hard mask strips 375 are not shown in FIG. 18A because the cross-sectional line A-A′ in FIG. 18D extends between the third hard mask strips 375 . Each third hard mask strip 375 may have a rectangular shape. In one embodiment, the third hard mask strips 375 may be located in every other gap region located between rectangular regions comprising respective adjacent pairs of rows of second pillar structures 250. . In this case, the third hard mask strips 375 do not have any area overlap with the second pillar structures 250 . In one embodiment, the third hard mask strips 375 may have their respective uniform widths, which may be in the range of 15 nm to 300 nm, although smaller and larger dimensions may also be used. The hard mask plates 373 overlie the respective first conductive via structures of the first conductive via structures 180 . The hard mask plates 373 can have rectangular shapes, circular shapes, or oval shapes. The photoresist layer may be subsequently removed, for example by ashing.

Referring to FIGS. 19A and 19B , a spacer material layer may be conformally deposited over the third hard mask strips 375 and hard mask plates 373 by a conformal deposition process. The spacer material layer includes a material different from those of the third hard mask strips 375 and the hard mask plates 373 . For example, the third hard mask strips 375 and hard mask plates 373 may include silicon oxide, and the spacer material layer may include silicon nitride. A thickness of the spacer material layer may be the same as a width of a row of second pillar structures 250 arranged along the first horizontal direction hd1 .

An anisotropic etch process may be performed to remove horizontal portions of the spacer material layer. The remaining portions of the spacer material layer include first spacer material portions 376 formed on the sidewalls of the third hard mask strips 375 and second portions formed on the sidewalls of the hard mask plates 373. Spacer material portions 374 . Each first spacer material portion 376 laterally surrounds a respective third hard mask strip of the third hard mask strips 375, and each second spacer material portion 374 surrounds the hard mask plates ( 373) laterally surrounds the respective hard mask plate. The first spacer material portion 376 may cover entire areas of two rows of second pillar structures 250 extending laterally along the first horizontal direction hd1 . A set of hard mask plate 373 and second spacer material portion 374 may cover the entire area of a respective first conductive via structure of first conductive via structures 180 .

Referring to FIGS. 20A-20D , a photoresist layer 379 may be applied over the second example structure and lithographically patterned to cover the hard mask plates 373 and the second spacer material portions 374 . It can be. An etch process may be performed to etch the third hard mask strips 375 selectively to the first spacer material portions 376 . For example, if the first spacer material portions 376 include silicon nitride and the third hard mask strips 375 include silicon oxide, a wet etch process using dilute hydrofluoric acid is performed. Thus, the third hard mask strips 375 may be selectively removed with respect to the first spacer material portions 376 . Photoresist layer 379 may be subsequently removed, for example by ashing.

21A-21D , another photoresist layer may be applied over the second exemplary structure, to cover the hard mask plates 373 and the second spacer material portions 374, and each of the first It may be lithographically patterned to cover a dominant portion of each first spacer material portion 376 without covering the end segments of the spacer material portion 376 . Physically exposed end segments of first spacer material portions 376 may be removed by an etch process, which may include a wet etch process or a dry etch process. Each first spacer material portion 376 may be divided into a respective pair of first spacer material portions 376 having a rectangular horizontal cross-sectional shape. Each of the first spacer material portions 376 retained after the etch process may extend laterally along the first horizontal direction hd1, and second pillar structures arranged along the first horizontal direction hd1 (250) can be placed on top of each row. The photoresist layer may be subsequently removed, for example by ashing.

22A to 22D, an anisotropic etch process is performed using a combination of first spacer material portions 376, hard mask plates 373, and second spacer material portions 374 as an etch mask. do. The anisotropic etch process removes the optional third barrier layer 37L, which is not masked by the combination of the first spacer material portions 376, the hard mask plates 373, and the second spacer material portions 374. The etching passes through portions of the three phase change memory layer 36L, the third selector layer 34L, and the third conductive material layer 32L. The chemistry of the anisotropic etch process sequentially etches through portions of the optional third barrier layer 37L, the third phase change memory layer 36L, the third selector layer 34L, and the third conductive material layer 32L. can be changed sequentially. The anisotropic etch process may stop at or below the top surface of the second dielectric material layers 260 . The patterns of the combination of first spacer material portions 376, hard mask plates 373, and second spacer material portions 374 are formed by an anisotropic etch process, forming an optional third barrier layer 37L, a third It is transferred through portions of the phase change memory layer 36L, the third selector layer 34L, and the third conductive material layer 32L. Second trenches extending laterally along the first horizontal direction hd1 are formed by anisotropic etching. The second trenches may be line trenches each having a uniform width.

The remaining portions of the third material layer stack 32L, 34L, 36L, 37L, and 375L include third stacked rail structures 350L and third electrically conductive lines ( 300), and plate stack structures 350M and conductive pad structures 310 underlying the combinations of hard mask plates 373 and second spacer material portions 374. The third electrically conductive lines 300 include patterned remaining portions of the third metallic layer 322L overlying the two-dimensional array of second pillar structures 250 . The conductive pad structures 310 include patterned remaining portions of the third metallic layer 322L overlying the first conductive via structures 180 .

The third stacked rail structures 350L are laterally spaced apart by third trenches along the first horizontal direction hd1. Each of the third stacked rail structures 350L includes, from bottom to top, the third selector rail 34', which is a patterned portion of the third selector layer 34L, and the third phase change memory layer 36L. A third phase change memory rail 36' as a patterned portion, and a third barrier rail 37' as a patterned portion of the third barrier layer 37L. The third stacked rail structures 350L laterally extend along the first horizontal direction hd1 and are laterally spaced apart from each other by third trenches along the second horizontal direction hd2.

In one embodiment, each third stacked rail structure 350L may include a third metallic nitride strip 324' that is a patterned portion of the third metallic nitride layer 324L. In one embodiment, each third selector rail 34' includes a third lower barrier material strip 342', a third ovonic threshold switch material rail 344', and a third upper barrier material strip 346' ) may include a vertical stack of The third lower barrier material strip 342' is a patterned portion of the optional third lower barrier material layer 342L. The third ovonic threshold switch material rail 344' is a patterned portion of the third ovonic threshold switch material layer 344L. The third upper barrier material strip 346' is a patterned portion of the optional third upper barrier material layer 346L. In one embodiment, each third phase change memory rail 36' includes, from bottom to top, a third optional lower conductive liner strip 362', a third phase change memory material rail 364', and a first 3 may include an optional top conductive liner strip 366'. Each third lower conductive liner strip 362' is a patterned portion of the third lower conductive liner layer 362L, and each third phase change memory material rail 364' is a third phase change memory material layer. 364L, and each third top conductive liner strip 366' is a patterned portion of the third top conductive liner layer 366L. The third stacked rail structures 350L extend laterally along the third horizontal direction hd2 and are laterally spaced from each other by third trenches over the first dielectric material layer 160 .

Each plate stack structure 350M includes, from bottom to top, a selector material plate 34" which is a patterned portion of the third selector layer 34L, a patterned portion of the third phase change memory layer 36L. a phase change memory material plate 36", and a barrier material plate 37" that is a patterned portion of the third barrier layer 37L. In one embodiment, each plate stack structure 350M comprises and a metallic nitride plate 324″ that is a patterned portion of the third metallic nitride layer 324L.

In one embodiment, each selector material plate 34″ comprises a third lower barrier material plate 342″, a third ovonic threshold switch material plate 344″, and a third upper barrier material plate 346″. may include a vertical stack of The third lower barrier material plate 342″ is a patterned portion of the optional third lower barrier material layer 342L. The third ovonic threshold switch material plate 344″ is the third ovonic threshold switch material layer ( 344L). The third upper barrier material plate 346″ is a patterned portion of the optional third upper barrier material layer 346L. In one embodiment, each phase change memory material plate 36″ is, from bottom to top , a third optional lower conductive liner plate 362″, a third phase change memory material plate 364″, and a third optional upper conductive liner plate 366″. Each third lower conductive liner Plate 362″ is a patterned portion of third lower conductive liner layer 362L, and each third phase change memory material plate 364″ is a patterned portion of third phase change memory material layer 364L. portion, and each third top conductive liner plate 366″ is a patterned portion of the third top conductive liner layer 366L. The plate stack structures 350M extend laterally along the third horizontal direction hd2 and are laterally spaced from each other by third trenches over the first dielectric material layer 160 .

Referring to FIGS. 23A-23D , a photoresist layer may be applied over the second example structure, lithography to form a line and space pattern covering each region of the two-dimensional array of second pillar structures 250 . can be patterned as Each line and space pattern may laterally extend along the second horizontal direction hd2. Plate stack structures 350M are not covered by a photoresist layer, and each second stacked rail structure 350L is covered with a plurality of patterned photoresist portions. An anisotropic etch process is performed to transfer the pattern into the photoresist layer through the first spacer material portions 376 and the unmasked portions of the third stacked rail structures 350L and plate stack structures 350M. ) is removed. The chemistry of the anisotropic etch process may be sequentially changed to etch through various material portions of the entirety of the plate stack structures 350M and the unmasked portions of the third stacked rail structures 350L. The etch chemistry of the terminal step of the anisotropic etch process may be selective for the materials of the third electrically conductive lines 300 and the conductive pad structures 310 . The hard mask plates 373, the second spacer material portions 374, and the plate stack structures 350M may be completely removed by an anisotropic etch process.

The third stacked rail structures 350L are patterned into third pillar structures 350 . In the illustrative example, each third pillar structure 350 includes, from bottom to top, a third selector pillar 34, which is a patterned portion of the third selector rail 34', a phase change memory rail 36' ), and an optional third barrier segment 37 that is a patterned portion of the third barrier strip 37'.

Each third selector pillar 34 is a selector element, that is, an element that provides nonlinear voltage-current characteristics to function as a conductor under third voltage bias conditions and as an insulator under third voltage bias conditions. In one embodiment, each third selector pillar 34 comprises a third lower barrier material portion 342, which is a patterned portion of a third lower barrier material strip 342', a third ovonic threshold switch material rail ( A vertical stack of a third ovonic threshold switch material portion 344, which is a patterned portion of 344'), and a third upper barrier material portion 346, which is a patterned portion of third upper barrier material strip 346'. can include

Each of the third phase change pillars 36 is a phase change memory element, that is, a structure that changes resistance according to the phase of the material therein. In one embodiment, each third phase change pillar 36 is an optional third lower conductive liner segment 362 that is a patterned portion of a third optional lower conductive liner strip 362', a third phase change memory material. third phase change memory material pillars 364, which are patterned portions of rails 364', and third optional top conductive liner segments 366, which are patterned portions of third top conductive liner strips 366'. Can include vertical stacks. The photoresist layer may be removed, for example by ashing.

Alternatively, the two-dimensional array of third pillar structures 350 may include a third two-dimensional array of memory elements. A third two-dimensional array of memory elements may be formed on top surfaces of the third electrically conductive lines 300 . Top surfaces of the third portions of the third electrically conductive lines 300 may be physically exposed between the third pillar structures 350 of each row arranged along the first horizontal direction.

Each conductive pad structure 310 may be formed on a top surface of a respective first conductive via structure of the first conductive via structures 180 . The conductive pad structures 310 may be arranged in multiple rows extending along the second horizontal direction hd2 . In one embodiment, the conductive pad structures 310 in each row may be arranged at a regular pitch, referred to herein as a second pitch p2. The second pitch p2 may be an integer multiple of the first pitch p1, which is the pitch of the first electrically conductive lines 100 along the second horizontal direction hd2. In one embodiment, the conductive pad structures 310 may be arranged as N rows, where N is an integer greater than one. In this case, the second pitch p2 may be N times the first pitch p1. Each conductive pad structure 310 may be electrically connected to a respective first electrically conductive line of the first electrically conductive lines 100 through a respective first conductive via structure of the first conductive via structures 180. can Each of the conductive pad structures 310 may have a pad width pw along the second horizontal direction hd2, which may be smaller than the second pitch p2 and larger than the first pitch p1. Accordingly, a lateral dimension of each conductive pad structure 310 along the second horizontal direction hd2 may be greater than a pitch of the first electrically conductive lines 100 along the second horizontal direction hd2.

24A to 24D, a third dielectric material layer 360, fourth electrically conductive lines 400, a two-dimensional array of fourth pillar structures 450, and a fourth dielectric material layer 460 It can be formed in the same way as this first embodiment.

Referring to FIGS. 25A to 25D , second via cavities may be formed directly on top surfaces of the conductive pad structures 310 and passing through the fourth dielectric layer 460 and the third dielectric layer 360 . In one embodiment, the second via-cavities are such that each row of second via-cavities extends along the second horizontal direction hd2 and rows of second via-cavities extend laterally along the first horizontal direction hd1. It may be formed as a plurality of rows of second via cavities spaced apart from each other.

At least one conductive material can be deposited in the second via cavities, and excess portions of the at least one conductive material can be removed from above a horizontal plane that includes the top surface of the fourth dielectric material layer 460 . The at least one conductive material may include, for example, a metallic nitride material such as TiN, TaN, or WN, and a metallic fill material such as W, Cu, Ru, Co, Mo, or alloys thereof. Each remaining portion of the at least one conductive material filling the second via cavities constitutes the second conductive via structure 380 . Each second conductive via structure 380 may contact a top surface of a respective conductive pad structure 310 . Each second conductive via structure 380 may have a top surface in a horizontal plane that includes the top surface of the fourth dielectric material layer 260 . The second conductive via structures 380 are formed through the fourth dielectric material layer 460 and the third dielectric material layer 360, and the fourth dielectric material layer 460 and the third dielectric material layer 360 can be in contact with the side walls of

Interconnection structures 180 , 210 , 380 are formed through dielectric material layers 160 , 260 , 360 , 460 . Interconnection structures 180 , 210 , 380 are formed on top surfaces of respective first electrically conductive lines of first electrically conductive lines 100 . Each interconnection structure 180, 210, 380 includes a first conductive via structure 180 contacting a respective first electrical conductive line of the first electrically conductive lines 100, a first conductive via structure 180 It may include a vertical stack of a conductive pad structure 310 in contact with the top surface of the conductive pad structure 310 and a second conductive via structure 380 in contact with the conductive pad structure 310 .

Referring to FIGS. 26A-26D , a metallic layer may be deposited over the fourth dielectric material layer 460 and the two-dimensional array of fourth pillar structures 450 . The metallic layer can be patterned to form fifth electrically conductive lines 500 . The fifth electrically conductive lines 500 may have the same pattern as the first electrically conductive lines 300 . A fifth dielectric material layer 560 may be formed around the fifth electrically conductive lines 500 .

In one embodiment, fifth electrically conductive lines 500 and fifth dielectric material layer 560 may be formed by repeating the processing steps described above. The fifth electrically conductive lines 500 may extend laterally along the first horizontal direction hd1.

Referring collectively to FIGS. 12A to 26D , a memory device is provided, comprising first electrically conductive lines 100 , a two-dimensional array of first pillar structures 150 , and a second electrically conductive line fields 200, two-dimensional array of second pillar structures 250, third electrically conductive lines 300, two-dimensional array of third pillar structures 350, fourth electrically conductive lines 400 , a two-dimensional array of fourth pillar structures 450, and a vertical stack including fifth electrically conductive lines 500 - first pillar structures 150, second pillar structures 250, third pillar structures 250, and fourth pillar structures 450 each including a respective memory element (such as a phase change memory material pillar); and interconnection structures (180, 310, 380) providing electrically conductive paths between the fifth electrically conductive lines (500) and the first electrically conductive lines (100) - interconnection structures (180, 310, 380). ) each of which is a first conductive via structure 180 in contact with the respective first electrical conductive line of the first electrically conductive lines 100, a conductive pad structure in contact with the upper surface of the first conductive via structure 180 ( 310 ), and a vertical stack of a conductive pad structure 310 and a second conductive via structure 380 in contact with a respective fifth electrical conductive line of the fifth electrical conductive lines 500 .

In one embodiment, the first electrically conductive lines 100, the third electrically conductive lines 300, and the fifth electrically conductive lines 500 extend laterally along the first horizontal direction hd1 and ; The second electrically conductive lines 200 and the fourth electrically conductive lines 400 extend laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

In one embodiment, the first electrically conductive lines 100 have a first pitch p1 along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1; The conductive pad structures 310 have a second pitch p2 along the second horizontal direction hd2; The second pitch p2 is an integer N times the first pitch p1 (N is an integer greater than 1). In one embodiment, the conductive pad structures 310 have a pad width pw along the second horizontal direction hd2, where the pad width pw is greater than the first pitch p1.

In one embodiment, the first conductive via structures 180 are arranged in N rows extending along the second horizontal direction hd2 and laterally spaced apart along the first horizontal direction hd1; The second conductive via structures 380 are arranged in N rows extending along the second horizontal direction hd2 and laterally spaced apart along the first horizontal direction hd1. In one embodiment, each row of first conductive via structures 180 is a respective sub of first conductive via structures 180 arranged along the second horizontal direction hd2 at a second pitch p2. contains a set; Each row of second conductive via structures 29 includes a respective subset of second conductive via structures 380 arranged along the second horizontal direction hd2 at a second pitch p2.

In one embodiment, the top surfaces of the conductive pad structures 310 are located in a horizontal plane that includes the top surfaces of the third electrically conductive lines 300; The bottom surfaces of the conductive pad structures 310 are located in a horizontal plane that includes the bottom surfaces of the third electrically conductive lines 300 .

In one embodiment, a two-dimensional array of first pillar structures 150 is formed in a first dielectric material layer 160 that laterally surrounds a bottom portion of each of first conductive via structures 180; A two-dimensional array of second pillar structures 250 is formed in the second dielectric material layer 260 laterally surrounding the bottom portion of each of the first conductive via structures 180 .

In one embodiment, the two-dimensional array of first pillar structures 150 includes a first periodic rectangular two-dimensional array of first memory elements; The two-dimensional array of second pillar structures 250 includes a second periodic rectangular two-dimensional array of second memory elements having the same two-dimensional periodicity as the two-dimensional array of first pillar structures 150 .

In one embodiment, each pillar structure 150, 250, 350, 450 may have at least one vertical or tapered sidewall extending vertically from its top surface to its bottom surface. In one embodiment, each pillar structure 150, 250, 350, 450 includes a series connection of a memory material portion and a selector material portion. In one embodiment, the memory material portion includes a phase change material; The selector material portion includes an ovonic threshold switch material.

Although a phase change memory (PCM) device is described above as an example memory device, any other type such as magnetic random access memory (MRAM) or metallic oxide resistive random access memory (ReRAM). It should be understood that the memory device of may be formed in place of the PCM device. Thus, in alternative embodiments, a series connection of a phase change memory element (eg, first phase change memory element 16) and a selector element (eg, first selector element 14) and optional barrier plate 17 may be replaced with any other type of memory element, such as a magnetic memory element with or without a selector element (eg, a diode steering element) or a metallic oxide (eg, titanium oxide or nickel oxide) resistive memory element. As such, each rectangular array of pillar structures formed at each memory level may include any type of pillar structures known in the art. All such variations are expressly contemplated herein.

Various embodiments of the present invention may provide interconnect structures that reduce parasitic capacitance and are less susceptible to electrical shorts to adjacent conductive line structures. Accordingly, the interconnection structures of the present invention are less susceptible to overlay deformations during fabrication steps, thus increasing device yield during fabrication and improving reliability of memory devices during use.

Although the foregoing refers to certain preferred embodiments, it will be understood that the present disclosure is not so limited. It will occur to those skilled in the art that various modifications can be made to the disclosed embodiments and that such modifications are intended to fall within the scope of the present disclosure. Where a particular structure and/or embodiment using a configuration is illustrated in this disclosure, this disclosure does not cover any other compatible structure that is functionally equivalent, unless such substitution is expressly prohibited or otherwise known to those skilled in the art to be impossible. It is understood that it may be practiced in various configurations and/or configurations. All publications, patent applications and patents cited herein are hereby incorporated by reference in their entirety.

Claims (40)

As a memory device,
First electrically conductive lines, two-dimensional array of first pillar structures, second electrically conductive lines, two-dimensional array of second pillar structures, third electrically conductive lines, two-dimensional array of third pillar structures, fourth A vertical stack comprising electrically conductive lines, a two-dimensional array of fourth pillar structures, and fifth electrically conductive lines - the first pillar structures, the second pillar structures, the third pillar structures, and the first pillar structures. 4 pillar structures each including a respective memory element, the two-dimensional array of first pillar structures overlying top surfaces of first portions of the first electrically conductive lines having a first width; and
interconnection structures providing electrically conductive pathways between the fifth electrically conductive lines and the first electrically conductive lines, each of the interconnection structures having a second width smaller than the first width; and in contact with a top surface of a second portion of a respective first electrically conductive line of the conductive lines. The method of claim 1, wherein each of the interconnection structures,
A first conductive line in contact with the top surface of the second portion of each of the first electrically conductive lines and extending vertically to a horizontal plane including the top surfaces of the two-dimensional array of second pillar structures. via structures; and
a second conductive via structure overlying the first conductive via structure and contacting a bottom surface of a respective fifth electrically conductive line of the fifth electrically conductive lines. 3. The memory device of claim 2, wherein the bottom surface of the second conductive via structure is in contact with the top surface of the first conductive via structure. According to claim 3,
the two-dimensional array of first pillar structures is formed in a first dielectric material layer that laterally surrounds a lower portion of each of the first conductive via structures;
wherein the two-dimensional array of second pillar structures is formed in a second dielectric material layer that laterally surrounds an upper portion of each of the first conductive via structures. According to claim 1,
the first electrically conductive lines, the third electrically conductive lines, and the fifth electrically conductive lines extend laterally along a first horizontal direction;
wherein the second electrically conductive lines and the fourth electrically conductive lines extend laterally along a second horizontal direction. According to claim 1,
a first portion of each of the first electrically conductive lines underlies and is in contact with a respective row of first pillar structures in the two-dimensional array of first pillar structures;
and a second portion of each of the first electrically conductive lines is laterally offset from a region containing the two-dimensional array of first pillar structures. According to claim 1,
Each of the first electrically conductive lines comprises a respective first portion having a pair of first sidewalls spaced apart by the first width and a respective second portion having a pair of second sidewalls spaced apart by the second width. contain;
Each second sidewall of the pair of second sidewalls is formed by half the difference between the first width and the second width along a horizontal direction perpendicular to the first horizontal direction. A memory device laterally offset from a sidewall. 8. The method of claim 7, wherein each of the first electrically conductive lines has the first width, is adjacent to the respective second portion, and is located at a vertical distance from the substrate equal to the two-dimensional array of first pillar structures. and a respective third portion in contact with bottom surfaces of the two-dimensional array of additional first pillar structures. According to claim 1,
each of the third electrically conductive lines includes a respective first portion having the first width and a respective second portion having the second width;
wherein each of the interconnection structures contacts a bottom surface of a second portion of one of the second portions of the third electrically conductive lines. The method of claim 1, wherein each of the first pillar structures, the second pillar structures, the third pillar structures, and the fourth pillar structures extends at least vertically from its uppermost surface to its lowermost surface. A memory device having one vertical or tapered sidewall. 11. The method of claim 10, wherein each of the first pillar structures, the second pillar structures, the third pillar structures, and the fourth pillar structures comprises a series connection of a memory material portion and a selector material portion. memory device. According to claim 11,
the memory material portion comprises a phase change material;
wherein the selector material portion comprises an ovonic threshold switch material. A method of forming a memory device comprising:
forming first electrically conductive lines extending laterally along a first horizontal direction over a substrate, the first electrically conductive lines having first portions having a first width and a second width smaller than the first width; including second parts having;
Over the two-dimensional array of first pillar structures, second electrically conductive lines, two-dimensional array of second pillar structures, third electrically conductive lines, two-dimensional array of third pillar structures, fourth electrically conductive lines, and Forming a vertical stack including a two-dimensional array of fourth pillar structures, each of the first pillar structures, the second pillar structures, the third pillar structures, and the fourth pillar structures having a respective one Contains memory elements -;
forming interconnection structures on top surfaces of the second portions of the first electrically conductive lines; and
forming fifth electrically conductive lines on top surfaces of the two-dimensional array of fourth pillar structures and on top surfaces of the interconnection structures. 14. The method of claim 13 wherein forming the interconnection structures comprises:
forming first conductive via structures on second portions of the first electrically conductive lines; and
Forming second conductive via structures over the first contact via structures, wherein the fifth electrically conductive lines are formed on the second conductive via structures, each of the second conductive via structures comprising the first conductive via and electrically connected to a respective first conductive via structure of the structures. 15. The method of claim 14, wherein each of the second conductive via structures is formed directly over a top surface of a respective first conductive via structure of the first conductive via structures. According to claim 15,
forming a first dielectric material layer around the two-dimensional array of first pillar structures; and
further comprising forming a second dielectric material layer around the two-dimensional array of second pillar structures, wherein the first conductive via structures are formed through the first dielectric material layer and the second dielectric material layer. How to. According to claim 14,
the first electrically conductive lines, the third electrically conductive lines, and the fifth electrically conductive lines extend laterally along the first horizontal direction;
wherein the second electrically conductive lines and the fourth electrically conductive lines extend laterally along a second horizontal direction. According to claim 13,
forming a layer of a first conductive material over the substrate;
forming a first material layer stack over the first conductive material layer;
forming hard mask strips having a first width over the first material layer stack;
trimming portions of the hard mask strips in the contact area to a second width while masking portions of the hard mask strips in the array area with a patterned masking layer; and
transferring the patterns of the hard mask strips through the first material layer stack and the first conductive material layer using an anisotropic etch process, wherein the patterned portions of the first conductive material layer are formed in a first electrically conductive liner Including - further comprising a method. 19. The method of claim 18, patterning remaining portions of the first material layer stack after the anisotropic etch process into a two-dimensional array of pillar structures, the two-dimensional array of pillar structures comprising: The method further comprising comprising an array. According to claim 13,
Each of the first pillar structures, the second pillar structures, the third pillar structures, and the fourth pillar structures may include at least one vertical or tapered vertical structure extending vertically from an uppermost surface thereof to a lowermost surface thereof. have side walls;
wherein each of the first pillar structures, the second pillar structures, the third pillar structures, and the fourth pillar structures comprises a series connection of a memory material portion and a selector material portion. delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete

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