KR102530789B1 - Memory system and operating method of memory system - Google Patents

Abstract

The present technology includes a plurality of blocks each including a host and a plurality of pages, a plurality of planes each including the blocks, and a plurality of dies each including the planes. A memory system including a memory device including a memory device and a controller controlling the memory device, wherein first data read from a first memory cell and second data of a second memory cell are converted into first symbol data and second symbol data. A first data conversion unit for conversion; an interference calculating unit which calculates an amount of interference between the first symbol data and the second symbol data; A compensator for calculating first interference elimination symbol data obtained by removing interference from the first symbol data using the amount of interference and third data read from the first memory cell, and the first interference elimination symbol data is first interference elimination It may include a memory system including a second data conversion unit for converting into data.

Description

Memory system and operation method of memory system {MEMORY SYSTEM AND OPERATING METHOD OF MEMORY SYSTEM}

The present invention relates to a memory system, and more particularly, to a memory system for compensating inter-cell interference (ICI) in a memory device and a method of operating the memory system.

Recently, a paradigm for a computer environment is shifting to ubiquitous computing that allows a computer system to be used anytime and anywhere. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers is rapidly increasing. Such a portable electronic device generally uses a memory system using a memory device, that is, a data storage device. Data storage devices are used as main storage devices or auxiliary storage devices in portable electronic devices.

A data storage device using a memory device has an advantage in that it has excellent stability and durability because it does not have a mechanical driving unit, and also has a very fast information access speed and low power consumption. As an example of a memory system having such an advantage, the data storage device includes a universal serial bus (USB) memory device, a memory card having various interfaces, a solid state drive (SSD), and the like.

An embodiment of the present invention provides a memory system for compensating for interference between cells and a method of operating the memory system.

A plurality of blocks each including a host and a plurality of pages according to an embodiment of the present invention, a plurality of planes each including the blocks, and a plurality of dies each including the planes A memory system including a memory device including dies and a controller controlling the memory device, wherein first data read from a first memory cell and second data of a second memory cell are converted into first symbol data and second data read from a first memory cell. A first data conversion unit for converting into 2 symbol data; an interference calculating unit calculating an amount of interference between the first symbol data and the second symbol data; A compensator for calculating first interference elimination symbol data obtained by removing interference from the first symbol data using the amount of interference and third data read from the first memory cell, and the first interference elimination symbol data is first interference elimination It may include a memory system including a second data conversion unit for converting into data.

A plurality of blocks each including a host and a plurality of pages according to an embodiment of the present invention, a plurality of planes each including the blocks, and a plurality of dies each including the planes A method of operating a memory system including a memory device including die and a controller controlling the memory device, wherein first data read from a first memory cell and second data of a second memory cell are converted into first symbol data and converting into second symbol data; calculating an amount of interference between the first symbol data and the second symbol data; Calculating first interference elimination symbol data from which interference is removed from the first symbol data using the amount of interference and third data read from the first memory cell, and first interference elimination of the first interference elimination symbol data It may include converting into data.

A memory system and a method of operating the memory system according to embodiments of the present invention compensate for interference of an interference cell affecting a victim cell by calculating interference using only data of an interference cell calculated through a hard decision instead of a soft decision. By performing, it is possible to minimize the complexity and performance degradation of the memory system. Existing cell interference compensation methods compensate by calculating the amount of interference from the soft outputs of victim cells and interfering cells, so read latency is too high to be used in situations where data is output in real time. In the present invention, real-time cell interference compensation can be performed by adjusting the increase in latency to a level that the application can handle when there is no read latency or when the increase is present.

1 is a diagram schematically illustrating an example of a data processing system including a memory system according to an embodiment of the present invention;
2 schematically illustrates an example of a memory device in a memory system according to an embodiment of the present invention;
3 schematically illustrates a memory cell array circuit of memory blocks in a memory device according to an embodiment of the present invention;
4 schematically illustrates a structure of a memory device in a memory system according to an embodiment of the present invention;
5 is a diagram schematically illustrating an example of a data processing operation in a memory device in a memory system according to an embodiment of the present invention;
6 is a diagram showing a detailed configuration of the memory system shown in FIG. 5 by way of example;
7 is a diagram for explaining a 2-bit soft decision read operation according to an embodiment of the present invention;
8 is a flowchart exemplarily illustrating a method of operating a memory system according to an embodiment of the present invention;
9 is a diagram comparing threshold voltage distributions of a plurality of victim cells according to an embodiment of the present invention;
10 is a diagram showing a threshold voltage graph through interference compensation according to an embodiment of the present invention.
11 to 19 schematically illustrate other examples of a data processing system including a memory system according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be configured in various different forms, but only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art within the scope of the present invention. It is provided to fully inform you.

1 is a diagram schematically illustrating an example of a data processing system including a memory system according to an embodiment of the present invention.

Referring to FIG. 1 , a data processing system 100 includes a host 102 and a memory system 110 . In addition, the host 102 includes electronic devices, for example, portable electronic devices such as mobile phones, MP3 players, and laptop computers, or electronic devices such as desktop computers, game consoles, TVs, and projectors, that is, wired and wireless electronic devices.

In addition, the host 102 includes at least one operating system (OS), and the operating system generally manages and controls the functions and operations of the host 102, and the data processing system 100 or Provides mutual operation between a user using the memory system 110 and the host 102 . Here, the operating system supports functions and operations corresponding to the user's purpose and purpose of use, and can be divided into a general operating system and a mobile operating system according to the mobility of the host 102, for example. In addition, the general operating system system in the operating system can be divided into a personal operating system and a corporate operating system according to the user's use environment. As an example, the personal operating system is characterized to support service provision functions for general users. As a system, it includes Windows and Chrome, etc., and the enterprise operating system is a system specialized to secure and support high performance, such as Windows server, Linux and Unix. can include In addition, the mobile operating system in the operating system is a system specialized to support a function of providing mobility services to users and a power saving function of the system, and may include Android, iOS, Windows Mobile, and the like. . At this time, the host 102 may include a plurality of operating systems, and also executes an operating system to perform an operation with the memory system 110 corresponding to a user request. Here, the host 102 ) transmits a plurality of commands corresponding to the user request to the memory system 110, and accordingly, the memory system 110 performs operations corresponding to the commands, that is, operations corresponding to the user request.

In addition, the memory system 110 operates in response to requests from the host 102, and stores data accessed by the host 102 in particular. In other words, the memory system 110 may be used as a main storage device or a secondary storage device of the host 102 . Here, the memory system 110 may be implemented as one of various types of storage devices according to a host interface protocol connected to the host 102 . For example, the memory system 110 may include a solid state drive (SSD), MMC, embedded MMC (eMMC), reduced size MMC (RS-MMC), and a multi-media card (MMC) in the form of micro-MMC. Multi Media Card), Secure Digital (SD) card in the form of SD, mini-SD, and micro-SD, Universal Storage Bus (USB) storage device, Universal Flash Storage (UFS) device, Compact Flash (CF) card, It may be implemented as one of various types of storage devices such as a smart media card, a memory stick, and the like.

In addition, storage devices implementing the memory system 110 include volatile memory devices such as dynamic random access memory (DRAM) and static RAM (SRAM), read only memory (ROM), mask ROM (MROM), and programmable memory devices (PROM). ROM), EPROM (erasable ROM), EEPROM (electrically erasable ROM), FRAM (ferromagnetic ROM), PRAM (phase change RAM), MRAM (magnetic RAM), RRAM (resistive RAM), flash memory, etc. can be implemented

The memory system 110 includes a memory device 150 that stores data accessed by the host 102 and a controller 130 that controls data storage into the memory device 150 .

Here, the controller 130 and the memory device 150 may be integrated into one semiconductor device. For example, the controller 130 and the memory device 150 may be integrated into a single semiconductor device to form an SSD. When the memory system 110 is used as an SSD, the operating speed of the host 102 connected to the memory system 110 may be further improved. In addition, the controller 130 and the memory device 150 may be integrated into a single semiconductor device to form a memory card. For example, a PC card (PCMCIA: Personal Computer Memory Card International Association), a compact flash card (CF) , Smart Media Card (SM, SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro), SD Card (SD, miniSD, microSD, SDHC), Universal Flash Storage (UFS), etc. can do.

In addition, as another example, the memory system 110 may be used in computers, ultra mobile PCs (UMPCs), workstations, net-books, personal digital assistants (PDAs), portable computers, and web tablets. ), tablet computer, wireless phone, mobile phone, smart phone, e-book, portable multimedia player (PMP), portable game console, navigation (navigation) devices, black boxes, digital cameras, digital multimedia broadcasting (DMB) players, 3-dimensional televisions, smart televisions, digital audio recorders recorder), digital audio player, digital picture recorder, digital picture player, digital video recorder, digital video player, data center storage constituting the network, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, and one of various electronic devices constituting a telematics network. One, a radio frequency identification (RFID) device, or one of various components constituting a computing system may be configured.

Meanwhile, the memory device 150 in the memory system 110 can maintain stored data even when power is not supplied, and in particular, stores data provided from the host 102 through a write operation and reads data. ) operation, the stored data is provided to the host 102. Here, the memory device 150 includes a plurality of memory blocks 152 , 154 , and 156 , and each of the memory blocks 152 , 154 , and 156 includes a plurality of pages, and each page , includes a plurality of memory cells to which a plurality of word lines (WL) are connected. In addition, the memory device 150 includes a plurality of planes each including a plurality of memory blocks 152, 154, and 156, and in particular, a plurality of memory dies each including a plurality of planes. may include In addition, the memory device 150 may be a non-volatile memory device, for example, a flash memory. In this case, the flash memory may have a three-dimensional stack structure.

Here, the structure of the memory device 150 and the three-dimensional stack structure of the memory device 150 will be described in detail with reference to FIGS. 2 to 4 below.

The controller 130 in the memory system 110 controls the memory device 150 in response to a request from the host 102 . For example, the controller 130 provides data read from the memory device 150 to the host 102 and stores the data provided from the host 102 in the memory device 150. To this end, the controller 130 , read, write, program, and erase operations of the memory device 150 are controlled.

More specifically, the controller 130 includes a host interface (Host I/F) unit 132, a processor 134, an error correction code (ECC) unit 138, power management A unit (PMU: Power Management Unit) 140, a memory interface (Memory I/F) unit 142, and a memory (Memory) 144 are included.

In addition, the host interface unit 132 processes commands and data of the host 102, and uses USB (Universal Serial Bus), MMC (Multi-Media Card), PCI-E (Peripheral Component Interconnect-Express) , Serial-attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), MIPI ( It may be configured to communicate with the host 102 through at least one of a variety of interface protocols, such as Mobile Industry Processor Interface). Here, the host interface unit 132 is an area that exchanges data with the host 102 and is driven through firmware called a host interface layer (HIL). can

In addition, the ECC unit 138 corrects error bits of data processed in the memory device 150 and may include an ECC encoder and an ECC decoder. Here, the ECC encoder performs error correction encoding on data to be programmed in the memory device 150 to generate data to which parity bits are added, and the data to which parity bits are added, It may be stored in the memory device 150 .

Here, the ECC unit 138, before performing the ECC decoder, in order to remove interference of the interference cell included in the data of the victim cell read from the memory device, the interference cell through hard decision. After calculating the data of the interfering cell, the symbol of the interfering cell is calculated using the data of the interfering cell, and the amount of interference is calculated only with the symbol, and then the interference of the interfering cell included in the data of the victim cell is removed by performing compensation. can If there is a lot of compensated interference, the data of the victim cell may be corrected or corrected. In this case, the row bit error rate of data is lowered, and the error rate of data that has passed through the ECC decoder that is continuously processed is also lowered.

That is, when reading data stored in the memory device 150, the ECC decoder detects and corrects an error included in the data read from the memory device 150. In other words, the ECC unit 138, after error correction decoding of the data read from the memory device 150, determines whether the error correction decoding is successful, and according to the determination result, an indication signal, for example, error correction decoding. Correction success/fail signals are output, and error bits of read data can be corrected using parity bits generated in the ECC encoding process. In this case, if the number of error bits exceeds the correctable error bit threshold, the ECC unit 138 cannot correct the error bits and may output an error correction failure signal corresponding to failure to correct the error bits.

Here, the ECC unit 138 is a low density parity check (LDPC) code, Bose, Chaudhri, Hocquenghem (BCH) code, turbo code, Reed-Solomon code, convolution Error correction can be performed using coded modulation such as convolution code, recursive systematic code (RSC), trellis-coded modulation (TCM), and block coded modulation (BCM). It is not. In addition, the ECC unit 138 may include all circuits, modules, systems, or devices for error correction.

And, the PMU (140) provides and manages the power of the controller 130, that is, the power of components included in the controller 130.

In addition, the memory interface unit 142 performs interfacing between the controller 130 and the memory device 150 so that the controller 130 controls the memory device 150 in response to a request from the host 102. It becomes a memory/storage interface. Here, the memory interface unit 142 is a NAND flash controller (NFC) when the memory device 150 is a flash memory, particularly when the memory device 150 is a NAND flash memory, and the processor 134 Under the control of , a control signal of the memory device 150 is generated and data is processed. Also, the memory interface unit 142 is an interface for processing commands and data between the controller 130 and the memory device 150, for example, operation of a NAND flash interface, in particular data between the controller 130 and the memory device 150. An area that supports input/output and exchanges data with the memory device 150 and can be driven through firmware called a Flash Interface Layer (FIL).

In addition, the memory 144 is an operation memory of the memory system 110 and the controller 130 and stores data for driving the memory system 110 and the controller 130 . More specifically, in the memory 144 , the controller 130 controls the memory device 150 in response to a request from the host 102 , for example, the controller 130 controls read from the memory device 150 Data is provided to the host 102, and the data provided from the host 102 is stored in the memory device 150. To this end, the controller 130 performs read, write, program, erase ( When an operation such as erase) is controlled, data necessary for performing such an operation between the memory system 110, that is, the controller 130 and the memory device 150, is stored.

Here, the memory 144 may be implemented as a volatile memory, and may be implemented as, for example, static random access memory (SRAM) or dynamic random access memory (DRAM). In addition, the memory 144, as shown in FIG. 1, may exist inside the controller 130 or may exist outside the controller 130, where data is received from the controller 130 through a memory interface. It may be implemented as an external volatile memory for input and output.

In addition, as described above, the memory 144 includes data required to perform operations such as writing and reading data between the host 102 and the memory device 150 and data when performing operations such as writing and reading data. and includes a program memory, a data memory, a write buffer/cache, a read buffer/cache, a data buffer/cache, a map buffer/cache, and the like for storing such data.

Also, the processor 134 controls the overall operation of the memory system 110, and in particular, controls a program operation or a read operation of the memory device 150 in response to a write request or a read request from the host 102. do. Here, the processor 134 drives firmware called a Flash Translation Layer (FTL) to control overall operations of the memory system 110 . Also, the processor 134 may be implemented as a microprocessor or a central processing unit (CPU).

For example, the controller 130 performs an operation requested from the host 102 in the memory device 150 through a processor 134 implemented as a microprocessor or a central processing unit (CPU), that is, the host ( A command operation corresponding to the command received from 102) is performed with the memory device 150. Here, the controller 130 performs a foreground operation as a command operation corresponding to a command received from the host 102, for example, a program operation corresponding to a write command, a read operation corresponding to a read command, and an erase operation. An erase operation corresponding to an erase command, a parameter set operation corresponding to a set parameter command or a set feature command, etc. may be performed with a set command.

Also, the controller 130 may perform a background operation of the memory device 150 through the processor 134 implemented as a microprocessor or a central processing unit (CPU). Here, the background operation of the memory device 150 is an operation of copying and processing data stored in an arbitrary memory block in the memory blocks 152 , 154 , and 156 of the memory device 150 to another arbitrary memory block. For example, a garbage collection (GC) operation, an operation of swapping and processing between the memory blocks 152, 154, and 156 of the memory device 150 or between data stored in the memory blocks 152, 154, and 156, for example, wear leveling ( A Wear Leveling (WL) operation, an operation of storing map data stored in the controller 130 as memory blocks 152, 154, and 156 of the memory device 150, for example, a map flush operation, or an operation in the memory device 150. An operation of bad management for the memory device 150, for example, a bad block management operation of identifying and processing bad blocks in the plurality of memory blocks 152, 154, and 156 included in the memory device 150.

In addition, the processor 134 of the controller 130 may include a management unit (not shown) for performing bad management of the memory device 150, and the management unit includes a plurality of memory devices 150. After checking the bad blocks in the memory blocks 152 , 154 , and 156 of , bad block management is performed to process the identified bad blocks as bad. Here, in the case of bad management, when the memory device 150 is a flash memory, for example, a NAND flash memory, a program failure may occur during data writing, for example, a data program, due to the characteristics of NAND. This refers to writing, ie, programming, the data for which the program has failed to a new memory block after bad processing the memory block in which the failure occurred. In addition, as described above, when the memory device 150 has a three-dimensional stack structure, if a corresponding block is treated as a bad block according to a program failure, the efficiency of use of the memory device 150 and the memory system 100 ) is rapidly degraded, it is necessary to perform more reliable bad block management. Hereinafter, a memory device in a memory system according to an embodiment of the present invention will be described in more detail with reference to FIGS. 2 to 4 .

2 schematically illustrates an example of a memory device in a memory system according to an exemplary embodiment, and FIG. 3 schematically illustrates a memory cell array circuit of memory blocks in a memory device according to an exemplary embodiment. FIG. 4 is a diagram schematically showing the structure of a memory device in a memory system according to an embodiment of the present invention, in which case the memory device is implemented as a 3D non-volatile memory device. .

First, referring to FIG. 2 , the memory device 150 includes a plurality of memory blocks, for example, block 0 (BLK (Block) 0) 210, block 1 (BLK1) 220, block 2 (BLK2) ( 230), and block N-1 (BLKN-1) 240, and each of the blocks 210, 220, 230, and 240 includes a plurality of pages, for example, 2M pages (2MPages). Here, for convenience of description, a plurality of memory blocks each including 2M pages will be described as an example, but the plurality of memories may each include M pages. Also, each page includes a plurality of memory cells to which a plurality of word lines (WL) are connected.

Also, the memory device 150 includes a plurality of memory blocks, according to the number of bits that can be stored or expressed in one memory cell, a single level cell (SLC) memory block and a multi-level cell (MLC: Multi Level Cell) can be included as a memory block. Here, the SLC memory block includes a plurality of pages implemented by memory cells that store 1-bit data in one memory cell, and has fast data operation performance and high durability. The MLC memory block includes a plurality of pages implemented by memory cells that store multi-bit data (eg, 2 bits or more bits) in one memory cell, and stores larger data than the SLC memory block. It has space, in other words, it can be highly integrated. In particular, the memory device 150 is an MLC memory block, which includes a plurality of pages implemented by memory cells capable of storing 2-bit data in one memory cell, as well as 3 pages in one memory cell. A triple level cell (TLC) memory block including a plurality of pages implemented by memory cells capable of storing bit data, and a plurality of pages implemented by memory cells capable of storing 4-bit data in one memory cell. A quadruple level cell (QLC) memory block including pages of QLC, or a multi-level including a plurality of pages implemented by memory cells capable of storing 5 bits or more bit data in one memory cell. A cell (multiple level cell) memory block may be included.

Here, in the embodiment of the present invention, for convenience of explanation, the memory device 150 is implemented as a flash memory, for example, a non-volatile memory such as a NAND flash memory, etc. as an example, but a phase change memory (PCRAM: Phase Change Random Access Memory), Resistive Random Access Memory (RRAM (ReRAM)), Ferroelectrics Random Access Memory (FRAM), and Spin Injection Magnetic Memory (STT-RAM (STT-MRAM): Spin Transfer Torque Magnetic Random Access Memory) may be implemented as any one of memories.

Each of the blocks 210 , 220 , 230 , and 240 stores data provided from the host 102 through a program operation and provides the stored data to the host 102 through a read operation.

Next, referring to FIG. 3 , in the plurality of memory blocks 152 , 154 , and 156 included in the memory device 150 of the memory system 110 , each memory block 330 is implemented as a memory cell array and bit lines BL0 to BLm-1) may include a plurality of cell strings 340 respectively connected to each other. The cell string 340 of each column may include at least one drain select transistor DST and at least one source select transistor SST. Between the selection transistors DST and SST, a plurality of memory cells or memory cell transistors MC0 to MCn-1 may be connected in series. Each of the memory cells MC0 to MCn−1 may be configured with an MLC that stores data information of a plurality of bits per cell. The cell strings 340 may be electrically connected to corresponding bit lines BL0 to BLm-1, respectively.

Here, although FIG. 3 shows each memory block 330 composed of NAND flash memory cells as an example, the plurality of memory blocks 152, 154, and 156 included in the memory device 150 according to an embodiment of the present invention are NAND flash. It is not limited to memory, but can be implemented as a NOR-type flash memory, a hybrid flash memory in which at least two or more types of memory cells are mixed, and a one-NAND flash memory in which a controller is embedded in a memory chip. In addition, the memory device 150 according to an embodiment of the present invention includes a charge trap flash (CTF) memory in which the charge storage layer is composed of an insulating film as well as a flash memory device in which the charge storage layer is composed of a conductive floating gate. It may also be implemented as a device or the like.

Also, the voltage supply unit 310 of the memory device 150 provides word line voltages (eg, program voltage, read voltage, pass voltage, etc.) to be supplied to each word line according to an operation mode, and a memory cell. A voltage to be supplied to a bulk (for example, a well region) in which these are formed may be provided, and at this time, a voltage generating operation of the voltage supply circuit 310 may be performed under the control of a control circuit (not shown). In addition, the voltage supply unit 310 may generate a plurality of variable read voltages to generate a plurality of read data, and may generate one of memory blocks (or sectors) of the memory cell array in response to a control of a control circuit. It is possible to select one of the word lines of the selected memory block, and to provide the word line voltage to the selected word line and non-selected word lines, respectively.

In addition, the read/write circuit 320 of the memory device 150 is controlled by a control circuit and operates as a sense amplifier or a write driver according to an operation mode. can For example, in the case of a verify/normal read operation, the read/write circuit 320 may operate as a sense amplifier for reading data from the memory cell array. Also, in the case of a program operation, the read/write circuit 320 may operate as a write driver that drives bit lines according to data to be stored in the memory cell array. The read/write circuit 320 may receive data to be written to the cell array from a buffer (not shown) during a program operation, and may drive bit lines according to the input data. To this end, the read/write circuit 320 includes a plurality of page buffers (PBs) 322, 324, and 326 respectively corresponding to columns (or bit lines) or column pairs (or bit line pairs). A plurality of latches (not shown) may be included in each of the page buffers 322 , 324 , and 326 .

In addition, the memory device 150 may be implemented as a two-dimensional or three-dimensional memory device, and in particular, as shown in FIG. 4, it may be implemented as a non-volatile memory device having a three-dimensional stack structure. When implemented as a structure, it may include a plurality of memory blocks BLK0 to BLKN-1. Here, FIG. 4 is a block diagram showing memory blocks 152, 154, and 156 of the memory device 150 shown in FIG. can For example, each of the memory blocks 152 , 154 , and 156 includes structures extending along the first to third directions, for example, the x-axis direction, the y-axis direction, and the z-axis direction, thereby forming a three-dimensional structure. can be implemented as

Also, each memory block 330 included in the memory device 150 may include a plurality of NAND strings NS extending along the second direction, and may include a plurality of NAND strings NS extending along the first and third directions. NAND strings NS may be provided. Here, each NAND string NS includes a bit line BL, at least one string select line SSL, at least one ground select line GSL, a plurality of word lines WL, and at least one dummy word. It may be connected to the line DWL and the common source line CSL, and may include a plurality of transistor structures TS.

That is, each memory block 330 in the plurality of memory blocks 152 , 154 , and 156 of the memory device 150 includes a plurality of bit lines BL, a plurality of string selection lines SSL, and a plurality of ground selection lines. (GSL), a plurality of word lines (WL), a plurality of dummy word lines (DWL), and a plurality of common source lines (CSL), and thus include a plurality of NAND strings (NS). can Also, in each memory block 330 , a plurality of NAND strings NS are connected to one bit line BL, so that a plurality of transistors may be implemented in one NAND string NS. In addition, the string select transistor SST of each NAND string NS may be connected to a corresponding bit line BL, and the ground select transistor GST of each NAND string NS may be connected to a common source line CSL. can be connected with Here, memory cells MC are provided between the string select transistor SST and the ground select transistor GST of each NAND string NS, that is, each memory in the plurality of memory blocks 152 , 154 , and 156 of the memory device 150 A plurality of memory cells may be implemented in block 330 .

5 is a diagram schematically illustrating a data processing operation in a memory system according to an embodiment of the present invention, and a basic data processing operation in the memory system for explaining an embodiment of the present invention will be briefly described. .

Referring to FIG. 5 , the controller may include an encoder 10, an equalizer 30, and a decoder 50.

)를 에러 정정 인코딩(error correction encoding)하여, 패리티(parity) 비트가 부가된 데이터(

)를 생성할 수 있으며, 상기 인코딩된 데이터(

)는 메모리 장치(150)에 저장될 수 있다. The encoder 10 is a message to be programmed into the memory device 150 (

) is subjected to error correction encoding, and data to which parity bits are added (

), and the encoded data (

) may be stored in the memory device 150 .

)를 요청받는 경우, 상기 컨트롤러(130)는 상기 메모리 장치(150)로부터 상기 데이터(

)를 리드할 수 있다. 그러나 상기 메모리 장치(150)로부터 리드된 상기 데이터(

)에 간섭셀에 의한 간섭 및 노이즈가 포함될 수 있다. 이하, 본 발명의 설명의 편의를 위해, 상기 데이터(

)에 간섭 및 노이즈가 포함된 데이터를 리드데이터(

)라고 명명하기라고 한다. 상기 리드데이터(

)는 상기 호스트(102)의 커맨드에 따라 상기 메모리 장치(200)로부터 리드되어 채널을 통해 상기 컨트롤러(120)의 등화기(10)에 전달되는 신호이다. 상기 리드데이터(

)는 상기 데이터(

)에 셀 간 간섭(ICI, Inter-Cell Interference) 및 소정의 잡음(AWGN, Additive White Gaussian Noise)이 부가된 신호이며, 상기 리드데이터(

)는 하기 수학식 1과 같이 나타낼 수 있다. Here, the controller 130 is the encoded data from the host (

), the controller 130 receives the data from the memory device 150 (

) can lead. However, the data read from the memory device 150 (

) may include interference and noise caused by interfering cells. Hereinafter, for convenience of description of the present invention, the data (

), the data containing interference and noise is read data (

) is called naming. The lead data (

) is a signal read from the memory device 200 according to a command of the host 102 and transmitted to the equalizer 10 of the controller 120 through a channel. The lead data (

) is the data (

) to which inter-cell interference (ICI, Inter-Cell Interference) and predetermined noise (AWGN, Additive White Gaussian Noise) are added, and the read data (

) can be expressed as in Equation 1 below.

는 상기 호스트의 커맨드에 따라 상기 메모리 장치(150)에 포함된 메모리 셀, 즉 희생셀에 저장된 원시 데이터를 의미한다. 그리고 상기

는 제

페이지의 입력 벡터를 나타내며, 상기

는 페이지의 인덱스를 의미한다. 상기

및 상기

는 상기 희생셀과 상기 희생셀에 간섭을 일으키는 간섭셀 간의 간섭 채널 가중치 및 백색 가우시안 잡음(AWGN) 벡터를 의미한다.here, above

denotes raw data stored in a memory cell included in the memory device 150, that is, a victim cell according to a command of the host. and remind

is the first

Indicates the input vector of the page,

means the index of the page. remind

and above

Means an interference channel weight and a white Gaussian noise (AWGN) vector between the victim cell and an interfering cell causing interference to the victim cell.

)로부터 심볼간 간섭신호 및 소정의 잡음을 제거하기 위해 상기 등화기(30) 및 디코더(50)를 수행할 수 있다. The controller 130 is the read data (

), the equalizer 30 and the decoder 50 may be performed to remove the inter-symbol interference signal and predetermined noise.

)를 수신하면, 상기 리드데이터(

)에 대해 등화동작을 수행할 수 있다. 상기 등화기(30)는 상기 리드데이터(

)에 대해 등화동작을 수행함으로써, 상기 리드데이터(

)로부터 셀 간 간섭 (ICI) 및 소정의 잡음을 제거할 수 있다. 즉, 상기 등화기(30)는 하드디시젼을 통해 상기 간섭셀의 데이터를 산출한 후, 상기 산출된 간섭셀의 데이터를 이용하여 희생셀에 영향을 주는 간섭양을 산출한다. 그리고 상기 등화기(30)는 상기 산출된 간섭양을 보상하므로써, 상기 리드데이터(

)로부터 간섭이 제거된 간섭제거데이터(

)를 산출할 수 있다. 그리고 상기 등화기(30)는 상기 간섭제거데이터(

)를 디코딩을 수행하기 위해, 상기 간섭제거데이터(

)를 상기 디코더에 전달한다. The equalizer 30 reads the read data from the memory device 150 (

) is received, the read data (

) can perform an equalization operation. The equalizer 30 is the read data (

) By performing an equalization operation on the read data (

) to remove inter-cell interference (ICI) and some noise. That is, the equalizer 30 calculates the data of the interference cell through hard decision, and then calculates the amount of interference affecting the victim cell using the calculated data of the interference cell. In addition, the equalizer 30 compensates for the calculated amount of interference, thereby compensating for the read data (

Interference cancellation data (with interference removed from )

) can be calculated. And the equalizer 30 is the interference cancellation data (

), the interference cancellation data (

) to the decoder.

)에 대해 에러정정동작을 수행한다. 상기 디코더(50)는 상기 간섭제거데이터(

)에 포함된 에러비트를 정정함으로써, 상기 원시데이터(

)로 복원할 수 있다.The decoder 50 receives the interference cancellation data (received from the equalizer 30)

) to perform error correction operation. The decoder 50 is the interference cancellation data (

) By correcting the error bit included in the raw data (

) can be restored.

)로부터 간섭셀에 의한 간섭을 보상하기 위한 방법에 관한 것으로, 도 6을 통해 상세히 설명하기로 한다. An embodiment of the present invention is the read data (

), which relates to a method for compensating for interference caused by an interfering cell, which will be described in detail with reference to FIG. 6.

FIG. 6 is a diagram showing a detailed configuration of the memory system shown in FIG. 5 as an example. An embodiment of the present invention will be described based on MLC storing two bits per cell based on 3D NAND, but is not limited thereto.

Referring to FIG. 6 , the memory system 110 may include the controller 130 and the memory device 150 . The controller may include an encoder 10, an equalizer 30 and a decoder 50.

)를 에러 정정 인코딩(error correction encoding)하여, 패리티(parity) 비트가 부가된 인코딩 데이터인, LSB데이터(

) 및 MSB데이터(

)를 상기 메모리 장치(150)에 전달된다. 상기 LSB데이터(

) 및 MSB데이터(

)는 상기 메모리 장치(150)에 포함된 물리페이지에 프로그램되며 상기 물리페이지에 프로그램된 데이터를 '

'라고 한다. The encoder 10 receives a message from the host (

) is encoded by error correction encoding, and parity bits are added to the encoded data, LSB data (

) and MSB data (

) is transferred to the memory device 150. The LSB data (

) and MSB data (

) is programmed into a physical page included in the memory device 150, and data programmed in the physical page is '

'.

)를 리드할 수 있다. 그러나 상기 희생셀로부터 리드한 데이터(

)에는 간섭셀에 의한 간섭 및 노이즈가 포함될 수 있다. 이하 설명의 편의를 위해, 상기 리드하고자 하는 데이터(

)에 간섭 및 노이즈가 포함된 데이터를 리드데이터(

)라고 하기로 한다. 여기서, 상기 컨트롤러(130)는 상기 리드데이터(

)로부터 상기 간섭셀에 의한 간섭을 제거하기 위해 상기 등화기(30)를 통해 간섭량을 산출하고, 산출된 간섭량을 이용하여 보상하므로써, 상기 리드데이터(

)로부터 간섭을 제거할 수 있다. 이하, 상기 컨트롤러(130)에 포함된 등화기(30)에 대해 상세히 설명하기로 한다. Before explaining the equalizer 30, the controller 130, when receiving a read command from the host 102, responds to the read command to a memory cell included in the memory device 150 (hereinafter, , data from the victim cell (Victim Cell) (

) can lead. However, data read from the victim cell (

) may include interference and noise caused by interfering cells. For convenience of description below, the data to be read (

), the data containing interference and noise is read data (

) is to be said. Here, the controller 130 is the read data (

), the amount of interference is calculated through the equalizer 30 to remove the interference caused by the interference cell, and the calculated amount of interference is used to compensate for the interference, so that the read data (

) can be removed from interference. Hereinafter, the equalizer 30 included in the controller 130 will be described in detail.

The interference equalizer 30 may include a first data conversion unit 31, an interference calculation unit 33, a compensation unit 35, and a second data conversion unit 37.

,

) 및 인접 간섭셀의 MSB 및 LSB 리드데이터(

)를 수신한다. 그리고, 상기 제1데이터 변환부(31)는 상기 메모리장치(150)로부터 수신한 상기 MSB 및 LSB 리드데이터(

)를 프로그램 상태 타입을 갖는 심볼데이터(

)로 변환하고, 상기 인접 간섭셀의 MSB 및 LSB 리드데이터(

)를 프로그램 상태를 갖는 인접심볼데이터(

)로 변환한다. 즉, MLC 낸드 플래시 메모리인 경우, 4가지의 프로그램 상태(일례로, PV0, PV1, PV2 및 PV3)를 가지기 때문에 상기 심볼데이터(

)는 상기 4가지의 프로그램 상태(PV0, PV1, PV2 및 PV3 중 하나로 변환할 수 있다.The first data conversion unit 31 converts MSB and LSB read data of the victim cell from the memory device 150 (

,

) and MSB and LSB read data of adjacent interfering cells (

) is received. And, the first data conversion unit 31 converts the MSB and LSB read data received from the memory device 150 (

) as symbol data having a program state type (

), and the MSB and LSB read data of the adjacent interference cell (

) to adjacent symbol data having a program state (

) is converted to That is, in the case of an MLC NAND flash memory, since it has four program states (eg, PV0, PV1, PV2, and PV3), the symbol data (

) can be converted to one of the four program states (PV0, PV1, PV2, and PV3).

) 및 상기 인접심볼데이터(

)를 상기 간섭산출부(33)로 전달한다.As such, the reason for converting to symbol data is that the amount of interference to be compensated for is calculated based on the program state data in order to perform an interference compensation operation. And, the first data conversion unit 31 is the symbol data (

) And the adjacent symbol data (

) is transmitted to the interference calculator 33.

,

)와 인접MSB 및 인접LSB 리드데이터(

,

)는 경판정방식(Hard Decision)을 통해 상기 메모리 장치(150)의 희생셀 및 희생셀 주변에 보상하고자 하는 모든 간섭셀이 포함된 MSB 및 LSB 페이지를 리드한 데이터이다. 상기 경판정 방식은, 소정의 기준 읽기 전압(Read Reference Voltage)을 희생셀이 포함된 워드라인에 인가하였을 때의 메모리 셀의 온/오프 특성에 따라 읽혀진 데이터이다. 일례로, 소정의 기준 전압이 R3인 경우, 제2프로그램 상태(PV2)와 제3프로그램 상태(PV3)를 구분한다. 또한, 소정의 기준 리드전압이 R3인 경우, 상기 기준 리드 전압 R3로 상기 희생셀로부터 MSB 및 LSB 리드데이터(

)를 리드할 수 있으며, 상기 간섭 셀로부터 인접MSB 및 인접LSB 리드데이터(

)를 리드할 수 있다. 여기서, 상기 희생 셀의 MSB 및 LSB 리드데이터(

)에 포함된 간섭을 제거하기 위해서는, 상기 희생 셀 주변에 존재하는 모든 간섭 셀을 리드해야 한다. 즉, 상기 간섭 셀이 포함된 MSB/LSB 페이지로부터 인접MSB 및 인접LSB 리드데이터(

)를 리드한다. 일례로, 희생셀의 데이터에 간섭을 유발시킨 간섭 셀의 개수 한 개이면, 해당 간섭 셀이 포함된 MSB/LSB 두 페이지를 리드해야 하고, 희생셀의 데이터에 간섭을 유발시킨 간섭 셀의 개수 2개이면, 각 간섭 셀이 포함된 MSB/LSB 두 페이지씩 리드하여 총 4페이지를 리드한다. Here, the MSB and LSB read data (

,

) and adjacent MSB and adjacent LSB read data (

,

) is data obtained by reading MSB and LSB pages including victim cells of the memory device 150 and all interference cells to be compensated for around the victim cells of the memory device 150 through a hard decision. The hard decision method is data read according to on/off characteristics of a memory cell when a predetermined read reference voltage is applied to a word line including a victim cell. For example, when the predetermined reference voltage is R3, the second program state PV2 and the third program state PV3 are distinguished. In addition, when the predetermined reference read voltage is R3, MSB and LSB read data (

) can be read, and the adjacent MSB and adjacent LSB read data from the interference cell (

) can lead. Here, MSB and LSB read data of the victim cell (

), all interfering cells existing around the victim cell must be read. That is, adjacent MSB and adjacent LSB read data from the MSB/LSB page including the interference cell (

) to lead. For example, if the number of interfering cells causing interference to the data of the victim cell is one, two MSB/LSB pages including the corresponding interfering cell should be read, and the number of interfering cells causing interference to the data of the victim cell is 2 , a total of 4 pages are read by reading two MSB/LSB pages including each interfering cell.

) 및 간섭셀의 상기 인접심볼데이터(

)를 수신한다. 그리고, 상기 간섭산출부(33)는 상기 간섭셀이 상기 희생셀에 영향을 주는 간섭량을 산출한다. 즉, 상기 간섭산출부(33)는 상기 희생셀의 심볼데이터(

) 및 간섭셀의 상기 인접심볼데이터(

)의 프로그램 상태에 따라 간섭량

)을 산출할 수 있다. 상기 희생셀의 심볼데이터(

) 및 간섭셀의 상기 인접심볼데이터(

)의 프로그램 상태에 따라 간섭량

)을 산출하는 방법은, 상기 희생셀의 심볼데이터(

)과 간섭셀의 상기 인접심볼데이터(

)의 프로그램 상태를 확인한 후, 룩업테이블(미도시)에서 상기 확인된 상기 희생셀의 심볼데이터(

)의 프로그램 상태(PV)와 간섭셀의 상기 인접심볼데이터(

)의 프로그램 상태(PV)에 대응하는 간섭량을 산출할 수 있다. 상기 룩업테이블(미도시)은 사전 특성 평가를 통해 얻어진 상기 메모리 장치에 포함된 모든 메모리 셀에 대한 프로그램 상태(PV) 및 상기 프로그램 상태(PV)에 따른 보상을 수행하기 위한 간섭량

)이 저장된 테이블이다. 또는 룩업테이블내의 간섭량들을 분석해서 룩업테이블 대신 간단한 수식으로 산출부를 구성할 수도 있다. 상기 간섭산출부(33)는 상기 산출된 간섭량

)을 상기 보상부(35)에 전달한다.The interference calculation unit 33 performs symbol data of the victim cell from the first data conversion unit 31 (

) and the neighboring symbol data of the interfering cell (

) is received. And, the interference calculation unit 33 calculates the amount of interference that the interference cell has an effect on the victim cell. That is, the interference calculator 33 is the symbol data of the victim cell (

) and the neighboring symbol data of the interfering cell (

) according to the program state of the interference amount

) can be calculated. Symbol data of the victim cell (

) and the neighboring symbol data of the interfering cell (

) according to the program state of the interference amount

), the symbol data of the victim cell (

) and the neighboring symbol data of the interfering cell (

After checking the program state of ), the symbol data of the victim cell checked in the lookup table (not shown) (

) of the program state (PV) and the adjacent symbol data of the interfering cell (

) can be calculated. The lookup table (not shown) is a program state (PV) of all memory cells included in the memory device obtained through preliminary characteristic evaluation and an interference amount for performing compensation according to the program state (PV)

) is the stored table. Alternatively, the calculation unit may be configured with a simple formula instead of the look-up table by analyzing the amount of interference in the look-up table. The interference calculation unit 33 calculates the amount of interference

) is transmitted to the compensation unit 35.

) 및 상기 메모리 장치로부터 희생셀 페이지데이터 (

,

) 가운데 간섭 보상이 필요한 것으로 판단되는 희생셀의 두 비트 소프트데이터인 MSB 및 LSB소프트데이터(

,

)를 수신한다. 상기 희생셀의 MSB 및 LSB소프트데이터(

,

)는 상기 희생셀이 포함된 페이지를 리드한 데이터이다. 여기서, 상기 희생셀의 MSB 및 LSB소프트데이터(

,

)를 산출하는 방법은 도 7을 참조하여 설명하기로 한다. 도 7은 본 발명의 실시예에 따른 2 비트 연판정 읽기 동작을 설명하기 위한 도면이다. 도 7을 참조하면, 상기 희생셀에 대한 MSB 및 LSB리드데이터(

,

)를 리드할 때, 제1리드전압(R3)을 기준으로 경판정 동작을 통해 리드된 데이터이다. 여기서, 상기 희생셀의 MSB 및 LSB소프트데이터(

,

)는 상기 제1리드전압(R3)을 기준으로 제2리드전압(

) 및 제3리드전압(

)을 추가하여, 상기 희생셀이 포함된 페이지를 리드한 데이터이다. 구체적으로, 상기 제2리드전압(

) 및 제3리드전압(

)으로 상기 희생셀이 포함된 페이지를 리드하는 경우, 상기 희생셀이 포함된 페이지의 모든 메모리셀들을 A영역(11), B영역(01), C영역(00) 및 D영역(10)으로 구분할 수 있다. 여기서, 간섭을 보상하기 위한 영역은 B영역(01) 및 C영역(00)이며, MSB 및 LSB소프트데이터(

,

)로 나타낼 수 있다. 이 때 B영역(01) 영역내 희생셀들은 소프트아웃풋(Cell threshold voltage)가

것으로 간주하고 간섭보상을 실시한다. 같은 방식으로 C영역(00)내의 셀들의 소프트아웃풋은

로 간주하고 후속의 간섭을 보상한다. 상기 MSB 및 LSB소프트데이터(

,

)는 후속의 디코더에서 디코딩 수행 시 적용될 수 있다.The compensation unit 35 calculates the amount of interference from the interference calculation unit 33.

) and victim cell page data from the memory device (

,

), MSB and LSB soft data, which are two-bit soft data of the victim cell determined to require interference compensation (

,

) is received. MSB and LSB soft data of the victim cell (

,

) is data obtained by reading a page including the victim cell. Here, the MSB and LSB soft data of the victim cell (

,

) will be described with reference to FIG. 7 . 7 is a diagram for explaining a 2-bit soft decision read operation according to an embodiment of the present invention. Referring to FIG. 7, MSB and LSB read data for the victim cell (

,

) is the data read through the hard decision operation based on the first read voltage R3. Here, the MSB and LSB soft data of the victim cell (

,

) is the second lead voltage (with respect to the first lead voltage R3)

) and the third lead voltage (

) is added to read the page including the victim cell. Specifically, the second lead voltage (

) and the third lead voltage (

) to read the page including the victim cell, all the memory cells of the page including the victim cell are assigned to region A 11, region B 01, region C 00, and region D 10. can be distinguished. Here, the areas for compensating for the interference are area B (01) and area C (00), and MSB and LSB soft data (

,

) can be expressed as At this time, the victim cells in area B (01) have a soft output (cell threshold voltage).

and perform interference compensation. In the same way, the soft output of cells in area C (00) is

and compensates for subsequent interference. The MSB and LSB soft data (

,

) may be applied when decoding is performed in a subsequent decoder.

) 및 상기 MSB 및 LSB소프트데이터(

,

)를 이용하여 상기 희생셀의 심볼데이터(

)로부터 간섭을 제거하여 간섭제거심볼데이터(

)를 산출할 수 있다. 상기 간섭제거심볼데이터(

)는 하기 수학식2와 같이 나타낼 수 있다.The compensating unit 35 determines the amount of interference

) and the MSB and LSB soft data (

,

), the symbol data of the victim cell (

) by removing interference from the interference removal symbol data (

) can be calculated. The interference cancellation symbol data (

) can be expressed as in Equation 2 below.

)를 상기 제2데이터변환부(37)에 전달한다.Specifically, referring to FIG. 7 , the compensation unit 35 may compensate for interference with one or more memory cells included in the B region 01 and the C region 00 . That is, in order to compensate for some cells of the B region 01, some cells of the B region 01 may be moved to the C region 00 and the D region 10. Accordingly, the program state of some cells of the B region 01 may be changed from PV2 to PV3. In addition, in order to compensate for some of the cells in area C (00), some cells in area C (00) may be moved to area A (11) and area B (01). Accordingly, the program state of some cells of the region C (00) may be changed from PV3 to PV2. And, the compensation unit 35 is the interference cancellation symbol data (

) is transmitted to the second data conversion unit 37.

)를 MSB 및 LSB간섭제거된 리드데이터(

)로 변경하여 상기 디코더(50)에 전달한다. The second data conversion unit 37 is the interference canceled symbol data received from the compensation unit 35 (

) to MSB and LSB interference-removed read data (

) and transmitted to the decoder 50.

)에 대해 디코딩을 수행한다. 이때, 상기 디코더(50)는 상기 MSB 및 LSB 소프트데이터(

,

)를 이용하여 상기 MSB 및 LSB간섭제거된 리드데이터(

)에 대해 디코딩을 수행할 수 있다. 상기 디코더(50)는 MSB 및 LSB간섭제거된 리드데이터(

)에 대해 디코딩 수행 후 상기 호스트(102)에게 간섭제거된 메세지(

)를 전달한다.The decoder 50 converts MSB and LSB interference canceled read data received from the second data conversion unit 37 (

) to perform decoding. At this time, the decoder 50 converts the MSB and LSB soft data (

,

) The MSB and LSB interference canceled read data (

) can be decoded. The decoder 50 is MSB and LSB interference canceled read data (

After performing decoding on ), the interference canceled message to the host 102 (

) is delivered.

8 is a flowchart exemplarily illustrating a method of operating a memory system according to an exemplary embodiment of the present invention.

)를 요청받는 경우, 상기 컨트롤러(130)는 상기 메모리 장치(150)로부터 상기 데이터(

)를 리드할 수 있다. 그러나 상기 컨트롤러(130)는 상기 메모리 장치(150)로부터 상기 데이터(

)를 리드할 때, 상기 데이터(

)에 간섭셀에 의한 간섭 및 노이즈가 포함될 수 있다. 이하, 본 발명의 설명의 편의를 위해, 상기 데이터(

)에 간섭 및 노이즈가 포함된 데이터를 리드데이터(

)라고 명명하기라고 한다. 상기 리드데이터(

)는 상기 호스트(102)의 커맨드에 따라 상기 메모리 장치(200)로부터 리드되어 채널을 통해 상기 컨트롤러(120)의 등화기(10)에 전달되는 신호이다. 상기 리드데이터(

)는 상기 데이터(

)에 셀 간 간섭(ICI, Inter-Cell Interference) 및 소정의 잡음(AWGN, Additive White Gaussian Noise)이 부가된 신호이며, 상기 리드데이터(

)는 하기 수학식 3과 같이 나타낼 수 있다. Prior to describing FIG. 8 , the controller 130 controls the encoded data from the host (

), the controller 130 receives the data from the memory device 150 (

) can lead. However, the controller 130 receives the data from the memory device 150 (

), the data (

) may include interference and noise caused by interfering cells. Hereinafter, for convenience of description of the present invention, the data (

), the data containing interference and noise is read data (

) is called naming. The lead data (

) is a signal read from the memory device 200 according to a command of the host 102 and transmitted to the equalizer 10 of the controller 120 through a channel. The lead data (

) is the data (

) to which inter-cell interference (ICI, Inter-Cell Interference) and predetermined noise (AWGN, Additive White Gaussian Noise) are added, and the read data (

) can be expressed as in Equation 3 below.

는 상기 호스트의 커맨드에 따라 상기 메모리 장치(150)에 포함된 메모리 셀, 즉 희생셀에 저장된 원시 데이터를 의미한다. 그리고 상기

는 제

페이지의 입력 벡터를 나타내며, 상기

는 페이지의 인덱스를 의미한다. 상기

및 상기

는 상기 희생셀과 상기 희생셀에 간섭을 일으키는 간섭셀 간의 간섭 채널 가중치 및 백색 가우시안 잡음(AWGN) 벡터를 의미한다.here, above

denotes raw data stored in a memory cell included in the memory device 150, that is, a victim cell according to a command of the host. and remind

is the first

Indicates the input vector of the page,

means the index of the page. remind

and above

Means an interference channel weight and a white Gaussian noise (AWGN) vector between the victim cell and an interfering cell causing interference to the victim cell.

)를 프로그램 상태(Program State, PV) 타입을 갖는 심볼데이터(

)로 변환하고, 상기 인접MSB 및 인접LSB 리드데이터(

)를 프로그램 상태(PV)를 갖는 인접심볼데이터(

)로 변환한다. 이와 같이, 심볼데이터로 변환하는 이유는 간섭에 대한 보상 동작을 수행하기 위해서는 프로그램 상태 데이터를 기준으로 수행하기 때문이다. 여기서, 여기서, 상기 MSB 및 LSB 리드데이터(

)와 인접MSB 및 인접LSB 리드데이터(

)는 경판정방식을 통해 상기 메모리 장치(150)의 희생셀 및 희생셀 주변에 보상하고자 하는 모든 간섭셀이 포함된 MSB 및 LSB 페이지를 리드한 데이터이다. 이와 관련하여 도 6에 상세히 설명하였기에 생략하기로 한다.Referring to FIG. 8, in step S801, the equalizer reads the MSB and LSB read data (received from the memory device 150).

) as symbol data having a program state (Program State, PV) type (

), and the adjacent MSB and adjacent LSB read data (

) to adjacent symbol data having a program state (PV) (

) is converted to In this way, the reason for conversion to symbol data is that the compensation operation for interference is performed based on the program state data. Here, the MSB and LSB read data (

) and adjacent MSB and adjacent LSB read data (

) is data obtained by reading MSB and LSB pages including the victim cell of the memory device 150 and all interference cells to be compensated for around the victim cell through the hard decision method. In relation to this, since it has been described in detail with reference to FIG. 6 , it will be omitted.

) 및 간섭셀의 상기 인접심볼데이터(

)의 프로그램 상태에 따라 간섭량

)을 산출할 수 있다. 상기 희생셀의 심볼데이터(

) 및 간섭셀의 상기 인접심볼데이터(

)의 프로그램 상태에 따라 간섭량

)을 산출하는 방법은, 상기 희생셀의 심볼데이터(

)과 간섭셀의 상기 인접심볼데이터(

)의 프로그램 상태를 확인한 후, 룩업테이블(미도시)에서 상기 확인된 상기 희생셀의 심볼데이터(

)의 프로그램 상태(PV)와 간섭셀의 상기 인접심볼데이터(

)의 프로그램 상태(PV)에 대응하는 간섭량을 산출할 수 있다. 상기 룩업테이블(미도시)은 사전 특성 평가를 통해 얻어진 상기 메모리 장치에 포함된 모든 메모리 셀에 대한 프로그램 상태(PV) 및 상기 프로그램 상태(PV)에 따른 보상을 수행하기 위한 간섭량

)이 저장된 테이블이다. In step S803, the equalizer calculates the amount of interference that the interference cell has on the victim cell. That is, the symbol data of the victim cell (

) and the neighboring symbol data of the interfering cell (

) according to the program state of the interference amount

) can be calculated. Symbol data of the victim cell (

) and the neighboring symbol data of the interfering cell (

) according to the program state of the interference amount

), the symbol data of the victim cell (

) and the neighboring symbol data of the interfering cell (

After checking the program state of ), the symbol data of the victim cell checked in the lookup table (not shown) (

) of the program state (PV) and the adjacent symbol data of the interfering cell (

) can be calculated. The lookup table (not shown) is a program state (PV) of all memory cells included in the memory device obtained through preliminary characteristic evaluation and an interference amount for performing compensation according to the program state (PV)

) is the stored table.

) 및 상기 MSB 및 LSB소프트데이터(

,

)를 이용하여 상기 희생셀의 심볼데이터(

)로부터 간섭을 제거하여 간섭제거심볼데이터(

)를 산출할 수 있다. 상기 희생셀의 MSB 및 LSB소프트데이터(

,

)는 상기 희생셀이 포함된 페이지를 리드한 데이터이다. 여기서, 상기 희생셀의 MSB 및 LSB소프트데이터(

,

)를 산출하는 방법은 도6의 보상부에서 상세히 설명하였기에 생략하기로 한다.In step S805, the compensating unit 35 determines the amount of interference

) and the MSB and LSB soft data (

,

), the symbol data of the victim cell (

) by removing interference from the interference removal symbol data (

) can be calculated. MSB and LSB soft data of the victim cell (

,

) is data obtained by reading a page including the victim cell. Here, the MSB and LSB soft data of the victim cell (

,

) is described in detail in the compensating unit of FIG. 6, so it will be omitted.

)를 디코딩하기 위해서, 이진데이터인 MSB 및 LSB간섭제거리드데이터(

)로 변경한다.In step S807, the interference cancellation symbol data from which interference has been removed (

In order to decode ), the binary data MSB and LSB interference removal read data (

) change to

9 is a diagram comparing threshold voltage distributions of a plurality of victim cells according to an embodiment of the present invention. Looking at (a) to (c) in FIG. 9, the distribution diagram before/after interference compensation from the victim cell that received interference from 4 interfering cells is shown.

)만큼 형성하면서 분포되어 있음을 보여준다.Referring to (a), (a) is a distribution diagram before interference compensation. The reason why there are multiple distribution curves is that the cell lead voltages of cells having the same condition of interference cells are grouped and represented. That is, each program state distribution is divided into a total of 256 detailed conditions by considering the 0th to 3rd program states (PV0 to PV3) of a plurality of interfering cells. Accordingly, each of the 0 to 3 program state distributions are overlapped with 256 distribution curves. In addition, a shift occurs due to other interference, and eventually the first interference range (

) shows that it is distributed while forming as much as

)가 제2간섭범위(

)만큼 감소되었음을 보여준다. 여기서, 상기 간섭을 제거하였더라도 노이즈가 남아 있기 때문에 간섭범위가 0이 아닌 제2간섭범위(

)만큼 남게 된다. (b) is a program state distribution diagram after performing an equalization operation through an embodiment of the present invention. That is, it is a distribution chart after interference compensation is performed for 256 distributions for each of the 0th to 3rd program states (PV0 to PV3), and as a result of interference compensation through an equalization operation, the first interference range (

) is the second interference range (

) is reduced by Here, even if the interference is removed, since the noise remains, the interference range is not 0 in the second interference range (

) will remain.

(c) is a diagram showing cumulatively divided distributions for the 0th to 3rd program states (PV0 to PV3) in (a) and (b). That is, looking at (b) and (c), it can be seen that when the interference from the victim cell to the interfering cell is compensated for according to an embodiment of the present invention, the overlapping portion of the program state distribution is significantly lowered.

FIG. 10 shows the degree to which the overlap of Vth distributions of each program state (PV) cell is lowered before and after compensation for interference, which is confirmed in , according to an embodiment of the present invention, based on Raw Data error. The error standard sets the error occurred in PV3 as 100 by the read voltage 3(R3) standard where the error occurs the most, and the error caused by the read voltage 2 in PV1(P1) and PV2(P2) is compensated for before and after each error. The degree of rate improvement was indicated. Referring to Figure 4, it can be seen that the error of P3 by R3, which has the greatest improvement, is improved by about 50%.

Hereinafter, referring to FIGS. 11 to 19 , a data processing system to which the memory system 110 including the memory device 150 and the controller 130 described in FIGS. 1 to 10 according to an embodiment of the present invention is applied. And electronic devices will be described in more detail.

11 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment of the present invention. Here, FIG. 11 is a diagram schematically illustrating a memory card system to which a memory system according to an embodiment of the present invention is applied.

Referring to FIG. 11 , a memory card system 6100 includes a memory controller 6120, a memory device 6130, and a connector 6110.

More specifically, the memory controller 6120 is connected to a memory device 6130 implemented as a non-volatile memory and is implemented to access the memory device 6130 . For example, the memory controller 6120 is implemented to control read, write, erase, and background operations of the memory device 6130 . Also, the memory controller 6120 is implemented to provide an interface between the memory device 6130 and a host, and is implemented to drive firmware for controlling the memory device 6130 . That is, the memory controller 6120 corresponds to the controller 130 in the memory system 110 described with reference to FIG. 1 , and the memory device 6130 corresponds to the memory device 150 in the memory system 110 described with reference to FIG. 1 . ) can correspond to

Accordingly, the memory controller 6120 includes components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction unit.

In addition, the memory controller 6120 may communicate with an external device, for example, the host 102 described in FIG. 1 , through the connector 6110 . For example, as described in FIG. 1 , the memory controller 6120 is a universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI express (PCIe), ATA ( Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer small interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI It may be configured to communicate with an external device through at least one of various communication standards such as , Bluetooth, etc., and accordingly, a memory system and a data processing system according to an embodiment of the present invention, such as wired / wireless electronic devices, particularly mobile electronic devices. this may apply.

In addition, the memory device 6130 is implemented as a non-volatile memory, for example, EPROM (Electrically Erasable and Programmable ROM), NAND flash memory, NOR flash memory, PRAM (Phase-change RAM), ReRAM (Resistive RAM), FRAM (Ferroelectric RAM), STT-MRAM (Spin-Torque Magnetic RAM), and the like.

In addition, the memory controller 6120 and the memory device 6130 may be integrated into a single semiconductor device, and for example, may be integrated into a single semiconductor device to form a solid state drive (SSD). PC Card (PCMCIA), Compact Flash Card (CF), Smart Media Card (SM, SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro, eMMC), SD Card (SD, miniSD, microSD, SDHC) , a memory card such as a universal flash memory (UFS).

12 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment of the present invention. Referring to FIG. 12 , the data processing system 6200 includes a memory device 6230 implemented with at least one non-volatile memory and a memory controller 6220 that controls the memory device 6230 . Here, the data processing system 6200 shown in FIG. 15 may be a storage medium such as a memory card (CF, SD, microSD, etc.) or a USB storage device, as described in FIG. 1, and a memory device 6230 ) may correspond to the memory device 150 in the memory system 110 described in FIG. 1 , and the memory controller 6220 may correspond to the controller 130 in the memory system 110 described in FIG. 1 . .

The memory controller 6220 controls read, write, and erase operations of the memory device 6230 in response to a request from the host 6210, and the memory controller 6220 controls at least one CPU 6221 , a buffer memory such as RAM 6222, an ECC circuit 6223, a host interface 6224, and a memory interface such as NVM interface 6225.

Here, the CPU 6221 may control overall operations of the memory device 6230, such as reading, writing, file system management, bad page management, and the like. The RAM 6222 operates under the control of the CPU 6221 and may be used as a work memory, buffer memory, cache memory, or the like. Here, when the RAM 6222 is used as a work memory, data processed by the CPU 6221 is temporarily stored, and when the RAM 6222 is used as a buffer memory, the memory device 6230 in the host 6210 ) or for buffering data transmitted from the memory device 6230 to the host 6210, and when the RAM 6222 is used as a cache memory, the low-speed memory device 6230 can be used to operate at high speed. there is.

In addition, the ECC circuit 6223 corresponds to the ECC unit 138 of the controller 130 described in FIG. 1, and as described in FIG. 1, the fail bit of the data received from the memory device 6230 Alternatively, an Error Correction Code (ECC) for correcting an error bit is generated. In addition, the ECC circuit 6223 performs error correction encoding on data provided to the memory device 6230 to form data to which parity bits are added. Here, parity bits may be stored in the memory device 6230. In addition, the ECC circuit 6223 may perform error correction decoding on data output from the memory device 6230, and in this case, the ECC circuit 6223 may correct errors using parity. For example, as described in FIG. 1, the ECC circuit 6223 uses various coded modulations such as LDPC code, BCH code, turbo code, Reed-Solomon code, convolution code, RSC, TCM, and BCM. so you can correct the error.

The memory controller 6220 transmits and receives data to and from the host 6210 through the host interface 6224 and transmits and receives data to and from the memory device 6230 through the NVM interface 6225. Here, the host interface 6224 may be connected to the host 6210 through a PATA bus, SATA bus, SCSI, USB, PCIe, NAND interface, or the like. In addition, the memory controller 6220 implements WiFi or Long Term Evolution (LTE) as a wireless communication function and mobile communication standard, and is connected to an external device, for example, the host 6210 or an external device other than the host 6210. Afterwards, it is possible to transmit and receive data, etc., and in particular, as it is configured to communicate with an external device through at least one of various communication standards, wired/wireless electronic devices, particularly mobile electronic devices, etc., the memory system according to an embodiment of the present invention and a data processing system may be applied.

13 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment of the present invention. Here, FIG. 13 is a diagram schematically illustrating a solid state drive (SSD) to which a memory system according to an embodiment of the present invention is applied.

Referring to FIG. 13 , an SSD 6300 includes a memory device 6340 including a plurality of nonvolatile memories and a controller 6320 . Here, the controller 6320 corresponds to the controller 130 in the memory system 110 described with reference to FIG. 1 , and the memory device 6340 corresponds to the memory device 150 in the memory system 110 described with reference to FIG. 1 . can correspond to

More specifically, the controller 6320 is connected to the memory device 6340 through a plurality of channels CH1, CH2, CH3, ??, CHi. The controller 6320 includes at least one processor 6321, a buffer memory 6325, an ECC circuit 6322, a host interface 6324, and a memory interface, for example, a non-volatile memory interface 6326.

Here, the buffer memory 6325 temporarily stores data received from the host 6310 or data received from a plurality of flash memories (NVMs) included in the memory device 6340, or a plurality of flash memories (NVMs). ) of meta data, for example, map data including a mapping table is temporarily stored. In addition, the buffer memory 6325 may be implemented with volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM. It exists inside the controller 6320 for convenience, but may also exist outside the controller 6320.

In addition, the ECC circuit 6322 calculates an error correction code value of data to be programmed into the memory device 6340 in a program operation, and converts the data read from the memory device 6340 into an error correction code value in a read operation. to perform an error correction operation, and in a recovery operation of failed data, an error correction operation of data recovered from the memory device 6340 is performed.

In addition, the host interface 6324 provides an interface function with an external device, for example, the host 6310, and the non-volatile memory interface 6326 provides an interface function with a memory device 6340 connected through a plurality of channels. do.

In addition, a plurality of SSDs 6300 to which the memory system 110 described in FIG. 1 is applied may be applied to implement a data processing system, for example, a RAID (Redundant Array of Independent Disks) system. At this time, the RAID system includes a plurality of SSDs. 6300 and a RAID controller controlling the plurality of SSDs 6300 may be included. Here, when the RAID controller receives a write command from the host 6310 and performs a program operation, data corresponding to the write command is stored in a plurality of RAID levels, that is, a plurality of SSDs 6300 in the host 6310. Corresponding to the RAID level information of the write command received from ), after selecting at least one memory system, that is, the SSD 6300, the output may be output to the selected SSD 6300. In addition, when the RAID controller receives a read command from the host 6310 and performs a read operation, a plurality of RAID levels, that is, a RAID level of the read command received from the host 6310 in the plurality of SSDs 6300. Corresponding to the information, after selecting at least one memory system, that is, the SSD 6300 , data may be provided to the host 6310 from the selected SSD 6300 .

14 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment of the present invention. Here, FIG. 18 is a diagram schematically illustrating an embedded multimedia card (eMMC) to which a memory system according to an embodiment of the present invention is applied.

Referring to FIG. 14 , the eMMC 6400 includes a memory device 6440 implemented with at least one NAND flash memory and a controller 6430 . Here, the controller 6430 corresponds to the controller 130 in the memory system 110 described with reference to FIG. 1 , and the memory device 6440 corresponds to the memory device 150 in the memory system 110 described with reference to FIG. 1 . can correspond to

More specifically, the controller 6430 is connected to the memory device 2100 through a plurality of channels. Also, the controller 6430 includes at least one core 6432, a host interface 6431, and a memory interface such as a NAND interface 6433.

Here, the core 6432 controls the overall operation of the eMMC 6400, the host interface 6431 provides an interface function between the controller 6430 and the host 6410, and the NAND interface 6433 provides memory Provides an interface function between the device 6440 and the controller 6430. For example, as described in FIG. 1, the host interface 6431 may be a parallel interface, for example, an MMC interface, and a serial interface, for example, UHS ((Ultra High Speed)-I/UHS-II?, UFS can be an interface.

15 to 18 are diagrams schematically illustrating another example of a data processing system including a memory system according to an embodiment of the present invention. Here, FIGS. 19 to 22 are diagrams schematically illustrating a universal flash storage (UFS) to which a memory system according to an embodiment of the present invention is applied.

15 to 18, each of the UFS systems 6500, 6600, 6700, and 6800 includes hosts 6510, 6610, 6710, and 6810, UFS devices 6520, 6620, 6720, and 6820, and UFS cards 6530, 6630, 6730, and 6830, respectively. Here, each of the hosts 6510, 6610, 6710, and 6810 may be an application processor of wired/wireless electronic devices, particularly mobile electronic devices, and each of the UFS devices 6520, 6620, 6720, and 6820 ) becomes embedded UFS (Embedded UFS) devices, and each UFS card (6530, 6630, 6730, 6830) is an external embedded UFS (External Embedded UFS) device or a removable UFS card It can be.

In addition, in each of the UFS systems (6500, 6600, 6700, and 6800), each of the hosts (6510, 6610, 6710, and 6810), UFS devices (6520, 6620, 6720, and 6820), and UFS cards (6530). , 6630, 6730, and 6830) can communicate with external devices, such as wired/wireless electronic devices, particularly mobile electronic devices, through the UFS protocol, respectively, and the UFS devices (6520, 6620, 6720, and 6820) and the UFS cards 6530 , 6630 , 6730 , and 6830 may be implemented as the memory system 110 described in FIG. 1 . For example, in each of the UFS systems 6500, 6600, 6700, and 6800, the UFS devices 6520, 6620, 6720, and 6820 include the data processing system 6200, SSD 6300, Alternatively, it may be implemented in the form of the eMMC 6400, and the UFS cards 6530, 6630, 6730, and 6830 may be implemented in the form of the memory card system 6100 described in FIG. 11.

In addition, in each of the UFS systems (6500, 6600, 6700, and 6800), each of the hosts (6510, 6610, 6710, and 6810), UFS devices (6520, 6620, 6720, and 6820), and UFS cards (6530). ,6630,6730,6830) can perform communication through a Universal Flash Storage (UFS) interface, such as MIPI M-PHY and MIPI UniPro (Unified Protocol) in MIPI (Mobile Industry Processor Interface), and also UFS Devices 6520, 6620, 6720, 6820 and UFS cards 6530, 6630, 6730, 6830 may communicate through protocols other than the UFS protocol, for example, various card protocols, for example UFDs and MMC. , SD (secure digital), mini SD, Micro SD, etc.

In the UFS system 6500 shown in FIG. 15, UniPro exists in the host 6510, the UFS device 6520, and the UFS card 6530, respectively, and the host 6510 has a UFS device 6520 and the UFS card 6530, respectively, to perform a switching operation, and in particular, the host 6510, through Link Layer switching in UniPro, for example, L3 switching, UFS device ( 6520) or performs communication with the UFS card 6530. At this time, communication may be performed between the UFS device 6520 and the UFS card 6530 through link layer switching in UniPro of the host 6510. Here, in the embodiment of the present invention, for convenience of explanation, one UFS device 6520 and one UFS card 6530 are connected to the host 6510 as an example, but a plurality of UFS devices and UFS cards may be connected to the host 6410 in parallel or star form, and a plurality of UFS cards may be connected to the UFS device 6520 in parallel or star form, or may be connected in series or chain form. .

In addition, in the UFS system 6600 shown in FIG. 16, the host 6610, the UFS device 6620, and the UFS card 6630 each have a UniPro, and a switching module 6640 that performs a switching operation; In particular, the host 6610 communicates with the UFS device 6620 or the UFS card 6630 through the switching module 6640 that performs link layer switching in UniPro, for example, L3 switching operation. . At this time, communication may be performed between the UFS device 6520 and the UFS card 6530 through link layer switching in the UniPro of the switching module 6640. Here, in the embodiment of the present invention, for convenience of description, it has been described that one UFS device 6620 and one UFS card 6630 are connected to the switching module 6640 as an example, but a plurality of UFS devices and UFS cards may be connected to the switching module 6640 in parallel or star form, and a plurality of UFS cards may be connected to the UFS device 6620 in parallel or star form, or may be connected in series or chain form. may be

In addition, in the UFS system 6700 shown in FIG. 17, the host 6710, the UFS device 6720, and the UFS card 6730 each have a UniPro, a switching module 6740 that performs a switching operation, In particular, the host 6710 communicates with the UFS device 6720 or the UFS card 6730 through the switching module 6740 that performs link layer switching in UniPro, for example, L3 switching operation. . At this time, communication may be performed between the UFS device 6720 and the UFS card 6730 through link layer switching in the UniPro of the switching module 6740, and the switching module 6740 may perform communication between the UFS device 6720 and the UFS card 6730. It can be implemented internally or externally as a single module with the UFS device 6720. Here, in the embodiment of the present invention, for convenience of explanation, it has been described that one UFS device 6620 and one UFS card 6630 are connected to the switching module 6740 as an example, but the switching module 6740 A plurality of modules each implemented with the UFS device 6720 may be connected to the host 6710 in a parallel form or star form, or may be connected in a series form or chain form between individual modules, and a plurality of UFS cards It may be connected to the switching module 6740 in a parallel or star fashion.

In the UFS system 6800 shown in FIG. 18, M-PHY and UniPro exist in the host 6810, the UFS device 6820, and the UFS card 6830, respectively, and the UFS device 6820, A switching operation is performed to communicate with the host 6810 and the UFS card 6830, respectively. In particular, the UFS device 6820 includes an M-PHY and UniPro module for communication with the host 6810 and a UFS card. Communication with the host 6810 or communication with the UFS card 6830 is performed between the M-PHY and the UniPro module for communication with the 6830, through switching, for example, target ID (identifier) switching. . At this time, communication may be performed between the host 6810 and the UFS card 6530 through target ID switching between the M-PHY and the UniPro module of the UFS device 6820. Here, in the embodiment of the present invention, for convenience of description, one UFS device 6820 is connected to the host 6810, and one UFS card 6830 is connected to one UFS device 6820. Although this has been described as an example, a plurality of UFS devices may be connected to the host 6810 in parallel or star form, or may be connected in series or chain form, and a plurality of UFS cards may be connected to one UFS device 6820 in parallel form. Alternatively, they may be connected in star form or in series or chain form.

19 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment of the present invention. Here, FIG. 23 is a diagram schematically showing a user system to which a memory system according to the present invention is applied.

Referring to FIG. 19 , a user system 6900 includes an application processor 6930, a memory module 6920, a network module 6940, a storage module 6950, and a user interface 6910.

More specifically, the application processor 6930 drives components included in the user system 6900 and an operating system (OS), and for example, the components included in the user system 6900 It may include controlling controllers, interfaces, graphic engines, and the like. Here, the application processor 6930 may be provided as a System-on-Chip (SoC).

Also, the memory module 6920 may operate as a main memory, working memory, buffer memory, or cache memory of the user system 6900 . Here, the memory module 6920 is a volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR3 SDRAM, LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, FRAM, etc. may contain memory. For example, the application processor 6930 and the memory module 6920 may be packaged and mounted based on POP (Package on Package).

Also, the network module 6940 may communicate with external devices. For example, the network module 6940 not only supports wired communication, but also code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiplex (TDMA) Access), LTE (Long Term Evolution), Wimax, WLAN, UWB, Bluetooth, WI-DI, etc., it is possible to perform communication with wired/wireless electronic devices, especially mobile electronic devices. Accordingly, the memory system and the data processing system according to an embodiment of the present invention may be applied to wired/wireless electronic devices. Here, the network module 6940 may be included in the application processor 6930.

In addition, the storage module 6950 may store data, for example, data received from the application processor 6930, and then transmit the data stored in the storage module 6950 to the application processor 6930. Here, the storage module 6950 may be implemented with non-volatile memory such as PRAM (Phasechange RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), NAND flash, NOR flash, 3D NAND flash, etc. , may also be provided as a removable storage medium such as a memory card or an external drive of the user system 6900. That is, the storage module 6950 may correspond to the memory system 110 described in FIG. 1 , and may also be implemented with the SSD, eMMC, or UFS described in FIGS. 13 to 18 .

Also, the user interface 6910 may include interfaces for inputting data or commands to the application processor 6930 or outputting data to an external device. For example, the user interface 6910 may include user input interfaces such as a keyboard, keypad, button, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, piezoelectric element, and the like. , and user output interfaces such as LCD (Liquid Crystal Display), OLED (Organic Light Emitting Diode) display devices, AMOLED (Active Matrix OLED) display devices, LEDs, speakers, motors, and the like.

In addition, when the memory system 110 described in FIG. 1 according to an embodiment of the present invention is applied to the mobile electronic device of the user system 6900, the application processor 6930 controls overall operations of the mobile electronic device, The network module 6940, as a communication module, controls wired/wireless communication with an external device as described above. In addition, the user interface 6910 displays data processed by the application processor 6930 as a display/touch module of the mobile electronic device or supports data input from the touch panel.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments and should not be defined by the scope of the following claims as well as those equivalent to the scope of these claims.

102 Host 130 Controller
10: encoder 30: equalizer
31: first data conversion unit 33: interference calculation unit
35: compensation unit 37: second data conversion unit
50: decoder 150: memory device

Claims (15)

A memory including a plurality of blocks each including a host and a plurality of pages, a plurality of planes each including the blocks, and a plurality of dies each including the planes A memory system comprising a device and a controller controlling the memory device,
a first data converter for converting first data read from the first memory cell into first symbol data and converting second data read from the second memory cell into second symbol data;
an interference calculating unit which calculates an amount of interference between the first symbol data and the second symbol data;
a compensation unit calculating first interference cancellation symbol data by removing interference from the first symbol data using the amount of interference and third data read from the first memory cell; and
and a second data conversion unit converting the first interference cancellation symbol data into first interference cancellation data.
According to claim 1,
The first data is 2-bit data obtained by reading data stored in the first memory cell through hard decision, and the second data is 2-bit data obtained by reading data stored in the second memory cell through hard decision. A memory system that contains data.
According to claim 1,
The first data,
A memory system including interference between the first memory cell and the second memory cell (ICI, Inter-Cell Interference) and predetermined noise (AWGN, Additive White Gaussian Noise).
According to claim 1,
The first symbol data and the second symbol data,
A memory system in which the first data and the second data are converted into program state types.
According to claim 1,
The interference calculation unit,
After checking the program states of the first symbol data and the second symbol data, the memory system calculates the amount of interference corresponding to the checked program states of the first symbol data and the second symbol data in the lookup table.
According to claim 5,
The lookup table is
A memory system in which a program state (PV) of all memory cells included in the memory device obtained through evaluation of all characteristics is stored and an amount of interference for performing compensation according to the program state is stored.
According to claim 1,
The third data,
As 2-bit soft data obtained by reading the data stored in the first memory cell through a soft decision, the second reference voltage and the third reference voltage are based on the first reference voltage applied when the first data is read through a hard decision. The memory system is data indicating an overlapping area when a reference voltage is added and read with the second reference voltage and the third reference voltage.
According to claim 1,
The compensation part,
The memory system calculates first interference cancellation symbol data by compensating for the amount of interference from the first symbol data through the amount of interference received from the interference calculation unit and the third data.
A memory including a plurality of blocks each including a host and a plurality of pages, a plurality of planes each including the blocks, and a plurality of dies each including the planes A method of operating a memory system comprising a device and a controller controlling the memory device,
converting first data read from the first memory cell into first symbol data and converting second data read from the second memory cell into second symbol data;
calculating an amount of interference between the first symbol data and the second symbol data;
calculating first interference cancellation symbol data obtained by removing interference from the first symbol data using the amount of interference and third data read from the first memory cell; and
converting the first interference elimination symbol data into first interference elimination data;
A memory system operation method comprising a.
According to claim 9,
The first data is 2-bit data obtained by reading data stored in the first memory cell through hard decision, and the second data is 2-bit data obtained by reading data stored in the second memory cell through hard decision. A method of operating a memory system containing data. According to claim 9,
The first data,
The method of operating a memory system including interference between the first memory cell and the second memory cell (ICI, Inter-Cell Interference) and predetermined noise (AWGN, Additive White Gaussian Noise).
According to claim 9,
The first symbol data and the second symbol data,
A method of operating a memory system in which the first data and the second data are converted into program state types.
According to claim 9,
In the step of calculating the amount of interference,
After checking the program state of the first symbol data and the second symbol data, the memory system operation method of calculating the amount of interference corresponding to the checked program state of the first symbol data and the second symbol data in a lookup table .
According to claim 13,
The lookup table is
A method of operating a memory system in which a program state (PV) of all memory cells included in the memory device obtained through evaluation of all characteristics and an interference amount for performing compensation according to the program state are stored.
According to claim 9,
The third data,
As 2-bit soft data obtained by reading the data stored in the first memory cell through a soft decision, the second reference voltage and the third reference voltage are based on the first reference voltage applied when the first data is read through a hard decision. The method of operating a memory system, which is data representing an overlapping area when a reference voltage is added and read with the second reference voltage and the third reference voltage.

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