KR102530074B1 - Display driving circuit and operating method thereof - Google Patents

Abstract

A display driving circuit and a display device including the same are disclosed. A display driving circuit according to an embodiment of the present disclosure includes a first amplifier driving a first data line of a display panel based on first pixel data and driving a second data line of the display panel based on second pixel data. and a second amplifier that operates when the data value representing one gray level between the first pixel data and the second pixel data is greater than or equal to a first threshold value, the second amplifier is turned off, and the first amplifier The first data line and the second data line may be driven based on the first pixel data and the second pixel data.

Description

Display driving circuit and operating method thereof {Display driving circuit and operating method thereof}

The technical concept of the present disclosure relates to a semiconductor device, and more particularly, to a display driving circuit and an operating method for driving a display panel to display an image on the display panel.

A display device includes a display panel for displaying images and a display driving circuit for driving the display panel. The display driving circuit may drive the display panel by receiving image data from an external host and applying an image signal corresponding to the received image data to a data line of the display panel. Recently, as the size and resolution of display panels increase, various technologies capable of reducing power consumption of display driving circuits are being researched.

An object to be solved by the technical idea of the present disclosure is to provide a display driving circuit and a method of operating the display driving circuit with reduced static power consumption.

A display driving circuit according to an embodiment of the present disclosure for achieving the above technical problem includes a first amplifier driving a first data line of a display panel based on first pixel data, and a display panel based on second pixel data. and a second amplifier for driving a second data line of , and when a first data difference between the first pixel data and the second pixel data is equal to or greater than a data value representing one gray level and equal to or less than a first threshold value, the first data line is equal to or greater than a first threshold value. 2 The amplifier may be turned off, and the first amplifier may drive the first data line and the second data line based on the first pixel data and the second pixel data.

A display driving circuit according to an embodiment of the present disclosure for achieving the above technical problem includes a first amplifier driving a first data line of a display panel based on first pixel data, and a display panel based on second pixel data. The first data difference between the first pixel data and the second pixel data is 1 in the first horizontal driving period in the second amplifier driving the second data line of and the low power operation mode. or more and less than or equal to the horizontal threshold value N (N is a positive integer), the first amplifier selected from among the first amplifier and the second amplifier is turned on and the other amplifier is turned off. and a controller controlling the second amplifier.

A method of operating a display driving circuit according to an embodiment of the present disclosure for achieving the above technical problem includes calculating, by a controller, a first data difference between first pixel data and second pixel data; Comparing the difference with a horizontal threshold, and if the first data difference is less than or equal to the horizontal threshold, a first amplifier performs a first data line and a second data line of the display panel based on the first pixel data and the second pixel data. It may include driving 2 data lines.

In a display driving circuit and a method of operating the display driving circuit according to the technical idea of the present disclosure, when a data difference between two pixel data corresponding to two adjacent pixels is less than or equal to a threshold value, one amplifier drives the two pixels and the other amplifier drives the display driving circuit. is turned off, thereby reducing static current consumption.

In addition, a display driving circuit and a method of operating the display driving circuit according to the technical idea of the present disclosure include driving two data lines respectively connected to two pixels at the same time by one amplifier during a horizontal driving period, and then additionally driving one data line. , two pixels can be driven without increasing the horizontal driving period.

In order to more fully understand the drawings cited in the detailed description of the present disclosure, a brief description of each drawing is provided.
1 is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure.
2 is a circuit diagram schematically illustrating a display driving circuit according to an exemplary embodiment of the present disclosure.
FIG. 3 is a circuit diagram illustrating the operation of a display driver when the display driving circuit of FIG. 2 operates in a normal mode.
4A and 4B are circuit diagrams illustrating coarse and fine driving of a data driver when the display driving circuit of FIG. 2 operates in a low power mode.
5 is a timing diagram illustrating operations of the data driver of FIGS. 4A and 4B.
6 is a circuit diagram illustrating an implementation example of a pixel included in a display panel.
7A is a circuit diagram illustrating an implementation example of a data driver according to an embodiment of the present disclosure, and FIGS. 7B and 7C are circuit diagrams illustrating an operation of the data driver of FIG. 7A.
8A is a circuit diagram illustrating an implementation example of a data driver according to an embodiment of the present disclosure, and FIGS. 8B and 8C are circuit diagrams illustrating an operation of the data driver of FIG. 8A.
9 is a timing diagram illustrating an operation example of the display driving circuit of FIG. 2 .
10 is a timing diagram illustrating an operation example of the display driving circuit of FIG. 2 .
11 is a timing diagram illustrating an operation example of a display driving circuit according to an embodiment of the present disclosure.
12 is a timing diagram illustrating an operation of a display driving circuit according to setting of a vertical threshold.
13 is a block diagram illustrating an implementation example of control logic according to an embodiment of the present disclosure.
14 is a diagram showing gamma characteristics of an OLED panel.
15 is a flowchart illustrating an operating method of the threshold value determiner of FIG. 13 .
16 is a flowchart illustrating an operating method of a display driving circuit according to an exemplary embodiment of the present disclosure.
17 is a flowchart illustrating an operating method of a display driving circuit according to an embodiment of the present disclosure.
18 is a block diagram illustrating a display driving circuit according to an exemplary embodiment of the present disclosure.
19 is a diagram illustrating one implementation example of a data driver and a pentile-structured display panel according to an embodiment of the present disclosure.

Hereinafter, various embodiments of the present disclosure will be described in conjunction with the accompanying drawings.

A display device according to various embodiments of the present disclosure may be mounted in an electronic device having an image display function. For example, the electronic device includes a smartphone, a tablet personal computer (PC), a portable multimedia player (PMP), a camera, a wearable device, a television, a digital video disk (DVD) player, Refrigerators, air conditioners, air purifiers, set-top boxes, various medical devices, navigation devices, GPS receivers (global positioning system receivers), vehicle devices, furniture, or various measuring devices may be included.

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure. Referring to FIG. 1 , a display device 1000 may include a display panel 100 and a display driving circuit 500 . The display driving circuit 500 drives the display panel 100 and may include a timing controller 200 , a data driver 300 and a scan driver 400 .

The display panel 100 includes a plurality of pixels PXs arranged in a matrix form, and may display an image in units of frames. The display panel 100 includes a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, an active-matrix OLED (AMOLED) display, an electrochromic display (ECD), a digital mirror device (DMD), It can be implemented as one of AMD (Actuated Mirror Device), GLV (Grating Light Valve), PDP (Plasma Display Panel), ELD (Electro Luminescent Display), VFD (Vacuum Fluorescent Display), and other types of flat panel displays or flexible It can be implemented as a display. For convenience of description, an OLED panel will be described below as an example in describing the present invention.

The display panel 100 includes scan lines SL1 to SLn (or gate lines) arranged in a row direction, data lines DL1 to DLm arranged in a column direction, and scan lines SL1 to SLn. ) and the pixels PXs formed at intersections of the data lines DL1 to DLm. In this case, among the pixels PX, some pixels PX connected to the same scan line, having different colors, and adjacent to each other may constitute a unit pixel. In this case, each of the some pixels PX is referred to as a sub-pixel. It can be.

The display panel 100 includes a plurality of horizontal lines (or rows), and one horizontal line is composed of pixels PXs connected to one scan line. For example, the pixels PX11 to PX1m of the first row connected to the first scan line SL1 constitute a first horizontal line, and the pixels PX21 to PX2m of the second row connected to the second scan line SL2 constitute a first horizontal line. This second horizontal line can be constituted.

During the horizontal driving period, the pixels PX of one horizontal line are driven, and during the next horizontal driving period, the pixels PX of the other horizontal line are driven. For example, during the first horizontal drive period, the pixels PX11 to PX1m of the first horizontal line may be driven, and then, during the second horizontal drive period, the pixels PX21 to PX2m of the second horizontal line may be driven. . As such, during the first through nth horizontal driving periods, the pixels PX of the display panel 100 may be driven.

The scan driver 400 supplies a scan clock (or referred to as a gate-on signal) to the scan lines SL1 to SLn in response to the scan driver control signal CTRL1 provided from the timing controller 200 to perform scan, The lines SL1 to SLn can be selected. According to the scan clock output from the scan driver 400, one of the scan lines SL1 to SLn is selected, and the pixels PXs of the horizontal line corresponding to the selected scan line are connected to the data lines DL1. A display operation may be performed by applying a pixel signal (or referred to as an image signal) corresponding to each of the pixels PX through ~DLm). In an embodiment, the scan lines SL1 to SLn may be sequentially or non-sequentially selected.

In response to the data driver control signal CTRL2, the data driver 300 converts the image data DATA to analog signal pixel signals (eg, pixels corresponding to each of the pixel data PD1, PD2, ..., PDm). The data lines DL1 to DLm may be driven by converting the pixel signals into grayscale voltages or currents corresponding to the respective grayscale voltages and providing the pixel signals to the data lines DL1 to DLm. For example, the data driver 300 may charge the data lines DL1 to DLm based on pixel signals. The data driver 300 may provide pixel signals of one line to the data lines DL1 to DLm during one horizontal driving period. Then, when the scan clock is provided, pixel signals may be provided to the pixels PXs of the horizontal line corresponding to the selected scan line through the data lines DL1 to DLm.

The data driver 300 may include a plurality of amplifiers SA1 to SAm, and each of the plurality of amplifiers SA1 to SAm may provide a pixel signal to at least one corresponding data line. An amplifier may be referred to as a channel amplifier or a source amplifier. According to the pixel data PD1 to PDm, some of the plurality of amplifiers SA1 to SAm may be turned off and other amplifiers may be turned on. Some amplifiers turned on can drive two data lines. In the present disclosure, driving a data line may be used as the same meaning as driving a pixel connected to a data line.

For example, when the data driver 300 drives the pixels PX21 to PX2m of the second horizontal line in the second horizontal driving period, the first pixel data PD1 corresponding to the pixel PX21 and the pixel PX22 When the data of the second pixel data PD2 to be generated is the same or the data difference is less than or equal to a preset first threshold value, one of the first and second amplifiers SA1 and SA2 is turned off. , the other one drives the first data line DL1 and the second data line DL2 in the second horizontal driving period, thereby driving the pixels PX21 and PX22. Since the first threshold is compared with a data difference between two pixel data corresponding to two pixels on the same horizontal line, the first threshold will be referred to as a horizontal threshold.

In an embodiment, if the two pixel data are different and the data difference between the two pixel data is equal to or less than a preset horizontal threshold, an amplifier that is turned on among the two amplifiers coarse-wires the two data lines based on one of the two pixel data. After coarse driving, one data line corresponding to the pixel data of the other of the two data lines may be fine driven based on the other one of the two pixel data. Accordingly, one amplifier can simultaneously drive two pixels respectively connected to two data lines. For example, when the first amplifier SA1 is turned on, the first amplifier SA1 outputs the first data line DL1 and the first data line DL1 based on the second pixel data PD2 in the first period of the second horizontal driving period. The second data line DL2 may be simultaneously coarse driven, and then, the first data line DL1 may be further fine driven based on the first pixel data PD1 in the second period of the second horizontal driving period. . Accordingly, the first amplifier SA1 may drive the pixels PX21 and PX22 during the second horizontal driving period.

As such, in the display device 1000 according to an embodiment of the present disclosure, one amplifier turns-on not only when the two pixel data are the same but also when the data difference between the two pixel data is small, that is, when the horizontal threshold is less than or equal to. Static current of the data driver 300 may be reduced by turning off and turning on the other amplifier to drive two pixels based on the two pixel data.

In the embodiment, even if the data difference between the two pixel data is less than or equal to the horizontal threshold, if the transition amount of at least one of the two pixel data exceeds the second threshold, both amplifiers are turned on, and each corresponding data lines can be driven. That is, when the data difference between the two pixel data is less than the horizontal threshold and the transition amount of each of the two pixel data is less than the second threshold, one amplifier is turned off and the other amplifier is turned on so that the two pixel data Two pixels can be driven based on .

In this case, the transition amount of pixel data means a data difference between the pixel data and previous pixel data. For example, assuming that the first pixel data PD1 and the second pixel data PD2 respectively correspond to the pixels PX21 and PX22 of the second horizontal line driven in the second horizontal driving period, the first pixel data PD1 The transition amount of ) is the data difference between the first previous pixel data corresponding to the pixel PX11 of the first horizontal line and the first pixel data PD1. Also, the transition amount of the second pixel data PD2 is a data difference between the second previous pixel data corresponding to the pixel PX12 of the first horizontal line and the second pixel data PD2. Since the second threshold is compared with a data difference between two pixel data corresponding to two pixels of different lines, the second threshold will be referred to as a vertical threshold.

When the data difference between the first pixel data PD1 and the second pixel data PD2 is less than or equal to the horizontal threshold, the first data difference between the first pixel data PD1 and the first previous pixel data and the second pixel data PD2 ) and the second previous pixel data is less than or equal to the vertical threshold, one of the first and second amplifiers SA1 and SA2 is turned off and the other is turned off in the second horizontal drive period. - It can be turned on to drive the first data line DL1 and the second data line DL2. In other words, the turned-on amplifier can drive the pixels PX21 and PX22 in the second horizontal driving period.

Even if the data difference between the first pixel data PD1 and the second pixel data PD2 is equal to or less than the horizontal threshold, when at least one of the first data difference and the second data difference exceeds the vertical threshold, the second horizontal drive During this period, both the first amplifier SA1 and the second amplifier SA2 are turned on, so that the first amplifier SA1 and the second amplifier SA2 are connected to the first data line DL1 and the second data line ( DL2) can be driven.

When one amplifier drives two data lines, the driving load of the amplifier increases. Furthermore, when the amount of transition of two pixel data is large, if one amplifier drives two data lines, the driving load of the amplifier excessively increases, so that at least one of the two data lines may not be charged to a target level. . Therefore, the pixel signal at the target level may not be provided to the pixel. When the data difference between the two pixel data is small and the amount of transition between the two pixel data is small, one of the two amplifiers is turned off and the other is turned on to drive the two data lines, thereby consuming the data driver 300. Deterioration of display quality can be prevented while current is reduced.

The timing controller 200 may control overall operations of the display device 1000 . For example, the timing controller 200 may receive image data (RGB) and timing signals (eg, a horizontal sync signal (Hsync), a vertical sync signal (Vsync), and a clock from an external device (eg, a host device (not shown))). A scan driver for receiving the signal DCLK and the data enable signal DE, and controlling the data driver 300 and the scan driver 400, respectively, based on the received pixel data RGB and timing signals. The control signal CTRL1 and the data driver control signal CTRL2 can be generated, and the timing controller 100 formats the image data RGB received from the outside to meet the interface specifications with the data driver 300. (format) may be converted, and the converted image data DATA may be transmitted to the data driver 300. For example, the converted image data DATA may include packet data.

Timing controller 200 may include control logic 210 . The control logic 210 may analyze pixel data PD1 to PDm corresponding to adjacent pixels PX of one line of the display panel 100 and control the operation of the data driver 300 according to the analysis result. there is. The control logic 210 may generate a control signal for controlling the operation of the data driver 300 based on the analysis result and provide the control signal to the data driver 300 as the data driver control signal CTRL2.

The control logic 210 may compare a data difference between two pixel data corresponding to two pixels disposed adjacent to each other on the same horizontal line with a horizontal threshold. Based on the comparison result, the control logic 210 may generate a control signal including signals controlling states and operations of the amplifiers according to the pixel data, as described above. In an embodiment, the control logic 210 may consider the transition amount of two pixel data together. As the data driver 300 operates under the control of the control logic 210 as described above, current consumption can be reduced without deteriorating image quality.

Meanwhile, in FIG. 1 , the control logic 210 is illustrated as being included inside the timing controller 200, but is not limited thereto, and the control logic 210 may be a separate circuit from the timing controller 200. At this time, the control logic 210 converts the control signal for controlling the operation of the data driver 300 to the data driver 300 as a second driver control signal separate from the data driver control signal CTRL2 provided from the timing controller 200. can be provided to In an embodiment, the control logic 210 may be included in the data driver 300 .

Although not shown, the display device 1000 may further include a voltage generator and an interface. The voltage generator may generate various voltages used in the display panel 100 and the display driving circuit 500 .

The interface may communicate with an external device, for example, a host processor, and receive image data (RGB) and timing signals from the external device. For example, the interface includes an RGB interface, a CPU interface, a serial interface, a mobile display digital interface (MDDI), an inter integrated circuit (I2C) interface, a serial peripheral interface (SPI), a micro controller unit (MCU) interface, MIPI ( Mobile industry processor interface), embedded displayport (eDP) interface, D-sub (D-subminiature), optical interface, D-sub (D-subminiature) or high-definition multimedia interface (HDMI). there is. The interface may also include various serial or parallel interfaces.

In this embodiment, the scan driver 400, the data driver 300, and the timing controller 200 are shown as different functional blocks. In one embodiment, each component may be implemented as a different semiconductor chip. In another embodiment, at least two components of the scan driver 400, the data driver 300, and the timing controller 200 may be implemented as a single semiconductor chip. For example, the data driver 300 and the timing controller 200 may be integrated into one semiconductor chip. Also, some components may be integrated on the display panel 100 . For example, the scan driver 400 may be integrated on the display panel 100 .

Hereinafter, operations of the control logic 210 and the data driver 300 of the display apparatus 1000 according to the above-described embodiment of the present disclosure will be described in detail.

FIG. 2 is a circuit diagram illustrating a display driving circuit according to an exemplary embodiment, and FIG. 3 is a circuit diagram illustrating an operation of a display driver when the display driving circuit of FIG. 2 operates in a normal mode. FIG. 2 is a circuit diagram illustrating the data driver 300 and the control logic 210 of the display device 1000 of FIG. 1 in more detail, and the contents described with reference to FIG. 1 may also be applied to the present embodiment.

Referring to FIG. 2 , the display driving circuit 500a may include a control logic 210a, a data driver 300a, a first output pad OP1 and a second output pad OP2. In addition to this, the display driving circuit 500a may further include other components shown in FIG. 1 .

The data driver 300a may include an amplifier circuit 310a and an output switching circuit 320a. The amplifier circuit 310a may generate an output signal based on input data. The amplifier circuit 310a may include a first amplifier SA1 and a second amplifier SA2.

For convenience of description, the amplifier circuit 310a includes two amplifiers SA1 and SA2, and the display panel 100a includes two data lines DL1 and DL2, but as shown in FIG. As such, the amplifier circuit 310a may include a larger number of amplifiers, and the display panel 100a may include a larger number of data lines. Also, although the first amplifier SA1 and the second amplifier SA2 are shown as being directly adjacent to each other, other amplifiers may be disposed between the first amplifier SA1 and the second amplifier SA2. In this case, among the pixels PX11 to PX41 in the first column and the pixels PX12 to PX42 in the second column, pixels in the same row, for example, pixels PX11 and PX12 may output light of the same color. The amplifier SA1 and the second amplifier SA2 may output output signals corresponding to the same color.

The first amplifier SA1 is turned on in response to the first enable signal EN1 to generate the first output signal SO1 based on the first input data Din1. The second amplifier SA2 is turned on in response to the second enable signal EN2 to generate the second output signal SO2 based on the second input data Din2.

Although not shown, the data driver 300a further includes a first decoder and a second decoder, and the first input data Din1 and the second input data Din2 are converted to grayscale voltages through the first decoder and the second decoder. Pixel signals converted to ? and corresponding to the first input data Din1 and the second input data Din2 may be provided to the first amplifier SA1 and the second amplifier SA2. That is, the first amplifier SA1 and the second amplifier SA2 convert pixel signals corresponding to the first input data Din1 and the second input data Din2 into the first output signal SO1 and the second output signal, respectively. It can be output as (SO2). This will be described later with reference to FIGS. 7A to 8C.

When the display driving circuit 500a operates in the normal mode, the first pixel data PD1 may be provided as first input data Din1 and the second pixel data PD2 may be provided as second input data Din2. there is. The first pixel data PD1 corresponds to the pixels PX11 to PX41 of the first row connected to the first data line DL1, and the second pixel data PD2 corresponds to the second pixel data PD2 connected to the second data line DL2. It may correspond to the pixels PX12 to PX42 of the column. In other words, the plurality of data values sequentially provided as the first pixel data PD1 correspond to the pixels PX11 to PX41 in the first column, respectively, and the plurality of data values sequentially provided as the second pixel data PD2. may correspond to the pixels PX12 to PX42 of the second column, respectively.

The output switching circuit 320a controls output paths of the output signals of the amplifier circuit 320a. The output switching circuit 320a may include a first output switch OSW1 , a second output switch OSW2 , and a connection switch CSW.

The first output switch OSW1 is connected between the output node of the first amplifier SA1 and the first output pad OP1, and is turned on in response to the first output control signal OC1 so that the first amplifier ( The output of SA1), for example, the first output signal SO1 may be provided to the first output pad OP1. The second output switch OSW2 is connected between the output node of the second amplifier SA2 and the second output pad OP2, and is turned on in response to the second output control signal OC2, so that the second amplifier ( The output of SA2), eg, the second output signal SO2, may be provided to the second output pad OP2. The connection switch CSW is connected between the first output pad OP1 and the second output pad OP2, and is turned on in response to the connection control signal CON to output the first amplifier SA1 to the second output pad. It may be provided to the output pad OP2 or the output of the second amplifier SA2 may be provided to the first output pad OP1.

The control logic 210a may control the operation of the data driver 300a and generate data driver control signals (hereinafter referred to as control signals) for controlling the data driver 300a. For example, the control signals include a first enable signal EN1, a second enable signal EN2, a first output control signal OC1, a second output control signal OC2, and a connection control signal CON. can do. In addition to the control signals, other signals may be further included.

The control logic 210a is based on the first enable signal EN1, the second enable signal EN2, the first output control signal OC1, the second output control signal OC2, and the connection control signal CON. In this way, the turn-on or turn-off of the first amplifier SA1 and the second amplifier SA2, that is, control whether or not they operate, and the output path of the outputs of the first amplifier SA1 and the second amplifier SA2 can control.

In an embodiment, the control logic 210a controls the first data line DL1 and the second data line DL1 of the display panel 100a based on the first pixel data PD1 and the second pixel data PD2 by the data driver 300a. Before driving the two data lines DL2 , the first pixel data PD1 and the second pixel data PD2 may be received and analyzed, and control signals may be generated based on the analysis result. For example, when the received first pixel data PD1 and second pixel data PD2 correspond to the pixels PX31 and PX32 of the third horizontal line, the control logic 210a controls the control logic 210a before the third horizontal driving period. , for example, the first pixel data PD1 and the second pixel data may be analyzed in the second horizontal driving period, and control signals may be generated based on the analysis result. The data driver 300a may operate based on control signals in the third horizontal driving period.

When the display driver circuit 500a operates in the normal mode, the control logic 210a may generate control signals regardless of the first pixel data PD1 and the second pixel data PD2. For example, the control logic 210a generates a first enable signal EN1, a second enable signal EN2, a first output control signal OC1, and a second output control signal OC2 that are logic high; A connection control signal CON that is logic low may be generated.

Referring to FIG. 3 , in the normal operation mode, the first enable signal EN1 , the second enable signal EN2 , the first output control signal OC1 , and the second output control signal OC2 are logic high. In response, the first amplifier SA1, the second amplifier SA2, the first output switch OSW1 and the second output switch SW2 are turned on and respond to the connection control signal CON, which is logic low. Thus, the connection switch CSW may be turned off.

The first pixel data PD1 corresponding to the first pixel PX1 is provided to the first amplifier SA1 as first input data Din1, and the second pixel data PD2 corresponding to the second pixel PX2 ) may be provided as second input data Din2 to the second amplifier SA2. Accordingly, the first amplifier SA1 drives the first data line DL1 based on the first pixel data PD1, and the second amplifier SA2 drives the second data line based on the second pixel data PD2. Line DL2 can be driven.

The first pixel signal (or image signal) corresponding to the first pixel data PD1 is output as the output of the first amplifier SA1, that is, the first output signal SO1, and corresponds to the second pixel data PD2. The second pixel signal to be output may be output as the output of the second amplifier SA2, that is, the second output signal SO2. The first amplifier SA1 charges the first data line DL1 based on the first pixel signal corresponding to the first pixel data PD1, and the second amplifier SA2 charges the second pixel data PD2. The second data line DL2 may be charged based on the second pixel signal corresponding to . When the scan clock CLK is applied to the scan line SL, the first pixel signal charged in the first data line DL1 is provided to the first pixel PX1 and the second data line DL2 is charged. A second pixel signal may be provided to the second pixel PX2 .

Referring back to FIG. 2 , when the display driving circuit 500a operates in the low power mode, the control logic 210a analyzes and analyzes image patterns, for example, first pixel data PD1 and second pixel data PD2. Based on the result, control signals can be generated.

The control logic 210a may generate control signals based on the first pixel data PD1 , the second pixel data PD2 , and the horizontal threshold value H_Dth. The control logic 210a may calculate a data difference between the first pixel data PD1 and the second pixel data PD2 and compare the calculated data difference with the horizontal threshold value H_Dth.

When the data difference is less than the horizontal threshold value H_Dth, the control logic 210a turns off one of the first and second amplifiers SA1 and SA2, and the other amplifier outputs the first pixel data PD1. ) and the second pixel data PD2, control signals for controlling driving of the first data line DL1 and the second data line DL2 may be generated. In an embodiment, the second amplifier SA2 is turned off, and the first amplifier SA1 outputs the first data line DL1 and the first data line DL1 based on the first pixel data PD1 and the second pixel data PD2. The second data line DL2 may be driven.

In the control logic 210a, when the data difference exceeds the horizontal threshold value H_Dth, the first amplifier SA1 drives the first data line DL1 based on the first pixel data PD1, and the second amplifier SA1 drives the first data line DL1 based on the first pixel data PD1. SA2 may control the second data line DL2 to be driven based on the second pixel data PD2. The driving operation of the data driver 300a at this time is the same as the driving operation of the data driver 300a in the normal operation mode. Therefore, a detailed description will be omitted.

Hereinafter, referring to FIGS. 4A, 4B, and 5 , when the data difference between the first pixel data PD1 and the second pixel data PD2 is equal to or less than the horizontal threshold value H_Dth, the driving operation of the data driver 300a will explain

4A and 4B are circuit diagrams illustrating coarse and fine driving of a data driver when the display driving circuit of FIG. 2 operates in a low power mode. 5 is a timing diagram illustrating operations of the data driver 300a of FIGS. 4A and 4B.

Referring to FIGS. 4A, 4B and 5 , the first amplifier SA1 generates a first data line DL1 and a second data line DL2 in a first period P1 of one horizontal driving period 1H. Coarse driving may be performed, and the second data line DL2 may be fine driven in the second period P2 of one horizontal driving period 1H.

When the data difference between the first pixel data PD1 and the second pixel data PD2 is equal to or less than the horizontal threshold value H_Dth, the first enable signal EN1 is logic high, and the second enable signal EN2 is logic high. may be low Also, the first output control signal OC1 is a logic high, and the second output control signal OC2 is a logic low. Accordingly, the output of the first amplifier SA1 may be provided to the first data line DL1.

Referring to FIGS. 4A and 5 , in the first period P1 of one horizontal driving period 1H, second pixel data PD2 may be provided to the first amplifier SA1 as first input data Din1. and the connection control signal CON may be logic high. Accordingly, the first amplifier SA1 may drive the first data line DL1 and the second data line DL2 based on the second pixel data PD2. For example, when the second pixel data PD2 represents 250 grayscale, the first amplifier SA1 outputs 250 grayscale to the first data line DL1 and the second data line LD2 during the first period P1. A second pixel signal corresponding to , for example, the 250 grayscale voltage V250 may be applied, and the first data line DL1 and the second data line LD2 may be charged to the level of the 250 grayscale voltage V250.

Referring to FIGS. 4B and 5 , in the second period P2 of one horizontal drive period 1H, the first pixel data PD1 may be provided to the first amplifier SA1 as first input data Din1. and the connection control signal CON may be logic low. Accordingly, the first amplifier SA1 may drive the first data line DL1 based on the first pixel data PD1. For example, when the first pixel data PD1 represents 255 gray levels, the first amplifier S1 outputs a first pixel signal corresponding to 255 gray levels to the second data line DL1 during the second period P2; For example, a 255 gradation voltage (V255) may be applied. Accordingly, the voltage level of the first data line DL1 may be increased from the 250 gradation voltage V250 level to the 255 gradation voltage V255 level.

In this way, the first amplifier SA1 outputs the first data line based on the second pixel data PD2 corresponding to the second pixel PX2 connected to the second data line DL2 during the first period P1. Coarse driving of the DL1 and the second data line DL2 is performed, and thereafter, the first pixel data PD1 corresponding to the first pixel PX1 connected to the first data line DL1 is generated during the second period P2. Based on this, the first data line DL1 may be fine driven. Accordingly, a second pixel signal corresponding to the second pixel data PD2, for example, a 250 grayscale voltage V250 is applied to the second data line DL2, and the first pixel data ( A second pixel signal corresponding to PD1), for example, a 255 grayscale voltage V255 may be applied.

Meanwhile, the horizontal drive period 1H may include a data charging time T _DC and a threshold voltage compensation time Tc. At the data charging time T _DC , the logic high scan clock CLK may be provided to the scan line SL, and at this time, the first data line DL1 and the second data line DL2 may be charged. . During the threshold voltage compensation time Tc, the first pixel PX1 stores the first pixel signal provided through the first data line DL1 in response to the logic low scan clock CLK, and the second pixel PX2 ) may store the second pixel signal provided through the second data line DL2. A data charging time (T _DC ) may be set based on a full range transition of pixel data. For example, when the minimum value of pixel data represents 0 grayscale and the maximum value represents 255 grayscale, the first data line DL1 and the second data line DL2 change from the 0 grayscale voltage V0 to the 255 grayscale voltage V255. The data charging time T _DC may be set based on the time required for charging. Referring to FIG. 6 , the data charging time T _DC and the threshold voltage compensating time Tc will be described.

6 is a circuit diagram illustrating an implementation example of a pixel included in a display panel. Referring to FIG. 6 , the pixel PX may include a switching transistor ST, a driving transistor DT, a compensation transistor CT, a capacitor C, and an organic light emitting diode D. In FIG. 6, the switching transistor ST, the driving transistor DT, and the compensation transistor CT are shown as PMOS transistors, but are not limited thereto, and the switching transistor ST, the driving transistor DT, and the compensation transistor CT may be implemented with NMOS transistors. During the data charging time T _DC , the scan clock CLK may be logic high. When the scan clock CLK is logic high, the switching transistor ST is turned off, and when a driving signal, for example, a grayscale voltage, is applied to the data line DL, the data line DL is charged up to the level of the driving signal. It can be. A plurality of pixels PX are connected to the data line DL, and thus a parasitic capacitor Cp may be formed. Accordingly, it may take a considerable amount of time for the data line DL to be charged to the level of the driving signal.

Thereafter, the scan clock CLK may be logic low during the threshold voltage compensation time Tc. When the scan clock CLK transitions from logic high to logic low, the switching transistor ST and the compensation transistor CT are turned on, and a pixel signal, that is, a grayscale voltage, may be provided to the first node N1. . As the compensation transistor CT is turned on, the driving transistor DT operates as a diode, and the potential of the second node N2 is the data voltage Vdata, that is, the voltage of the pixel signal. The threshold voltage (Vth) of (hereinafter, referred to as a threshold voltage) rises to the subtracted voltage level. That is, the voltage obtained by compensating the threshold voltage Vth from the data voltage Vdata is stored in the capacitor C. When a current corresponding to a gate-source voltage difference (eg, ELVDD-(Vdata-Vth)) of the driving transistor DT flows through the organic light emitting diode D, the organic light emitting diode D emits light. In this case, since the current supplied to the organic light emitting diode D through the driving transistor DT is constant even though the threshold voltage Vth of the driving transistor DT is different between the pixels, the light output from the pixels has the same brightness. have

Referring back to FIG. 5 , the first period P1 may overlap with the data charging time T _DC , and the second period P2 may overlap with the threshold voltage compensation time Tc. That is, the data 1 amplifier SA1 coarsely drives the first data line DL1 and the second data line DL1 based on the second pixel data PD2 at the data charging time T _DC , and compensates for the threshold voltage. At time Tc, the first data line DL1 may be fine driven based on the first pixel data PD1. Since the data difference between the second pixel data PD2 and the first pixel data PD1 is equal to or less than the horizontal threshold, the voltage level of the first data line DL1 is at the grayscale voltage level corresponding to the second pixel data PD2. The time required to rise or fall to the grayscale voltage level corresponding to the first pixel data PD1, that is, the actual fine driving time Δt, may be very short. Therefore, even if the fine driving time Δt overlaps the threshold voltage compensation time Tc, the effect on the threshold voltage compensation of the first pixel PX1 may not be large.

Meanwhile, in FIG. 5 , the time when the scan clock CLK becomes logic low and the time when the connection control signal CON becomes logic low, that is, the start time of the second period P2 are shown as the same. However, it is not limited thereto. The start time of the second period P2 may be earlier than the time when the scan clock CLK becomes logic low. Accordingly, the fine driving time Δt of the first data line DL1 may partially overlap the data charging period T _DC . In an embodiment, the first period P1 and the second period P2 may be included in the data charging period T _DC .

As described above, in the display driving circuit 500a according to an embodiment of the present disclosure, one amplifier may drive two pixels when the two pixel data are the same or the data difference between the two pixel data is equal to or less than the horizontal threshold. there is. Also, the display driving circuit 500a can drive two pixels without increasing the horizontal driving period 1H through coarse driving and fine driving. Accordingly, the display driving circuit 500a can reduce static current consumption without deteriorating image quality.

7A is a circuit diagram illustrating an implementation example of a data driver according to an embodiment of the present disclosure, and FIGS. 7B and 7C are circuit diagrams illustrating an operation of the data driver of FIG. 7A.

Referring to FIG. 7A , the data driver 300b may include an amplifier circuit 310b, an output switching circuit 320b, a decoder unit 330b, an input switching circuit 340b, and a shift register 350b.

The shift register 350b stores image data DATA provided from the timing controller (300 in FIG. 1 ), for example, pixel data for one line, based on a vertical synchronization signal (Hsync in FIG. 5 ) or a vertical synchronization signal. Pixel data for one line can be output in synchronization with the generated timing signal. For example, the shift register 350b may output first pixel data PD1 and second pixel data PD2.

The decoder unit 330b may include a first decoder DEC1 and a second decoder DEC2. The first decoder DEC1 may select a grayscale voltage corresponding to the first pixel data PD1 from among the plurality of grayscale voltages V0 to V255 and output the selected grayscale voltage as a first pixel signal. The second decoder DEC2 may select a grayscale voltage corresponding to the second pixel data PD2 from among the plurality of grayscale voltages V0 to V255 and output the selected grayscale voltage as a second pixel signal.

The input switching circuit 340a may include a first input switch ISW1, a second input switch ISW2, and an input connection switch ICSW, and the first input switch ISW1 may include a first input control signal ICON1. ), and the second input switch ISW2 and the input connection switch ICSW may be turned on or off in response to the second input control signal ICON2. The first input control signal ICON1 and the second input control signal ICON2 are provided from the control logic (eg, 210a of FIG. 2 ) or are connected to the first enable signal EN1 and the second enable signal EN2. The control signal CON may be generated through a logic operation. For example, the first input control signal ICON1 is a signal generated by an exclusive OR operation of the first enable signal EN1 and the connection control signal CON, and the second input control signal ICON2 is a second enable signal. It may be a signal generated by an exclusive OR operation of the signal EN2 and the connection control signal CON.

When the display driving circuit (500a in FIG. 2) operates in the normal mode, the first input switch ISW1 and the second input switch ISW2 are turned on, and the input connection switch ICSW is turned off. . Accordingly, the first decoder DEC1 may provide the first pixel signal to the first amplifier SA1, and the second decoder DEC2 may provide the second pixel signal to the second amplifier SA2.

When the display driving circuit 500a operates in the low power mode, as shown in FIG. 7B , the first input switch ISW1 is turned off during the first period of the horizontal driving period, and the second input switch ISW2 and when the input connection switch ICSW is turned on, the second decoder DEC2 provides the second pixel signal to the first amplifier SA1, and as shown in FIG. 7C, the second period of the horizontal drive period. The first input switch ISW1 is turned on, and the second input switch ISW2 and the input connection switch ICSW are turned off, so that the first decoder DEC1 transmits the first pixel signal to the first amplifier ( SA1) can be provided. Accordingly, the first amplifier SA1 outputs the second pixel signal through the first output pad OP1 and the second output pad OP2 during the first driving period, and the first amplifier SA1 outputs the second pixel signal during the second driving period. ) may output the first pixel signal through the first output pad OP1. Operations of the amplifier circuit 310b and the output switching circuit 320b are the same as those of the amplifier circuit 310a and the output switching circuit 320a described with reference to FIG. 2 . Therefore, a detailed description will be omitted.

8A is a circuit diagram illustrating an implementation example of a data driver according to an embodiment of the present disclosure, and FIGS. 8B and 8C are circuit diagrams illustrating an operation of the data driver of FIG. 8A.

Referring to FIG. 8A , the data driver 300c may include an amplifier circuit 310c, an output switching circuit 320c, a decoder unit 330c, an input switching circuit 340c, and a shift register 350c. Compared to the data driver 300c of FIG. 7A , the input switching circuit 340c may be connected between the shift register 350c and the decoder unit 330c.

When the display driving circuit (500a in FIG. 2) operates in the normal mode, the first input switch ISW1 and the second input switch ISW2 are turned on, and the input connection switch ICSW is turned off. . Accordingly, the first decoder DEC1 may provide the first pixel signal to the first amplifier SA1, and the second decoder DEC2 may provide the second pixel signal to the second amplifier SA2.

When the display driving circuit 500a operates in the low power mode, the second decoder DEC2 may not operate. As shown in FIG. 8B, in the first period of the horizontal driving period, the first input switch ISW1 is turned off, the second input switch ISW2 and the input connection switch ICSW are turned on, The 2-pixel data PD2 is input to the first decoder DEC1, and the first decoder DEC1 may provide the second pixel signal to the first amplifier SA1. In addition, as shown in FIG. 8C, in the second period of the horizontal driving period, the first input switch ISW1 is turned on, and the second input switch ISW2 and the input connection switch ICSW are turned off. , the first pixel data PD1 is input to the first decoder DEC1, and the first decoder DEC1 may provide the first pixel signal to the first amplifier SA1.

9 is a timing diagram illustrating an operation example of the display driving circuit of FIG. 2 .

In FIG. 9 , the horizontal threshold H_Dth is 5, and as shown, pixels corresponding to the first pixels PX11 to PX41 connected to the first data line DL1 in the control logic (210a of FIG. 2 ). Data G230, G255, G250, and G230 are sequentially received as first pixel data PD1, and pixel data G240, G250, and G250 corresponding to the second pixels PX12 to PX42 connected to the second data line DL2; and G250 will be described assuming that they are received as the second pixel data PD2.

The first pixel data PD1 and the second pixel data PD2 are transmitted to the first input data Din1 of the first amplifier SA1 and/or the second amplifier SA2 in response to the vertical synchronization signal Hsync. It may be provided as the second input data Din2. The first pixel data PD1 received by the control logic 210a in the first horizontal drive period H1 is G255 and the second pixel data PD2 is G250, and the data difference is 5, which is the horizontal threshold ( H_Dth) or less. Accordingly, the control signals output from the control logic 210a, that is, the first enable signal EN1, the second enable signal EN2, the first output control signal OC1, and the second output control signal OC2 , and the connection control signal CON, the second amplifier SA2 is turned off and the first amplifier SA1 is turned on in the second horizontal driving period H2, and the first period P1 In the second period P2, the first data line DL1 and the second data line DL2 are driven based on the second pixel data PD2 G250, and based on the first pixel data PD1 G255 during the second period P2. to drive the first data line DL1.

The first pixel data PD1 and the second pixel data PD2 received by the control logic 210a during the second horizontal drive period H2 are equal to each other as G250. During the third horizontal drive period H3, the second amplifier SA2 is turned off, and the first amplifier SA1 controls the first data line DL1 and the second data line based on the first pixel data PD1. (DL2) can be driven.

The first pixel data PD1 received during the third horizontal driving period H3 is G230 and the second pixel data PD2 is G250, which is different from each other, and the data difference is 10, which is greater than the horizontal threshold value H_Dth. Accordingly, both the first amplifier SA1 and the second amplifier SA2 may be turned on during the fourth horizontal driving period H4. Since the second amplifier SA2 is turned off during the third horizontal driving period H3, the second enable operation takes into account the time WT required for the second amplifier SA2 to turn on and operate normally. The signal EN2 transitions to logic high before the start of the fourth horizontal driving period H4, and in response to the second enable signal EN2, the second amplifier SA2 operates the fourth horizontal driving period H4. ) may be turned on in advance before the start of

10 is a timing diagram illustrating an operation example of the display driving circuit of FIG. 2 .

9, the second amplifier SA2 is turned off and the first amplifier SA1 is turned on, so that the first amplifier SA1 drives two data lines. However, referring to FIG. 10, the second amplifier SA2 is turned off and the first amplifier SA1 is turned on in the second horizontal driving period H2, whereas in the third horizontal driving period H3 The first amplifier SA1 is turned off and the second amplifier SA2 is turned on to drive the first data line DL1 and the second data line DL2. One of the first amplifier SA1 and the second amplifier SA2 may be selectively turned on in consideration of the first pixel data PD1 and the second pixel data PD2 and the transition of the pixel data. .

In an embodiment, as shown, when the first pixel data PD1 is equal to or greater than the second pixel data PD2, the first amplifier SA1 is turned on, and the first pixel data PD1 is If it is less than the second pixel data PD2, the second amplifier SA2 may be turned on. However, it is not limited thereto, and the control logic ( 210a in FIG. 1 ) performs the first pixel data PD1 , the second pixel data PD2 , and the transition between the first pixel data PD1 and the second pixel data PD2 . An amplifier to be turned on from among the first amplifier SA1 and the second amplifier SA2 may be selected in consideration of the quantity and the like.

Meanwhile, when determining whether to operate the first amplifier SA1 and the second amplifier SA2, the amount of transition of pixel data may be considered. This will be described with reference to FIG. 11 .

11 is a timing diagram illustrating an operation example of a display driving circuit according to an embodiment of the present disclosure.

Referring to FIG. 11 , the data difference between the first pixel data PD1 and the second pixel data PD2 is equal to or less than the horizontal threshold value H_Dth, the transition amount of the first pixel data PD1 and the second pixel data ( When the transition amount of PD2 is less than the vertical threshold V_Dth, one of the first and second amplifiers SA1 and SA2 is turned off, and the other amplifier operates on the first data line DL1 and the second amplifier SA2. 2 data lines DL2 can be driven.

The first pixel data PD1 received during the first horizontal driving period H1 is G255, and the second pixel data PD2 is G250. A data difference between the first pixel data PD1 and the second pixel data PD2 is equal to 5, which is the horizontal threshold value H_Dth. The transition amount of the first pixel data PD1 is 127, which is smaller than the vertical threshold value V_Dth of 128. However, the transition amount of the second pixel data PD2 is 250, which is greater than the vertical threshold value V_Dth. Therefore, in the second horizontal driving period H2, both the first amplifier SA1 and the second amplifier SA2 are turned on, and each can drive one data line.

The first pixel data PD1 received during the second horizontal driving period H2 is G245, and the second pixel data PD2 is G250. A data difference between the first pixel data PD1 and the second pixel data PD2 is equal to 5, which is the horizontal threshold value H_Dth. The transition amount of the first pixel data PD1 is 10 and is smaller than the vertical threshold value V_Dth of 128. Also, the transition amount of the second pixel data PD2 is zero. Therefore, in the third horizontal drive period H3, one of the first amplifier SA1 and the second amplifier SA2, for example, the first amplifier SA1 is turned on to drive the two data lines, and the second amplifier SA1 is turned on. (SA1) can be turned off.

The first pixel data PD1 received in the third horizontal driving period H3 is G230 and the second pixel data PD2 is G250. A data difference between the first pixel data PD1 and the second pixel data PD2 is 20, which is greater than the horizontal threshold value H_Dth. Therefore, in the fourth horizontal driving period H4, both the first amplifier SA1 and the second amplifier SA2 are turned on, and each can drive one data line.

As such, when the control logic (eg, 210a of FIG. 2 ) determines whether one amplifier drives two data lines, the amplifier is driven by considering not only the data difference between pixel data but also the transition amount of the two pixel data. It is possible to reduce the burden and prevent deterioration of image quality.

12 is a timing diagram illustrating an operation of a display driving circuit according to setting of a vertical threshold.

12 shows first periods P1a and P1b and second periods P2a and P2b within one horizontal driving period 1H according to a vertical threshold when one amplifier, for example, the first amplifier drives two data lines. ) is set.

Referring to a of FIG. 12 , when the vertical threshold value V_Dth is 256, the first period P1a may be set equal to the data charging time T _DC . As described above, the data charging time (T _DC ) is It can be set based on full range transition of data.

Referring to b of FIG. 12, when the vertical threshold (V_Dth) is 128, the first period (P1a) is set less than the data charging time (T _DC ), and the first data line is within the data charging time (T _DC ). Fine driving for can be started.

When the vertical threshold V_Dth is set relatively small, the maximum driving load of the amplifier when one amplifier drives two data lines can be reduced compared to the case where the vertical threshold V_Dth is set relatively large. there is. Therefore, it is okay even if the coarse driving time is set small. When the vertical threshold V_Dth is small, the coarse driving time is set to be small, so that the fine driving start time may be advanced or the fine driving time may be increased.

13 is a block diagram illustrating an implementation example of control logic according to an embodiment of the present disclosure. 14 is a diagram showing gamma characteristics of an OLED panel by way of example. Referring to FIG. 13 , the control logic 210 may include a threshold value determiner 211 , a controller 212 and a buffer 213 .

The threshold value determiner 211 may receive the gamma set value GM_reg and the horizontal threshold voltage H_Vth, and set the horizontal threshold value H_Dth based on them. Also, the threshold determiner 211 may further receive a vertical threshold voltage (V_Vth) and set a vertical threshold (V_Dth) based on the received vertical threshold voltage (V_Vth). The threshold determiner 211 sets the horizontal threshold value (H_Dth) for each gradation and color based on the gamma register value (GM_reg) representing the gamma characteristics of the display panel (100 in FIG. 1) and the horizontal threshold voltage (H_Vth). can

Referring to FIG. 14 , a gamma characteristic, that is, a gamma curve may not increase or decrease linearly according to grayscale data. Since the increase or decrease of the gradation voltage is not constant as the gradation increases, the difference in gradation voltage according to the same gradation difference is not constant for each gradation. Therefore, the threshold value determiner 211 sets the horizontal threshold value H_Dth for each gradation or for each gradation section (or gradation area) in consideration of the gamma characteristics so that the horizontal threshold voltage H_Vth can be constant in each gradation. can For example, the horizontal threshold value H_Dth at 0 gradation G0 may be smaller than the horizontal threshold value H_Dth at 255 gradation G255. Also, since gamma characteristics are different for each color, the threshold value determiner 211 may set a plurality of horizontal threshold values H_Dth for each color.

For example, as illustrated, the slope of the gamma curve may greatly change in the 15th gray level (G15). The threshold value determination unit 211 sets the first horizontal threshold value H_Dtha for the first grayscale region Dth_a between 0 grayscale G0 and 15th grayscale G15 in consideration of the horizontal threshold voltage V_Vth. And, the second horizontal threshold value H_Dthb may be set for the second grayscale region Dth_b between 15th gray level (G15) and 255th grayscale level (G255). The first horizontal threshold value H_Dtha and the second horizontal threshold value H_Dthb may be different.

Similarly, the threshold value determiner 211 may set the vertical threshold value V_Dth for each gradation and color in consideration of the gamma characteristic so that the vertical threshold voltage V_Vth is constant in each gradation. However, it is not limited thereto, and in an embodiment, the threshold value determiner 211 may set one vertical threshold value (H_Dth) regardless of gray level or color.

Continuing to refer to FIG. 13 , the threshold value determiner 211 may include a lookup table (LUT), and the horizontal threshold value (H_Dth) and vertical threshold value (V_Dth) set for each gradation and color are the lookup table (LUT).

Buffer 213 may provide pixel data to controller 212 . For convenience of description, it is illustrated that the buffer 213 provides the first pixel data PX1 and the second pixel data PX2 to the controller 212, but it is not limited thereto, and the buffer 213 is provided in one horizontal Pixel data corresponding to the pixels of the line may be provided to the controller 212 in turn. In addition, if the controller 212 considers the vertical threshold V_Dth when comparing data, the buffer 213 stores pixel data corresponding to pixels of one horizontal line and previous pixels corresponding to pixels of the previous horizontal line. Data may be provided to the controller 212 . The buffer 213 may store pixel data for one line or two lines. Buffer 213 may be implemented as a line buffer or memory.

The controller 212 may generate control signals based on pixel data provided from the buffer 213 , for example, first pixel data PD1 and second pixel data PD2 . As described above with reference to FIG. 2, the control signals include the enable signals EN1 and EN2 for determining whether the amplifier operates, the output control signals OC1 and OC2 for controlling the output of the amplifier, and the connection control signal CON. can include

The controller 212 may generate control signals based on the first pixel data PD1 , the second pixel data PD2 , and the horizontal threshold value H_Dth. The controller 212 calculates a data difference between the first pixel data PD1 and the second pixel data PD2, compares the data difference with the horizontal threshold value H_Dth, and uses the comparison result to a data driver (FIG. 2). It is possible to generate control signals for controlling 300a) of. In the embodiment, as described above, the horizontal threshold value (H_Dth) may be set for each gray level, and at this time, the controller 212 refers to the lookup table (LUT) of the threshold value determiner 211 to determine the data difference. It may be compared with the horizontal threshold value H_Dth corresponding to the gray level indicated by the first pixel data PD1 or the second pixel data PD2.

In an embodiment, the controller 212 may generate control signals based on the first pixel data PD1 , the second pixel data PD2 , the horizontal threshold value H_Dth and the vertical threshold value V_Dth. The controller 212 may calculate a first data difference between the first pixel data PD1 and the second pixel data PD2 and compare the first data difference with the horizontal threshold value H_Dth. The controller 212 also outputs a second data difference between the first pixel data PD1 and the previously received first previous pixel data and third data between the second pixel data PD2 and the previously received second previous pixel data. The difference may be calculated, and the second data difference and the third data difference may be compared with the vertical threshold value V_Dth. The controller 212 may generate control signals for controlling the data driver (300a in FIG. 2) based on the comparison results.

15 is a flowchart illustrating a method of operating the threshold value determiner of FIG. 13 . In detail, FIG. 15 is a flowchart illustrating a step of setting a horizontal threshold value for each gray level corresponding to a red color by a threshold value determiner.

Referring to FIG. 15 , the threshold value determiner ( 211 of FIG. 13 ) may obtain reference threshold data ( S10 ). For example, the reference threshold data may include a horizontal threshold voltage (H_Vth), a first reference threshold value (R_Dth_a) corresponding to the first grayscale region, and a second reference threshold value (R_Dth_b) corresponding to the second grayscale region. As described with reference to FIG. 14 , the slope of the gamma curve of the first grayscale region may be different from the slope of the gamma curve of the second grayscale region. A reference threshold gray level, which is a criterion for rapidly changing the gradient, may be further set. In an embodiment, the threshold determiner may convert a gamma register value for red color into a grayscale voltage for red color, and calculate a gamma characteristic for red color based on the converted grayscale voltage. The threshold value determiner may set reference threshold values based on gamma characteristics. In another embodiment, the reference threshold data may be provided from an external device, such as a host processor.

Thereafter, a horizontal threshold value for each gray level may be set in the first gray level area (S30). The threshold value determiner calculates the grayscale voltage V_a corresponding to the first reference threshold value R_Dth_a in each grayscale included in the first grayscale area (S31), and converts the grayscale voltage V_a into a horizontal threshold voltage H_Vth It can be compared with (S32). If the grayscale voltage V_a is equal to or less than the horizontal threshold voltage H_Vth, the first reference threshold value R_Dth_a may be stored as the horizontal threshold value H_Dth_a of the corresponding grayscale of the first grayscale region (S33). When the grayscale voltage V_a is greater than the horizontal threshold voltage H_Vth, the first reference threshold value R_Dth_a may be decreased by 1 (a 1-bit data value) (S34). Thereafter, step S31 may be performed again based on the newly set first reference threshold value R_Dth_a, and the grayscale voltage V_a corresponding to the newly set first reference threshold value R_Dth_a is equal to or less than the threshold voltage H_Vth. Steps S31, S32 and S34 may be repeatedly performed until

Thereafter, a horizontal threshold value for each gray level may be set in the second gray level area (S40). In each grayscale in the second grayscale area, a grayscale voltage V_b corresponding to the second reference threshold value R_Dth_b may be calculated (S41), and the grayscale voltage V_b may be compared with the horizontal threshold voltage H_Vth (S42). ). If the grayscale voltage V_b is equal to or less than the horizontal threshold voltage H_Vth, the second reference threshold value R_Dth_b may be stored as the horizontal threshold value H_Dth_b of the corresponding grayscale of the second grayscale region (S43). When the grayscale voltage V_b is greater than the horizontal threshold voltage H_Vth, the first reference threshold value R_Dth_b may be decreased by 1 (a 1-bit data value) (S44). Thereafter, step S41 may be performed again based on the newly set second reference threshold value R_Dth_b, and the grayscale voltage V_b corresponding to the newly set second reference threshold value R_Dth_b is less than or equal to the threshold voltage H_Vth. Steps S41, S42 and S44 may be repeatedly performed until

Step S30 is performed for each gradation in the first grayscale area and step S40 is performed for each gradation in the second grayscale area, so that the horizontal threshold value H_Vth for each gradation for the red color may be set.

Meanwhile, the threshold determiner may set the horizontal threshold value H_Dth for each gray level similarly to the above description for other colors, for example, blue and green colors.

16 is a flowchart illustrating an operating method of a display driving circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 16 , a controller (eg, 212 of FIG. 13 ) may calculate a first data difference D1 between first pixel data and second pixel data (S210). The first pixel data and the second pixel data may be pixel data corresponding to two pixels located on the same horizontal line and having the same color.

The controller may compare the first data difference D1 with the horizontal threshold value H_Dth (S220). When the first data difference D1 is equal to or less than the horizontal threshold value H_Dth, the controller may turn on the first amplifier and turn off the second amplifier (S230). The turned-on first amplifier may drive the first data line and the second data line based on the first pixel data and the second pixel data (S240). The second amplifier may coarsely drive the first data line and the second data line based on the second pixel data, and then fine drive the first data line based on the first pixel data.

When the first data difference D1 exceeds the horizontal threshold value H_Dth, the controller may turn on both the second amplifier and the second amplifier (S250). The first amplifier and the second amplifier may respectively drive the first data line and the second data line (S260). The first amplifier may drive the first data line based on the first pixel data, and the second amplifier may drive the second data line based on the second pixel data.

17 is a flowchart illustrating an operating method of a display driving circuit according to an embodiment of the present disclosure.

Referring to FIG. 17 , a controller (eg, 210 of FIG. 13 ) determines a first data difference D1 between first pixel data and second pixel data corresponding to two pixels having the same color and located on the same horizontal line, and first pixel data A second data difference D2 between the pixel data and the first previous pixel data, and a third data difference D3 between the second pixel data and the second previous pixel data may be calculated (S310). The second data difference D2 represents the transition amount of the first pixel data, and the third data difference D3 represents the transition amount of the second pixel data.

The controller may compare the first data difference D1 with the horizontal threshold value H_Dth (S320). If the first data difference D1 is equal to or less than the horizontal threshold value H_Dth, the controller may compare the second data difference D2 and the third data difference D3 with the vertical threshold value V_Dth (S330). When both the second data difference D2 and the third data difference D3 are less than or equal to the vertical threshold value V_Dth, the controller may turn on the first amplifier and turn off the second amplifier (S340). The turned-on first amplifier may drive the first data line and the second data line based on the first pixel data and the second pixel data (S350).

Meanwhile, if the first data difference D1 exceeds the horizontal threshold value H_Dth or at least one of the second data difference D2 and the third data difference D3 exceeds the vertical threshold value V_Dth, It may be a load condition where one amplifier cannot drive two data lines. The controller may turn on both the first amplifier and the second amplifier (S360). The first amplifier and the second amplifier may respectively drive the first data line and the second data line (S370). A first amplifier may drive a second data line based on the first pixel data, and a second amplifier may drive a second data line based on the second pixel data.

18 is a block diagram illustrating a display driving circuit according to an exemplary embodiment of the present disclosure, and FIG. 19 is a diagram illustrating one implementation example of a data driver and a pentile structure display panel according to an exemplary embodiment of the present disclosure. FIG. 18 is a block diagram illustrating the control logic 210 and the data driver 300 of the display device 1000 of FIG. 1 in more detail, and the contents described with reference to FIG. 1 may be applied to the present embodiment.

Referring to FIG. 18 , the display driving circuit may include a control logic 210e and a data driver 300e. In addition to this, the display driving circuit may further include other components shown in FIG. 1 .

The control logic 210e may include a threshold value determiner 211 , a controller 212 and a buffer 213 . The contents of the control logic 210 described with reference to FIG. 13 may also be applied to the control logic 210e of FIG. 18 .

The threshold determiner 211 may set a horizontal threshold value and a vertical threshold value corresponding to each color based on the gamma register value GM_reg, the horizontal threshold voltage H_Vth, and the vertical threshold voltage V_Vth. For example, the threshold determiner 211 may set horizontal threshold values (H_Dth_R, H_Dth_G, H_Dth_B) and vertical threshold values (V_Dth_R, V_Dth_G, V_Dth_B) for red, green, and blue colors.

The buffer 213 may store and output one line of pixel data (PD1 to PDm) or two lines of pixel data. The buffer 213 may provide one line of pixel data PD1 to PDm to the controller 212 and to the shift register 350e of the data driver 300e. The buffer 213 may be implemented as a line buffer, memory, or the like. In an embodiment, when the display driving circuit includes a graphic memory that stores image data of one frame, the graphic memory may operate as the buffer 213 .

The controller 212 controls the buffer 213 based on the horizontal threshold values (H_Dth_R, H_Dth_G, H_Dth_B) and vertical threshold values (V_Dth_R, V_Dth_G, V_Dth_B) for the red, green, and blue colors provided from the threshold determiner 112. ) may be analyzed, and control signals may be generated based on the analysis result. The control signals may include enable signals EN, an output control signal CO, and a connection control signal CON provided to each of the amplifiers SA1 to SAm of the data driver 300e.

The data driver 300e may include an amplifier circuit 310e, an output switching circuit 320e, and a shift register 350e. As shown in FIGS. 7A and 8A , the data driver 300e may further include an output switching circuit.

The shift register 350e sequentially receives one line of pixel data (PD1 to PDm), enable signals (EN), an output control signal (CO), and a connection control signal (CON) from the control logic 210e. , in response to a horizontal synchronization signal or timing signal, one line of pixel data (PD1 to PDm) and enable signals (EN) are provided to the amplifier circuit 310e, and an output control signal (CO) and a connection control signal ( CON) to the output switching circuit 320e (and the input switching circuit). According to the above-described embodiments, each of a plurality of amplifiers (eg, S1 to Sn) may drive each of the pixels of the display panel or one amplifier may drive two pixels of the display panel.

For example, as shown in FIG. 19 , the data driver 300e may drive a display panel having a pentile structure. As a non-limiting example, in a display panel having a pentile structure, red, first green, blue, and second green sub-pixels belonging to the same horizontal line and sequentially arranged are one pixel (eg, the first pixel PX1, A second pixel PX2) may be configured. For example, the first to fourth amplifiers S1 to S4 of the amplifier circuit 310e drive the red, first green, blue, and second green sub-pixels of the first pixel PX1, and the fifth to fourth amplifiers S1 to S4 are driven. Eight amplifiers S5 to S4 may drive red, first green, blue, and second green sub-pixels included in the second pixel PX2 adjacent to the first pixel PX1. When the data difference between the red sub-pixels belonging to the first pixel PX1 and the second pixel PX2 is less than the horizontal threshold value H_Dth_R corresponding to the red color, the fifth amplifier S5 is turned off and the first The amplifier S1 may drive the red sub-pixels of the first pixel PX1 and the second pixel PX2 during one horizontal driving period. In the embodiment, as described above with reference to FIG. 11, the turn-on or turn-off of the fifth amplifier S5 is the transition amount and the second pixel data corresponding to the red sub-pixel of the first pixel PX1. A transition amount of pixel data corresponding to the red sub-pixel of the 2-pixel PX2 may be considered.

Meanwhile, amplifiers driving sub-pixels belonging to the same pixel, for example, the first to fourth amplifiers S1 to S4 may operate in common or individually. For example, the first to fourth amplifiers S1 to S4 may operate in response to the same enable signal or in response to different enable signals.

When the first to fourth amplifiers S1 to S4 operate in common, the fifth to eighth amplifiers S5 to S8 and the first to fourth connection switches CSW1 to CSW4 may also operate in common. Data difference between red subpixels belonging to the first pixel PX1 and second pixel PX2 , data difference between first green subpixels, data difference between blue subpixels, and data difference between second green subpixels If each is below the horizontal threshold (e.g., the horizontal threshold corresponding to each color), the fifth to eighth amplifiers S5 to S8 are turned off and the first to fourth amplifiers S1 to S4 are turned on. The turned-on first to fourth amplifiers S1 to S4 correspond to subpixels of the first pixel PX1 and the second pixel PX2 as described above with reference to FIGS. 4A to 5 . Each sub-pixel of the desired color may be driven.

However, it is not limited thereto, and in another embodiment, amplifiers connected to the same pixel may individually operate according to data of subpixels of corresponding colors. For example, the first and fourth amplifiers S1 and S4 operate according to the data difference between the red subpixels, and the second and fifth amplifiers S2 and S5 operate according to the data difference between the first green subpixels. can do. As such, the third and seventh amplifiers S3 and S7 and the fourth and eighth amplifiers S4 and S8 may also operate according to data differences between corresponding subpixels.

As above, exemplary embodiments have been disclosed in the drawings and specifications. Although the present disclosure has been described with reference to the embodiments shown in the drawings, this is only exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (20)

a first amplifier driving a first data line of a display panel based on first pixel data;
A second amplifier driving a second data line of the display panel based on second pixel data;
When the first data difference between the first pixel data and the second pixel data is greater than or equal to a data value representing one gray level and less than or equal to a first threshold value, the second amplifier is turned off, and driving the first data line and the second data line based on pixel data and the second pixel data;
The first amplifier drives the first data line and the second data line based on the second pixel data during a first sub-period of the horizontal driving period, and the first amplifier drives the first data line and the second data line during the second sub-period of the horizontal driving period. and driving the first data line based on pixel data. delete The display device of claim 1 , further comprising: a first output pad connected to the first data line;
a second output pad connected to the second data line; and
and a connection switch connected to the first output pad and the second output pad and turned on during the first sub period and turned off during the second sub period in response to a control signal. . According to claim 1,
a first decoder outputting a first grayscale voltage selected from among a plurality of grayscale voltages based on the first pixel data;
a second decoder outputting a second grayscale voltage selected from among the plurality of grayscale voltages based on the second pixel data; and
An input switching circuit configured to provide the second grayscale voltage to the first amplifier during the first sub period in response to a control signal and to provide the first grayscale voltage to the first amplifier during the second sub period. A display driving circuit comprising: According to claim 1,
a first decoder that selects one of a plurality of grayscale voltages as a first grayscale voltage based on received first input data and provides the first grayscale voltage to the first amplifier; and
and a second decoder configured to select one of the plurality of grayscale voltages as a second grayscale voltage based on received second input data and to provide the second grayscale voltage to the second amplifier. According to claim 1,
Comparing the first data difference with the first threshold value and generating a second enable signal indicating whether the second amplifier is operating and a control signal controlling an output path of the first amplifier based on the comparison result A display driving circuit further comprising a controller. According to claim 6,
and a threshold value determiner configured to calculate a plurality of first threshold values for each gradation based on the first threshold voltage and the gamma register value. The method of claim 7, wherein the threshold value determiner
Store the plurality of first threshold values in a lookup table;
wherein the controller determines whether to operate the second amplifier based on a first threshold value according to a data value of the first pixel data among the plurality of first threshold values. According to claim 1,
The first pixel data corresponds to a first pixel connected to a K-th scan line (K is an integer greater than or equal to 2) and the first data line of the display panel, and the second pixel data corresponds to the K-th scan line and the first pixel data. Corresponds to a second pixel connected to 2 data lines;
A second data difference between the first pixel data and first previous pixel data corresponding to a third pixel connected to the K-1 scan line and the first data line and the K-1 scan line and the second data When at least one of the third data difference between the second previous pixel data corresponding to the fourth pixel connected to the line and the second pixel data exceeds the second threshold value, in the K-th horizontal driving period, the first amplifier The display driving circuit of claim 1 , wherein the first data line is driven based on first pixel data, and the second amplifier drives the second data line based on second pixel data. According to claim 9,
When the first data difference is equal to or less than the first threshold value, and the second data difference and the third data difference are equal to or less than the second threshold value, the second amplifier is turned off, and the first amplifier is leveled driving the first data line and the second data line during a first period of a driving period, and driving the first data line during a second period of the horizontal driving period;
The length of the first period when the second threshold is set to a second value smaller than the first value is set to be less than the length of the first period when the second threshold is set to the first value. A display driving circuit, characterized in that. According to claim 9,
The first data difference is compared with the first threshold value, the second data difference and the third data difference are compared with the second threshold value, and based on the comparison results, whether the second amplifier operates is determined. and a controller for generating a second enable signal indicating and a control signal for controlling an output path of the first amplifier. According to claim 1,
The first data line and the second data line are connected to pixels of the same color and are adjacent to each other. The display driving circuit of claim 1 , wherein the display panel includes Organic Light Emitting Diode (OLED) pixels. a first amplifier driving a first data line of a display panel based on first pixel data;
a second amplifier driving a second data line of the display panel based on second pixel data; and
In the low power operation mode, the first pixel data and the second pixel data are received in a first horizontal driving period, the first data difference between the first pixel data and the second pixel data is 1 or more, and the horizontal threshold value N ( N is less than or equal to a positive integer), the first amplifier and the second amplifier are turned on and the other amplifier is turned off during the second horizontal driving period. A controller controlling the second amplifier;
When the first amplifier is selected, the first amplifier drives the first data line and the second data line based on the second pixel data during a first period of the second horizontal driving period, and and driving the first data line based on the first pixel data during a second period of the horizontal driving period. delete According to claim 14,
The first pixel data and the second pixel data correspond to K-th pixels of the first data line and the second data line, respectively;
The controller includes the first pixel data, the second pixel data, the third pixel data corresponding to the K-1 th pixel of the first data line, and the K-1 th pixel of the second data line. Based on the data values of the 4 pixel data, select the one amplifier;
The display driving circuit of claim 1 , wherein the K-1 th pixel is driven in the first horizontal driving period. The method of claim 16, wherein the controller,
When the first pixel data and the second pixel data are greater than the third pixel data and the fourth pixel data and the third pixel data is less than the fourth pixel data, the first amplifier is turned on. A display driving circuit characterized in that for controlling. calculating a first data difference between the first pixel data and the second pixel data;
comparing the first data difference to a horizontal threshold; and
and driving, by a first amplifier, a first data line and a second data line of a display panel based on the first pixel data and the second pixel data when the first data difference is less than or equal to the horizontal threshold. ,
Driving the first data line and the second data line,
Coarse driving, by the first amplifier, the first data line and the second data line based on the second pixel data; and
and fine-driving, by the first amplifier, the first data line based on the first pixel data. delete According to claim 18,
When the first data difference exceeds the horizontal threshold, the first amplifier drives the first data line based on the first pixel data, and a second amplifier having the same structure as the first amplifier The method of operating a display driving circuit further comprising driving the second data line based on second pixel data.

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