KR102528454B1 - Power conversion circuit with battery cell balancing - Google Patents

Abstract

The present invention relates to a power conversion circuit capable of performing battery charging and cell balancing functions in a structure in which a plurality of cells are connected in series. One aspect of the present invention, in a power conversion circuit for receiving power from an external charger and performing charging and cell balancing functions of a battery in which a plurality of cells including a first cell and a second cell are connected in series, a buck converter a first converter circuit selectively operating in a switched capacitor converter mode, charging the battery in the buck converter mode, and performing the cell balancing function in the switched capacitor converter mode; a second converter circuit operating in a switched capacitor converter mode and performing the cell balancing function; a current path management circuit that manages a bus voltage and a connection between the first converter circuit, the second converter circuit, and the battery; and a controller controlling the first converter circuit, the second converter circuit, and the current path management circuit.

Description

Power conversion circuit including battery cell balancing function {POWER CONVERSION CIRCUIT WITH BATTERY CELL BALANCING}

The present invention relates to a power conversion circuit including a battery cell balancing function. Specifically, the present invention relates to a power conversion circuit capable of performing battery charging and cell balancing functions in a structure in which a plurality of cells are connected in series.

Recently, as the power demand of an electronic device using a battery increases, attempts to use a battery in which a plurality of cells are connected in series are increasing. In addition, interest in a structure in which each of the dual monitors is provided with a separate cell in a foldable mobile phone or the like, but two cells are connected in series together and can be utilized, is also increasing.

In the case of a structure in which a plurality of cells are connected in series as described above, a device for charging the battery when an external charger (TA) is connected is required, as well as a cell balancing device for balancing two cells. There is a problem in which the structure is complicated.

In addition, with the recent diversification of chargers for externally charging mobile electronic devices, a method in which the voltage provided by an external charger is fixed to a predetermined voltage such as 5V or 9V, and a method in which the voltage provided by the external charger is variable in the range of 3V to 11V or 3V to 20V Various charging methods are used. For example, a USB-PD USB Power Delivery Programmable Power Supply (PPS) type external charger may adjust and provide a voltage required by the electronic device in the range of 3V to 20V in units of 20mV through communication with the electronic device. In this case, the electronic device may operate in an optimal condition by requesting an optimal voltage from an external charger according to its own state.

Due to these various charging methods, the power conversion circuit not only must be able to operate efficiently at the voltage supplied from the external charger when it is fixed at a predetermined value, but also the external charger that can be varied within a predetermined voltage range. When is connected, it is necessary to request a voltage suitable for the internal situation of the electronic device from an external charger and receive the corresponding voltage to implement high-speed or ultra-fast charging with high efficiency.

As such, in a situation where a plurality of cells are connected in series and external charger methods are diversified, the need for a power conversion circuit having a cell balancing function while efficiently charging a battery is increasing.

An object of the present invention is to provide a power conversion circuit having a cell balancing function while efficiently charging a battery in a situation where a plurality of cells are connected in series and charging methods are diversified.

One object of the present invention, according to an embodiment, is to provide a power conversion circuit capable of performing a cell balancing function in a state in which an external charger is not connected.

One object of the present invention, according to an embodiment, is to provide a power conversion circuit capable of performing battery charging and cell balancing functions in a state in which an external charger providing a predetermined fixed voltage is connected.

One object of the present invention is to provide a power conversion circuit capable of performing high-speed charging of a battery and cell balancing functions in a state in which an external charger providing a variable voltage within a predetermined range is connected.

One object of the present invention is to provide a power conversion circuit capable of reducing the number of parts, implementing a simple structure, and operating at high efficiency, while achieving the above objects, according to embodiments.

One aspect of the present invention, in a power conversion circuit for receiving power from an external charger and performing charging and cell balancing functions of a battery in which a plurality of cells including a first cell and a second cell are connected in series, a buck converter a first converter circuit selectively operating in a switched capacitor converter mode, charging the battery in the buck converter mode, and performing the cell balancing function in the switched capacitor converter mode; a second converter circuit operating in a switched capacitor converter mode and performing the cell balancing function; a current path management circuit that manages a bus voltage and a connection between the first converter circuit, the second converter circuit, and the battery; and a controller controlling the first converter circuit, the second converter circuit, and the current path management circuit.

In the power conversion circuit, when the external charger is not connected, the current path management circuit connects the high voltage of the second cell to the input voltage of the first converter circuit and the input voltage of the second converter circuit; The first converter circuit and the second converter circuit may each operate in the switched capacitor converter mode to perform a cell balancing function between the first cell and the second cell.

In the power conversion circuit, the first converter circuit and the second converter circuit may perform a switching operation with a phase difference of substantially 180 degrees from each other.

In the power conversion circuit, when a variable output voltage external charger is connected, the current path management circuit converts the bus voltage into a high voltage of the second cell, an input voltage of the first converter circuit, and an input voltage of the second converter circuit. , wherein the first converter circuit and the second converter circuit may each operate in the switched capacitor converter mode to perform a cell balancing function between the first cell and the second cell.

In the power conversion circuit, the current path management circuit may directly perform high-speed charging of the battery by connecting the bus voltage to the high voltage of the second cell.

In the power conversion circuit, the controller may request the variable output voltage external charger to adjust an output voltage so that the bus voltage becomes a voltage suitable for directly performing high-speed charging of the battery.

In the power conversion circuit, the first converter circuit and the second converter circuit may perform a switching operation with a phase difference of substantially 180 degrees from each other.

In the power conversion circuit, when a fixed output voltage external charger is connected, the current path management circuit connects the bus voltage to the input voltage of the first converter circuit, and connects the high voltage of the second cell to the second converter circuit. The first converter circuit operates in the buck converter mode to charge the first cell, and the second converter circuit operates in the switched capacitor converter mode to charge the first cell and the second converter circuit. A cell balancing function between cells may be performed.

In the power conversion circuit, the first converter circuit may operate with a duty determined based on a voltage ratio between the bus voltage and the first cell in the buck converter mode.

In the power conversion circuit, the buck converter mode in which the first converter circuit operates may be a 3-level buck converter operation mode using an inductor.

In the power conversion circuit, the current path management circuit includes: a first transistor QRB1 selectively connecting the bus voltage and the input voltage of the first converter circuit; a second transistor (QST1) selectively connecting the input voltage of the first converter circuit and the high voltage of the second cell; a third transistor (QRB2) selectively connecting the bus voltage and the input voltage of the second converter circuit; and a fourth transistor QST2 selectively connecting the input voltage of the second converter circuit and the high voltage of the second cell.

In the power conversion circuit, the current path management circuit may further include a fifth transistor QSB selectively connecting the high voltage of the first cell and the low voltage of the second cell.

In the power conversion circuit, the first transistor QRB1, the second transistor QST1, the third transistor QRB2, and the fourth transistor QST2 may be bi-directional control transistors capable of bi-directional conduction control. there is.

In the power conversion circuit, the first converter circuit includes: a transistor QA1, a transistor QB1, a transistor QC1, and a transistor QD1 sequentially connected in series between an input voltage of the first converter circuit and a ground (PGND); and a first flying capacitor CFLY1 connected between a contact point between the transistor QA1 and the transistor QB1 and a contact point between the transistor QC1 and the transistor QD1. A first inductor L1 having one end connected to a contact point between the transistor QB1 and the transistor QC1 may be included.

In the power conversion circuit, the first converter circuit may selectively operate in a buck converter mode or a switched capacitor converter mode according to an on/off sequence of the transistor QA1, the transistor QB1, the transistor QC1, and the transistor QD1. .

In the power conversion circuit, the first converter circuit includes: a transistor QA1, a transistor QB1, a transistor QC1, and a transistor QD1 sequentially connected in series between an input voltage of the first converter circuit and a ground (PGND); a first flying capacitor CFLY1 coupled between a contact point between the transistor QA1 and the transistor QB1 and a contact point between the transistor QC1 and the transistor QD1; a transistor QE1 and a transistor QF1 connected in series between both ends of the first flying capacitor CFLY1; A first inductor L1, one end of which is connected to a contact of the transistor QB1 and the transistor QC1, the other end of the first inductor L1 functions as an output node of a buck converter mode, and the transistor QE1 and the transistor QF1 The contact can function as an output node in switched capacitor converter mode.

In the power conversion circuit, the other end of the first inductor L1 may be connected to the low voltage of the second cell, and a junction between the transistor QE1 and the transistor QF1 may be connected to the high voltage of the first cell.

In the power conversion circuit, a transistor QSB is connected between the high voltage of the first cell and the low voltage of the second cell to selectively connect the high voltage of the first cell and the low voltage of the second cell.

In the power conversion circuit, the first converter circuit operates while the transistors QA1, QE1, transistor QF1, and transistor QD1 are repeatedly turned on/off at a predetermined switching cycle in the switched capacitor converter mode; In the buck converter mode, the transistor QA1 , the transistor QB1 , the transistor QC1 , and the transistor QD1 may operate while repeatedly turning on/off at a predetermined switching cycle.

In the power conversion circuit, the first converter circuit operates such that a ratio of an input voltage to an output voltage has a relationship of substantially 2:1 in the switched capacitor converter mode, and in the buck converter mode, the output voltage is It can be adjusted within a lower range than the voltage, and the second converter circuit can operate so that the ratio of the input voltage to the output voltage has a relationship of substantially 2:1 in the switched capacitor converter mode.

According to the present invention, according to embodiments, it is possible to provide a power conversion circuit having a cell balancing function while efficiently charging a battery in a situation where a plurality of cells are connected in series and charging methods are diversified.

According to the present invention, according to an embodiment, it is possible to provide a power conversion circuit capable of performing a cell balancing function in a state in which an external charger is not connected.

According to the present invention, according to an embodiment, it is possible to provide a power conversion circuit capable of performing battery charging and cell balancing functions in a state in which an external charger providing a predetermined fixed voltage is connected.

According to the present invention, according to an embodiment, it is possible to provide a power conversion circuit capable of performing high-speed charging of a battery and cell balancing functions in a state in which an external charger providing a variable voltage within a predetermined range is connected.

According to the present invention, according to an embodiment, it is possible to provide a power conversion circuit that can reduce the number of parts, be implemented with a simple structure, and operate with high efficiency.

1 illustrates a power conversion circuit according to one embodiment of the present invention.
2 to 5 illustrate how the current path management circuit in the embodiment of FIG. 1 operates according to a state of an external charger.
FIG. 6 illustrates an operating waveform when the first converter circuit according to the embodiment of FIG. 1 operates in a switched capacitor converter mode.
7 and 8 illustrate operating waveforms when the first converter circuit according to the embodiment of FIG. 1 operates in buck converter mode.
FIG. 9 illustrates an operating waveform when the second converter circuit according to the embodiment of FIG. 1 operates in a switched capacitor converter mode.
10 illustrates another embodiment of the first converter circuit.
FIG. 11 illustrates an operating waveform when the first converter circuit according to the embodiment of FIG. 10 operates in a switched capacitor converter mode.
12 and 13 illustrate operating waveforms when the first converter circuit according to the embodiment of FIG. 10 operates in buck converter mode.
14 illustrates a power conversion circuit in the case of using another embodiment of the second converter circuit.

Hereinafter, some embodiments of the present invention will be described in detail through exemplary drawings. In adding reference numerals to components of each drawing, it should be noted that the same components have the same numerals as much as possible even if they are displayed on different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description will be omitted.

Also, terms such as first, second, A, B, (a), and (b) may be used in describing the components of the present invention. These terms are only used to distinguish the component from other components, and the nature, order, or order of the corresponding component is not limited by the term. When an element is described as being “connected,” “coupled to,” or “connected” to another element, that element is directly connected or connectable to the other element, but there is another element between the elements. It will be understood that elements may be “connected”, “coupled” or “connected”.

1 illustrates a power conversion circuit according to one embodiment of the present invention.

Referring to FIG. 1 , the power conversion circuit 100 according to the present embodiment may include a current path management circuit, a first converter circuit, a second converter circuit, and a controller 110 .

The current path management circuit may include a first transistor QRB1 , a second transistor QST1 , a third transistor QRB2 , a fourth transistor QST2 , and a fifth transistor QSB. The first converter circuit may include a transistor QA1 , a transistor QB1 , a transistor QC1 , a transistor QD1 , a first flying capacitor CFLY1 , and a first inductor L1 . The second converter circuit may include a transistor QA2 , a transistor QB2 , a transistor QC2 , a transistor QD2 , and a second flying capacitor CFLY2 .

The power conversion circuit 100 may receive power from an external charger TA and provide power to a battery and/or electronic device system. Specifically, the power conversion circuit 100 receives power from an external charger (TA), charging and cell balancing functions of a battery in which a plurality of cells including a first cell 11 and a second cell 12 are connected in series can be performed. The batteries 11 and 12 are generally understood as external components of the power conversion circuit 100, but in some cases, the batteries 11 and 12 may be included in the power conversion circuit 100.

The power conversion circuit 100 may be connected to an external charger TA through an input port (not shown). The input port may be directly connected to the external charger TA of the electronic device or indirectly connected through another circuit to receive power from the external charger TA. The voltage provided from the external charger TA may be fixed at a predetermined voltage, such as 5V or 9V, or may be a variable voltage in the range of 3V to 11V or 3V to 20V. For example, the input port may be USB A-type or USB C-type, but is not limited thereto.

The power conversion circuit 100 may use the voltage provided from the external charger TA without any special processing, but other circuits may be added between the output of the external charger TA and the input VBUS of the power conversion circuit 100. there is. For example, an overvoltage protection circuit, an overcurrent protection circuit, or a voltage regulator may be selectively added between the output of the external charger TA and the input VBUS of the power conversion circuit 100 . Depending on the embodiment, when using an external charger (TA) capable of providing a high voltage (eg, 19V, etc.), the output voltage of the external charger (TA) goes through another step-down converter to 10V, which is about twice the cell voltage. After the voltage is lowered to a level, it may be provided to the power conversion circuit 100 .

As illustrated in FIG. 1, among the elements of the power conversion circuit 100, active elements (controllers, transistors, etc.) are disposed in the integrated circuit 120, and passive elements (capacitors, inductors, etc.) are integrated circuits ( 120), but elements disposed within the integrated circuit 120 may be variously changed. For example, some of the transistors may be located external to integrated circuit 120 and/or some of the passive components may be located within integrated circuit 120 .

1 shows various nodes (or terminals) for connecting the inside and outside of the integrated circuit 120 . VBUS can be understood as an input node of the power conversion circuit 100 as a bus voltage node. MIDVBUS1 is an input voltage node of the first converter circuit, C1P and C1N are nodes connected to both terminals of the first flying capacitor CFLY1, MIDVBUS2 is an input voltage node of the second converter circuit, and C2P and C2N are the second flying capacitor A node connected to both terminals of (CFLY2), BATP_T is a high voltage (+) node of the second cell 12, BATP_B is a high voltage (+) node of the first cell 11, PGND is a node connected to the ground, It can be understood that VSYS is a system voltage node connected to a system load, VOUT1 is an output voltage node of the first converter circuit, and VOUT2 is an output voltage node of the second converter circuit. However, the names of the nodes illustrated in FIG. 1 are examples containing general meanings, and if the names do not match the descriptions below, the names should not be interpreted differently from the descriptions below. . In addition, in the present specification, in the case where there is no concern for confusion, a node and a voltage of a corresponding node may be indicated by the same symbol for convenience of description. For example, 'VBUS' may mean a bus voltage node, but may mean the voltage of a bus voltage node (ie, bus voltage) in some cases.

Next, the current path management circuit, the first converter circuit, the second converter circuit, and the controller 110 included in the power conversion circuit 100 will be described.

The current path management circuit may manage connections between the bus voltage VBUS, the first converter circuit, the second converter circuit, and the batteries 11 and 12 . To this end, the current path management circuit includes a first transistor QRB1 that selectively connects the bus voltage VBUS and the input voltage MIDVBUS1 of the first converter circuit, the input voltage MIDVBUS1 of the first converter circuit and the second transistor QRB1. A second transistor QST1 selectively connecting the high voltage BATP_T of the cell 12, a third transistor QRB2 selectively connecting the bus voltage VBUS and the input voltage MIDVBUS2 of the second converter circuit, and A fourth transistor QST2 selectively connecting the input voltage MIDVBUS2 of the second converter circuit and the high voltage BATP_T of the second cell may be included. According to an embodiment, the current path management circuit further includes a fifth transistor QSB selectively connecting the high voltage BATP_B of the first cell 11 and the low voltage (ie, the VSYS node) of the second cell 12. can include

The current path management circuit may selectively connect the input voltage MIDVBUS1 of the first converter circuit to the bus voltage VBUS and/or the high voltage BATP_T of the second cell 12 through this circuit configuration. Also, the current path management circuit may selectively connect the input voltage MIDVBUS2 of the second converter circuit to the bus voltage VBUS and/or to the high voltage BATP_T of the second cell 12 .

Here, the first transistor QRB1, the second transistor QST1, the third transistor QRB2, the fourth transistor QST2, and the fifth transistor QSB may be bi-directional control transistors capable of bi-directional conduction control. As an example of a transistor capable of bidirectional conduction control, a back-gate control MOSFET or a back-to-back MOSFET may be used, but is not limited thereto.

The first converter circuit may selectively operate in a buck converter mode and a switched capacitor converter mode. The first converter circuit may charge the battery in a buck converter mode and perform a cell balancing function in a switched capacitor converter mode.

Here, in the buck converter mode, the output voltage (MIDVBUS1 in FIG. 1) to the input voltage (MIDVBUS1 in FIG. In FIG. 1, it can be understood as an operation mode in which the ratio of VOUT1) can be variably adjusted in the range of 0 to 1. That is, since the first converter circuit can operate in the buck converter mode, it can operate in response to various relationships between input voltages and output voltages in a range where the output voltage is lower than the input voltage. For example, when the voltage of the first cell 11 is 5V, the first cell 11 operates at various input voltages (eg, 9V, 12V, 19V, etc.) where the input voltage VBUS of the power conversion circuit 100 is 5V or higher. (11) can be charged.

The switched capacitor converter mode may be understood as a mode in which the ratio of the output voltage to the input voltage is substantially fixed to a predetermined value. The first converter circuit illustrated in FIG. 1 may operate such that the ratio of output voltage to input voltage has a relationship of substantially 2:1. That is, in the switched capacitor converter mode, although there is a restriction that the ratio of output voltage to input voltage operates in a substantially fixed state, it can be understood as an operating mode that can operate at high efficiency and high current with less loss compared to the buck converter mode. there is.

When operating in the switched capacitor converter mode, the first converter circuit may perform a cell balancing function between the first cell 11 and the second cell 12 . When the transistor QST1 and the transistor QSB of the current path management circuit are in a conducting state, the high voltage BATP_T of the second cell 12 is connected to the input voltage MIDVBUS1 of the first converter circuit, and the output voltage VOUT1 of the first converter circuit ) is connected to the high voltage BATP_B of the first cell 11 and the low voltage of the second cell 12 through the first inductor L1. Since the first converter circuit operates so that the input voltage MIDVBUS1 and the output voltage VOUT1 have a substantially 2:1 relationship in the switched capacitor converter mode, voltages equal to the first cell 11 and the second cell 12 are obtained. can be formed. Accordingly, the first converter circuit may perform a cell balancing function between the two cells 11 and 12 .

Exemplarily, the first converter circuit includes transistor QA1, transistor QB1, transistor QC1, transistor QD1, transistor QA1 and transistor QB1 connected in series between the input voltage MIDVBUS1 and the ground PGND. It may include a first flying capacitor CFLY1 connected between the contact point of QC1 and the transistor QD1, and a first inductor L1 having one end connected to the contact point between the transistor QB1 and the transistor QC1. The other end of the first inductor L1 is connected to the system voltage VSYS to function as a current output node.

The first converter circuit configured as described above may selectively operate in a buck converter mode or a switched capacitor converter mode according to an on/off sequence of transistors QA1 , transistor QB1 , transistor QC1 , and transistor QD1 . As described above, the first converter circuit can adjust the output voltage (VOUT1) within a lower range than the input voltage (MIDVBUS1) in the buck converter mode, and in the switched capacitor converter mode, the input voltage (MIDVBUS1) and the output voltage ( The ratio of VOUT1) may be operated so as to have a relationship of substantially 2:1.

Although an embodiment of the first converter circuit is shown in FIG. 1, the first converter circuit is not limited to the circuit illustrated in FIG. 1, and any converter circuit capable of selectively operating in a buck converter mode and a switched capacitor converter mode It can be used in the first converter circuit of the embodiment.

The second converter circuit may operate in a switched capacitor converter mode and perform a cell balancing function. The second converter circuit operates in the switched capacitor converter mode so that the ratio of the input voltage (MIDVBUS2 in the case of the embodiment of FIG. 1) and the output voltage (VOUT2 in the case of the embodiment of FIG. 1) has a substantially 2:1 relationship. there is.

Illustratively, the second converter circuit includes transistor QA2, transistor QB2, transistor QC2, transistor QD2, transistor QA2 and transistor QB2 connected in series between the input voltage MIDVBUS2 and the ground PGND of the second converter circuit. A second flying capacitor CFLY2 connected between the transistor QC2 and the contact point of the transistor QD2 may be included. The junction of transistor QB2 and transistor QC2 can be understood as the output voltage node VOUT2.

The second converter circuit configured as described above operates in a switched-capacitor converter mode according to the on/off sequence of the transistors QA2, QB2, transistor QC2, and transistor QD2 so that the ratio of the input voltage to the output voltage has a relationship of substantially 2:1. It can work.

When the transistor QST2 and the transistor QSB of the current path management circuit are in a conducting state, the high voltage BATP_T of the second cell 12 is connected to the input voltage MIDVBUS2 of the second converter circuit and the output voltage VOUT2 of the first cell The high voltage BATP_B of (11) and the low voltage of the second cell 12 are connected. In the second converter circuit, the relationship between the input voltage MIDVBUS2 and the output voltage VOUT2 is substantially 2:1 in the switched capacitor converter mode. Since it operates to have , equal voltages can be formed in the first cell 11 and the second cell 12 . Accordingly, the second converter circuit may perform a cell balancing function between the two cells 11 and 12 .

Although an embodiment of the second converter circuit is shown in FIG. 1, the second converter circuit is not limited to the circuit illustrated in FIG. can be used for

The controller 110 may perform overall control of the power conversion circuit 100 . That is, the controller 110 may control the first converter circuit, the second converter circuit, and the current path management circuit. The controller 110 may communicate with a power management integrated circuit (PMIC, not shown) that manages power of the electronic device system and transmit/receive information for controlling the power conversion circuit 100 according to an embodiment. Illustratively, the controller 110 controls on/off switching operations of a plurality of transistors inside the power conversion circuit 100 to supply voltage and current to the battery voltage nodes BATP_T and BATP_B and the system voltage node VSYS. , at least one of the power can be adjusted. When the external charger (TA) can vary the output voltage, the controller 110 directly requests information on the voltage to be provided from the external charger (TA) to the external charger (TA) or other information such as a power management integrated circuit By requesting the external charger (TA) through the device, the power conversion circuit 100 can operate at the optimal bus voltage (VBUS).

Depending on the embodiment, the controller 110 is implemented as software and stored in a computer-readable storage medium (memory, etc.), and may perform its function by an arithmetic device such as a CPU. Alternatively, according to embodiments, the controller 110 may be implemented in hardware such as an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA).

1 illustrates various voltage stabilizing capacitors (CVBUS, CMID1, CMID2, CVSYS, CTOP). Capacitor CVBUS is a capacitor for stabilizing the bus voltage (VBUS) of the power conversion circuit 100, capacitor CMID1 is a capacitor for stabilizing the input voltage (MIDVBUS1) of the first converter circuit, and capacitor CMID2 is a capacitor for stabilizing the input voltage (MIDVBUS1) of the second converter circuit. The capacitor CVSYS is a capacitor for stabilizing the input voltage MIDVBUS2, the capacitor CVSYS is a capacitor for stabilizing the system voltage VSYS, and the capacitor CTOP is a voltage between the system voltage VSYS and the input voltage MIDVBUS2 of the second converter circuit. It can be understood as a capacitor for stabilization. The voltage stabilization capacitors (CVBUS, CMID1, CMID2, CVSYS, CTOP) illustrated in FIG. 1 may be selectively used as needed, and other stabilization capacitors not illustrated in FIG. 1 may be added as needed.

The power conversion circuit 100 may include a transistor driving buffer (not shown). The buffer may be selectively used as needed to receive a signal provided by the controller 110 to drive a transistor and to apply an appropriate driving signal to a corresponding transistor. For example, the buffer may be used to amplify a current applied to a gate terminal of a transistor, amplify a voltage, or drive a transistor in a floating state. If the controller 110 can directly drive the transistor, a buffer for driving the transistor may not be used.

2 to 5 illustrate how the current path management circuit in the embodiment of FIG. 1 operates according to the external charger state.

Referring to FIG. 2 , three states of the external charger TA may be considered. That is, a state in which an external charger is not connected, a state in which a variable output voltage external charger is connected, and a state in which a fixed output voltage external charger is connected may be considered. Figure 2 illustrates the on (ON) or off (OFF) state of the transistors of the current path management circuit for the above three states. It can be understood that each transistor conducts in an on state and shuts off in an off state. Below, the operation of the current path management circuit in three connection states of the external charger will be described in detail with reference to FIGS. 3 to 5 .

3 conceptually describes a case in which an external charger TA is not connected. Referring to FIGS. 2 and 3 , when the external charger TA is not connected, among the transistors of the current path management circuit, transistors QST1, QST2, and QSB may be turned on, and transistors QRB1 and QRB2 may be turned off. That is, the current path management circuit may connect the high voltage BATP_T of the second cell 12 to the input voltage MIDVBUS1 of the first converter circuit and the input voltage MIDVBUS2 of the second converter circuit through the transistors QST1 and QST2. . Also, the current path management circuit may connect the high voltage BATP_B of the first cell 11 and the low voltage of the second cell 12 through the transistor QSB.

In this case, the input voltage MIDVBUS1 of the first converter circuit and the input voltage MIDVBUS2 of the second converter circuit are connected to the high voltage BATP_T of the second cell 12, respectively, and the output voltage VOUT1 of the first converter circuit ) and the output voltage VOUT2 of the second converter circuit are connected to the contact points of the high voltage BATP_B of the first cell 11 and the low voltage of the second cell 12, respectively, the first converter circuit and the second converter circuit Each may operate in a switched capacitor converter mode to perform a cell balancing function between the first cell 11 and the second cell 12 . Since the transistors QRB1 and QRB2 are off when the external charger TA is not connected, the bus voltage VBUS may not be connected to the first converter circuit and the second converter circuit.

When the first converter circuit and the second converter circuit each operate in the switched capacitor converter mode, according to embodiments, the first converter circuit and the second converter circuit may perform a switching operation with a phase difference of substantially 180 degrees from each other. According to this method, since the currents of the first converter circuit and the second converter circuit are out of phase by 180 degrees, the peak value of the current for cell balancing is reduced.

4 conceptually illustrates a case in which a variable output voltage external charger TA is connected. Referring to FIGS. 2 and 4 , when the variable output voltage external charger TA is connected, all of the transistors QRB1, QST1, QRB2, QST2, and QSB of the current path management circuit may be turned on. That is, the current path management circuit may connect the bus voltage VBUS to the high voltage BATP_T of the second cell, the input voltage MIDVBUS1 of the first converter circuit, and the input voltage MIDVBUS2 of the second converter circuit. Also, the current path management circuit may connect the high voltage BATP_B of the first cell 11 and the low voltage of the second cell 12 through the transistor QSB.

In this case, the input voltage MIDVBUS1 of the first converter circuit and the input voltage MIDVBUS2 of the second converter circuit are connected to the high voltage BATP_T of the second cell 12, and the output voltage VOUT1 of the first converter circuit and the output voltage VOUT2 of the second converter circuit is connected to the contact point of the high voltage BATP_B of the first cell 11 and the low voltage of the second cell 12, so the first converter circuit and the second converter circuit are each switched By operating in a capacitor converter mode, a cell balancing function between the first cell 11 and the second cell 12 may be performed.

At this time, the current path management circuit may directly perform high-speed charging of the batteries 11 and 12 by connecting the bus voltage VBUS to the high voltage BATP_T of the second cell 12 . That is, the current path management circuit directly converts the power provided from the external charger TA from the bus voltage VBUS through the transistors QRB1 and QST1 without passing through the first converter circuit or the second converter circuit to the high voltage of the second cell 12 ( BATP_T) or from the bus voltage VBUS through the transistors QRB2 and QST2, by providing a path directly supplied to the high voltage BATP_T of the second cell 12, the power provided from the external charger TA is supplied to the battery 11 , 12) to perform high-speed charging.

To this end, the controller 110 may request the external charger TA, which provides a variable output voltage, to adjust the output voltage so that the bus voltage VBUS becomes a voltage suitable for directly performing high-speed charging of the batteries 11 and 12. there is. That is, when an external charger (TA) providing a variable output voltage is connected, the power conversion circuit 100 considers the voltage, state of charge, temperature, etc. Charging efficiency may be increased by requesting a voltage suitable for charging from an external charger (TA) and directly charging the batteries 11 and 12 using a current path management circuit.

Meanwhile, when a variable output voltage external charger is connected, the first converter circuit and the second converter circuit may each operate in a switched capacitor converter mode and perform a cell balancing function. According to an embodiment, the first converter circuit and the second converter The circuits can operate switching with a phase difference of substantially 180 degrees from each other. According to this method, as described above, there is an advantage in that the peak value of the current is reduced due to a phase difference between the currents for cell balancing in the first converter circuit and the second converter circuit.

5 conceptually illustrates a case in which a fixed output voltage external charger is connected. Referring to FIGS. 2 and 5 , when a fixed output voltage external charger is connected, transistors QRB1 , QST2 , and QSB of the current path management circuit may be turned on, and transistors QST1 and QRB2 may be turned off. That is, the current path management circuit connects the bus voltage VBUS to the input voltage MIDVBUS1 of the first converter circuit through the transistor QRB1, and connects the high voltage BATP_T of the second cell to the input of the second converter circuit through the transistor QST2. It can be connected to the voltage (MIDVBUS2). Also, the current path management circuit may connect the high voltage BATP_B of the first cell 11 and the low voltage of the second cell 12 through the transistor QSB.

In this case, the input voltage MIDVBUS1 of the first converter circuit is connected to the bus voltage VBUS, and the output voltage VOUT1 of the first converter circuit is connected to the high voltage BATP_B of the first cell 11 through the transistor QSB. Accordingly, the first converter circuit operates in a buck converter mode to charge the first cell 11 by supplying the power received from the bus voltage VBUS to the first cell 11 .

When an external charger providing a fixed output voltage is connected, the relationship between the bus voltage (VBUS) and the first cell 11 voltage may be different from 2:1. In this case, the switched capacitor converter mode is used to charge the battery. Considering how difficult it can be. That is, the power conversion circuit 100 of the present embodiment has the advantage of being able to effectively respond to a situation where the voltage provided by an external charger can be varied by allowing the first converter circuit to selectively operate even in the buck converter mode. there is.

Depending on the embodiment, the first converter circuit may operate with a duty determined based on a ratio between the bus voltage VBUS and the voltage of the first cell 11 in the buck converter mode. That is, the first converter circuit may charge the first cell 11 in response to various bus voltages (VBUS) by adjusting the duty. Here, the duty may be understood as a ratio of a conduction period of transistors to a switching period. According to embodiments, the buck converter mode in which the first converter circuit operates may be a 3-level buck converter operating mode using an inductor.

When an external charger providing a fixed output voltage is connected, the input voltage MIDVBUS2 of the second converter circuit is connected to the high voltage BATP_T of the second cell 12 through the transistor QST2, and the output voltage of the second converter circuit ( Since VOUT2 is connected to the contact point of the high voltage (BATP_B) of the first cell 11 and the low voltage of the second cell 12, the second converter circuit operates in a switched capacitor converter mode to convert the first cell 11 to the second cell 11. A cell balancing function between cells 12 may be performed. As described above, since the power supplied from the external charger TA charges the first cell 11 through the first converter circuit, the second converter circuit transfers power from the first cell 11 to the second cell 12. Cell balancing may be performed by supplying power.

FIG. 6 illustrates an operating waveform when the first converter circuit according to the embodiment of FIG. 1 operates in a switched capacitor converter mode.

In FIG. 6 , VC1P is the voltage of the C1P node, VOUT1 is the output voltage of the first converter circuit, and VC1N is the voltage of the C1N node. Since the first flying capacitor CFLY1 is connected between the C1P node and the C1N node, the voltage obtained by subtracting VC1N from VC1P can be understood as the voltage VCFLY1 of the first flying capacitor CFLY1.

Referring to FIG. 6 , transistor QA1 and transistor QC1 are turned on/off substantially simultaneously with a duty of 0.5, and transistor QB1 and transistor QD1 may be turned on/off substantially opposite to transistor QA1. Here, the duty may be defined as the ratio of the on-period of the transistor (eg, QA1) to the switching period (the sum of the on-period and off-period).

Operations in the on-period of the transistors QA1 and QC1 will be described as an example. In this case, the C1P node is connected to the input voltage (VIN, which corresponds to the input voltage (MIDVBUS1) of the first converter circuit in the embodiment of FIG. 1, but is indicated as the input voltage (VIN) for convenience of explanation) through the transistor QA1. and the C1N node is connected to the output voltage VOUT1 through the transistor QC1. Accordingly, a voltage obtained by subtracting the first flying capacitor voltage VCFLY1 from the input voltage VIN is applied to the C1N node and the output voltage VOUT1.

Next, operations in the on-period of the transistors QB1 and QD1 will be exemplarily described. In this case, the C1P node is connected to the output voltage (VOUT1) through the transistor QB1, and the C1N node is connected to the ground (PGND) through the transistor QD1. Accordingly, the first flying capacitor voltage VCFLY1 is applied to the C1P node and the output voltage VOUT1. That is, the first flying capacitor voltage VCFLY1 and the output voltage VOUT1 become equal to each other.

As such, the first flying capacitor voltage VCFLY1 and the output voltage VOUT1 are equal to each other, and the input voltage VIN is equal to the sum of the first flying capacitor voltage VCFLY1 and the output voltage VOUT1. 1 The flying capacitor voltage (VCFLY1) and the output voltage (VOUT1) are each half of the input voltage (VIN). Therefore, since the ratio of the input voltage VIN and the output voltage VOUT1 theoretically has a relationship of 2:1, the first converter circuit performs a cell balancing function between the first cell 11 and the second cell 12 can be done

Here, the ratio of the input voltage (VIN) to the output voltage (VOUT1) is actually referred to as 2:1 in this specification in that a slight difference from 2:1 may occur due to the voltage drop of the elements, etc. It should be understood as including a range that can be seen as having a 2:1 relationship. Similarly, even when the value of a certain physical quantity (eg, voltage, etc.) is referred to in this specification, it should be understood to include a range that can be viewed as having a substantially corresponding value.

7 and 8 illustrate operating waveforms when the first converter circuit according to the embodiment of FIG. 1 operates in buck converter mode. 7 illustrates a case in which the duty is greater than or equal to 0.5, and FIG. 8 illustrates a case in which the duty is less than 0.5.

7 illustrates on/off operations and main waveforms (VC1P, VOUT1, VC1N, IL1) of transistor QA1, transistor QB1, transistor QC1, and transistor QD1 in buck converter mode (D ≥ 0.5). IL1 is the current of the first inductor (L1).

Referring to FIG. 7 , the transistor QA1 may be turned on/off repeatedly with an adjustable duty. The duty may be defined as the ratio of the on-period to the switching period (the sum of the on-period and off-period). For convenience of explanation, the duty in the buck converter mode will be defined as the duty of the transistor QA1. For example, the duty of the transistor QA1 can be understood as a ratio of the sum of the lengths of the sections ①, ②, and ④ (the on-period of the transistor QA1) to the sum of the lengths of the sections ① to ④. Transistor QB1 has the same duty as transistor QA1 but can be turned on/off in a phase shifted by substantially 180 degrees. Transistor QC1 can be turned on and off substantially the opposite of transistor QB1. Transistor QD1 can be turned on and off substantially the opposite of transistor QA1.

First, an operation in section 1 of FIG. 7 , that is, an ON section of transistor QA1 and transistor QC1 will be exemplarily described. The C1P node is connected to the input voltage VIN through the transistor QA1, and the C1N node is connected to the output voltage VOUT1 and one end of the first inductor L1 through the transistor QC1. The other end of the first inductor L1 is connected to the system voltage VSYS, and when the fifth transistor QSB is turned on, the other end of the first inductor L1 is also connected to the high voltage BATP_B of the first cell 11. can At this time, a voltage obtained by subtracting the first flying capacitor voltage VCFLY1 from the input voltage VIN (VIN - VCFLY1 = VIN/2) is applied to the output voltage VOUT1 to which one end of the first inductor L1 is connected, The system voltage VSYS is applied to the other end of the first inductor L1. When the duty is greater than 0.5, the system voltage VSYS is greater than half of the input voltage VIN as will be described later, so that the first inductor current ( IL1) decreases.

Next, an operation in section ② of FIG. 7 , that is, an ON section of transistor QA1 and transistor QB1 will be described as an example. The C1P node is connected to the input voltage VIN through the transistor QA1 and connected to the output voltage VOUT1 and one end of the first inductor L1 through the transistor QB1. A voltage obtained by subtracting the first flying capacitor voltage VCFLY1 from the input voltage VIN is applied to the C1N node. The other end of the first inductor L1 is connected to the system voltage VSYS. At this time, the input voltage VIN is applied to the output voltage VOUT1 to which one end of the first inductor L1 is connected, and the system voltage VSYS is applied to the other end of the first inductor L1. ) is higher than the system voltage (VSYS), so the inductor current (IL) increases.

Next, an operation in section ③ of FIG. 7, that is, an ON section of transistor QB1 and transistor QD1, will be described as an example. The C1P node is connected to the output voltage VOUT1 and one end of the first inductor L1 through the transistor QB1. The C1N node is connected to ground (PGND) through transistor QD1. The other end of the first inductor L1 is connected to the system voltage VSYS. At this time, the first flying capacitor voltage (VCFLY1 = VIN/2) is applied to the output voltage VOUT1 to which one end of the first inductor L1 is connected, and the system voltage VSYS is applied to the other end of the first inductor L1. However, since the system voltage VSYS is higher than the first flying capacitor voltage VCFLY1, the first inductor current IL1 decreases.

Next, since the operation in section ④ of FIG. 7, ie, the on-period of transistor QA1 and transistor QB1, is similar to that in section ②, a detailed description thereof will be omitted.

When the duty is greater than 0.5 in the buck converter mode, the operations of sections ① to ④ in FIG. 7 are repeated. The output voltage VOUT1 is applied to one end of the first inductor L1 and the system voltage VSYS to the other end. this is authorized At this time, half of the input voltage VIN is applied to the output voltage VOUT1 in sections ① and ③, and the input voltage VIN is applied in sections ② and ④. Since the capacitance of the system input terminal is usually sufficiently large, it can be assumed that the system voltage VSYS has a constant value without change within one switching cycle. In addition, since the average of the voltages applied to one end and the other end of the first inductor L1 in a steady-state is the same, the average of the output voltage VOUT1 and the average of the system voltage VSYS become the same. Accordingly, the system voltage VSYS has a value higher than half of the input voltage VIN and lower than the input voltage VIN.

The ratio of the system voltage VSYS to the input voltage VIN can be controlled by adjusting the ratio of the sum of the section ① and section ③ or the sum of section ② and section ④ with respect to the switching period. That is, the ratio of the system voltage VSYS to the input voltage VIN (that is, the voltage conversion ratio) can be adjusted through the duty of the transistor QA1 (for convenience of explanation, the duty of the transistor QA1 is taken as a representative example, but other transistors It can also be understood that it is adjusted according to the duty of ).

As such, the first converter circuit may be adjusted in a range where the output voltage VOUT1 or the system voltage VSYS is higher than half of the input voltage VIN and lower than the input voltage VIN when the duty is 0.5 or more in the buck converter mode. can In other words, the ratio of the output voltage to the input voltage can be adjusted in the range of 0.5 to 1.

8 illustrates the on/off operations and main waveforms (VC1P, VOUT1, VC1N, IL1) of transistor QA1, transistor QB1, transistor QC1, and transistor QD1 in buck converter mode (D < 0.5).

Referring to FIG. 8 , the transistor QA1 may be turned on/off repeatedly with an adjustable duty. Transistor QB1 has the same duty as transistor QA1 but can be turned on/off in a phase shifted by substantially 180 degrees. Transistor QC1 can be turned on and off substantially the opposite of transistor QB1. Transistor QD1 can be turned on and off substantially the opposite of transistor QA1. That is, the driving method for the transistors in the buck converter mode (D < 0.5) is the same as the driving method in the buck converter mode (D ≥ 0.5) illustrated in FIG. 7 . However, there is a difference in that the on/off combination of the four transistors is partially different from that of FIG.

First, an operation in section 1 of FIG. 8, that is, an on-period of transistor QA1 and transistor QC1, will be exemplarily described. The C1P node is connected to the input voltage VIN through the transistor QA1, and the C1N node is connected to the output voltage VOUT1 and one end of the first inductor L1 through the transistor QC1. The other end of the first inductor L1 is connected to the system voltage VSYS, and may also be connected to the high voltage BATP_B of the first cell 11 when the transistor QSB is turned on. At this time, a voltage obtained by subtracting the first flying capacitor voltage VCFLY1 from the input voltage VIN (VIN - VCFLY1 = VIN/2) is applied to the output voltage VOUT1 to which one end of the first inductor L1 is connected, The system voltage VSYS is applied to the other end of the first inductor L1. When the duty is less than 0.5, the system voltage VSYS is less than half of the input voltage VIN as will be described later, so that the first inductor current ( IL1) increases.

Next, an operation in section ② of FIG. 8, that is, an ON section of transistor QC1 and transistor QD1, will be described as an example. A first flying capacitor voltage (VCFLY1 = VIN/2) is applied to the C1P node. The C1N node is connected to the output voltage VOUT1 and one end of the first inductor L1 through the transistor QC1, and is also connected to the ground PGND through the transistor QD1. The other end of the first inductor L1 is connected to the system voltage VSYS. At this time, the ground (PGND) voltage (ie, 0V) is applied to the output voltage (VOUT1) to which one end of the first inductor (L1) is connected, and the system voltage (VSYS) is applied to the other end of the first inductor (L). , the first inductor current IL1 decreases.

Next, an operation in section ③ of FIG. 8, that is, an ON section of transistor QB1 and transistor QD1, will be described as an example. The C1P node is connected to the output voltage VOUT1 and one end of the first inductor L1 through the transistor QB1. The C1N node is connected to ground (PGND) through transistor QD1. The other end of the first inductor L1 is connected to the system voltage VSYS. At this time, the first flying capacitor voltage (VCFLY1 = VIN/2) is applied to the output voltage VOUT1 to which one end of the first inductor L1 is connected, and the system voltage VSYS is applied to the other end of the first inductor L1. However, since the system voltage VSYS is lower than the first flying capacitor voltage VCFLY1, the first inductor current IL1 increases.

Next, since the operation in the period ④ of FIG. 8, that is, the ON period of the transistor QC1 and the transistor QD1, is similar to the operation in the period ②, a detailed description thereof will be omitted.

In the buck mode, when the duty is less than 0.5, the operations of sections ① to ④ in FIG. 8 are repeated. At this time, half of the input voltage VIN is applied to the output voltage VOUT1 in sections ① and ③, and ground voltage (ie, 0V) is applied in sections ② and ④. In the steady-state, since the average of the voltage across the inductor is equal to each other, the average of the output voltage VOUT1 and the average of the system voltage VSYS are equal to each other. Accordingly, the system voltage VSYS has a value lower than half of the input voltage VIN. The ratio of the system voltage VSYS to the input voltage VIN can be controlled by adjusting the ratio (ie, duty) of the sum of the period ① and the period ③ with respect to the switching period.

As such, when the duty cycle of the first converter circuit is less than 0.5 in the buck converter mode, the output voltage VOUT1 or the system voltage VSYS may be adjusted within a range lower than half of the input voltage VIN. In other words, the ratio of the output voltage to the input voltage can be adjusted in the range of 0 to 0.5.

As described above with reference to FIGS. 7 and 8, the first converter circuit can adjust the ratio of the output voltage to the input voltage in the range of 0 to 1 by adjusting the duty of the transistors when operating in the buck converter mode. 1 The converter circuit can operate in response to changes in battery voltage and various input voltages. For example, the power conversion circuit 100 can effectively respond even when an external charger provides various fixed voltages by utilizing the buck converter mode of the first converter circuit.

FIG. 9 illustrates an operating waveform when the second converter circuit according to the embodiment of FIG. 1 operates in a switched capacitor converter mode.

9, VC2P is the voltage of the C2P node, VOUT2 is the output voltage of the second converter circuit, and VC2N is the voltage of the C2N node. Since the second flying capacitor CFLY2 is connected between the C2P node and the C2N node, the voltage obtained by subtracting VC2N from VC2P can be understood as the voltage VCFLY2 of the second flying capacitor.

Referring to FIG. 9 , the transistors QA2 and QC2 may be turned on/off simultaneously with a duty of substantially 0.5, and the transistors QB2 and QD2 may be substantially turned on/off opposite to the transistor QA2. Here, the duty may be defined as the ratio of the on-period of the transistor (eg, QA2) to the switching period (the sum of the on-period and off-period).

Operations in the on-period of the transistors QA2 and QC2 will be described as an example. The C2P node is connected to the input voltage (VIN, which corresponds to the input voltage (MIDVBUS2) of the second converter circuit in the embodiment of FIG. 1, but is indicated as the input voltage (VIN) for convenience of explanation) through the transistor QA2, and C2N. The node is connected to the output voltage (VOUT2) through transistor QC2. Accordingly, a voltage obtained by subtracting the second flying capacitor voltage VCFLY2 from the input voltage VIN (VIN - VCFLY2 = VIN/2) is applied to the C2N node and the output voltage VOUT2.

Next, operations in the on-period of the transistors QB2 and QD2 will be described as an example. The C2P node is connected to the output voltage (VOUT2) through transistor QB2, and the C2N node is connected to ground (PGND) through transistor QD2. Accordingly, the second flying capacitor voltage VCFLY2 is applied to the C2P node and the output voltage VOUT2. That is, the second flying capacitor voltage VCFLY2 and the output voltage VOUT2 become equal to each other.

As such, the second flying capacitor voltage VCFLY2 and the output voltage VOUT2 are equal to each other, and the input voltage VIN is equal to the sum of the second flying capacitor voltage VCFLY2 and the output voltage VOUT2. 2 The flying capacitor voltage (VCFLY2) and the output voltage (VOUT2) are each half of the input voltage (VIN). Therefore, since the ratio of the input voltage VIN and the output voltage VOUT2 theoretically has a relationship of 2:1, the second converter circuit performs a cell balancing function between the first cell 11 and the second cell 12 can be done

10 illustrates another embodiment of the first converter circuit. The circuit illustrated in FIG. 10 may be used instead of the first converter circuit described with reference to FIG. 1 .

Referring to FIG. 10, the first converter circuit includes a transistor QA1, a transistor QB1, a transistor QC1, a transistor QD1, and a transistor sequentially connected in series between the input voltage (VIN, ie, MIDVBUS1) of the first converter circuit and the ground (PGND). A first flying capacitor CFLY1 connected between the contact point of QA1 and transistor QB1 and the contact point of transistor QC1 and transistor QD1, transistor QE1 and transistor QF1 connected in series between both ends of the first flying capacitor CFLY1, transistor QB1 and transistor QC1 It may include a first inductor (L1) one end connected to the contact of.

At this time, the other end of the first inductor L1 is connected to the low voltage and the system voltage VSYS of the second cell 12 to function as a buck converter mode current output node. In addition, the contact point VOUT3 of the transistor QE1 and the transistor QF1 is connected to the high voltage BATP_B of the first cell 11 to function as an output voltage node of the switched capacitor converter mode. A transistor QSB is connected between the high voltage BATP_B of the first cell 11 and the low voltage of the second cell 12 to selectively convert the high voltage BATP_B of the first cell 11 and the low voltage of the second cell 12. (Here, the transistor QSB may be understood to be included in the current path management circuit as described with reference to FIG. 1).

In the first converter circuit configured as described above, the transistor QA1, the transistor QE1, the transistor QF1, and the transistor QD1 operate while repeating on/off at a predetermined switching cycle in the switched capacitor converter mode, so that the input voltage VIN and the output voltage VOUT3 are substantially It can be made to have a 2:1 relationship. In addition, the first converter circuit operates while repeating on/off of the transistors QA1, transistor QB1, transistor QC1, and transistor QD1 in a buck converter mode at a predetermined switching cycle, thereby increasing the output voltages VOUT1 and VSYS lower than the input voltage VIN. can be adjusted in range. Below, the operation of the first converter circuit illustrated in FIG. 10 will be described in detail with reference to FIGS. 11 to 13 .

FIG. 11 illustrates an operating waveform when the first converter circuit according to the embodiment of FIG. 10 operates in a switched capacitor converter mode.

In FIG. 11, VOUT3 is the switched capacitor mode output voltage of the first converter circuit. Referring to FIG. 11 , transistor QA1 and transistor QF1 may be turned on/off simultaneously with a duty of substantially 0.5, and transistor QE1 and transistor QD1 may be substantially turned on/off opposite to transistor QA1.

The operation in the on-period of the transistor QA1 and the transistor QF1 will be described as an example. In this case, the C1P node is connected to the input voltage VIN through the transistor QA1, and the C1N node is connected to the output voltage VOUT3 through the transistor QF1. Accordingly, a voltage obtained by subtracting the first flying capacitor voltage VCFLY1 from the input voltage VIN is applied to the C1N node and the output voltage VOUT3.

Next, operations in the on-period of the transistors QE1 and QD1 will be exemplarily described. In this case, the C1P node is connected to the output voltage (VOUT3) through the transistor QE1, and the C1N node is connected to the ground (PGND) through the transistor QD1. Accordingly, the first flying capacitor voltage VCFLY1 is applied to the C1P node and the output voltage VOUT3. That is, the first flying capacitor voltage VCFLY1 and the output voltage VOUT3 become equal to each other.

As such, the first flying capacitor voltage VCFLY1 and the output voltage VOUT3 are equal to each other, and the input voltage VIN is equal to the sum of the first flying capacitor voltage VCFLY1 and the output voltage VOUT3. 1 The flying capacitor voltage (VCFLY1) and the output voltage (VOUT3) are each half of the input voltage (VIN). Therefore, since the ratio of the input voltage VIN and the output voltage VOUT3 theoretically has a relationship of 2:1, the first converter circuit performs a cell balancing function between the first cell 11 and the second cell 12 can be done

12 and 13 illustrate operating waveforms when the first converter circuit according to the embodiment of FIG. 10 operates in buck converter mode.

12 illustrates on/off operations and main waveforms (VC1P, VOUT1, VC1N, IL1) of transistor QA1, transistor QB1, transistor QC1, and transistor QD1 in buck converter mode (D ≥ 0.5).

Referring to FIG. 12 , the transistor QA1 may be turned on/off repeatedly with an adjustable duty. For example, the duty of the transistor QA1 can be understood as a ratio of the sum of the lengths of the sections ①, ②, and ④ (the ON period of the transistor QA1) to the sum of the lengths of the sections ① to ④. Transistor QB1 has the same duty as transistor QA1 but can be turned on/off in a phase shifted by substantially 180 degrees. Transistor QC1 can be turned on and off substantially the opposite of transistor QB1. Transistor QD1 can be turned on and off substantially the opposite of transistor QA1.

First, an operation in section 1 of FIG. 12, that is, an ON section of transistor QA1 and transistor QC1, will be exemplarily described. The C1P node is connected to the input voltage VIN through the transistor QA1, and the C1N node is connected to the output voltage VOUT1 and one end of the first inductor L1 through the transistor QC1. The other end of the first inductor L1 is connected to the system voltage VSYS, and when the transistor QSB is turned on, the other end of the first inductor L1 may also be connected to the high voltage BATP_B of the first cell 11. At this time, a voltage obtained by subtracting the first flying capacitor voltage VCFLY1 from the input voltage VIN (VIN - VCFLY1 = VIN/2) is applied to the output voltage VOUT1 to which one end of the first inductor L1 is connected, The system voltage VSYS is applied to the other end of the first inductor L1. When the duty cycle is 0.5 or more, the system voltage VSYS is greater than half of the input voltage VIN as will be described later, so the first inductor current IL1 ) decreases.

Next, an operation in section ② of FIG. 12, that is, an on-period of transistor QA1 and transistor QB1 will be described as an example. The C1P node is connected to the input voltage VIN through the transistor QA1 and connected to the output voltage VOUT1 and one end of the first inductor L1 through the transistor QB1. A voltage obtained by subtracting the first flying capacitor voltage VCFLY1 from the input voltage VIN is applied to the C1N node. The other end of the first inductor L1 is connected to the system voltage VSYS. At this time, the input voltage VIN is applied to the output voltage VOUT1 to which one end of the first inductor L1 is connected, and the system voltage VSYS is applied to the other end of the first inductor L1. ) is higher than the system voltage (VSYS), so the inductor current (IL) increases.

Next, an operation in section ③ of FIG. 12, that is, an ON section of transistor QB1 and transistor QD1, will be described as an example. The C1P node is connected to the output voltage VOUT1 and one end of the first inductor L1 through the transistor QB1. The C1N node is connected to ground (PGND) through transistor QD1. The other end of the first inductor L1 is connected to the system voltage VSYS. At this time, the first flying capacitor voltage (VCFLY1 = VIN/2) is applied to the output voltage VOUT1 to which one end of the first inductor L1 is connected, and the system voltage VSYS is applied to the other end of the first inductor L1. However, since the system voltage VSYS is higher than the first flying capacitor voltage VCFLY1, the first inductor current IL1 decreases.

Next, since the operation in the period ④ of FIG. 12, that is, the ON period of the transistor QA1 and the transistor QB1, is similar to the operation in the period ②, a detailed description thereof will be omitted.

When the duty is 0.5 or more in the buck converter mode, the operations of sections ① to ④ of FIG. 12 are repeated. The output voltage VOUT1 is applied to one end of the first inductor L1 and the system voltage VSYS is authorized At this time, half of the input voltage VIN is applied to the output voltage VOUT1 in sections ① and ③, and the input voltage VIN is applied in sections ② and ④. Accordingly, the system voltage VSYS has a value higher than half of the input voltage VIN and lower than the input voltage VIN.

The ratio of the system voltage VSYS to the input voltage VIN can be controlled by adjusting the ratio of the sum of the period ① and ③ or the sum of the period ② and ④ (ie, duty) for the switching period.

As such, in the first converter circuit according to the embodiment of FIG. 10 , when the duty is 0.5 or more in the buck converter mode, the output voltage VOUT1 or the system voltage VSYS is higher than half of the input voltage VIN and the input voltage VIN ) can be adjusted in a lower range than In other words, the ratio of the output voltage to the input voltage can be adjusted in the range of 0.5 to 1.

13 illustrates the on/off operations and main waveforms (VC1P, VOUT1, VC1N, IL1) of transistor QA1, transistor QB1, transistor QC1, and transistor QD1 in buck converter mode (D < 0.5).

Referring to FIG. 13 , the transistor QA1 may be turned on/off repeatedly with an adjustable duty. Transistor QB1 has the same duty as transistor QA1 but can be turned on/off in a phase shifted by substantially 180 degrees. Transistor QC1 can be turned on and off substantially the opposite of transistor QB1. Transistor QD1 can be turned on and off substantially the opposite of transistor QA1. That is, the driving method for the transistors in the buck converter mode (D < 0.5) is the same as the driving method in the buck converter mode (D ≥ 0.5) illustrated through FIG. 12 . However, there is a difference in that the on/off combination of the four transistors is partially different from that of FIG.

First, the operation in section 1 of FIG. 13, that is, the on section of the transistor QA1 and the transistor QC1, will be exemplarily described. The C1P node is connected to the input voltage VIN through the transistor QA1, and the C1N node is connected to the output voltage VOUT1 and one end of the first inductor L1 through the transistor QC1. The other end of the first inductor L1 is connected to the system voltage VSYS, and may also be connected to the high voltage BATP_B of the first cell 11 when the transistor QSB is turned on. At this time, a voltage obtained by subtracting the first flying capacitor voltage VCFLY1 from the input voltage VIN (VIN - VCFLY1 = VIN/2) is applied to the output voltage VOUT1 to which one end of the first inductor L1 is connected, The system voltage VSYS is applied to the other end of the first inductor L1. When the duty cycle is less than 0.5, the system voltage VSYS is lower than half of the input voltage VIN as will be described later, so that the first inductor current ( IL1) increases.

Next, an operation in section ② of FIG. 13 , that is, an ON section of transistor QC1 and transistor QD1 will be exemplarily described. A first flying capacitor voltage (VCFLY1 = VIN/2) is applied to the C1P node. The C1N node is connected to the output voltage VOUT1 and one end of the first inductor L1 through the transistor QC1, and is also connected to the ground PGND through the transistor QD1. The other end of the first inductor L1 is connected to the system voltage VSYS. At this time, the ground (PGND) voltage (ie, 0V) is applied to the output voltage (VOUT1) to which one end of the first inductor (L1) is connected, and the system voltage (VSYS) is applied to the other end of the first inductor (L). , the first inductor current IL1 decreases.

Next, an operation in the period ③ of FIG. 13, that is, the ON period of the transistor QB1 and the transistor QD1, will be exemplarily described. The C1P node is connected to the output voltage VOUT1 and one end of the first inductor L1 through the transistor QB1. The C1N node is connected to ground (PGND) through transistor QD1. The other end of the first inductor L1 is connected to the system voltage VSYS. At this time, the first flying capacitor voltage (VCFLY1 = VIN/2) is applied to the output voltage VOUT1 to which one end of the first inductor L1 is connected, and the system voltage VSYS is applied to the other end of the first inductor L1. However, since the system voltage VSYS is lower than half of the input voltage VIN, the first inductor current IL1 increases.

Next, since the operation in the period ④ of FIG. 13, that is, the ON period of the transistor QC1 and the transistor QD1, is similar to the operation in the period ②, a detailed description thereof will be omitted.

In the buck mode, when the duty is less than 0.5, operations in sections ① to ④ in FIG. 13 are repeated. At this time, half of the input voltage VIN is applied to the output voltage VOUT1 in sections ① and ③, and ground voltage (ie, 0V) is applied in sections ② and ④. Accordingly, the system voltage VSYS has a value lower than half of the input voltage VIN. The ratio of the system voltage VSYS to the input voltage VIN can be controlled by adjusting the ratio (ie, duty) of the sum of the period ① and the period ③ with respect to the switching period.

As such, when the duty cycle of the first converter circuit is less than 0.5 in the buck converter mode, the output voltage VOUT1 and the system voltage VSYS may be adjusted within a range lower than half of the input voltage VIN. In other words, the ratio of the output voltage to the input voltage can be adjusted in the range of 0 to 0.5.

As described above with reference to FIGS. 11 to 13 , the first converter circuit according to the embodiment of FIG. 10 uses the transistor QA1, transistor QE1, transistor QF1 and transistor QD1 in the switched capacitor converter mode to generate an input voltage (VIN) Not only is it possible to achieve a substantially 2:1 relationship between V and output voltage (VOUT3), but in buck converter mode, by utilizing transistor QA1, transistor QB1, transistor QC1, and transistor QD1, the ratio of output voltage to input voltage can be It can be adjusted in the range of 0 to 1. Therefore, the power conversion circuit 100 can perform the cell balancing function by utilizing the switched capacitor converter mode of the first converter circuit according to the embodiment of FIG. In response to the provided case, the battery can be charged.

14 illustrates a power conversion circuit 1400 when using another embodiment for the second converter circuit.

Referring to FIG. 14 , the second converter circuit used in the power conversion circuit 1400 is illustrated in FIG. 1 in that it further includes a second inductor L2 between the output voltage VOUT2 and the system voltage VSYS. There is a difference from the second converter circuit.

Since the switching sequence and main waveforms of the second converter circuit illustrated in FIG. 14 are similar to those described with reference to FIG. 9 , overlapping descriptions are omitted. However, the second converter circuit illustrated in FIG. 14 may reduce the current peak when there is a voltage difference between the output voltage VOUT2 and the system voltage VSYS due to the existence of the second inductor L2. That is, in the steady-state, the output voltage (VOUT2) and the system voltage (VSYS) will substantially match, so the second inductor (L2) will not play a significant role, but due to various factors, the output voltage (VOUT2) And/or when the system voltage VSYS is in a transient state, the second inductor L2 may reduce a change in current flowing between the output voltage VOUT2 and the system voltage VSYS.

As described above, according to the present invention, according to embodiments, a power conversion circuit having a cell balancing function while efficiently charging a battery in a situation where a plurality of cells are connected in series and charging methods are diversified can be provided. there is. In addition, according to the present invention, according to an embodiment, it is possible to provide a power conversion circuit capable of performing a cell balancing function in a state in which an external charger is not connected. In addition, according to the present invention, according to an embodiment, it is possible to provide a power conversion circuit capable of performing battery charging and cell balancing functions in a state in which an external charger providing a predetermined fixed voltage is connected. In addition, according to the present invention, according to embodiments, a power conversion circuit capable of performing high-speed charging of a battery and cell balancing in a state in which an external charger providing a variable voltage within a predetermined range is connected can be provided. In addition, according to the present invention, according to embodiments, it is possible to provide a power conversion circuit having a reduced number of parts, a simple structure, and high efficiency operation.

Terms such as "comprise", "comprise" or "having" described above mean that the corresponding component may be inherent unless otherwise stated, and therefore do not exclude other components. It should be construed that it may further include other components. All terms, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs, unless defined otherwise. Commonly used terms, such as terms defined in a dictionary, should be interpreted as consistent with the meaning in the context of the related art, and unless explicitly defined in the present invention, they are not interpreted in an ideal or excessively formal meaning.

The above description is merely an example of the technical idea of the present invention, and various modifications and variations can be made to those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed according to the claims below, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

Claims (20)

In a power conversion circuit for receiving power from an external charger and performing charging and cell balancing functions of a battery in which a first cell and a second cell are connected in series,
a first converter circuit selectively operating between a buck converter mode and a switched capacitor converter mode, charging the battery in the buck converter mode and performing the cell balancing function in the switched capacitor converter mode;
a second converter circuit operating in a switched capacitor converter mode and performing the cell balancing function;
current path management circuitry managing connections between a bus voltage node, the first converter circuit, the second converter circuit, and the battery; and
A controller for controlling the first converter circuit, the second converter circuit, and the current path management circuit; including,
When the external charger is not connected, the current path management circuit connects a high voltage node of the second cell to an input voltage node of the first converter circuit and an input voltage node of the second converter circuit, and the first converter circuit and the second converter circuit each operate in the switched capacitor converter mode to perform a cell balancing function between the first cell and the second cell;
When a fixed output voltage external charger is connected, the current path management circuit connects the bus voltage node to the input voltage node of the first converter circuit and the high voltage node of the second cell to the input voltage node of the second converter circuit. The first converter circuit operates in the buck converter mode to charge the first cell, and the second converter circuit operates in the switched capacitor converter mode to charge the first cell between the first cell and the second cell. A power conversion circuit that performs a cell balancing function. delete The method of claim 1,
wherein the first converter circuit and the second converter circuit perform a switching operation with a phase difference of substantially 180 degrees from each other. The method of claim 1,
When a variable output voltage external charger is connected,
the current path management circuit connects the bus voltage node to the high voltage node of the second cell, the input voltage node of the first converter circuit and the input voltage node of the second converter circuit;
Wherein the first converter circuit and the second converter circuit each operate in the switched capacitor converter mode to perform a cell balancing function between the first cell and the second cell. The method of claim 4,
wherein the current path management circuit directly performs fast charging of the battery by connecting the bus voltage node to a high voltage node of the second cell. The method of claim 5,
Wherein the controller requests the variable output voltage external charger to adjust an output voltage so that the bus voltage becomes a voltage suitable for directly performing fast charging of the battery. The method of claim 4,
wherein the first converter circuit and the second converter circuit perform a switching operation with a phase difference of substantially 180 degrees from each other. delete The method of claim 1,
The first converter circuit operates with a duty determined based on a voltage ratio of the bus voltage and the first cell in the buck converter mode. The method of claim 1,
The power conversion circuit of claim 1 , wherein the buck converter mode in which the first converter circuit operates is a 3-level buck converter operation mode using an inductor. The method of claim 1,
The current path management circuit,
a first transistor (QRB1) selectively connecting the bus voltage node and an input voltage node of the first converter circuit;
a second transistor (QST1) selectively connecting an input voltage node of the first converter circuit and a high voltage node of the second cell;
a third transistor (QRB2) selectively connecting the bus voltage node and an input voltage node of the second converter circuit; and
and a fourth transistor (QST2) selectively connecting an input voltage node of the second converter circuit and a high voltage node of the second cell. The method of claim 11,
The current path management circuit further comprises a fifth transistor (QSB) selectively connecting a high voltage node of the first cell and a low voltage node of the second cell. The method of claim 11,
The first transistor (QRB1), the second transistor (QST1), the third transistor (QRB2), and the fourth transistor (QST2) are bi-directional control transistors capable of bi-directional conduction control. The method of claim 1,
The first converter circuit,
a transistor QA1, a transistor QB1, a transistor QC1, and a transistor QD1 sequentially connected in series between an input voltage node of the first converter circuit and a ground (PGND); and
a first flying capacitor CFLY1 coupled between a contact point between the transistor QA1 and the transistor QB1 and a contact point between the transistor QC1 and the transistor QD1;
A power conversion circuit comprising a first inductor (L1) having one end connected to a contact of the transistor QB1 and the transistor QC1. The method of claim 14,
Wherein the first converter circuit selectively operates in a buck converter mode or a switched capacitor converter mode according to an on/off sequence of the transistor QA1, the transistor QB1, the transistor QC1, and the transistor QD1. The method of claim 1,
The first converter circuit,
a transistor QA1, a transistor QB1, a transistor QC1, and a transistor QD1 sequentially connected in series between an input voltage node of the first converter circuit and a ground (PGND);
a first flying capacitor CFLY1 coupled between a contact point between the transistor QA1 and the transistor QB1 and a contact point between the transistor QC1 and the transistor QD1;
a transistor QE1 and a transistor QF1 connected in series between both ends of the first flying capacitor CFLY1;
A first inductor L1 having one end connected to a contact of the transistor QB1 and the transistor QC1,
The other end of the first inductor (L1) functions as an output node of a buck converter mode, and the contact between the transistor QE1 and the transistor QF1 functions as an output node of a switched capacitor converter mode. The method of claim 16
The other end of the first inductor (L1) is connected to the low voltage node of the second cell,
and a junction of the transistor QE1 and the transistor QF1 is connected to a high voltage node of the first cell. The method of claim 17
A transistor QSB is connected between the high voltage node of the first cell and the low voltage node of the second cell to selectively connect the high voltage node of the first cell and the low voltage node of the second cell. The method of claim 16
The first converter circuit,
In the switched capacitor converter mode, the transistor QA1, the transistor QE1, the transistor QF1, and the transistor QD1 operate while repeating on/off at a predetermined switching cycle;
In the buck converter mode, the transistor QA1, the transistor QB1, the transistor QC1, and the transistor QD1 operate while repeating on/off at a predetermined switching cycle. The method of claim 1,
The first converter circuit operates such that the ratio of input voltage to output voltage has a relationship of substantially 2:1 in the switched capacitor converter mode, and in the buck converter mode, the output voltage is within a lower range than the input voltage. can be adjusted,
The power conversion circuit of claim 1 , wherein the second converter circuit operates such that a ratio of an input voltage to an output voltage has a relationship of substantially 2:1 in the switched capacitor converter mode.

Images