KR102526264B1 - Device for controlling single-phase transformerless virtual-ground buck-boost inverter - Google Patents

Abstract

A device for controlling a single-phase virtual ground buck-boost inverter of the present invention may comprise: a control unit for controlling turn-on/off of a plurality of switches included in the single-phase virtual ground buck-boost inverter based on a control signal, wherein the single-phase virtual ground buck-boost inverter may comprise: an input power supply; a first switch and a second switch which are connected to the input power supply and are connected to each other in series; a third switch and a fourth switch which are connected to the input power supply, are connected to the first switch and the second switch in parallel, and are connected to each other in series; a first high-frequency switch having one end connected to the first switch and the third switch, and configured to operate at a higher frequency than the first to fourth switches; a second high-frequency switch having one end connected to the first high-frequency switch and configured to operate at a higher frequency than the first to fourth switches; and an inductor having one end connected to the input power supply and the other end connected to the other end of the first high-frequency switch and one end of the second high-frequency switch. According to the present invention, It is possible to provide an inverter control device that achieves high efficiency and has low voltage stress.

Description

Single Phase Virtual Ground Buck-Boost Inverter Control {DEVICE FOR CONTROLLING SINGLE-PHASE TRANSFORMERLESS VIRTUAL-GROUND BUCK-BOOST INVERTER}

The present invention relates to an inverter control device, and more particularly, to a device for controlling an inverter that reduces leakage current using a virtual ground.

Compared to isolated inverters, transformerless non-isolated buck-boost inverters are popular because of their small size, high efficiency and cost reduction. However, inverters without a transformer due to lack of galvanic isolation have a problem of earth leakage current.

Although an additional switch can solve the leakage current problem, the additional device can negatively impact cost and efficiency due to the operation of the two-step power process. Therefore, research on a single stage non-isolated buck-boost inverter is needed.

One object of the present invention relates to a device for controlling an inverter having two switches operating at a high frequency.

One object of the present invention relates to a device for controlling an inverter that reduces leakage current using a virtual ground.

An apparatus for controlling a single-phase virtual ground buck-boost inverter according to an embodiment is a apparatus for controlling a single-phase virtual ground buck-boost inverter, wherein a plurality of switches included in a single-phase virtual ground buck-boost inverter are turned on/off. It includes a control unit for controlling based on a control signal, wherein the single-phase virtual ground buck-boost inverter includes: an input power supply; a first switch and a second switch connected to the input power and connected in series to each other; a third switch and a fourth switch connected to the input power, connected in parallel to the first switch and the second switch, and connected in series to each other; a first high frequency switch having one end connected to the first switch and the third switch and operating at a higher frequency than the first to fourth switches; a second high frequency switch having one end connected to the first high frequency switch and operating at a higher frequency than the first to fourth switches; The inductor may include an inductor having one end connected to the input power source and the other end connected to the other end of the first high frequency switch and one end of the second high frequency switch.

Here, the controller determines the sign of the output voltage between the node between the first switch and the second switch and the node between the third switch and the fourth switch, and the control signal according to the sign of the output voltage. The plurality of switches may be controlled based on a duty ratio related to a duty cycle of .

Here, first to fourth diodes connected in parallel to the first to fourth switches, respectively; a fifth diode connected in parallel to the first high frequency switch; and a sixth diode connected in parallel to the second high frequency switch.

Here, when the sign of the output voltage is positive, the control unit causes the first switch and the fourth switch to operate in an on state, the second switch and the third switch to operate in an off state, and the input The first high frequency switch is controlled based on a first control signal generated according to an input voltage and the output voltage of the power supply, and the second high frequency switch is controlled based on a second control signal generated according to the input voltage and the output voltage. switch can be controlled.

Here, the control unit generates the second control signal based on a first duty ratio, and the first duty ratio is a voltage gain and a line frequency that are ratios of the input voltage and the output voltage of the single-phase virtual ground buck-boost inverter. can be determined by

Here, the first control signal may be a signal obtained by inverting the second control signal.

Here, the control unit sets the first mode when the second high frequency switch is in an on state and the first high frequency switch is in an off state, and when the first high frequency switch and the second high frequency switch are in an off state. is set as the second mode, and the case where the first high frequency switch is in an on state and the second high frequency switch is in an off state is set as a third mode, the first mode, the second mode, and the third mode. The first control signal and the second control signal may be generated so that is sequentially repeated.

Here, when the sign of the output voltage is negative, the control unit causes the second switch and the third switch to operate in an on state, the first switch and the fourth switch to operate in an off state, and the input The first high frequency switch is controlled based on a third control signal generated according to the input voltage and the output voltage of the power supply, and the second high frequency switch is controlled based on a fourth control signal generated according to the input voltage and the output voltage. switch can be controlled.

Here, the fourth control signal may be a signal obtained by inverting the third control signal.

Here, the control unit sets the fourth mode when the second high frequency switch is in an on state and the first high frequency switch is in an off state, and when the first high frequency switch and the second high frequency switch are in an off state. is set as a fifth mode, and a case in which the first high frequency switch is in an on state and the second high frequency switch is in an off state is set as a sixth mode, and the fourth mode, the fifth mode and the sixth mode are set. The third control signal and the fourth control signal may be generated so that is sequentially repeated.

Here, the control unit generates the fourth control signal based on a first duty ratio, and the first duty ratio is a voltage gain and a line frequency that are ratios of the input voltage and the output voltage of the single-phase virtual ground buck-boost inverter. can be determined by

According to an embodiment of the present invention, an inverter control device capable of achieving high efficiency and having low voltage stress by controlling an inverter having two switches operating at a high frequency may be provided.

According to an embodiment of the present invention, an apparatus for controlling an inverter reducing a leakage current by reducing a voltage fluctuation of a parasitic capacitor using a virtual ground may be provided.

1 is a circuit diagram of a single stage buck-boost inverter according to an embodiment of the present invention.
2 is a timing diagram of an inverter gate signal of an inverter control device according to an embodiment of the present invention.
Figure 3 is a block diagram showing a control signal input of the inverter of the present invention.
4 is a diagram showing a circuit according to a mode of an inverter according to an embodiment of the present invention.
5 is a diagram showing a circuit and a simplified circuit for a grid connection mode of an inverter according to an embodiment of the present invention.
6 and 7 are graphs showing simulation results in the boost operation of the inverter.
8 is a graph showing simulation results in buck operation of an inverter.

The embodiments described in this specification are intended to clearly explain the spirit of the present invention to those skilled in the art to which the present invention belongs, so the present invention is not limited to the embodiments described in this specification, and the The scope should be construed to include modifications or variations that do not depart from the spirit of the invention.

The terms used in this specification have been selected as general terms that are currently widely used as much as possible in consideration of the functions in the present invention, but these may vary depending on the intention of those skilled in the art, precedents, or the emergence of new technologies to which the present invention belongs. can However, in the case where a specific term is defined and used in an arbitrary meaning, the meaning of the term will be separately described. Therefore, the terms used in this specification should be interpreted based on the actual meaning of the term and the overall content of this specification, not the simple name of the term.

The drawings accompanying this specification are intended to easily explain the present invention, and the shapes shown in the drawings may be exaggerated as necessary to aid understanding of the present invention, so the present invention is not limited by the drawings.

If it is determined that a detailed description of a known configuration or function related to the present invention in this specification may obscure the gist of the present invention, a detailed description thereof will be omitted if necessary.

1 is a circuit diagram of a single stage buck-boost inverter according to an embodiment of the present invention.

Referring to FIG. 1 , a single-stage buck-boost inverter according to an embodiment of the present invention may include a plurality of switches. The inverter circuit may include four switches (S1, S2, S3, and S4) operating at line frequency and two switches (S_H1 and S_H2) operating at high frequency. In this case, the line frequency may be a frequency of a grid associated with the inverter.

Since the inverter of the present invention has a relatively small number of switches operating at a high frequency of two, power loss can be greatly reduced compared to the conventional inverter topology. That is, since the number of switches operating at a high frequency is smaller than that of the conventional topology in which all switches operate at a high frequency, electromagnetic interference (EMI) due to interaction between switches is reduced, thereby reducing power loss.

In the inverter circuit, the first switch S1 and the second switch S2 are connected in series with each other. In addition, the third switch (S3) and the fourth switch (S4) are connected in series with each other. The first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are connected in parallel to each other.

In the inverter circuit, an AC load or grid may be connected to a node between the first switch S1 and the second switch S2 and a node between the third switch S3 and the fourth switch S4. That is, a voltage between a node between the first switch S1 and the second switch S2 and a node between the third switch S3 and the fourth switch S4 may be the output voltage. The inverter topology of the present invention may be a type of full-bridge topology or H-bridge topology.

Each of the first switch S1 to the fourth switch S4 may be connected in parallel with a diode.

In the inverter circuit, the first switch S1 and the third switch S3 may be connected to the first high frequency switch S_H1. Also, the first high frequency switch S_H1 may be connected to the capacitor and the second high frequency switch S_H2.

Also, the second high frequency switch S_H2 may be connected to an inductor, and the inductor may be connected to an input power source V_in. At this time, the input power source V_in may be connected in parallel with the second high frequency switch S_H2.

The single-phase virtual ground buck-boost inverter of the present invention has the structure of FIG. 1, is capable of buck-boost operation, has low leakage current, and has high power density because only one inductor and capacitor are used for buck-boost operation. can In addition, since only two switches operate at a high frequency, efficiency is high, and the other switches operate at a line frequency, resulting in low voltage and current stress. At this time, low frequency operation and voltage stress can enable the use of MOSFETs with low drain-source on-resistance.

2 is a timing diagram of an inverter gate signal of an inverter control device according to an embodiment of the present invention. Processing of the inverter control device may be performed by an internal control unit (processor). In this case, the control unit may be a micro control unit (MCU) of the inverter. Specifically, the controller may be a logic circuit for applying a control signal to the inverter.

Referring to Figure 2, the inverter control device of the present invention can control a plurality of switches of the inverter circuit according to the sign of the output voltage.

First, the control unit may determine the sign of the output voltage. Regarding the timing, the control unit can be divided into a case where the sign of the output voltage is positive (positive half cycle) and a case where the sign of the output voltage is negative (negative half cycle).

During a positive half-cycle in which the sign of the output voltage is positive, the control unit may control the first switch S1 and the fourth switch S4 to operate in an on state. Also, at this time, the control unit may control the second switch S2 and the third switch S3 to operate in an off state.

At this time, the control unit may distinguish the mode according to the on/off states of the first high frequency switch S_H1 and the second high frequency switch S_H2.

For example, the controller may set the case where the second high frequency switch S_H2 is in an on state and the first high frequency switch S_H1 is in an off state as the first mode. Specifically, the control unit may set the first mode from the moment when the second high frequency switch S_H2 is turned off to the moment when it is switched back to the off state within a certain period.

In addition, the controller may set the second mode when both the first high frequency switch S_H1 and the second high frequency switch S_H2 are in an off state. Specifically, the controller controls the time from the moment when the second high frequency switch S_H2 is switched from being on to the off state within a certain period to the moment when the first high frequency switch S_H1 is switched from being off to being turned on. 2 modes can be set.

Also, the control unit may set the case where the first high frequency switch S_H1 is in an on state and the second high frequency switch S_H2 is in an off state as the third mode. Specifically, the controller may set the third mode from the moment when the first high frequency switch S_H1 is in an on-off state and then switched to an on-state to the moment when it is switched back to an off-state within a certain period.

Also, the controller may set the first buffer mode when both the first high frequency switch S_H1 and the second high frequency switch S_H2 are in an off state. Specifically, the control unit controls the time from the moment when the first high frequency switch S_H1 is switched from being on to the off state within a certain period to the moment when the second high frequency switch S_H2 is switched from being off to on. 1 Can be set to buffer mode. The first buffer mode may be substantially the same as the second mode.

The first buffer mode may be some dead time for safe operation of the complementary switch. That is, for safe operation of the first high-frequency switch S_H1 and the second high-frequency switch S_H2 operating at high frequency, the buffer time may be in which both switches are off before the next state.

The controller may control the inverter so that the pattern of the first mode - the second mode - the third mode is repeated. That is, the control unit may generate control signals for the plurality of switches such that patterns of the first mode, the second mode, the third mode, and the first mode are repeated.

Alternatively, the controller may control the inverter to repeat a pattern of the first mode - the second mode - the third mode - the first buffer mode. That is, the control unit may generate control signals for the plurality of switches such that patterns of the first mode, the second mode, the third mode, the first buffer mode, and the first mode are repeated.

In order for the above pattern to be repeated, the length of a section in which either one of the first high frequency switch S_H1 and the second high frequency switch S_H2 is in an off state may have to be longer than the length of a section in which the other one is in an on state.

The control unit may repeat the first mode, the second mode, and the third mode in a positive half cycle until the output voltage is zero.

During a negative half-cycle in which the sign of the output voltage is negative, the controller may control the second switch S2 and the third switch S3 to operate in an on state. Also, at this time, the control unit may control the first switch S1 and the fourth switch S4 to operate in an off state.

At this time, the control unit may distinguish the mode according to the on/off states of the first high frequency switch S_H1 and the second high frequency switch S_H2.

For example, the controller may set the fourth mode when the second high frequency switch S_H2 is in an on state and the first high frequency switch S_H1 is in an off state. Specifically, the controller may set the fourth mode from the moment when the second high frequency switch S_H2 is turned off to the moment when it is switched back to the off state within a certain period.

In addition, the controller may set the fifth mode when both the first high frequency switch S_H1 and the second high frequency switch S_H2 are in an off state. Specifically, the controller controls the time from the moment when the second high frequency switch S_H2 is switched from being on to the off state within a certain period to the moment when the first high frequency switch S_H1 is switched from being off to being turned on. 5 modes can be set.

In addition, the controller may set the case where the first high frequency switch S_H1 is in an on state and the second high frequency switch S_H2 is in an off state as the sixth mode. Specifically, the controller may set the sixth mode from the moment when the first high frequency switch S_H1 is in an on-off state and then switched to an on-state to the moment when it is switched back to an off-state within a certain period.

In addition, the controller may set the second buffer mode when both the first high frequency switch S_H1 and the second high frequency switch S_H2 are in an off state. Specifically, the control unit controls the time from the moment when the first high frequency switch S_H1 is switched from being on to the off state within a certain period to the moment when the second high frequency switch S_H2 is switched from being off to on. 2 can be set to buffer mode. The second buffer mode may be substantially the same as the fifth mode.

The second buffer mode may be some dead time for safe operation of the complementary switch. That is, for safe operation of the first high-frequency switch S_H1 and the second high-frequency switch S_H2 operating at high frequency, the buffer time may be in which both switches are off before the next state.

The controller may control the inverter so that the pattern of the fourth mode - the fifth mode - the sixth mode is repeated. That is, the control unit may generate control signals for the plurality of switches such that patterns of the fourth mode, the fifth mode, the sixth mode, and the fourth mode are repeated.

Alternatively, the controller may control the inverter to repeat the pattern of the fourth mode - the fifth mode - the sixth mode - the second buffer mode. That is, the control unit may generate control signals for the plurality of switches such that patterns of the fourth mode, the fifth mode, the sixth mode, the second buffer mode, and the fourth mode are repeated.

In order for the above pattern to be repeated, the length of a section in which either one of the first high frequency switch S_H1 and the second high frequency switch S_H2 is in an off state may have to be longer than the length of a section in which the other one is in an on state.

The fourth mode, the fifth mode, and the sixth mode may be repeated until the output voltage is zero in a negative half cycle by the control unit.

Figure 3 is a block diagram showing a control signal input of the inverter of the present invention.

Referring to FIG. 3 , the control signal generation step of the control unit can be grasped through a block diagram. The control unit includes a first control signal for controlling the first switch S1 and the fourth switch S4, a second control signal for controlling the second switch S2 and the third switch S3, and a first high frequency switch S_H1. ) and a fourth control signal for controlling the second high frequency switch S_H2.

The control unit may generate the fourth control signal according to the following equation. Equations 1 and 2 below are equations representing a duty ratio related to the duty cycle of the fourth control signal.

[Equation 1]

,

: 라인 주파수)(

,

: line frequency)

The duty ratio d1 can be expressed as a voltage gain G=V_o/V_in, and the equation is as follows.

[Equation 2]

As shown in FIG. 3 , the fourth control signal for the second high frequency switch S_H2 may be obtained from Equation 2.

The control unit may obtain a third control signal for controlling the first high frequency switch S_H1 as a signal complementary to the fourth control signal. The first control signal for controlling the first switch S1 and the fourth switch S4 may be a signal based on a line frequency. The control unit may obtain the second control signal as a signal complementary to the first control signal. Specifically, the first control signal and the second control signal may be generated by comparing the reference signal V_ref and the ground signal.

4 is a diagram showing a circuit according to a mode of an inverter according to an embodiment of the present invention. 4(a) to 4(c) are circuits in a positive half cycle, and FIGS. 4(d) to 4(f) are diagrams showing circuits in a negative half cycle.

Figure 4 (a) is a circuit diagram showing the current flow in the first mode, Figure 4 (b) is a circuit diagram showing the current flow in the second mode, Figure 4 (c) is a current flow in the third mode This is the circuit diagram shown.

Referring to FIG. 4(a) , according to the timing diagram of FIG. 2 in the first mode, only the first switch S1, the fourth switch S4, and the second high frequency switch S_H2 are turned on. At this time, the inductor (L) stores energy and the capacitor (c) supplies energy to the load. The inductor current ripple is:

[Equation 3]

: 스위칭 기간)(

: switching period)

Referring to FIG. 4(b) , only the first switch S1 and the fourth switch S4 are turned on according to the timing diagram of FIG. 2 in the second mode. In the second mode, the inductor (L) can supply energy to the capacitor (C) and the load. In the second mode, both high frequency switches are turned off due to dead time, and current flows through the body diode of the first high frequency switch S_H1.

Referring to FIG. 4(c) , according to the timing diagram of FIG. 2 in the third mode, only the first switch S1, the fourth switch S4, and the first high frequency switch S_H1 are turned on. In the third mode, the first high-frequency switch S_H1 is turned on, and current can flow through the channel of the MOSFET, so that the advantage of synchronous rectification can be obtained.

At this time, the current ripple is as follows.

[Equation 4]

Referring to FIG. 4(d) , only the second switch S2, the third switch S3, and the second high frequency switch S_H2 are turned on according to the timing diagram of FIG. 2 in the fourth mode. At this time, the inductor (L) stores energy and the capacitor (c) supplies energy to the load. The inductor current ripple is similar to the first mode.

Referring to FIG. 4(e), in the fifth mode, according to the timing diagram of FIG. 2, only the second switch S2 and the third switch S3 are turned on. In the fifth mode, the inductor L may supply energy to the capacitor C and the load. In the fifth mode, both high frequency switches are turned off due to dead time, and current flows through the body diode of the first high frequency switch S_H1.

Referring to FIG. 4(f), according to the timing diagram of FIG. 2 in the sixth mode, only the first switch S1, the fourth switch S4, and the first high frequency switch S_H1 are turned on. In the sixth mode, the first high-frequency switch S_H1 is turned on, and current can flow through the channel of the MOSFET, so that the advantage of synchronous rectification can be obtained.

At this time, the current ripple is as follows.

[Equation 5]

5 is a diagram showing a circuit and a simplified circuit for a grid connection mode of an inverter according to an embodiment of the present invention.

5(a) shows a circuit for the grid connection mode of the inverter, FIG. 5(b) shows a simplified circuit in a positive half cycle where the sign of the output voltage is positive, and FIG. 5(b) shows the output voltage It shows a simplified circuit in the negative half cycle where the sign of is negative.

Referring to FIG. 5 (a), it can be seen a general grid connection configuration of the inverter of the present invention. The parasitic percapacitor of the photovoltaic panel may be expressed as a first parasitic capacitor C_p1 and a second parasitic capacitor C_p2, and the voltage may be expressed as a first voltage v_p1 and a second voltage v_p2. . The inductor (L0) filters out high-frequency harmonics and is also required for existing grid-connected inverters.

Since solar power generation is mostly grid-connected, leakage current can be an important design parameter. In a photovoltaic system without a grid-tied transformer, leakage current can flow through the parasitic capacitors of the photovoltaic panels. Significant high-frequency voltage fluctuations across the parasitic capacitors result in large leakage currents, while line frequency fluctuations result in low leakage currents. If there is no change in the parasitic capacitor voltage, the leakage current can be zero.

Referring to FIGS. 5(b) and 5(c) , it can be seen that the voltages of the capacitors C_p1 and C_p2 vary according to the sign of the output voltage.

In the positive half cycle, the voltage of the first parasitic capacitor C_p1 is 0 and the voltage of the second parasitic capacitor C_p2 is -V_in. In the negative half cycle, the voltage of the first parasitic capacitor C_p1 is (V_in-Vc) and the voltage of the second parasitic capacitor C_p2 is -Vc.

That is, in the positive half cycle, since the AC ground is directly connected to the DC bus and the voltages of the parasitic capacitors V_p1 and V_p2 are constant without fluctuation, the leakage current will be zero.

However, in the negative half cycle, both the voltage of the first parasitic capacitor C_p1 and the voltage of the second parasitic capacitor C_p2 depend on Vc. The input voltage is constant, and Vc changes as a sine wave according to the line frequency. This may mean that the leakage current is lower than when the line frequency fluctuates across the parasitic capacitor, not the high frequency fluctuation, rather than the high frequency fluctuation.

From the point of view of high-frequency signals, capacitor C can provide a low-impedance path and can be seen as virtually connecting the negative terminal of the photovoltaic panel to the ground of the grid. Thus, the inverter of the present invention may include a virtual ground circuit.

6 and 7 are graphs showing simulation results in the boost operation of the inverter. 6 and 7 show boost mode waveforms when the input voltage is 100V.

Figure 6 (a) shows the simulation results of the gate signal, and Figure 6 (b) shows the simulation results of the input voltage (V_in), output voltage (V0), inductor current (iL) and input current (i_in) .

7(a) shows the simulation results of the voltage across the filter capacitor Vc and the drain-source voltage of the switches S_H1 and S_H2, and FIG. 7(b) shows the voltage of the switches S1, S2, S3 and S4 It shows the simulation result of the drain-source voltage.

8 is a graph showing simulation results in buck operation of an inverter. 8 shows a buck mode waveform when the input voltage is 200V.

8(a) shows simulation results of the input voltage (V_in), the output voltage (V0), the inductor current (iL), and the input current (i_in). 8(b) shows simulation results of the voltage across the filter capacitor Vc and the drain-source voltage of the switches S_H1 and S_H2, and FIG. 8(c) shows simulation results of the voltages v_p1 and v_p2 of the parasitic capacitors. that showed the result.

Referring to the simulation results of FIGS. 6 to 8 , it can be seen that only the high frequency switches S_H1 and S_H2 have the same voltage stress as (V_in+V0). It can also be seen that the voltage stress of the line frequency switch is low and is equal to the peak output voltage V0. In addition, it can be seen that the voltage across the parasitic capacitor is as described above.

That is, in the positive half cycle, the voltage of the first parasitic capacitor C_p1 and the voltage of the second parasitic capacitor C_p2 are fixed to DC values. On the other hand, it can be seen that the voltage of the first parasitic capacitor (C_p1) and the voltage of the second parasitic capacitor (C_p2) vary according to the line frequency in the negative half cycle, and the high frequency ripple is greatly reduced by the filter capacitor (C). . Therefore, it can be seen that there is a small leakage current in the negative half cycle of the output voltage, but much lower than the industry standard.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. Program commands recorded on the medium may be specially designed and configured for the embodiment or may be known and usable to those skilled in computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic media such as floptical disks. - includes hardware devices specially configured to store and execute program instructions, such as magneto-optical media, and ROM, RAM, flash memory, and the like. Examples of program instructions include high-level language codes that can be executed by a computer using an interpreter, as well as machine language codes such as those produced by a compiler. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

As described above, although the embodiments have been described with limited examples and drawings, those skilled in the art can make various modifications and variations from the above description. For example, the described techniques may be performed in an order different from the method described, and/or components of the described system, structure, device, circuit, etc. may be combined or combined in a different form than the method described, or other components may be used. Or even if it is replaced or substituted by equivalents, appropriate results can be achieved.

Therefore, other implementations, other embodiments, and equivalents of the claims are within the scope of the following claims.

Claims (11)

In the single-phase virtual ground buck-boost inverter control device,
A controller for controlling on/off of a plurality of switches included in a single-phase virtual ground buck-boost inverter based on a control signal,
The single-phase virtual ground buck-boost inverter,
input power;
a first switch and a second switch connected to the input power and connected in series to each other;
a third switch and a fourth switch connected to the input power, connected in parallel to the first switch and the second switch, and connected in series to each other;
a first high frequency switch having one end connected to the first switch and the third switch and operating at a higher frequency than the first to fourth switches;
a second high frequency switch having one end connected to the first high frequency switch and operating at a higher frequency than the first to fourth switches; and
an inductor having one end connected to the input power source and the other end connected to the other end of the first high frequency switch and one end of the second high frequency switch;
The control unit when the sign of the output voltage is positive,
Operating the first switch and the fourth switch in an on state;
Operating the second switch and the third switch in an off state;
The first high-frequency switch is controlled based on a first control signal generated according to the input voltage and the output voltage of the input power, and the second control signal generated according to the input voltage and the output voltage is used to control the first high-frequency switch. 2 to control the high-frequency switch
Single-phase virtual ground buck-boost inverter control unit.
According to claim 1,
The control unit determines a sign of the output voltage between a node between the first switch and the second switch and a node between the third switch and the fourth switch, and determines the sign of the control signal according to the sign of the output voltage. Controlling the plurality of switches based on a duty ratio related to a duty cycle.
Single-phase virtual ground buck-boost inverter control unit.
According to claim 1,
first to fourth diodes connected in parallel to the first to fourth switches, respectively;
a fifth diode connected in parallel to the first high frequency switch; and
A sixth diode connected in parallel to the second high frequency switch
Single-phase virtual ground buck-boost inverter control unit.
delete According to claim 1,
The control unit generates the second control signal based on a first duty ratio,
The first duty ratio is determined by a line frequency and a voltage gain that is a ratio of the input voltage and the output voltage of the single-phase virtual ground buck-boost inverter.
Single-phase virtual ground buck-boost inverter control unit.
According to claim 5,
The first control signal is a signal obtained by inverting the second control signal.
Single-phase virtual ground buck-boost inverter control unit.
According to claim 1,
The control unit,
A case in which the second high frequency switch is in an on state and the first high frequency switch is in an off state is set as a first mode;
A case in which the first high frequency switch and the second high frequency switch are off is set as a second mode;
A case in which the first high frequency switch is in an on state and the second high frequency switch is in an off state is set as a third mode;
Generating the first control signal and the second control signal such that the first mode, the second mode, and the third mode are sequentially repeated
Single-phase virtual ground buck-boost inverter control unit.
In the single-phase virtual ground buck-boost inverter control device,
A controller for controlling on/off of a plurality of switches included in a single-phase virtual ground buck-boost inverter based on a control signal,
The single-phase virtual ground buck-boost inverter,
input power;
a first switch and a second switch connected to the input power and connected in series to each other;
a third switch and a fourth switch connected to the input power, connected in parallel to the first switch and the second switch, and connected in series to each other;
a first high frequency switch having one end connected to the first switch and the third switch and operating at a higher frequency than the first to fourth switches;
a second high frequency switch having one end connected to the first high frequency switch and operating at a higher frequency than the first to fourth switches; and
an inductor having one end connected to the input power source and the other end connected to the other end of the first high frequency switch and one end of the second high frequency switch;
The control unit when the sign of the output voltage is negative,
operating the second switch and the third switch in an on state;
operating the first switch and the fourth switch in an off state;
The first high-frequency switch is controlled based on a third control signal generated according to the input voltage and the output voltage of the input power, and the third control signal is generated based on the input voltage and the output voltage. 2 to control the high-frequency switch
Single-phase virtual ground buck-boost inverter control unit.
According to claim 8,
The third control signal is a signal obtained by inverting the fourth control signal.
Single-phase virtual ground buck-boost inverter control unit.
According to claim 8,
The control unit,
A case in which the second high frequency switch is in an on state and the first high frequency switch is in an off state is set as a fourth mode;
A case in which the first high frequency switch and the second high frequency switch are off is set as a fifth mode;
A sixth mode is set when the first high-frequency switch is in an on state and the second high-frequency switch is in an off state;
Generating the third control signal and the fourth control signal such that the fourth mode, the fifth mode, and the sixth mode are sequentially repeated
Single-phase virtual ground buck-boost inverter control unit.
According to claim 8,
The control unit generates the fourth control signal based on a first duty ratio,
The first duty ratio is determined by a line frequency and a voltage gain that is a ratio of the input voltage and the output voltage of the single-phase virtual ground buck-boost inverter.
Single-phase virtual ground buck-boost inverter control unit.

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