KR102522942B1 - Memory device based on self-rectifying ferroelectric tunnel junction element capable of operating in dual mode - Google Patents

Abstract

The present invention provides a memory device based on a self-rectifying ferroelectric tunnel junction element capable of operating in a dual mode of CAM and PUF and an operating method thereof. The memory device comprises: a plurality of memory cells including two self-rectifying ferroelectric tunnel junction elements (SR-FTJ) each connected between a plurality of match lines extending in a first direction and a plurality of search line pairs extending in a second direction intersecting the first direction; a power supply unit supplying voltage according to an operating state to the plurality of match lines and the plurality of search line pairs; and a PUF response generator, when operating in a PUF mode among content addressable memory (CAM) and physically unclonable function (PUF) modes, detecting and amplifying a voltage change occurring at a selected match line, due to a leakage current generated when a reverse voltage is applied to two SR-FTJs of each of a plurality of memory cells connected to a match line selected according to an address transmitted as a challenge, and generating a response corresponding to the challenge. Accordingly, space efficiency of the memory device can be greatly improved.

Description

[0001] Memory device based on self-rectifying ferroelectric tunnel junction element capable of operating in dual mode

The present invention relates to a memory device and an operating method thereof, and more particularly, to a memory device based on a self-rectifying ferroelectric tunnel junction element capable of operating in a dual mode of a content addressable memory and a PUF, and an operating method thereof.

A content addressable memory (CAM) is a memory having a plurality of memory cells to store data, and is a memory configured to receive data as an input and output an address at which the applied data is stored. CAM is used in various application fields requiring high-speed retrieval, such as a search engine in a network router, an image process, or a neural network.

On the other hand, PUF (Physically Unclonable Function) is a physically unclonable function, such as line delay and gate delay, in circuits manufactured by minute process variations that inevitably occur in the process, even if circuits are manufactured according to the same manufacturing process under the same design. It refers to a security technique that uses the characteristic that there is deviation from.

Even if the same input is applied, the PUF device outputs an output key randomly determined by a physical deviation according to manufacturing process conditions. Since an output key determined according to process conditions cannot be predicted even by a circuit designer, the PUF device can provide a high level of security and is applied to various devices requiring security.

The PUF device is configured to, when an input called a challenge is applied, output an output key called a response corresponding to the challenge applied. In addition, a plurality of challenge-response pairs (CRPs) in which a plurality of challenges for the PUF device and responses corresponding to each challenge are matched in pairs are stored in advance in the authentication server that verifies the security of the PUF device. Accordingly, the authentication server for authenticating the PUF device transmits a challenge to the PUF device and determines whether a response returned from the PUF device conforms to a pre-stored CRP, thereby authenticating the PUF device that has transmitted the response.

Due to the recent development of the Internet of Things (IoT), the importance of security of various IoT devices is on the rise, so the demand for PUF devices is increasing. In addition, since many IoT devices are manufactured as small and low power consumption devices, randomness, independence, stability, area efficiency, and low power operation are essential for PUF devices applied to IoT devices.

As a conventional PUF device, a memory PUF generating a random response using a memory structure has been mainly used. Similar to memory cells, in the memory PUF, a plurality of PUF cells are arranged in an array structure, and an address for a PUF cell is applied as a challenge. Accordingly, the memory PUF may select a PUF cell corresponding to the address applied as a challenge and output a value stored or generated in the selected PUF cell as a response.

Both CAM and PUF can be implemented as volatile or non-volatile memory, but in the past, CAM and PUF are manufactured as separate memory devices, or even when manufactured as one memory device, memory cells operating as CAM and PUF operating as The memory cells were separated from each other. That is, CAM and PUF are implemented using different memory cells. As a result, there is a problem that the capacity and size required for the memory device are large.

Korean Registered Patent No. 10-2179789 (registered on November 11, 2020)

An object of the present invention is to provide a memory device based on a self-rectifying ferroelectric tunnel junction element capable of operating in a dual mode of CAM and PUF and an operating method thereof.

Another object of the present invention is to provide a memory device based on a self-rectifying ferroelectric tunnel junction element that can easily operate as a CAM or PUF according to a voltage level applied to a memory cell and an operating method thereof.

Another object of the present invention is to provide a self-rectifying ferroelectric tunnel junction device-based memory device that can be manufactured in a small size and has excellent randomness, and an operating method thereof.

In order to achieve the above object, a memory device based on a self-rectifying ferroelectric tunnel junction device according to an embodiment of the present invention includes a plurality of match lines extending in a first direction and a plurality of match lines extending in a second direction crossing the first direction. a plurality of memory cells composed of two self-rectifying ferroelectric tunnel junction elements (hereinafter referred to as SR-FTJ) each connected between a pair of search lines; a power supply unit supplying voltages according to operating states to the plurality of match line pairs and the plurality of search line pairs; And reverse to two SR-FTJs of each of a plurality of memory cells connected to a match line selected according to an address transmitted as a challenge when operating in the PUF mode among CAM (Content Addressable Memory) mode and PUF (Physically Unclonable Function) mode. and a PUF response generating unit generating a response corresponding to the challenge by sensing and amplifying a voltage change generated on a selected match line by a leakage current generated when a voltage is applied.

Each of the plurality of memory cells includes a first SR-FTJ connected between a corresponding match line among the plurality of match lines and a search line of a corresponding search line pair among the plurality of search line pairs; and a second SR-FTJ connected between a corresponding match line among the plurality of match lines and a search line bar of a corresponding search line pair among the plurality of search line pairs.

The response generating unit includes a plurality of muxes connected to a predetermined number of different match lines among the plurality of match lines and selecting a match line corresponding to the challenge; and at least one sense amplifier generating the response by sensing and amplifying a voltage difference between match lines selected by two corresponding muxes among the multiple muxes.

The power supply unit applies a ground voltage level so that the plurality of match lines and the plurality of search line pairs are discharged in the discharge step of the PUF mode, which operates in a discharge step and a response generation step, and generates the response In the step, a voltage applied to a match line selected according to an address designated by the challenge among the plurality of match lines is cut off and floated, and a power supply voltage having a predetermined voltage level is applied to the remaining match lines and the search line pair, A reverse voltage may be applied to two SR-FTJs of a plurality of memory cells connected to the selected matchline.

The at least one sense amplifier selects and connects a match line according to an address designated by the challenge when two corresponding muxes among the plurality of muxes select and connect a match line in the response generating step, a plurality of memories connected to the selected two match lines. The response may be generated by sensing and amplifying a voltage difference between match lines that changes by a leakage current generated when a reverse voltage is applied to two SR-FTJs in each cell.

When data “0” is stored by the write operation of the CAM mode, in which each of the plurality of memory cells operates by being divided into a write operation and a search operation, the first SR-FTJ is in a high resistance state (HRS ) And the second SR-FTJ has a low resistance state (LRS), and when data “1” is stored, the first SR-FTJ has a low resistance state and the second SR-FTJ has a high Can have a resistance state.

The power supply unit applies the ground voltage to a match line selected according to an applied address among a plurality of match lines in the high-resistance setting step of the write operation, and applies 1/1 of the write voltage of a predetermined voltage level to the remaining match lines. A two-level voltage is applied, and a voltage according to data to be stored in the corresponding memory cell MC is applied to each of the plurality of search line pairs, and in the low resistance setting step of the write operation, the match line selected A write voltage may be applied, and the voltage applied in the high resistance setting step may be maintained with the remaining match lines and the plurality of search line pairs.

When the data to be stored in a memory cell is “0” during a write operation in the CAM mode, the power supply unit applies the write voltage to a search line from a corresponding search line pair and applies the ground voltage to a search line bar. and if the data to be stored in the memory cell is “1”, the ground voltage may be applied to the search line in the corresponding search line pair, and the write voltage may be applied to the search line bar.

The power supply unit applies and precharges the power supply voltage to the plurality of match lines and the plurality of search line pairs in the precharging step of the search operation, and applies the power voltage to the plurality of match lines in the match evaluation step of the search operation. The power supply may be cut off to float, and a voltage corresponding to data to be searched may be applied to the plurality of search line pairs.

If the data to be searched during the search operation is “0”, the power supply unit applies the ground voltage to the search line in the corresponding search line pair, and applies the power supply voltage to the search line bar. If the data is “1”, the power supply voltage may be applied to the search line in the corresponding search line pair, and the ground voltage may be applied to the search line bar.

In the plurality of memory cells, search lines and search line bars of each of the plurality of search line pairs are disposed above and below the plurality of match lines, respectively, and the two SR-FTJs are disposed between corresponding match lines and search lines and It can be implemented as a stacked 3D structure between the corresponding match line and search line bar.

In order to achieve the above object, a method of operating a memory device based on a self-rectifying ferroelectric tunnel junction device according to another embodiment of the present invention includes a plurality of match lines extending in a first direction and extending in a second direction intersecting the first direction. A method of operating a memory device including a plurality of memory cells composed of two self-rectifying ferroelectric tunnel junction elements (SR-FTJ) each connected between a plurality of search line pairs In the method, determining an operation mode of a CAM mode or a PUF mode according to an applied command; If the determined operation mode is the PUF mode, a leakage current generated when a reverse voltage is applied to two SR-FTJs of each of a plurality of memory cells connected to a match line selected according to an address transmitted as a challenge results in the selected match line and generating a response corresponding to the challenge by sensing and amplifying a voltage change generated in .

Accordingly, a self-rectifying ferroelectric tunnel junction element-based memory device and method of operation thereof according to an embodiment of the present invention are a content addressable memory and a content addressable memory according to a voltage level applied to a memory cell implemented with two self-rectification ferroelectric tunnel junction elements. Since the PUF can operate in dual mode, the space efficiency of the memory device can be greatly improved. And it can be implemented in a 3D cross point array structure, so it can be manufactured in a smaller size. In addition, when operating as a PUF, it is possible to provide excellent security performance due to high randomness by comparing row by row.

1 is a diagram for explaining characteristics of a ferroelectric tunnel junction device.
2 is a diagram for explaining characteristics of a self-rectifying ferroelectric tunnel junction device.
FIG. 3 is a diagram for explaining leakage current characteristics according to reverse voltage of the self-rectifying ferroelectric tunnel junction device of FIG. 2 .
4 illustrates a memory cell array structure of a memory device according to an exemplary embodiment of the present invention.
FIG. 5 shows an example of a 3D structure of the memory cell array of FIG. 4 .
6 and 7 are diagrams for explaining a write operation in a CAM mode of a memory device according to an exemplary embodiment.
8 and 9 are diagrams for explaining a search operation in a CAM mode of a memory device according to an exemplary embodiment.
10 illustrates an example of a configuration for operating a memory device according to the present embodiment in a PUF mode.
11 and 12 are diagrams for explaining an operation of a memory cell in a PUF mode according to an exemplary embodiment.
13 illustrates a method of operating a memory device according to an embodiment of the present invention.

In order to fully understand the present invention and its operational advantages and objectives achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the accompanying drawings. However, the present invention may be embodied in many different forms and is not limited to the described embodiments. And, in order to clearly describe the present invention, parts irrelevant to the description are omitted, and the same reference numerals in the drawings indicate the same members.

Throughout the specification, when a part "includes" a certain component, it means that it may further include other components, not excluding other components unless otherwise stated. In addition, terms such as "... unit", "... unit", "module", and "block" described in the specification mean a unit that processes at least one function or operation, which is hardware, software, or hardware. And it can be implemented as a combination of software.

1 is a diagram for explaining characteristics of a ferroelectric tunnel junction device.

In FIG. 1, (a) shows the structure of a ferroelectric tunnel junction (FTJ), (b) shows a polarization state of the FTJ, and (c) shows a current voltage graph of the FTJ. And (d) is a diagram for explaining a sneak current path different from the characteristics of the FTJ device.

As shown in (a), the FTJ may have a structure in which, for example, a ferroelectric tunnel layer 12, a ferroelectric layer 13, and a metal layer 14 are sequentially stacked on a semiconductor layer 11. For example, the semiconductor layer 11 may be formed of P-type Si, the ferroelectric tunnel layer 12 may be formed of zirconium (Zr) doped with hafnium oxide (HfO ₂ ), and the ferroelectric layer may be formed of (13) is implemented with aluminum oxide (Al ₂ O ₃ ), and the metal layer 14 may be implemented with titanium (Ti) or aluminum (Au).

Such an FTJ is a ferroelectric layer 13, depending on whether a reverse write voltage (or forward negative write voltage) (-V _W ) is applied as shown on the left side of (b) or a forward write voltage (V _W ) is applied as shown on the right side. Polarization of is formed in different directions to become a low resistance state (LRS) or a high resistance state (HRS).

If the reverse write voltage (-V _W ) is applied to the FTJ to have a low resistance state (LRS), the current flows smoothly at the read voltage at a voltage level lower than the write voltage (V _W ) as shown in the black line in the graph of (c). and can be seen in the switched-on state. On the other hand, if the forward write voltage (also called positive write voltage) (V _W ) is applied and the FTJ has a high resistance state (HRS), the positive write voltage (V _W ) is applied as shown in the red line and the current at the read voltage Since it does not flow smoothly, it can be seen as a switched off state.

Such an FTJ may be used as a switch element or a memory element in which the low resistance state LRS represents logic “1” and the high resistance state HRS represents logic “0”.

In the above, it is assumed that the semiconductor layer 11 is formed of a P-type, and if the semiconductor layer 11 is formed of an N-type, the FTJ is applied with a reverse write voltage (-V _W ). It may have a high resistance state (HRS) of 0" and a low resistance state (LRS) of logic "1" when a positive write voltage (V _W ) is applied.

However, since this FTJ is a bidirectional switch element in which current can flow in both directions according to the voltage applied to both ends, when configuring a memory array using the FTJ, as shown in (d), unintended during read operation There is a problem that a current path is formed as a path and a sneak current may flow. In the past, FTJs have been limited in their use in memory devices or CAMs.

2 is a diagram for explaining characteristics of a self-rectifying ferroelectric tunnel junction device.

In order to solve the problem caused by the bidirectional characteristic of the above-mentioned FTJ, recently, the self-rectifying ferroelectric tunnel junction element (SR-FTJ) adjusted so that the above-described FTJ has a unidirectional characteristic rather than a bidirectional characteristic ) was developed. The SR-FTJ is a semiconductor layer 11, a ferroelectric tunnel layer 12, a ferroelectric layer 13, and a metal layer 14 in the FTJ shown in (a) of FIG. It can be implemented by changing the polarization characteristics according to

In (a) of FIG. 2, the left and right graphs represent the voltage-polarization (V-P) characteristic curve and the voltage-current (I-V) characteristic curve of the conventional FTJ and SR-FTJ, respectively. In the case of the existing FTJ, as shown on the left, since the polarization (P) according to the voltage (V) is achieved not only in the forward voltage but also in the reverse voltage, the voltage-current (I-V) characteristic curve also has a bidirectional characteristic. On the other hand, in the case of the SR-FTJ, as shown on the right, since the polarization (P) according to the voltage (V) is made only at the positive voltage, the voltage-current (I-V) characteristic curve as shown in the enlarged graph in (c) It can be seen that this has a one-way characteristic. This indicates that the SR-FTJ can suppress reverse current flow by having rectification characteristics similar to diodes.

FIG. 3 is a diagram for explaining leakage current characteristics according to reverse voltage of the self-rectifying ferroelectric tunnel junction device of FIG. 2 .

In FIG. 3, (a) shows the leakage current change according to the reverse voltage of the SR-FTJ. As described above, the SR-FTJ has a rectification characteristic similar to that of a diode, and as shown in (a) of ^FIG . represents the rectifying ratio (RR) of That is, when reverse voltage is applied, SR-FTJ suppresses reverse current flow. However, the reverse current is not completely suppressed, and thus leakage current flows.

Figure 3 (b) shows the leakage current change according to the state of each SR-FTJ device. Like most memory cells, SR-FTJs also have a leakage current difference between SR-FTJ devices due to slight process deviations during manufacturing. That is, as shown on the left side of (b), when both SR-FTJ elements (A, B) are in a high resistance state (HRS), the same leakage current is present in the two SR-FTJ elements (A, B). While the first leakage current (I leak,A) flows in one SR-FTJ element (A), the second leakage current (I _leak,A ) different from the first leakage current (I _leak,A ) flows in the remaining SR-FTJ element (B). A leakage current (I _leak,B ) flows. In each SR-FTJ, leakage currents (I _leak,A , I _leak,B ) may flow to each other according to a Gaussian distribution, and such leakage currents (I _leak,A , I _leak,B ) Although the size varies according to the change, the relative magnitude between the leakage currents of each SR-FTJ remains the same when different SR-FTJs change the same state.

That is, as shown on the right side of (b), when the state of the two SR-FTJ elements (A, B) is changed to the low resistance state (LRS), the state change of the two SR-FTJ elements (A, B) A change (ΔΔI _leak ) occurs in the leakage current ₍ I _leak,A , I _leak,B ) according to occurs in size. Therefore, the difference in leakage current (I _leak,A +ΔI _leak , I _leak,B +ΔI _leak ) for each device remains the same even when the states of the SR-FTJ devices A and B are changed. This indicates that if the two SR-FTJ elements (A, B) are in the same state, leakage currents of different magnitudes flow when reverse voltage is applied according to the manufacturing characteristics of each SR-FTJ element (A, B) . Therefore, the memory device composed of the SR-FTJ elements A and B can be used as a PUF even by using the leakage currents I _leak,A and I _leak,B of the SR-FTJ elements A and B. However, in order to construct a PUF using the leakage currents (I _leak,A , I _leak,B ) of the SR-FTJ elements (A, B), the change in leakage current according to the state of the SR-FTJ elements (A, B) ( The states of the two SR-FTJ devices (A, B) must be the same so that ΔI _leak ) is not reflected.

4 illustrates a memory cell array structure of a memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 4 , the memory device according to the present exemplary embodiment may include a plurality of memory cell arrays, and each memory cell array intersects a plurality of match lines ML extending in a first direction and the first direction. Connection between a corresponding match line among the plurality of search line pairs SL and SLB and the plurality of match lines ML extending in the second direction and a corresponding search line pair among the plurality of search line pairs SL and SLB, respectively. It includes a plurality of memory cells (MC) including two SR-FTJs (F1, F2). In this embodiment, each of the plurality of memory cells MC may operate as a CAM cell for storing CAM data.

Each of the plurality of memory cells (MC) includes two SR-FTJs (F1, F2), and a first SR-FTJ (F1) among the two SR-FTJs (F1, F2) has a corresponding match line (ML ) and the corresponding search line (SL), and the second SR-FTJ (F2) is connected between the corresponding match line (ML) and the corresponding search line bar (SLB). That is, the first SR-FTJ (F1) and the second SR-FTJ (F2) have one end connected in common to the corresponding match line ML, while the other end has a corresponding search line SL or a corresponding search line bar (SLB) and connected.

Therefore, in the memory device according to the present embodiment, each of the plurality of memory cells MC is composed of only two SR-FTJs (F1, F2) connected between the match line (ML) and the search line pair (SL, SLB), As a result, the size of the memory device can be greatly reduced.

Here, for convenience of description, two match lines (ML[0], ML[1]) and three search line pairs ((SL[0], SLB[0]), (SL[1], SLB[1]) ), (SL[2], SLB[2])), and 6 memory cells ((MC[00], MC[01], MC[02]), ( Only MC[10], MC[11], and MC[12])) are shown. In the following, 6 memory cells ((MC[00], MC[01], MC[02]), (MC[10], MC[11], MC[12])) are arranged according to the arrangement position of the eleventh memory. Cells MC[00] through 23rd memory cells MC[12] are referred to. The first match line (ML[0]) and three search line pairs ((SL[0], SLB[0]), (SL[1], SLB[1]), (SL[2], SLB[2] ])), the three memory cells MC connected therebetween are referred to as 11th to 13th memory cells MC[00], MC[01], and MC[02], respectively, and the second match line ML[1] ) and three pairs of search lines ((SL[0], SLB[0]), (SL[1], SLB[1]), (SL[2], SLB[2])) The cells MC are referred to as 21st to 23rd memory cells MC[10], MC[11], and MC[12], respectively.

FIG. 5 shows an example of a 3D structure of the memory cell array of FIG. 4 .

Each of a plurality of memory cell arrays in the memory device according to the present embodiment shown in FIG. 4 may be implemented in a 3D structure as shown in FIG. 5 . 5, for convenience of explanation, two match lines (ML[0], ML[1]) and three search line pairs ((SL[0], SLB[0]), (SL[1], SLB[ 1]), 6 memory cells ((MC[00], MC[01], MC[02]), (MC[10], MC[11] connected between (SL[2], SLB[2])) ], MC[12])) only.

Referring to FIG. 5 , a memory cell array having a 3D structure extends in a second direction perpendicular to the first direction on an upper side centered on a plurality of match lines ML[0] and ML[1] extending in a first direction. A plurality of search lines (SL[0], SL[1], and SL[2]) are formed, and a plurality of search line bars (SLB[0], SLB[1], SLB [2]) is formed. And between the corresponding match line among the plurality of match lines (ML[0], ML[1]) and the corresponding search line among the plurality of search lines (SL[0], SL[1], and SL[2]), 1 SR-FTJ (F1) is formed, and the corresponding match line among a plurality of match lines (ML[0], ML[1]) and a plurality of search line bars (SLB[0], SLB[1], SLB[ 2]), a second SR-FTJ (F2) is formed between the corresponding search line bars.

As shown in FIG. 5, a plurality of search lines (SL[0], SL[1], SL[2]) and a plurality of search line bars (SLB[0], SLB[1], SLB[2]) If are formed to extend in the vertical direction to the match lines (ML[0], ML[1]) by being located in the upper and lower layers centered on the matchlines (ML[0], ML[1]), each memory cell ( The two SR-FTJs (F1, F2) of (MC[00], MC[01], MC[02]), (MC[10], MC[11], MC[12]) have a stacked structure. is formed Accordingly, the size of the memory device can be further reduced.

Meanwhile, although not shown, the memory device of the present embodiment may further include a power supply unit (not shown) for supplying voltages to each of the plurality of match lines ML and the plurality of search line pairs SL and SLB.

6 and 7 are diagrams for explaining a write operation in a CAM mode of a memory device according to an exemplary embodiment.

6 and 7 , the 11th memory cell MC[00], the 12th memory cell MC[01], and the 13th memory cell (MC[01]) of the first row connected to the first match line ML[0] Assume that data "0", "1", and "1" are written to MC[02]), respectively. Also, here, assuming that the semiconductor layer 11 is formed in an N-type, memory cells ((MC[00], MC[01], MC[02]), (MC[10], MC[11], MC The two SR-FTJs (F1, F2) of [12]) have a high resistance state (HRS) when a reverse write voltage (-V _W ) is applied, and a low resistance state when a forward write voltage (V _W ) is applied. (LRS).

In the present embodiment, when the first SR-FTJ (F1) is in a high resistance state (HRS) and the second SR-FTJ (F2) is in a low resistance state (LRS) in each memory cell (MC), the corresponding memory cell It is assumed that (MC) is in a state where data of “0” is stored. Therefore, when the first SR-FTJ (F1) is in a low resistance state (LRS) and the second SR-FTJ (F2) is in a high resistance state (HRS), the corresponding memory cell (MC) stores data of “1” can be said to be in one state.

A write operation in the CAM mode of the memory cell according to the present embodiment is divided into a high resistance setting step shown in FIG. 5 and a low resistance setting step shown in FIG. 6 . Here, the high resistance setting step depends on the data to be stored in the memory cells ((MC[00], MC[01], MC[02]), (MC[10], MC[11], MC[12])). The corresponding SR-FTJs (F1, F2) have a high resistance state (HRS), and the low resistance setting step causes the corresponding SR-FTJs (F1, F2) to have a low resistance state (LRS).

During light operation, multiple search line pairs ((SL[0], SLB[0]), (SL[1], SLB[1]), (SL[2], Voltages according to data to be stored in the corresponding memory cells (MC[00], MC[01], MC[02]) are applied to SLB[2])). Here, it is assumed that “0”, “1”, and “1” are written to three memory cells (MC[00], MC[01], and MC[02]), respectively. Accordingly, the write voltage V _W having a predetermined voltage level is applied to the search line SL[0] of the first search line pair SL[0] and SLB[0], and the search line bar SLB[ 0]), a ground voltage (0V) is applied. On the other hand, as the search lines SL[1] and SL[2] of the second and third search line pairs ((SL[1], SLB[1]), (SL[2], SLB[2])] A ground voltage (0V) is applied, and a write voltage (V _W ) is applied to the search line bars SLB[1] and SLB[2].

Meanwhile, referring to FIG. 5, in the high-resistance setting step of the write operation, data is applied together with data to select memory cells (MC[00], MC[01], MC[02]) on which data is to be written in units of rows. A match line ML[0] corresponding to the address is selected, and a ground voltage 0V is applied to the selected match line ML[0]. A voltage of V _W /2 level, which is half of the write voltage V _W , is applied to the remaining unselected match lines ML[1].

Therefore, the first SR-FTJ ( The ground voltage (0V) applied as the match line (ML[0]) and the search line ( The write voltage (V _W ) is applied in the reverse direction by the write voltage (V W ) applied to the SL[0] ₎ and the search line bars (SLB[1], SLB[2]), which is the negative write voltage (-V _W ) can be seen as approved. Accordingly, the 1st SR-FTJ(F1) of the 11th memory cell MC[00] and the 2nd SR-FTJ(F2) of the 12th and 13th memories MC[01] and MC[02] have high resistance has a status (HRS).

At this time, the 2nd SR-FTJ(F2) of the 11th memory cell MC[00] and the 1st SR-FTJ(F1) of the 12th and 13th memories MC[01] and MC[02] are matched. Since the voltages of the line (ML[0]), the search line bar (SLB[0]), and the search lines (SL[1], SL[2]) are all the same as the ground voltage (0V), no voltage difference occurs, change does not occur

And in the case of memory cells (MC[10], MC[11], MC[12]) connected to unselected matchlines (ML[1]), write voltage (V _W ) with matchlines (ML[1]) Since a voltage of half of V _W /2 level is applied, both ends of the first and second SR-FTJs (F1, F2) of the memory cells (MC[10], MC[11], MC[12]) The applied voltage is V _W /2 or -V _W /2 level. Accordingly, the states of the memory cells MC[10], MC[11], and MC[12] connected to the non-selected match line ML[1] also do not change.

Meanwhile, referring to FIG. 6, in the low resistance setting step of the write operation, the write voltage (V _W ) is applied to the match line (ML[0]) for which data is selected, and the remaining match lines (ML[1]) that are not selected , the voltage of the V _W /2 level applied in the high resistance setting step is maintained and applied.

Therefore, the match line is applied to the 2nd SR-FTJ(F2) of the 11th memory cell MC[00] and the 1st SR-FTJ(F1) of the 12th and 13th memories MC[01] and MC[02]. Positive by the light voltage (V _W ) applied to (ML[0]) and the ground voltage (0V) applied to the search line bar (SLB[0]) and search lines (SL[1], SL[2]) A write voltage (V _W ) is applied. Accordingly, the 2nd SR-FTJ(F2) of the 11th memory cell MC[00] and the 1st SR-FTJ(F1) of the 12th and 13th memories MC[01] and MC[02] have low resistance state (LRS).

At this time, the 1st SR-FTJ(F1) of the 11th memory cell MC[00] and the 2nd SR-FTJ(F2) of the 12th and 13th memories MC[01] and MC[02] are matched. Since the voltages of the line (ML[0]) and the search line bar (SLB[0]) or the search lines (SL[1], SL[2]) are all the same as the write voltage (V _W ), no voltage difference occurs, The high resistance state (HRS) set in the high resistance setting step is maintained.

And the memory cells (MC[10], MC[11], MC[12]) connected to the unselected match line (ML[1]) have a voltage of V _W /2 level as the match line (ML[1]). It is applied as it is, and the voltage across the first and second SR-FTJs (F1, F2) of the memory cells (MC[10], MC[11], MC[12]) is also V _W /2 or -V _W /2. Accordingly, the states of the memory cells MC[10], MC[11], and MC[12] connected to the non-selected match line ML[1] also do not change.

As a result, during the write operation, the ground voltage (0V) and the write voltage (V _W ) are sequentially applied to the match line (ML[1]) selected in the high resistance setting step and the low resistance setting step, and the search line pair ((SL[ 0], SLB[0]), (SL[1], SLB[1]), (SL[2], SLB[2])) the voltage (V _W , 0V) corresponding to the data to be stored. applied so that the first and second SR-FTJs (F1, F2) of the memory cells (MC[10], MC[11], MC[12]) have a high resistance state (HRS) and a low resistance state (LRS) do.

8 and 9 are diagrams for explaining a search operation in a CAM mode of a memory device according to an exemplary embodiment.

In the memory device of this embodiment, similar to the write operation, the search operation is also composed of two steps: a precharge step shown in FIG. 8 and a match evaluation step shown in FIG. 9 .

Referring to FIG. 8, in the precharge step, a plurality of match lines (ML[0], ML[1]) and a plurality of search line pairs ((SL[0], SLB[0]), (SL[1], A power supply voltage (V _DD ) having a predetermined voltage level between the ground voltage (0V) and the write voltage (V _W ) is applied to SLB[1]) and (SL[2], SLB[2]). Therefore, multiple match lines (ML[0], ML[1]) and multiple search line pairs ((SL[0], SLB[0]), (SL[1], SLB[1]), (SL[ 2] and SLB[2])) are all precharged with the power supply voltage (V _DD ).

Here, not only multiple match lines (ML[0], ML[1]) but also multiple search line pairs ((SL[0], SLB[0]), (SL[1], SLB[1]), (SL [2], SLB[2])) also applies the power supply voltage (V _DD ) to a plurality of memory cells ((MC[00], MC[01], MC[02]), (MC[10] , MC[11], MC[12]) precharged in a plurality of match lines (ML[0], ML[1]) by the leakage currents of the first and second SR-FTJs (F1, F2) This is to prevent the power supply voltage (V _DD ) from dropping.

On the other hand, referring to FIG. 9, in the match evaluation step, the power supplied to the plurality of match lines (ML[0], ML[1]) is cut off and floating, thereby making the plurality of match lines (ML[0], ML[1]) 1]) to maintain the precharged power supply voltage (V _DD ).

And a number of search line pairs ((SL[0], SLB[0]), (SL[1], SLB[1]), (SL[2], SLB[2])) Apply voltage. Here, it is assumed that data “011” is searched, and three memory cells (MC[00], MC[01], MC[02]) connected to the first match line (ML[0]) and the second match line It is assumed that data “101” and “011” are stored in three memory cells (MC[10], MC[11], MC[12]) connected to (ML[1]), respectively.

Accordingly, in a plurality of search line pairs ((SL[0], SLB[0]), (SL[1], SLB[1]), (SL[2], SLB[2])), the first search line (SL) [0]) and the second and third search line bars SLB[1] and SLB[2], a ground voltage 0V is applied, and a ground voltage 0V is applied to the first search line bar SLB[0] and the second and third search line bars SLB[0]. 3 Apply the power supply voltage (V _DD ) to the search lines (SL[1], SL[2]).

In this way, the data to be searched with multiple search line pairs ((SL[0], SLB[0]), (SL[1], SLB[1]), (SL[2], SLB[2])) When a voltage according to the voltage is applied, the eleventh and second memory cells ((MC[00], MC[01], MC[02]), (MC[10], MC[11], MC[12])) Since the positive supply voltage (V _DD ) is applied between both ends of the first and second SR-FTJs (F1, F2) having a low resistance state (LRS) in 12 memory cells (MC[00], MC[01]), , a current path is formed through the first SR-FTJ(F1) of the 11th memory cell MC[00] and the second SR-FTJ(F2) of the 12th memory cell MC[01]. At this time, a positive supply voltage (V _DD ) is also applied to both ends of the second SR-FTJ(F2) of the 13th memory cell (MC[02]), but the second SR-FTJ(F2) is in a high resistance state (HRS) Therefore, no current path is formed. Accordingly, the voltage level of the first match line ML[0] drops to the ground voltage level 0V by the current flowing through the search line SL[0] and the search line bar SLB[1].

On the other hand, in the second match line ML[1], the data "011" stored in the three memory cells (MC[10], MC[11], MC[12]) is matched with the data "011" to be searched for. . Therefore, the first SR-FTJ (F1) of the 21st memory cell (MC[10]) and the 22nd and 23rd memory cells (MC[11], MC[12]) to which the positive supply voltage (V _DD ) is applied to both ends The second SR-FTJs (F2) of are all in a high resistance state (HRS). Accordingly, since a current path is not formed, the precharged power supply voltage V _DD of the second match line ML[1] is maintained.

As a result, the second match line (ML[1]) storing the data matching the data “011” to be searched maintains the precharged power supply voltage (V _DD ) level, while the remaining match lines (ML[0]) Since the voltage drops to the level of the ground voltage (0V) in , it is possible to easily determine the match line (ML[1]) storing matched data and obtain a corresponding address. That is, it can operate as a CAM.

10 illustrates an example of a configuration for operating a memory device according to the present embodiment in a PUF mode.

In this embodiment, the memory device operates as a PUF by using two SR-FTJs (F1, F2) connected between a plurality of match lines (ML) and a plurality of search line pairs (SL, SLB) as shown in FIG. ), multiple muxes Mux1 and Mux2 each connected to a predetermined number of match lines ML, and at least one sense amplifier SA. Here, for convenience of description, the plurality of memory cells MC are divided into a plurality of memory cell arrays (Array 1 and Array 2) by a plurality of muxes (Mux1 and Mux2) connected to a predetermined number of match lines ML. to explain. That is, in the present embodiment, it can be seen that the plurality of memory cells MC are not physically separated, but are pseudo-divided into a plurality of memory cell arrays Array 1 and Array 2 by muxes Mux1 and Mux2.

When operating in the PUF mode, the plurality of muxes Mux1 and Mux2 select one match line among the plurality of match lines ML according to the address applied as a challenge, and the corresponding sense of at least one sense amplifier SA Connect to the amp. At this time, the address applied as the challenge may be applied as an address for two match lines ML so that one match line ML can be independently selected from each of the two memory cell arrays Array 1 and Array 2. , only the address of one match line ML in the two memory cell arrays Array 1 and Array 2 may be applied.

If the addresses for the two match lines (ML) disposed in different memory cell arrays (Array 1 and Array 2) are applied as challenges, the two muxes (Mux1 and Mux2) each match the match lines (ML) corresponding to the corresponding addresses. ML) and connect it to the sense amplifier (SA). Each of the at least one sense amplifier SA amplifies and outputs a voltage difference between two match lines ML connected by corresponding two muxes Mux1 and Mux2 among a plurality of muxes.

When the memory device of the present embodiment selects two match lines (ML) disposed in different memory cell arrays (Array 1 and Array 2) during a PUF operation and connects them to the sense amplifier (SA), the selected match line (ML) This is to ensure that a response can be generated by checking the manufacturing characteristics of the memory cell MC connected to ).

In a conventional PUF, when an address for a plurality of memory cells is generally applied as a challenge, a response according to the characteristics of each memory cell is generated and output, and security verification is performed by comparing the output response with a previously prepared CRP. That is, a response was generated based on the individual manufacturing characteristics of each of the plurality of memory cells. However, if the memory cell is configured to generate a response according to manufacturing characteristics of each memory cell in this way, the corresponding memory cell cannot be used as a storage device for storing specific data. This is because a change in characteristics may occur according to a value of data stored in each memory cell.

In this embodiment, by overcoming this problem, as shown in FIGS. 6 to 9, each of a plurality of memory cells (MC) composed of two SR-FTJs (F1, F2) is operated as a CAM while simultaneously PUF A method of generating a response by comparing and amplifying a manufacturing characteristic difference with another memory cell MC is used so that the memory cell MC can be used as a memory cell MC.

In particular, in the memory device of the present embodiment, by allowing two muxes Mux1 and Mux2 to select the match line ML, respectively, differences in manufacturing characteristics are compared and amplified in units of memory cell rows instead of single memory cells MC. Use a method that generates a response.

In this embodiment, leakage generated in a plurality of memory cells MC composed of two SR-FTJs (F1, F2) so that the data stored for the CAM mode in the memory cells MC is not changed when operating in the PUF mode. The current is obtained and used as a response according to manufacturing characteristics. However, the leakage current is a microcurrent generated when reverse voltage is applied to the two SR-FTJs (F1, F2). Therefore, even if a method of comparing and amplifying relative characteristics with other memory cells is used, it is difficult to generate a stable response by comparing leakage currents between individual memory cells MC. In order to solve this problem, in the present embodiment, an accurate response can be generated by summing the leakage currents generated from a plurality of memory cells MC connected to each match line ML and performing mutual comparison in units of memory cell rows. make it possible

As described above, in the memory device of this embodiment, each of the plurality of memory cells MC is composed of only two SR-FTJs (F1 and F2), and regardless of the data stored in the memory cells MC, two SR-FTJs - The states of FTJs (F1, F2) always have different states. That is, when the data stored in the memory cell MC is “0” or “1”, one of the two SR-FTJs (F1, F2) has a high resistance state (HRS), while the other one has a low resistance state (HRS). It has a resistance state (LRS).

Therefore, even if different data are stored in a plurality of memory cells MC connected to each match line ML, the number of memory cells MC connected to each match line ML is the same, resulting in a low resistance state ( The number of SR-FTJs having LRS and the number of SR-FTJs having high resistance states HRS are also equal to the number of memory cells MC connected to match lines ML.

And as described in (b) of FIG. 3, the magnitude of the basic leakage current (I _leak ) according to manufacturing characteristics is the same, and the change in leakage current (ΔI _leak ) generated according to the state change of the SR-FTJ is all SR -Same in FTJ. When the magnitudes of leakage currents generated from the same number of memory cells MC are compared, the changes in leakage currents (ΔI _leak ) generated according to the state change are equal and cancel each other, so that the data stored in the memory cells MC Regardless, a response can be generated by comparing only the magnitude of the leakage current (I _leak ) according to manufacturing characteristics.

Here, for convenience of explanation, it is illustrated that muxes Mux1 and Mux2 corresponding to each of a plurality of memory cell arrays Array 1 and Array 2 are included, but the muxes Mux1 and Mux2 are memory cell arrays Array 1 and Array 1. 2) and can be seen as a separate composition. In particular, the muxes Mux1 and Mux2 and the sense amplifier SA may be referred to as PUF response generators.

11 and 12 are diagrams for explaining an operation of a memory cell in a PUF mode according to an exemplary embodiment.

For convenience of understanding, two match lines (ML[0], ML[1]) and three search line pairs ((SL[0], SLB[0]), ( Six memory cells ((MC[00], MC[01], MC[02]), (MC[02]) connected between SL[1], SLB[1]), (SL[2], SLB[2])) [10], MC[11], MC[12])) is shown as one memory cell array. And each of the six memory cells (MC[00], MC[01], MC[02]), (MC[10], MC[11], MC[12]) has two SR-FTJs (F1, F2) is included.

Similar to the search operation in the CAM mode, the operation in the PUF mode also consists of two steps: a discharge step shown in FIG. 11 and a response generation step shown in FIG. 12 .

Referring to FIG. 11, in the discharge step, contrary to the precharge step of FIG. 8, a plurality of match lines (ML[0], ML[1]) and a plurality of search line pairs ((SL[0], SLB[0]) ), (SL[1], SLB[1]), (SL[2], SLB[2])) by applying ground voltage (0V) to discharge.

Referring to FIG. 12, in the response generation step, a match line (herein, as an example, a first match line ML[0]) selected from among a plurality of match lines ML[0] and ML[1] is an applied voltage. It is blocked and plotted, and the remaining match lines (ML[1]) except for the selected match line (ML[0]) and a number of search line pairs ((SL[0], SLB[0]), (SL[1], The power supply voltage (V _DD ) is applied to SLB[1]), (SL[2], SLB[2])).

A number of search line pairs ((SL[0], SLB[0]), (SL[1], SLB[1]), (SL[2], SLB[2])) supply voltage (V _DD ) When applied, since the first match line ML[0] is in a floating state after the ground voltage 0V is discharged, each of the connected memory cells MC[00], MC[01], and MC[02] Reverse voltage is applied to the two SR-FTJs (F1, F2) to generate leakage current, which causes the voltage level of the first match line ML[0] to rise.

On the other hand, unselected matchlines (ML[1]) are multiple search line pairs ((SL[0], SLB[0]), (SL[1], SLB[1]), (SL[2], SLB Since the power supply voltage (V _DD ) is being applied in the same manner as in [2])), voltage change does not occur.

Each of the at least one sense amplifier (SA) senses and amplifies the voltage difference between two match lines (ML) selected by the muxes (Mux1, Mux2) in different memory cell arrays (Array 1 and Array 2) and generates a response. do. The response generated here is just one bit of data.

Accordingly, when a multi-bit response is to be generated to increase the security of the PUF, the challenge includes the address of the match line (ML) of a plurality of different memory cell arrays, and the mux (Mux1, Mux2) and sense amplifier ( SA) may be configured to generate a bit-by-bit response iteratively. However, in this case, since the PUF operation speed is slowed down by sequentially generating a response for each bit, a plurality of muxes simultaneously selects the match line (ML) designated by the challenge to match the corresponding sense amplifier among the plurality of sense amplifiers (SA). It is also possible to improve the operation speed by connecting them to generate the response of each bit in parallel and at the same time.

13 illustrates a method of operating a memory device according to an embodiment of the present invention.

Referring to the method of operating the memory device of FIG. 13 with reference to FIGS. 1 to 12, first, it is determined whether to operate in the CAM mode (S10). The memory device of this embodiment can operate in either the CAM mode or the PUF mode, and whether to operate in the CAM mode or the PUF mode can be determined according to an applied command. For example, the memory device may be configured to operate in a CAM mode when a write command or a search command is applied, and to operate in a PUF mode when a challenge is applied.

If it is determined to operate in the CAM mode, a CAM step is performed. In the CAM step, it is first determined whether a write command has been applied (S21). If the write command is applied, one of the two SR-FTJs (F1, F2) of the plurality of memory cells (MC) connected to the match line (ML) corresponding to the address applied with the write command is fixed according to the applied data. It is set to the resistance state (HRS) (S22).

In the step of setting the high resistance state (S22), a ground voltage (0V) is applied to one match line among a plurality of match lines according to the applied address, and a write voltage (with a predetermined voltage level) is applied to the remaining match lines. A voltage of V _W /2 level, which is half of V _W ), is applied, and a voltage according to data to be stored in the corresponding memory cell MC is applied to each of the plurality of search line pairs SL and SLB. At this time, if the data to be stored in the memory cell MC is “0”, the write voltage V _W is applied from the search line pair SL and SLB to the search line SL, and to the search line bar SLB. Apply ground voltage (0V). On the other hand, if the data to be stored is “1”, the ground voltage (0V) is applied to the search line (SL) and the write voltage (V _W ) is applied to the search line bar (SLB) in the search line pair (SL, SLB). authorize Accordingly, a write voltage (V _W ) in the reverse direction is applied to one of the two SR-FTJs (F1, F2) of the memory cell MC connected to the selected match line ML, and thus the high resistance state HRS is set. .

Thereafter, the other one of the two SR-FTJs (F1, F2) of the plurality of memory cells (MC) connected to the match line (ML) corresponding to the applied address is set to a low resistance state (LRS) according to the applied data Do (S23).

Even in the step of setting the low resistance state (S23), the voltage according to the data to be stored in the corresponding memory cell MC is maintained and applied to each of the plurality of search line pairs SL and SLB. Also, the voltage of the applied V _W /2 level is maintained for the unselected match line. However, a write voltage (V _W ) is applied to the selected match line corresponding to the applied address. Therefore, among the two SR-FTJs (F1, F2) of the memory cell (MC) connected to the selected match line (ML), the forward write voltage (V _W ) is applied to the other one that is not set to the high resistance state (HRS). , and is thus set to the low resistance state (LRS).

On the other hand, if a search command is applied without a write command, the power supply voltage (V _DD ) is applied to the plurality of match lines (ML) and the plurality of search line pairs (SL, SLB) according to the search command to precharge ( S24).

Thereafter, power applied to the plurality of match lines (ML) is cut off and floated, and a match evaluation is performed by applying a voltage corresponding to data to be searched to a plurality of search line pairs (SL and SLB) (S25). At this time, if the data to be searched is “0”, the ground voltage (0V) is applied to the search line (SL), and the power supply voltage (V _DD ) is applied to the search line bar (SLB). On the other hand, if the data to be searched is “1”, the power supply voltage (V _DD ) is applied to the search line (SL), and the ground voltage (0V) is applied to the search line bar (SLB).

Accordingly, a mismatch with a voltage applied through a corresponding search line pair (SL, SLB) occurs in at least one memory cell among a plurality of memory cells (MC) connected to each of a plurality of match lines (ML), resulting in two SRs. -When forward voltage is applied to SR-FTJ in low resistance state (LRS) among FTJs (F1, F2), the level of the power supply voltage (V _DD ) precharged in the corresponding match line (ML) is the ground voltage (0V) level descend with On the other hand, if the data stored in the plurality of memory cells MC connected to the match line ML match all the voltages applied through the corresponding search line pairs SL and SLB, all of the memory cells MC have a low voltage. A reverse voltage is applied to the SR-FTJ in the resistance state LRS, so that the precharged power voltage V _DD of the corresponding match line ML is maintained. Therefore, by determining the voltage levels of the plurality of match lines ML, it is possible to easily search for an address where data corresponding to the applied data is stored.

Meanwhile, if a challenge rather than a CAM command is applied, a PUF step operating in the PUF mode rather than the CAM mode is performed. In the PUF step, first, a ground voltage (0V) is applied to a plurality of match lines (ML) and a plurality of search line pairs (SL, SLB) to discharge them (S31).

Then, match line due to leakage current generated by applying reverse voltage to two SR-FTJs (F1, F2) of a plurality of memory cells (MC) connected to the match line (ML) selected according to the address transmitted as a challenge. A change in (ML) is sensed and amplified to generate a response (S32).

Specifically, in the response generating step (S32), one match line (ML) is selected from two different memory cell arrays among a plurality of memory cell arrays divided into muxes according to the address transmitted as the challenge, and the selected match The line ML blocks the applied voltage and makes it float, and the power supply voltage V _DD is applied to the match line ML except for the selected match line ML and a plurality of search line pairs. That is, reverse voltages are applied to all of the two SR-FTJs (F1, F2) constituting the plurality of memory cells MC connected to the selected match line.

As a result, a leakage current having a magnitude corresponding to manufacturing characteristics flows in the two SR-FTJs F1 and F2 connected to the selected match line ML, and thus the voltage level of the selected match line ML rises. Therefore, the voltage level of each match line (ML) selected from different memory cell arrays rises at different speeds depending on the manufacturing characteristics of the connected two SR-FTJs (F1, F2) constituting the connected memory cell (MC). , When each mux connects the selected match line ML to a corresponding sense amplifier SA, the sense amplifier SA generates a response by sensing and amplifying a voltage difference between the two connected match lines ML.

As a result, the memory device according to the present embodiment not only consists of two SR-FTJs (F1 and F2), but also can be implemented in a 3D stacked structure, so that it can be manufactured in a very small size. It can be used to store the data of the CAM and at the same time generate the response of the PUF. That is, it can operate in dual mode. In particular, since the two SR-FTJs (F1, F2) of each memory cell (MC) always have different states of high resistance state (HRS) and low resistance state (LRS) regardless of stored data, It can provide randomness, independence, stability and area efficiency.

The method according to the present invention may be implemented as a computer program stored in a medium for execution on a computer. Here, computer readable media may be any available media that can be accessed by a computer, and may also include all computer storage media. Computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, including read-only memory (ROM) dedicated memory), random access memory (RAM), compact disk (CD)-ROM, digital video disk (DVD)-ROM, magnetic tape, floppy disk, optical data storage device, and the like.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is only exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom.

Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

ML: Matchline SL: Searchline
SLB: search line bar MC: memory cell
Mux: Mux SA: Sense Amp

Claims (20)

Two self-rectifying ferroelectric tunnel junction elements each connected between a plurality of match lines extending in a first direction and a plurality of search line pairs extending in a second direction crossing the first direction. : a plurality of memory cells composed of SR-FTJ);
a power supply unit supplying voltages according to operating states to the plurality of match line pairs and the plurality of search line pairs; and
When operating in the PUF mode between CAM (Content Addressable Memory) mode and PUF (Physically Unclonable Function) mode, reverse voltage to each of the two SR-FTJs of a plurality of memory cells connected to a match line selected according to the address transmitted as a challenge and a PUF response generation unit configured to sense and amplify a voltage change generated on a selected match line by the leakage current generated by the application of the leakage current and generate a response corresponding to the challenge. 2. The method of claim 1, wherein each of the plurality of memory cells
a first SR-FTJ connected between a corresponding match line among the plurality of match lines and a search line of a corresponding search line pair among the plurality of search line pairs; and
and a second SR-FTJ connected between a corresponding match line among the plurality of match lines and a search line bar of a corresponding search line pair among the plurality of search line pairs. The method of claim 2, wherein the response generator
a plurality of muxes connected to a predetermined number of different match lines among the plurality of match lines to select a match line corresponding to the challenge; and
and at least one sense amplifier configured to generate the response by sensing and amplifying a voltage difference between match lines selected by two corresponding muxes among the plurality of muxes. The method of claim 3, wherein the power supply unit
In the discharge step of the PUF mode, which is divided into a discharge step and a response generation step, a ground voltage level is applied so that the plurality of match line pairs and the plurality of search line pairs are discharged;
In the response generation step, a voltage applied to a match line selected according to an address specified by the challenge among the plurality of match lines is cut off and floated, and a power supply voltage of a predetermined voltage level is applied to the remaining match line and the search line pair. Memory device to authorize. 5. The method of claim 4, wherein the at least one sense amplifier
In the response generating step, when two corresponding muxes among the plurality of muxes select and connect match lines according to addresses designated by the challenge, two SR- A memory device generating the response by sensing and amplifying a voltage difference between match lines that changes by a leakage current generated when a reverse voltage is applied to the FTJ. 5. The method of claim 4, wherein each of the plurality of memory cells
When data “0” is stored by the write operation of the CAM mode, which is divided into a write operation and a search operation, the first SR-FTJ has a high resistance state (HRS), and the second SR -FTJ has a low resistance state (LRS),
When data “1” is stored, the first SR-FTJ has a low resistance state and the second SR-FTJ has a high resistance state. The method of claim 6, wherein the power supply unit
In the high-resistance setting step of the write operation, the ground voltage is applied to a match line selected according to an applied address among a plurality of match lines, and a voltage of 1/2 of the write voltage of a predetermined voltage level is applied to the remaining match lines. and applying a voltage according to data to be stored in a corresponding memory cell MC to each of the plurality of search line pairs,
In the low resistance setting step of the write operation, the write voltage is applied to a selected match line, and the voltage applied in the high resistance setting step is maintained to the remaining match lines and the plurality of search line pairs. The method of claim 7, wherein the power supply unit
During a write operation in the CAM mode, if data to be stored in a memory cell is “0”, the write voltage is applied to a search line in a corresponding search line pair, and the ground voltage is applied to a search line bar;
If data to be stored in a memory cell is “1”, the memory device applies the ground voltage to a search line and the write voltage to a search line in a corresponding search line pair. The method of claim 6, wherein the power supply unit
In the precharging step of the search operation, precharging is performed by applying the power supply voltage to the plurality of match line pairs and the plurality of search line pairs;
In the match evaluation step of the search operation, power supplied to the plurality of match lines is cut off and floated, and a voltage corresponding to data to be searched is applied to the plurality of search line pairs. The method of claim 9, wherein the power supply unit
If the data to be searched during the search operation is “0”, the ground voltage is applied to the search line in the corresponding search line pair, and the power supply voltage is applied to the search line bar;
If the data to be searched is “1”, the power voltage is applied to a search line in a corresponding search line pair, and the ground voltage is applied to a search line. The method of claim 1 , wherein the plurality of memory cells
Search lines and search line bars of each of the plurality of search line pairs are disposed above and below the plurality of match lines, respectively, and the two SR-FTJs search between corresponding match lines and search lines and between corresponding match lines and search lines. A memory device implemented as a 3D structure stacked between line bars. Two self-rectifying ferroelectric tunnel junction elements each connected between a plurality of match lines extending in a first direction and a plurality of search line pairs extending in a second direction crossing the first direction. : In the operating method of a memory device including a plurality of memory cells composed of SR-FTJ),
determining an operation mode of a CAM mode or a PUF mode according to an applied command;
If the determined operation mode is the PUF mode, a leakage current generated when a reverse voltage is applied to two SR-FTJs of each of a plurality of memory cells connected to a match line selected according to an address transmitted as a challenge results in the selected match line and generating a response corresponding to the challenge by sensing and amplifying a voltage change generated in the memory device. 13. The method of claim 12, wherein each of the plurality of memory cells
a first SR-FTJ connected between a corresponding match line among the plurality of match lines and a search line of a corresponding search line pair among the plurality of search line pairs; and
A method of operating a memory device comprising a second SR-FTJ connected between a corresponding match line among the plurality of match lines and a search line bar of a corresponding search line pair among the plurality of search line pairs. 14. The method of claim 13, wherein generating the response comprises:
discharging a ground voltage by applying a ground voltage to the plurality of match line pairs and the plurality of search line pairs;
blocking and floating a voltage applied to a match line selected from among the plurality of match lines according to an address designated by the challenge, and applying a power supply voltage having a predetermined voltage level to the remaining match lines and the search line pair; and
A selected match line that changes by a leakage current generated in two SR-FTJs in each of a plurality of memory cells connected to the two match lines selected to select a match line according to the address specified by the challenge and generate the response A method of operating a memory device comprising detecting and amplifying a voltage difference between 14. The method of claim 13, wherein each of the plurality of memory cells
When data "0" is stored, the first SR-FTJ has a high resistance state (HRS) and the second SR-FTJ has a low resistance state (LRS),
When data “1” is stored, the first SR-FTJ has a low resistance state and the second SR-FTJ has a high resistance state. 16. The method of claim 15, wherein the method of operating the memory device
determining whether a write command or a search command is applied if the determined operation mode is the CAM mode;
if the write command is applied, writing the applied data to a memory cell according to an address applied together with the write command among the plurality of memory cells; and
and searching a memory cell storing data applied together with the search command when the search command is applied. 17. The method of claim 16, wherein the lighting step
A ground voltage is applied to a match line selected according to an applied address among a plurality of match lines, and a voltage of 1/2 level of a write voltage of a predetermined voltage level is applied to the remaining match lines. a high resistance setting step of applying a voltage according to data to be stored in the corresponding memory cell MC to each; and
and a low resistance setting step of applying the write voltage to a selected match line and maintaining the voltage applied in the high resistance setting step to the remaining match lines and the plurality of search line pairs. 18. The method of claim 17, wherein the lighting step
If the data to be stored in the memory cell is “0”, the write voltage is applied to the search line in the corresponding search line pair, and the ground voltage is applied to the search line bar;
If data to be stored in a memory cell is "1", the ground voltage is applied to a search line in a corresponding search line pair, and the write voltage is applied to a search line. 17. The method of claim 16, wherein the searching step
precharging by applying a power supply voltage having a predetermined voltage level to the plurality of match line pairs and the plurality of search line pairs; and
Power supplied to the plurality of match lines is cut off and floated, and a voltage corresponding to data to be searched is applied to the plurality of search line pairs, and a memory cell storing data corresponding to the applied data is connected to the match line. A method of operating a memory device comprising a match evaluation step of causing a voltage to drop. 20. The method of claim 19, wherein the searching step
If the data to be searched is “0”, a ground voltage is applied to the search line in the corresponding search line pair, and the power supply voltage is applied to the search line bar;
If the data to be searched is "1", the power supply voltage is applied to a search line in a corresponding search line pair, and the ground voltage is applied to a search line.

Images